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authorTom Rini <[email protected]>2024-04-15 07:39:14 -0600
committerTom Rini <[email protected]>2024-04-15 07:39:14 -0600
commit6e316e3f397b5e01e98c5dd56cdbaab961daeedf (patch)
tree0e8293a905ca3233da6a9c9c22b340373b19b1c2 /drivers/serial
parentdb972665794f38c7bf224d69f6a6206a4083d85d (diff)
parent8ecb0931940cc19728d686b9dba06585f4d93709 (diff)
Merge tag 'u-boot-imx-master-20240415' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/20348 - Update the imx_rgpio2p to only access one address as per the dt-schema. - Remove unused imx9_cpu.c file. - Only use the LPUART ipg clk for i.MX7ULP. - Use the correct anatop base for accessing the PLL clocks on i.MX93.
Diffstat (limited to 'drivers/serial')
-rw-r--r--drivers/serial/serial_lpuart.c42
1 files changed, 26 insertions, 16 deletions
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index ce08a6b4486..3f2be72b830 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -109,28 +109,35 @@ u32 __weak get_lpuart_clk(void)
}
#if CONFIG_IS_ENABLED(CLK)
-static int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
+static int get_lpuart_clk_rate(struct udevice *dev, u32 *clk_rate)
{
- struct clk per_clk;
+ struct lpuart_serial_plat *plat = dev_get_plat(dev);
+ struct clk clk;
ulong rate;
int ret;
+ char *name;
- ret = clk_get_by_name(dev, "per", &per_clk);
+ if (plat->devtype == DEV_MX7ULP)
+ name = "ipg";
+ else
+ name = "per";
+
+ ret = clk_get_by_name(dev, name, &clk);
if (ret) {
- dev_err(dev, "Failed to get per clk: %d\n", ret);
+ dev_err(dev, "Failed to get clk: %d\n", ret);
return ret;
}
- rate = clk_get_rate(&per_clk);
+ rate = clk_get_rate(&clk);
if ((long)rate <= 0) {
- dev_err(dev, "Failed to get per clk rate: %ld\n", (long)rate);
+ dev_err(dev, "Failed to get clk rate: %ld\n", (long)rate);
return ret;
}
- *clk = rate;
+ *clk_rate = rate;
return 0;
}
#else
-static inline int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
+static inline int get_lpuart_clk_rate(struct udevice *dev, u32 *clk_rate)
{ return -ENOSYS; }
#endif
@@ -479,19 +486,22 @@ static int lpuart_serial_pending(struct udevice *dev, bool input)
static int lpuart_serial_probe(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(CLK)
+ struct lpuart_serial_plat *plat = dev_get_plat(dev);
struct clk per_clk;
struct clk ipg_clk;
int ret;
- ret = clk_get_by_name(dev, "per", &per_clk);
- if (!ret) {
- ret = clk_enable(&per_clk);
- if (ret) {
- dev_err(dev, "Failed to enable per clk: %d\n", ret);
- return ret;
+ if (plat->devtype != DEV_MX7ULP) {
+ ret = clk_get_by_name(dev, "per", &per_clk);
+ if (!ret) {
+ ret = clk_enable(&per_clk);
+ if (ret) {
+ dev_err(dev, "Failed to enable per clk: %d\n", ret);
+ return ret;
+ }
+ } else {
+ debug("%s: Failed to get per clk: %d\n", __func__, ret);
}
- } else {
- debug("%s: Failed to get per clk: %d\n", __func__, ret);
}
ret = clk_get_by_name(dev, "ipg", &ipg_clk);