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authorTom Rini <[email protected]>2022-09-26 11:28:14 -0400
committerTom Rini <[email protected]>2022-09-26 11:28:14 -0400
commit55ccdee3155c6cc30eeee846879d06aba6e3fabe (patch)
tree4cda01be7fa0553410ffc193f4f931910efbbf57 /drivers/spi
parentffa2c88bcf8618b6d6fb71f5263beede9a179b20 (diff)
parentf2641f066b53a2bbb933bccffd696a875fd9adf5 (diff)
Merge tag 'xilinx-for-v2023.01-rc1-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2023.01-rc1 (round 2) xilinx: - Add support for new Versal NET SOC zynqmp: - Use mdio bus for ethernet phy description - Wire ethernet phy reset via i2c-gpio versal: - Config cleanup
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/Kconfig2
-rw-r--r--drivers/spi/cadence_ospi_versal.c3
-rw-r--r--drivers/spi/zynqmp_gqspi.c3
3 files changed, 5 insertions, 3 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 07e50e240e3..2f12081f88d 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -148,7 +148,7 @@ config CQSPI_REF_CLK
config CADENCE_OSPI_VERSAL
bool "Configure Versal OSPI"
- depends on ARCH_VERSAL && CADENCE_QSPI
+ depends on (ARCH_VERSAL || ARCH_VERSAL_NET) && CADENCE_QSPI
imply DM_GPIO
help
This option is used to enable Versal OSPI DMA operations which
diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c
index a25c50bc508..a9547a82003 100644
--- a/drivers/spi/cadence_ospi_versal.c
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -130,6 +130,7 @@ int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv)
#if defined(CONFIG_DM_GPIO)
int cadence_qspi_versal_flash_reset(struct udevice *dev)
{
+#ifndef CONFIG_ARCH_VERSAL_NET
struct gpio_desc gpio;
u32 reset_gpio;
int ret;
@@ -165,7 +166,7 @@ int cadence_qspi_versal_flash_reset(struct udevice *dev)
/* Set value 1 to pin */
dm_gpio_set_value(&gpio, 1);
udelay(1);
-
+#endif
return 0;
}
#else
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index 4e718c545c6..d3cc8554b8f 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -308,7 +308,8 @@ void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n",
__func__, reqhz, clk_rate, baudrateval);
- if (!IS_ENABLED(CONFIG_ARCH_VERSAL)) {
+ if (!(IS_ENABLED(CONFIG_ARCH_VERSAL) ||
+ IS_ENABLED(CONFIG_ARCH_VERSAL_NET))) {
if (reqhz <= GQSPI_FREQ_40MHZ) {
tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
TAP_DLY_BYPASS_LQSPI_RX_SHIFT;