Merge branch 'next'

5 files changed, 167 insertions, 2 deletions

diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 7b8ab56ed32..20b5af7e260 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -139,6 +139,13 @@ config DESIGNWARE_APB_TIMER
 	  Enables support for the Designware APB Timer driver. This timer is
 	  present on Altera SoCFPGA SoCs.
 
+config GXP_TIMER
+	bool "HPE GXP Timer"
+	depends on TIMER
+	help
+	  Enables support for the GXP Timer driver. This timer is
+	  present on HPE GXP SoCs.
+
 config MPC83XX_TIMER
 	bool "MPC83xx timer support"
 	depends on TIMER
@@ -272,4 +279,13 @@ config IMX_GPT_TIMER
 	  Select this to enable support for the timer found on
 	  NXP i.MX devices.
 
+config XILINX_TIMER
+	bool "Xilinx timer support"
+	depends on TIMER
+	select REGMAP
+	select SPL_REGMAP if SPL
+	help
+	  Select this to enable support for the timer found on
+	  any Xilinx boards (axi timer).
+
 endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index b2f002d5978..d9822a53700 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_$(SPL_)ATMEL_PIT_TIMER) += atmel_pit_timer.o
 obj-$(CONFIG_$(SPL_)ATMEL_TCB_TIMER) += atmel_tcb_timer.o
 obj-$(CONFIG_CADENCE_TTC_TIMER)	+= cadence-ttc.o
 obj-$(CONFIG_DESIGNWARE_APB_TIMER)	+= dw-apb-timer.o
+obj-$(CONFIG_GXP_TIMER)		+= gxp-timer.o
 obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
 obj-$(CONFIG_NOMADIK_MTU_TIMER)	+= nomadik-mtu-timer.o
 obj-$(CONFIG_NPCM_TIMER)        += npcm-timer.o
@@ -27,3 +28,4 @@ obj-$(CONFIG_X86_TSC_TIMER)	+= tsc_timer.o
 obj-$(CONFIG_MTK_TIMER)		+= mtk_timer.o
 obj-$(CONFIG_MCHP_PIT64B_TIMER)	+= mchp-pit64b-timer.o
 obj-$(CONFIG_IMX_GPT_TIMER)	+= imx-gpt-timer.o
+obj-$(CONFIG_XILINX_TIMER)	+= xilinx-timer.o
diff --git a/drivers/timer/gxp-timer.c b/drivers/timer/gxp-timer.c
new file mode 100644
index 00000000000..6f316bc8c5c
--- /dev/null
+++ b/drivers/timer/gxp-timer.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * GXP timer driver
+ *
+ * (C) Copyright 2022 Hewlett Packard Enterprise Development LP.
+ * Author: Nick Hawkins <[email protected]>
+ * Author: Jean-Marie Verdun <[email protected]>
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <timer.h>
+#include <asm/io.h>
+
+#define USTIMELO	0x18
+#define USTIMEHI	0x1C
+
+struct gxp_timer_priv {
+	void __iomem *base;
+};
+
+static u64 gxp_timer_get_count(struct udevice *dev)
+{
+	struct gxp_timer_priv *priv = dev_get_priv(dev);
+	u64 val;
+
+	val = readl(priv->base + USTIMEHI);
+	val = (val << 32) | readl(priv->base + USTIMELO);
+
+	return val;
+}
+
+static int gxp_timer_probe(struct udevice *dev)
+{
+	struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct gxp_timer_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_read_addr_ptr(dev);
+	if (!priv->base)
+		return -ENOENT;
+
+	uc_priv->clock_rate = 1000000;
+
+	return 0;
+}
+
+static const struct timer_ops gxp_timer_ops = {
+	.get_count = gxp_timer_get_count,
+};
+
+static const struct udevice_id gxp_timer_ids[] = {
+	{ .compatible = "hpe,gxp-timer" },
+	{}
+};
+
+U_BOOT_DRIVER(gxp_timer) = {
+	.name = "gxp-timer",
+	.id = UCLASS_TIMER,
+	.of_match = gxp_timer_ids,
+	.priv_auto = sizeof(struct gxp_timer_priv),
+	.probe = gxp_timer_probe,
+	.ops = &gxp_timer_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/timer/omap-timer.c b/drivers/timer/omap-timer.c
index 25a6108fef2..aa2e4360c1b 100644
--- a/drivers/timer/omap-timer.c
+++ b/drivers/timer/omap-timer.c
@@ -11,6 +11,7 @@
 #include <timer.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
+#include <asm/omap_common.h>
 #include <linux/bitops.h>
 
 /* Timer register bits */
@@ -61,13 +62,13 @@ static int omap_timer_probe(struct udevice *dev)
 	if (!uc_priv->clock_rate)
 		uc_priv->clock_rate = V_SCLK;
 
-	uc_priv->clock_rate /= (2 << CONFIG_SYS_PTV);
+	uc_priv->clock_rate /= (2 << SYS_PTV);
 
 	/* start the counter ticking up, reload value on overflow */
 	writel(0, &priv->regs->tldr);
 	writel(0, &priv->regs->tcrr);
 	/* enable timer */
-	writel((CONFIG_SYS_PTV << 2) | TCLR_PRE_EN | TCLR_AUTO_RELOAD |
+	writel((SYS_PTV << 2) | TCLR_PRE_EN | TCLR_AUTO_RELOAD |
 	       TCLR_START, &priv->regs->tclr);
 
 	return 0;
diff --git a/drivers/timer/xilinx-timer.c b/drivers/timer/xilinx-timer.c
new file mode 100644
index 00000000000..75b4473b639
--- /dev/null
+++ b/drivers/timer/xilinx-timer.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2022 Advanced Micro Devices, Inc
+ * Michal Simek <[email protected]>
+ *
+ * (C) Copyright 2007 Michal Simek
+ * Michal SIMEK <[email protected]>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <timer.h>
+#include <regmap.h>
+#include <dm/device_compat.h>
+
+#define TIMER_ENABLE_ALL    0x400 /* ENALL */
+#define TIMER_PWM           0x200 /* PWMA0 */
+#define TIMER_INTERRUPT     0x100 /* T0INT */
+#define TIMER_ENABLE        0x080 /* ENT0 */
+#define TIMER_ENABLE_INTR   0x040 /* ENIT0 */
+#define TIMER_RESET         0x020 /* LOAD0 */
+#define TIMER_RELOAD        0x010 /* ARHT0 */
+#define TIMER_EXT_CAPTURE   0x008 /* CAPT0 */
+#define TIMER_EXT_COMPARE   0x004 /* GENT0 */
+#define TIMER_DOWN_COUNT    0x002 /* UDT0 */
+#define TIMER_CAPTURE_MODE  0x001 /* MDT0 */
+
+#define TIMER_CONTROL_OFFSET	0
+#define TIMER_LOADREG_OFFSET	4
+#define TIMER_COUNTER_OFFSET	8
+
+struct xilinx_timer_priv {
+	struct regmap *regs;
+};
+
+static u64 xilinx_timer_get_count(struct udevice *dev)
+{
+	struct xilinx_timer_priv *priv = dev_get_priv(dev);
+	u32 value;
+
+	regmap_read(priv->regs, TIMER_COUNTER_OFFSET, &value);
+
+	return value;
+}
+
+static int xilinx_timer_probe(struct udevice *dev)
+{
+	struct xilinx_timer_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	/* uc_priv->clock_rate has already clock rate */
+	ret = regmap_init_mem(dev_ofnode(dev), &priv->regs);
+	if (ret) {
+		dev_dbg(dev, "failed to get regbase of timer\n");
+		return ret;
+	}
+
+	regmap_write(priv->regs, TIMER_LOADREG_OFFSET, 0);
+	regmap_write(priv->regs, TIMER_CONTROL_OFFSET, TIMER_RESET);
+	regmap_write(priv->regs, TIMER_CONTROL_OFFSET,
+		     TIMER_ENABLE | TIMER_RELOAD);
+
+	return 0;
+}
+
+static const struct timer_ops xilinx_timer_ops = {
+	.get_count = xilinx_timer_get_count,
+};
+
+static const struct udevice_id xilinx_timer_ids[] = {
+	{ .compatible = "xlnx,xps-timer-1.00.a" },
+	{}
+};
+
+U_BOOT_DRIVER(xilinx_timer) = {
+	.name = "xilinx_timer",
+	.id = UCLASS_TIMER,
+	.of_match = xilinx_timer_ids,
+	.priv_auto = sizeof(struct xilinx_timer_priv),
+	.probe = xilinx_timer_probe,
+	.ops = &xilinx_timer_ops,
+};