diff options
| author | Sean Anderson <[email protected]> | 2020-10-25 21:46:58 -0400 |
|---|---|---|
| committer | Andes <[email protected]> | 2020-10-26 10:01:28 +0800 |
| commit | 47d7e3b5eb72fd540930c830d568ece19b3defa0 (patch) | |
| tree | e57f62c59ae2d6b062be897a5094d38dcb50137e /drivers/timer | |
| parent | 7dbebebb7949655f35d90c612eaf92e3d2c9ed24 (diff) | |
riscv: Move timer portions of SiFive CLINT to drivers/timer
Half of this driver is a DM-based timer driver, and half is RISC-V-specific
IPI code. Move the timer portions in with the other timer drivers. The
KConfig is not moved, since it also enables IPIs. It could also be split
into two configs, but no boards use the timer but not the IPI atm, so I
haven't split it.
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
Diffstat (limited to 'drivers/timer')
| -rw-r--r-- | drivers/timer/Makefile | 1 | ||||
| -rw-r--r-- | drivers/timer/sifive_clint_timer.c | 47 |
2 files changed, 48 insertions, 0 deletions
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 226227c8ecb..eb5c48cc6ce 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o +obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint_timer.o obj-$(CONFIG_STI_TIMER) += sti-timer.o obj-$(CONFIG_STM32_TIMER) += stm32_timer.o obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o diff --git a/drivers/timer/sifive_clint_timer.c b/drivers/timer/sifive_clint_timer.c new file mode 100644 index 00000000000..00ce0f08d6e --- /dev/null +++ b/drivers/timer/sifive_clint_timer.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020, Sean Anderson <[email protected]> + * Copyright (C) 2018, Bin Meng <[email protected]> + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <timer.h> +#include <asm/io.h> +#include <linux/err.h> + +/* mtime register */ +#define MTIME_REG(base) ((ulong)(base) + 0xbff8) + +static u64 sifive_clint_get_count(struct udevice *dev) +{ + return readq((void __iomem *)MTIME_REG(dev->priv)); +} + +static const struct timer_ops sifive_clint_ops = { + .get_count = sifive_clint_get_count, +}; + +static int sifive_clint_probe(struct udevice *dev) +{ + dev->priv = dev_read_addr_ptr(dev); + if (!dev->priv) + return -EINVAL; + + return timer_timebase_fallback(dev); +} + +static const struct udevice_id sifive_clint_ids[] = { + { .compatible = "riscv,clint0" }, + { } +}; + +U_BOOT_DRIVER(sifive_clint) = { + .name = "sifive_clint", + .id = UCLASS_TIMER, + .of_match = sifive_clint_ids, + .probe = sifive_clint_probe, + .ops = &sifive_clint_ops, + .flags = DM_FLAG_PRE_RELOC, +}; |
