usb: dwc2: Align macros with Linux kernel definitions

Update the DWC2 macros to match those used in the Linux kernel, making
it easier to synchronize updates with kernel. Also removed some unused
macros to cleanup the code.

Signed-off-by: Kongyang Liu <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Tested-by: Peter Robinson <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
Signed-off-by: Junhui Liu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mattijs Korpershoek <[email protected]>

3 files changed, 218 insertions, 217 deletions

diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c
index b89f751b8cc..b08ea5ba79a 100644
--- a/drivers/usb/gadget/dwc2_udc_otg.c
+++ b/drivers/usb/gadget/dwc2_udc_otg.c
@@ -160,7 +160,7 @@ struct dwc2_core_regs *reg;
 
 bool dfu_usb_get_reset(void)
 {
-	return !!(readl(&reg->global_regs.gintsts) & INT_RESET);
+	return !!(readl(&reg->global_regs.gintsts) & GINTSTS_USBRST);
 }
 
 __weak void otg_phy_init(struct dwc2_udc *dev) {}
@@ -240,8 +240,8 @@ static int udc_enable(struct dwc2_udc *dev)
 
 static int dwc2_gadget_pullup(struct usb_gadget *g, int is_on)
 {
-	clrsetbits_le32(&reg->device_regs.dctl, SOFT_DISCONNECT,
-			is_on ? 0 : SOFT_DISCONNECT);
+	clrsetbits_le32(&reg->device_regs.dctl, DCTL_SFTDISCON,
+			is_on ? 0 : DCTL_SFTDISCON);
 
 	return 0;
 }
@@ -471,7 +471,7 @@ static void reconfig_usbd(struct dwc2_udc *dev)
 	u32 max_hw_ep;
 	int pdata_hw_ep;
 
-	writel(CORE_SOFT_RESET, &reg->global_regs.grstctl);
+	writel(GRSTCTL_CSFTRST, &reg->global_regs.grstctl);
 
 	debug("Resetting OTG controller\n");
 
@@ -498,19 +498,20 @@ static void reconfig_usbd(struct dwc2_udc *dev)
 
 	/* 3. Put the OTG device core in the disconnected state.*/
 	uTemp = readl(&reg->device_regs.dctl);
-	uTemp |= SOFT_DISCONNECT;
+	uTemp |= DCTL_SFTDISCON;
 	writel(uTemp, &reg->device_regs.dctl);
 
 	udelay(20);
 
 	/* 4. Make the OTG device core exit from the disconnected state.*/
 	uTemp = readl(&reg->device_regs.dctl);
-	uTemp = uTemp & ~SOFT_DISCONNECT;
+	uTemp = uTemp & ~DCTL_SFTDISCON;
 	writel(uTemp, &reg->device_regs.dctl);
 
 	/* 5. Configure OTG Core to initial settings of device mode.*/
 	/* [][1: full speed(30Mhz) 0:high speed]*/
-	writel(EP_MISS_CNT(1) | DEV_SPEED_HIGH_SPEED_20, &reg->device_regs.dcfg);
+	writel(FIELD_PREP(DCFG_EPMISCNT_MASK, 1) |
+	       FIELD_PREP(DCFG_DEVSPD_MASK, DCFG_DEVSPD_HS), &reg->device_regs.dcfg);
 
 	mdelay(1);
 
@@ -518,12 +519,12 @@ static void reconfig_usbd(struct dwc2_udc *dev)
 	writel(GINTMSK_INIT, &reg->global_regs.gintmsk);
 
 	/* 7. Set NAK bit of EP0, EP1, EP2*/
-	writel(DEPCTL_EPDIS | DEPCTL_SNAK, &reg->device_regs.out_endp[EP0_CON].doepctl);
-	writel(DEPCTL_EPDIS | DEPCTL_SNAK, &reg->device_regs.in_endp[EP0_CON].diepctl);
+	writel(DXEPCTL_EPDIS | DXEPCTL_SNAK, &reg->device_regs.out_endp[EP0_CON].doepctl);
+	writel(DXEPCTL_EPDIS | DXEPCTL_SNAK, &reg->device_regs.in_endp[EP0_CON].diepctl);
 
 	for (i = 1; i < DWC2_MAX_ENDPOINTS; i++) {
-		writel(DEPCTL_EPDIS | DEPCTL_SNAK, &reg->device_regs.out_endp[i].doepctl);
-		writel(DEPCTL_EPDIS | DEPCTL_SNAK, &reg->device_regs.in_endp[i].diepctl);
+		writel(DXEPCTL_EPDIS | DXEPCTL_SNAK, &reg->device_regs.out_endp[i].doepctl);
+		writel(DXEPCTL_EPDIS | DXEPCTL_SNAK, &reg->device_regs.in_endp[i].diepctl);
 	}
 
 	/* 8. Unmask EPO interrupts*/
@@ -551,12 +552,12 @@ static void reconfig_usbd(struct dwc2_udc *dev)
 	writel(rx_fifo_sz, &reg->global_regs.grxfsiz);
 
 	/* 12. Set Non Periodic Tx FIFO Size */
-	writel((np_tx_fifo_sz << 16) | rx_fifo_sz,
+	writel(FIELD_PREP(FIFOSIZE_DEPTH_MASK, np_tx_fifo_sz) |
+	       FIELD_PREP(FIFOSIZE_STARTADDR_MASK, rx_fifo_sz),
 	       &reg->global_regs.gnptxfsiz);
 
 	/* retrieve the number of IN Endpoints (excluding ep0) */
-	max_hw_ep = (readl(&reg->global_regs.ghwcfg4) & GHWCFG4_NUM_IN_EPS_MASK) >>
-		    GHWCFG4_NUM_IN_EPS_SHIFT;
+	max_hw_ep = FIELD_GET(GHWCFG4_NUM_IN_EPS_MASK, readl(&reg->global_regs.ghwcfg4));
 	pdata_hw_ep = dev->pdata->tx_fifo_sz_nb;
 
 	/* tx_fifo_sz_nb should equal to number of IN Endpoint */
@@ -568,24 +569,27 @@ static void reconfig_usbd(struct dwc2_udc *dev)
 		if (pdata_hw_ep)
 			tx_fifo_sz = dev->pdata->tx_fifo_sz_array[i];
 
-		writel((rx_fifo_sz + np_tx_fifo_sz + (tx_fifo_sz * i)) |
-			tx_fifo_sz << 16, &reg->global_regs.dptxfsizn[i]);
+		writel(FIELD_PREP(FIFOSIZE_DEPTH_MASK, tx_fifo_sz) |
+		       FIELD_PREP(FIFOSIZE_STARTADDR_MASK,
+				  rx_fifo_sz + np_tx_fifo_sz + tx_fifo_sz * i),
+		       &reg->global_regs.dptxfsizn[i]);
 	}
 	/* Flush the RX FIFO */
-	writel(RX_FIFO_FLUSH, &reg->global_regs.grstctl);
-	while (readl(&reg->global_regs.grstctl) & RX_FIFO_FLUSH)
+	writel(GRSTCTL_RXFFLSH, &reg->global_regs.grstctl);
+	while (readl(&reg->global_regs.grstctl) & GRSTCTL_RXFFLSH)
 		debug("%s: waiting for DWC2_UDC_OTG_GRSTCTL\n", __func__);
 
 	/* Flush all the Tx FIFO's */
-	writel(TX_FIFO_FLUSH_ALL, &reg->global_regs.grstctl);
-	writel(TX_FIFO_FLUSH_ALL | TX_FIFO_FLUSH, &reg->global_regs.grstctl);
-	while (readl(&reg->global_regs.grstctl) & TX_FIFO_FLUSH)
+	writel(FIELD_PREP(GRSTCTL_TXFNUM_MASK, GRSTCTL_TXFNUM_ALL), &reg->global_regs.grstctl);
+	writel(FIELD_PREP(GRSTCTL_TXFNUM_MASK, GRSTCTL_TXFNUM_ALL) | GRSTCTL_TXFFLSH,
+	       &reg->global_regs.grstctl);
+	while (readl(&reg->global_regs.grstctl) & GRSTCTL_TXFFLSH)
 		debug("%s: waiting for DWC2_UDC_OTG_GRSTCTL\n", __func__);
 
 	/* 13. Clear NAK bit of EP0, EP1, EP2*/
 	/* For Slave mode*/
 	/* EP0: Control OUT */
-	writel(DEPCTL_EPDIS | DEPCTL_CNAK,
+	writel(DXEPCTL_EPDIS | DXEPCTL_CNAK,
 	       &reg->device_regs.out_endp[EP0_CON].doepctl);
 
 	/* 14. Initialize OTG Link Core.*/
@@ -1127,8 +1131,8 @@ static int dwc2_udc_otg_probe(struct udevice *dev)
 		if (plat->force_b_session_valid &&
 		    !plat->force_vbus_detection) {
 			/* Override VBUS detection: enable then value*/
-			setbits_le32(&usbotg_reg->global_regs.gotgctl, VB_VALOEN);
-			setbits_le32(&usbotg_reg->global_regs.gotgctl, VB_VALOVAL);
+			setbits_le32(&usbotg_reg->global_regs.gotgctl, GOTGCTL_VBVALOEN);
+			setbits_le32(&usbotg_reg->global_regs.gotgctl, GOTGCTL_VBVALOVAL);
 		} else {
 			/* Enable VBUS sensing */
 			setbits_le32(&usbotg_reg->global_regs.ggpio,
@@ -1137,9 +1141,9 @@ static int dwc2_udc_otg_probe(struct udevice *dev)
 		if (plat->force_b_session_valid) {
 			/* Override B session bits: enable then value */
 			setbits_le32(&usbotg_reg->global_regs.gotgctl,
-				     A_VALOEN | B_VALOEN);
+				     GOTGCTL_AVALOEN | GOTGCTL_BVALOEN);
 			setbits_le32(&usbotg_reg->global_regs.gotgctl,
-				     A_VALOVAL | B_VALOVAL);
+				     GOTGCTL_AVALOVAL | GOTGCTL_BVALOVAL);
 		} else {
 			/* Enable ID detection */
 			setbits_le32(&usbotg_reg->global_regs.ggpio,
@@ -1205,10 +1209,10 @@ U_BOOT_DRIVER(dwc2_udc_otg) = {
 int dwc2_udc_B_session_valid(struct udevice *dev)
 {
 	struct dwc2_plat_otg_data *plat = dev_get_plat(dev);
-	struct dwc2_usbotg_reg *usbotg_reg =
-		(struct dwc2_usbotg_reg *)plat->regs_otg;
+	struct dwc2_core_regs *usbotg_reg =
+		(struct dwc2_core_regs *)plat->regs_otg;
 
-	return readl(&usbotg_reg->gotgctl) & B_SESSION_VALID;
+	return readl(&usbotg_reg->global_regs.gotgctl) & GOTGCTL_BSESVLD;
 }
 #else
 int dm_usb_gadget_handle_interrupts(struct udevice *dev)
diff --git a/drivers/usb/gadget/dwc2_udc_otg_regs.h b/drivers/usb/gadget/dwc2_udc_otg_regs.h
index 34b1c15ea17..6aec55970db 100644
--- a/drivers/usb/gadget/dwc2_udc_otg_regs.h
+++ b/drivers/usb/gadget/dwc2_udc_otg_regs.h
@@ -22,54 +22,53 @@ struct dwc2_usbotg_phy {
 /*definitions related to CSR setting */
 
 /* DWC2_UDC_OTG_GOTGCTL */
-#define B_SESSION_VALID			BIT(19)
-#define A_SESSION_VALID			BIT(18)
-#define B_VALOVAL			BIT(7)
-#define B_VALOEN			BIT(6)
-#define A_VALOVAL			BIT(5)
-#define A_VALOEN			BIT(4)
-#define VB_VALOVAL			BIT(3)
-#define VB_VALOEN			BIT(2)
+#define GOTGCTL_BSESVLD			BIT(19)
+#define GOTGCTL_ASESVLD			BIT(18)
+#define GOTGCTL_BVALOVAL		BIT(7)
+#define GOTGCTL_BVALOEN			BIT(6)
+#define GOTGCTL_AVALOVAL		BIT(5)
+#define GOTGCTL_AVALOEN			BIT(4)
+#define GOTGCTL_VBVALOVAL		BIT(3)
+#define GOTGCTL_VBVALOEN		BIT(2)
 
 /* DWC2_UDC_OTG_GOTINT */
 #define GOTGINT_SES_END_DET		BIT(2)
 
 /* DWC2_UDC_OTG_GAHBCFG */
-#define PTXFE_HALF			(0 << 8)
-#define PTXFE_ZERO			(1 << 8)
-#define NPTXFE_HALF			(0 << 7)
-#define NPTXFE_ZERO			(1 << 7)
-#define MODE_SLAVE			(0 << 5)
-#define MODE_DMA			(1 << 5)
-#define BURST_SINGLE			(0 << 1)
-#define BURST_INCR			(1 << 1)
-#define BURST_INCR4			(3 << 1)
-#define BURST_INCR8			(5 << 1)
-#define BURST_INCR16			(7 << 1)
-#define GBL_INT_UNMASK			(1 << 0)
-#define GBL_INT_MASK			(0 << 0)
+#define GAHBCFG_AHB_SINGLE		BIT(23)
+#define GAHBCFG_NOTI_ALL_DMA_WRIT	BIT(22)
+#define GAHBCFG_REM_MEM_SUPP		BIT(21)
+#define GAHBCFG_P_TXF_EMP_LVL		BIT(8)
+#define GAHBCFG_NP_TXF_EMP_LVL		BIT(7)
+#define GAHBCFG_DMA_EN			BIT(5)
+#define GAHBCFG_HBSTLEN_MASK		GENMASK(4, 1)
+#define GAHBCFG_HBSTLEN_SINGLE		0
+#define GAHBCFG_HBSTLEN_INCR		1
+#define GAHBCFG_HBSTLEN_INCR4		3
+#define GAHBCFG_HBSTLEN_INCR8		5
+#define GAHBCFG_HBSTLEN_INCR16		7
+#define GAHBCFG_GLBL_INTR_EN		BIT(0)
 
 /* DWC2_UDC_OTG_GRSTCTL */
-#define AHB_MASTER_IDLE			BIT(31)
-#define CORE_SOFT_RESET			BIT(0)
+#define GRSTCTL_AHBIDLE			BIT(31)
+#define GRSTCTL_CSFTRST			BIT(0)
 
 /* DWC2_UDC_OTG_GINTSTS/DWC2_UDC_OTG_GINTMSK core interrupt register */
-#define INT_RESUME			BIT(31)
-#define INT_DISCONN			BIT(29)
-#define INT_CONN_ID_STS_CNG		BIT(28)
-#define INT_OUT_EP			BIT(19)
-#define INT_IN_EP			BIT(18)
-#define INT_ENUMDONE			BIT(13)
-#define INT_RESET			BIT(12)
-#define INT_SUSPEND			BIT(11)
-#define INT_EARLY_SUSPEND		BIT(10)
-#define INT_GOUTNakEff			BIT(7)
-#define INT_GINNakEff			BIT(6)
-#define INT_NP_TX_FIFO_EMPTY		BIT(5)
-#define INT_RX_FIFO_NOT_EMPTY		BIT(4)
-#define INT_SOF				BIT(3)
-#define INT_OTG				BIT(2)
-#define INT_HOST_MODE			BIT(1)
+#define GINTSTS_WKUPINT			BIT(31)
+#define GINTSTS_DISCONNINT		BIT(29)
+#define GINTSTS_CONIDSTSCHNG		BIT(28)
+#define GINTSTS_OEPINT			BIT(19)
+#define GINTSTS_IEPINT			BIT(18)
+#define GINTSTS_ENUMDONE		BIT(13)
+#define GINTSTS_USBRST			BIT(12)
+#define GINTSTS_USBSUSP			BIT(11)
+#define GINTSTS_ERLYSUSP		BIT(10)
+#define GINTSTS_NPTXFEMP		BIT(5)
+#define GINTSTS_RXFLVL			BIT(4)
+#define GINTSTS_SOF			BIT(3)
+#define GINTSTS_OTGINT			BIT(2)
+#define GINTSTS_MODEMIS			BIT(1)
+#define GINTSTS_CURMODE_HOST		BIT(0)
 
 #define FULL_SPEED_CONTROL_PKT_SIZE	8
 #define FULL_SPEED_BULK_PKT_SIZE	64
@@ -81,28 +80,18 @@ struct dwc2_usbotg_phy {
 #define NPTX_FIFO_SIZE			1024
 #define PTX_FIFO_SIZE			384
 
-#define DEPCTL_TXFNUM_0			(0x0 << 22)
-#define DEPCTL_TXFNUM_1			(0x1 << 22)
-#define DEPCTL_TXFNUM_2			(0x2 << 22)
-#define DEPCTL_TXFNUM_3			(0x3 << 22)
-#define DEPCTL_TXFNUM_4			(0x4 << 22)
+#define FIFOSIZE_DEPTH_MASK		GENMASK(31, 16)
+#define FIFOSIZE_STARTADDR_MASK		GENMASK(15, 0)
 
 /* Enumeration speed */
-#define USB_HIGH_30_60MHZ		(0x0 << 1)
-#define USB_FULL_30_60MHZ		(0x1 << 1)
-#define USB_LOW_6MHZ			(0x2 << 1)
-#define USB_FULL_48MHZ			(0x3 << 1)
-
-/* DWC2_UDC_OTG_GRXSTSP STATUS */
-#define OUT_PKT_RECEIVED		(0x2 << 17)
-#define OUT_TRANSFER_COMPLELTED		(0x3 << 17)
-#define SETUP_TRANSACTION_COMPLETED	(0x4 << 17)
-#define SETUP_PKT_RECEIVED		(0x6 << 17)
-#define GLOBAL_OUT_NAK			(0x1 << 17)
+#define DSTS_ENUMSPD_MASK		GENMASK(2, 1)
+#define DSTS_ENUMSPD_HS			0
+#define DSTS_ENUMSPD_FS			1
+#define DSTS_ENUMSPD_LS			2
 
 /* DWC2_UDC_OTG_DCTL device control register */
-#define NORMAL_OPERATION		BIT(0)
-#define SOFT_DISCONNECT			BIT(1)
+#define DCTL_SFTDISCON			BIT(1)
+#define DCTL_RMTWKUPSIG			BIT(0)
 
 /* DWC2_UDC_OTG_DAINT device all endpoint interrupt register */
 #define DAINT_OUTEP_MASK		GENMASK(31, 16)
@@ -110,44 +99,51 @@ struct dwc2_usbotg_phy {
 
 /* DWC2_UDC_OTG_DIEPCTL0/DOEPCTL0 device
    control IN/OUT endpoint 0 control register */
-#define DEPCTL_EPENA			BIT(31)
-#define DEPCTL_EPDIS			BIT(30)
-#define DEPCTL_SETD1PID			BIT(29)
-#define DEPCTL_SETD0PID			BIT(28)
-#define DEPCTL_SNAK			BIT(27)
-#define DEPCTL_CNAK			BIT(26)
-#define DEPCTL_STALL			BIT(21)
-#define DEPCTL_TYPE_MASK		GENMASK(19, 18)
-#define DEPCTL_CTRL_TYPE		(0x0 << 18)
-#define DEPCTL_ISO_TYPE			(0x1 << 18)
-#define DEPCTL_BULK_TYPE		(0x2 << 18)
-#define DEPCTL_INTR_TYPE		(0x3 << 18)
-#define DEPCTL_USBACTEP			BIT(15)
-#define DEPCTL_NEXT_EP_MASK		GENMASK(14, 11)
-#define DEPCTL_MPS_MASK			GENMASK(10, 0)
-
-#define DEPCTL0_MPS_64			(0x0 << 0)
-#define DEPCTL0_MPS_32			(0x1 << 0)
-#define DEPCTL0_MPS_16			(0x2 << 0)
-#define DEPCTL0_MPS_8			(0x3 << 0)
-#define DEPCTL_MPS_BULK_512		(512 << 0)
-#define DEPCTL_MPS_INT_MPS_16		(16 << 0)
-
-#define DIEPCTL0_NEXT_EP_BIT		(11)
+#define DXEPCTL_EPENA			BIT(31)
+#define DXEPCTL_EPDIS			BIT(30)
+#define DXEPCTL_SETD1PID		BIT(29)
+#define DXEPCTL_SETODDFR		BIT(29)
+#define DXEPCTL_SETD0PID		BIT(28)
+#define DXEPCTL_SETEVENFR		BIT(28)
+#define DXEPCTL_SNAK			BIT(27)
+#define DXEPCTL_CNAK			BIT(26)
+#define DXEPCTL_STALL			BIT(21)
+#define DXEPCTL_EPTYPE_MASK		GENMASK(19, 18)
+#define DXEPCTL_EPTYPE_CONTROL		0
+#define DXEPCTL_EPTYPE_ISO		1
+#define DXEPCTL_EPTYPE_BULK		2
+#define DXEPCTL_EPTYPE_INTERRUPT	3
+#define DXEPCTL_EOFRNUM			BIT(16)
+#define DXEPCTL_USBACTEP		BIT(15)
+#define DXEPCTL_NEXTEP_MASK		GENMASK(14, 11)
+#define DXEPCTL_MPS_MASK		GENMASK(10, 0)
+
 
 /* DWC2_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint
    common interrupt mask register */
 /* DWC2_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */
-#define BACK2BACK_SETUP_RECEIVED	BIT(6)
-#define INTKNEPMIS			BIT(5)
-#define INTKN_TXFEMP			BIT(4)
-#define NON_ISO_IN_EP_TIMEOUT		BIT(3)
-#define CTRL_OUT_EP_SETUP_PHASE_DONE	BIT(3)
-#define AHB_ERROR			BIT(2)
-#define EPDISBLD			BIT(1)
-#define TRANSFER_DONE			BIT(0)
-
-#define USB_PHY_CTRL_EN0		BIT(0)
+#define DIEPMSK_NAKMSK			BIT(13)
+#define DIEPMSK_BNAININTRMSK		BIT(9)
+#define DIEPMSK_TXFIFOUNDRNMSK		BIT(8)
+#define DIEPMSK_TXFIFOEMPTY		BIT(7)
+#define DIEPMSK_INEPNAKEFFMSK		BIT(6)
+#define DIEPMSK_INTKNEPMISMSK		BIT(5)
+#define DIEPMSK_INTKNTXFEMPMSK		BIT(4)
+#define DIEPMSK_TIMEOUTMSK		BIT(3)
+#define DIEPMSK_AHBERRMSK		BIT(2)
+#define DIEPMSK_EPDISBLDMSK		BIT(1)
+#define DIEPMSK_XFERCOMPLMSK		BIT(0)
+
+#define DOEPMSK_BNAMSK			BIT(9)
+#define DOEPMSK_BACK2BACKSETUP		BIT(6)
+#define DOEPMSK_STSPHSERCVDMSK		BIT(5)
+#define DOEPMSK_OUTTKNEPDISMSK		BIT(4)
+#define DOEPMSK_SETUPMSK		BIT(3)
+#define DOEPMSK_AHBERRMSK		BIT(2)
+#define DOEPMSK_EPDISBLDMSK		BIT(1)
+#define DOEPMSK_XFERCOMPLMSK		BIT(0)
+
+#define USB_PHY_CTRL_EN0                BIT(0)
 
 /* OPHYPWR */
 #define PHY_0_SLEEP			BIT(5)
@@ -176,47 +172,46 @@ struct dwc2_usbotg_phy {
 #define EXYNOS4X12_CLK_SEL_24MHZ	(0x05 << 0)
 
 /* Device Configuration Register DCFG */
-#define DEV_SPEED_HIGH_SPEED_20		(0x0 << 0)
-#define DEV_SPEED_FULL_SPEED_20		(0x1 << 0)
-#define DEV_SPEED_LOW_SPEED_11		(0x2 << 0)
-#define DEV_SPEED_FULL_SPEED_11		(0x3 << 0)
-#define EP_MISS_CNT(x)			((x) << 18)
-#define DEVICE_ADDRESS(x)		((x) << 4)
+#define DCFG_EPMISCNT_MASK		GENMASK(22, 18)
+#define DCFG_DEVADDR_MASK		GENMASK(10, 4)
+#define DCFG_DEVSPD_MASK		GENMASK(1, 0)
+#define DCFG_DEVSPD_HS			0
+#define DCFG_DEVSPD_FS			1
+#define DCFG_DEVSPD_LS			2
+#define DCFG_DEVSPD_FS48		3
 
 /* Core Reset Register (GRSTCTL) */
-#define TX_FIFO_FLUSH			BIT(5)
-#define RX_FIFO_FLUSH			BIT(4)
-#define TX_FIFO_NUMBER(x)		((x) << 6)
-#define TX_FIFO_FLUSH_ALL		TX_FIFO_NUMBER(0x10)
+#define GRSTCTL_TXFNUM_MASK		GENMASK(10, 6)
+#define GRSTCTL_TXFFLSH			BIT(5)
+#define GRSTCTL_RXFFLSH			BIT(4)
+#define GRSTCTL_TXFNUM_ALL		0x10
 
 /* Masks definitions */
-#define GINTMSK_INIT	(INT_OUT_EP | INT_IN_EP | INT_RESUME | INT_ENUMDONE\
-			| INT_RESET | INT_SUSPEND | INT_OTG)
-#define DOEPMSK_INIT	(CTRL_OUT_EP_SETUP_PHASE_DONE | AHB_ERROR|TRANSFER_DONE)
-#define DIEPMSK_INIT	(NON_ISO_IN_EP_TIMEOUT|AHB_ERROR|TRANSFER_DONE)
-#define GAHBCFG_INIT	(PTXFE_HALF | NPTXFE_HALF | MODE_DMA | BURST_INCR4\
-			| GBL_INT_UNMASK)
-
-/* Device Endpoint X Transfer Size Register (DIEPTSIZX) */
-#define DIEPT_SIZ_PKT_CNT(x)		((x) << 19)
-#define DIEPT_SIZ_XFER_SIZE(x)		((x) << 0)
-
-/* Device OUT Endpoint X Transfer Size Register (DOEPTSIZX) */
-#define DOEPT_SIZ_PKT_CNT(x)		((x) << 19)
-#define DOEPT_SIZ_XFER_SIZE(x)		((x) << 0)
-#define DOEPT_SIZ_XFER_SIZE_MAX_EP0	(0x7F << 0)
-#define DOEPT_SIZ_XFER_SIZE_MAX_EP	(0x7FFF << 0)
+#define GINTMSK_INIT	(GINTSTS_WKUPINT | GINTSTS_OEPINT | GINTSTS_IEPINT | GINTSTS_ENUMDONE | \
+			 GINTSTS_USBRST | GINTSTS_USBSUSP | GINTSTS_OTGINT)
+#define DOEPMSK_INIT	(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | DOEPMSK_XFERCOMPLMSK)
+#define DIEPMSK_INIT	(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | DIEPMSK_XFERCOMPLMSK)
+#define GAHBCFG_INIT	(GAHBCFG_DMA_EN | \
+			 FIELD_PREP(GAHBCFG_HBSTLEN_MASK, GAHBCFG_HBSTLEN_INCR4) | \
+			 GAHBCFG_GLBL_INTR_EN)
+
+/* Device Endpoint X Transfer Size Register (DIEPTSIZX/DOEPTSIZX) */
+#define DIEPTSIZ0_PKTCNT_MASK		GENMASK(20, 19)
+#define DIEPTSIZ0_XFERSIZE_MASK		GENMASK(6, 0)
+
+#define DOEPTSIZ0_SUPCNT_MASK		GENMASK(30, 29)
+#define DOEPTSIZ0_PKTCNT		BIT(19)
+#define DOEPTSIZ0_XFERSIZE_MASK		GENMASK(6, 0)
+
+#define DXEPTSIZ_MC_MASK		GENMASK(30, 29)
+#define DXEPTSIZ_PKTCNT_MASK		GENMASK(28, 19)
+#define DXEPTSIZ_XFERSIZE_MASK		GENMASK(18, 0)
 
 /* Device Endpoint-N Control Register (DIEPCTLn/DOEPCTLn) */
-#define DIEPCTL_TX_FIFO_NUM_MASK	GENMASK(25, 22)
-
-/* Device ALL Endpoints Interrupt Register (DAINT) */
-#define DAINT_IN_EP_INT(x)		((x) << 0)
-#define DAINT_OUT_EP_INT(x)		((x) << 16)
+#define DXEPCTL_TXFNUM_MASK		GENMASK(25, 22)
 
 /* User HW Config4 */
-#define GHWCFG4_NUM_IN_EPS_MASK		(0xf << 26)
-#define GHWCFG4_NUM_IN_EPS_SHIFT	26
+#define GHWCFG4_NUM_IN_EPS_MASK		GENMASK(29, 26)
 
 /* OTG general core configuration register (OTG_GCCFG:0x38) for STM32MP1 */
 #define GGPIO_STM32_OTG_GCCFG_VBDEN	BIT(21)
diff --git a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
index ceefae1b1d1..64d2fe7bbde 100644
--- a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
+++ b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
@@ -35,10 +35,10 @@ static inline void dwc2_udc_ep0_zlp(struct dwc2_udc *dev)
 
 	writel(phys_to_bus((unsigned long)usb_ctrl_dma_addr),
 	       &reg->device_regs.in_endp[EP0_CON].diepdma);
-	writel(DIEPT_SIZ_PKT_CNT(1), &reg->device_regs.in_endp[EP0_CON].dieptsiz);
+	writel(FIELD_PREP(DXEPTSIZ_PKTCNT_MASK, 1), &reg->device_regs.in_endp[EP0_CON].dieptsiz);
 
 	ep_ctrl = readl(&reg->device_regs.in_endp[EP0_CON].diepctl);
-	writel(ep_ctrl | DEPCTL_EPENA | DEPCTL_CNAK,
+	writel(ep_ctrl | DXEPCTL_EPENA | DXEPCTL_CNAK,
 	       &reg->device_regs.in_endp[EP0_CON].diepctl);
 
 	debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
@@ -53,13 +53,13 @@ static void dwc2_udc_pre_setup(void)
 	debug_cond(DEBUG_IN_EP,
 		   "%s : Prepare Setup packets.\n", __func__);
 
-	writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
+	writel(FIELD_PREP(DXEPTSIZ_PKTCNT_MASK, 1) | sizeof(struct usb_ctrlrequest),
 	       &reg->device_regs.out_endp[EP0_CON].doeptsiz);
 	writel(phys_to_bus((unsigned long)usb_ctrl_dma_addr),
 	       &reg->device_regs.out_endp[EP0_CON].doepdma);
 
 	ep_ctrl = readl(&reg->device_regs.out_endp[EP0_CON].doepctl);
-	writel(ep_ctrl | DEPCTL_EPENA, &reg->device_regs.out_endp[EP0_CON].doepctl);
+	writel(ep_ctrl | DXEPCTL_EPENA, &reg->device_regs.out_endp[EP0_CON].doepctl);
 
 	debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
 		__func__, readl(&reg->device_regs.in_endp[EP0_CON].diepctl));
@@ -80,13 +80,13 @@ static inline void dwc2_ep0_complete_out(void)
 	debug_cond(DEBUG_IN_EP,
 		"%s : Prepare Complete Out packet.\n", __func__);
 
-	writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
+	writel(FIELD_PREP(DXEPTSIZ_PKTCNT_MASK, 1) | sizeof(struct usb_ctrlrequest),
 	       &reg->device_regs.out_endp[EP0_CON].doeptsiz);
 	writel(phys_to_bus((unsigned long)usb_ctrl_dma_addr),
 	       &reg->device_regs.out_endp[EP0_CON].doepdma);
 
 	ep_ctrl = readl(&reg->device_regs.out_endp[EP0_CON].doepctl);
-	writel(ep_ctrl | DEPCTL_EPENA | DEPCTL_CNAK,
+	writel(ep_ctrl | DXEPCTL_EPENA | DXEPCTL_CNAK,
 	       &reg->device_regs.out_endp[EP0_CON].doepctl);
 
 	debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
@@ -121,9 +121,10 @@ static int setdma_rx(struct dwc2_ep *ep, struct dwc2_request *req)
 				ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
 
 	writel(phys_to_bus((unsigned long)ep->dma_buf), &reg->device_regs.out_endp[ep_num].doepdma);
-	writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
+	writel(FIELD_PREP(DXEPTSIZ_PKTCNT_MASK, pktcnt) |
+	       FIELD_PREP(DXEPTSIZ_XFERSIZE_MASK, length),
 	       &reg->device_regs.out_endp[ep_num].doeptsiz);
-	writel(DEPCTL_EPENA | DEPCTL_CNAK | ctrl, &reg->device_regs.out_endp[ep_num].doepctl);
+	writel(DXEPCTL_EPENA | DXEPCTL_CNAK | ctrl, &reg->device_regs.out_endp[ep_num].doepctl);
 
 	debug_cond(DEBUG_OUT_EP != 0,
 		   "%s: EP%d RX DMA start : DOEPDMA = 0x%x,"
@@ -163,25 +164,27 @@ static int setdma_tx(struct dwc2_ep *ep, struct dwc2_request *req)
 		pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
 
 	/* Flush the endpoint's Tx FIFO */
-	writel(TX_FIFO_NUMBER(ep->fifo_num), &reg->global_regs.grstctl);
-	writel(TX_FIFO_NUMBER(ep->fifo_num) | TX_FIFO_FLUSH, &reg->global_regs.grstctl);
-	while (readl(&reg->global_regs.grstctl) & TX_FIFO_FLUSH)
+	writel(FIELD_PREP(GRSTCTL_TXFNUM_MASK, ep->fifo_num), &reg->global_regs.grstctl);
+	writel(FIELD_PREP(GRSTCTL_TXFNUM_MASK, ep->fifo_num) | GRSTCTL_TXFFLSH,
+	       &reg->global_regs.grstctl);
+	while (readl(&reg->global_regs.grstctl) & GRSTCTL_TXFFLSH)
 		;
 
 	writel(phys_to_bus((unsigned long)ep->dma_buf), &reg->device_regs.in_endp[ep_num].diepdma);
-	writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
+	writel(FIELD_PREP(DXEPTSIZ_PKTCNT_MASK, pktcnt) |
+	       FIELD_PREP(DXEPTSIZ_XFERSIZE_MASK, length),
 	       &reg->device_regs.in_endp[ep_num].dieptsiz);
 
 	ctrl = readl(&reg->device_regs.in_endp[ep_num].diepctl);
 
 	/* Write the FIFO number to be used for this endpoint */
-	ctrl &= ~DIEPCTL_TX_FIFO_NUM_MASK;
-	ctrl |= FIELD_PREP(DIEPCTL_TX_FIFO_NUM_MASK, ep->fifo_num);
+	ctrl &= ~DXEPCTL_TXFNUM_MASK;
+	ctrl |= FIELD_PREP(DXEPCTL_TXFNUM_MASK, ep->fifo_num);
 
 	/* Clear reserved (Next EP) bits */
-	ctrl &= ~DEPCTL_NEXT_EP_MASK;
+	ctrl &= ~DXEPCTL_NEXTEP_MASK;
 
-	writel(DEPCTL_EPENA | DEPCTL_CNAK | ctrl, &reg->device_regs.in_endp[ep_num].diepctl);
+	writel(DXEPCTL_EPENA | DXEPCTL_CNAK | ctrl, &reg->device_regs.in_endp[ep_num].diepctl);
 
 	debug_cond(DEBUG_IN_EP,
 		"%s:EP%d TX DMA start : DIEPDMA0 = 0x%x,"
@@ -214,9 +217,9 @@ static void complete_rx(struct dwc2_udc *dev, u8 ep_num)
 	ep_tsr = readl(&reg->device_regs.out_endp[ep_num].doeptsiz);
 
 	if (ep_num == EP0_CON)
-		xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP0);
+		xfer_size = FIELD_PREP(DIEPTSIZ0_XFERSIZE_MASK, ep_tsr);
 	else
-		xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP);
+		xfer_size = FIELD_PREP(DXEPTSIZ_XFERSIZE_MASK, ep_tsr);
 
 	xfer_size = ep->len - xfer_size;
 
@@ -384,7 +387,7 @@ static void process_ep_in_intr(struct dwc2_udc *dev)
 	ep_intr = FIELD_GET(DAINT_INEP_MASK, ep_intr);
 
 	while (ep_intr) {
-		if (ep_intr & DAINT_IN_EP_INT(1)) {
+		if (ep_intr & BIT(EP0_CON)) {
 			ep_intr_status = readl(&reg->device_regs.in_endp[ep_num].diepint);
 			debug_cond(DEBUG_IN_EP,
 				   "\tEP%d-IN : DIEPINT = 0x%x\n",
@@ -393,7 +396,7 @@ static void process_ep_in_intr(struct dwc2_udc *dev)
 			/* Interrupt Clear */
 			writel(ep_intr_status, &reg->device_regs.in_endp[ep_num].diepint);
 
-			if (ep_intr_status & TRANSFER_DONE) {
+			if (ep_intr_status & DIEPMSK_XFERCOMPLMSK) {
 				complete_tx(dev, ep_num);
 
 				if (ep_num == 0) {
@@ -445,10 +448,9 @@ static void process_ep_out_intr(struct dwc2_udc *dev)
 			writel(ep_intr_status, &reg->device_regs.out_endp[ep_num].doepint);
 
 			if (ep_num == 0) {
-				if (ep_intr_status & TRANSFER_DONE) {
+				if (ep_intr_status & DOEPMSK_XFERCOMPLMSK) {
 					ep_tsr = readl(&epsiz_reg);
-					xfer_size = ep_tsr &
-						   DOEPT_SIZ_XFER_SIZE_MAX_EP0;
+					xfer_size = ep_tsr & DOEPTSIZ0_XFERSIZE_MASK;
 
 					if (xfer_size == req_size &&
 					    dev->ep0state == WAIT_FOR_SETUP) {
@@ -462,14 +464,13 @@ static void process_ep_out_intr(struct dwc2_udc *dev)
 					}
 				}
 
-				if (ep_intr_status &
-				    CTRL_OUT_EP_SETUP_PHASE_DONE) {
+				if (ep_intr_status & DOEPMSK_SETUPMSK) {
 					debug_cond(DEBUG_OUT_EP != 0,
 						   "SETUP packet arrived\n");
 					dwc2_handle_ep0(dev);
 				}
 			} else {
-				if (ep_intr_status & TRANSFER_DONE)
+				if (ep_intr_status & DOEPMSK_XFERCOMPLMSK)
 					complete_rx(dev, ep_num);
 			}
 		}
@@ -504,13 +505,13 @@ static int dwc2_udc_irq(int irq, void *_dev)
 		return IRQ_HANDLED;
 	}
 
-	if (intr_status & INT_ENUMDONE) {
+	if (intr_status & GINTSTS_ENUMDONE) {
 		debug_cond(DEBUG_ISR, "\tSpeed Detection interrupt\n");
 
-		writel(INT_ENUMDONE, &reg->global_regs.gintsts);
-		usb_status = (readl(&reg->device_regs.dsts) & 0x6);
+		writel(GINTSTS_ENUMDONE, &reg->global_regs.gintsts);
+		usb_status = FIELD_GET(DSTS_ENUMSPD_MASK, readl(&reg->device_regs.dsts));
 
-		if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) {
+		if (usb_status != DSTS_ENUMSPD_HS) {
 			debug_cond(DEBUG_ISR,
 				   "\t\tFull Speed Detection\n");
 			set_max_pktsize(dev, USB_SPEED_FULL);
@@ -523,16 +524,16 @@ static int dwc2_udc_irq(int irq, void *_dev)
 		}
 	}
 
-	if (intr_status & INT_EARLY_SUSPEND) {
+	if (intr_status & GINTSTS_ERLYSUSP) {
 		debug_cond(DEBUG_ISR, "\tEarly suspend interrupt\n");
-		writel(INT_EARLY_SUSPEND, &reg->global_regs.gintsts);
+		writel(GINTSTS_ERLYSUSP, &reg->global_regs.gintsts);
 	}
 
-	if (intr_status & INT_SUSPEND) {
+	if (intr_status & GINTSTS_USBSUSP) {
 		usb_status = readl(&reg->device_regs.dsts);
 		debug_cond(DEBUG_ISR,
 			"\tSuspend interrupt :(DSTS):0x%x\n", usb_status);
-		writel(INT_SUSPEND, &reg->global_regs.gintsts);
+		writel(GINTSTS_USBSUSP, &reg->global_regs.gintsts);
 
 		if (dev->gadget.speed != USB_SPEED_UNKNOWN
 		    && dev->driver) {
@@ -541,7 +542,7 @@ static int dwc2_udc_irq(int irq, void *_dev)
 		}
 	}
 
-	if (intr_status & INT_OTG) {
+	if (intr_status & GINTSTS_OTGINT) {
 		gotgint = readl(&reg->global_regs.gotgint);
 		debug_cond(DEBUG_ISR,
 			   "\tOTG interrupt: (GOTGINT):0x%x\n", gotgint);
@@ -558,9 +559,9 @@ static int dwc2_udc_irq(int irq, void *_dev)
 		writel(gotgint, &reg->global_regs.gotgint);
 	}
 
-	if (intr_status & INT_RESUME) {
+	if (intr_status & GINTSTS_WKUPINT) {
 		debug_cond(DEBUG_ISR, "\tResume interrupt\n");
-		writel(INT_RESUME, &reg->global_regs.gintsts);
+		writel(GINTSTS_WKUPINT, &reg->global_regs.gintsts);
 
 		if (dev->gadget.speed != USB_SPEED_UNKNOWN
 		    && dev->driver
@@ -570,13 +571,13 @@ static int dwc2_udc_irq(int irq, void *_dev)
 		}
 	}
 
-	if (intr_status & INT_RESET) {
+	if (intr_status & GINTSTS_USBRST) {
 		usb_status = readl(&reg->global_regs.gotgctl);
 		debug_cond(DEBUG_ISR,
 			"\tReset interrupt - (GOTGCTL):0x%x\n", usb_status);
-		writel(INT_RESET, &reg->global_regs.gintsts);
+		writel(GINTSTS_USBRST, &reg->global_regs.gintsts);
 
-		if ((usb_status & 0xc0000) == (0x3 << 18)) {
+		if (usb_status & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) {
 			if (reset_available) {
 				debug_cond(DEBUG_ISR,
 					"\t\tOTG core got reset (%d)!!\n",
@@ -595,10 +596,10 @@ static int dwc2_udc_irq(int irq, void *_dev)
 		}
 	}
 
-	if (intr_status & INT_IN_EP)
+	if (intr_status & GINTSTS_IEPINT)
 		process_ep_in_intr(dev);
 
-	if (intr_status & INT_OUT_EP)
+	if (intr_status & GINTSTS_OEPINT)
 		process_ep_out_intr(dev);
 
 	spin_unlock_irqrestore(&dev->lock, flags);
@@ -770,7 +771,8 @@ static int dwc2_fifo_read(struct dwc2_ep *ep, void *cp, int max)
 static void udc_set_address(struct dwc2_udc *dev, unsigned char address)
 {
 	u32 ctrl = readl(&reg->device_regs.dcfg);
-	writel(DEVICE_ADDRESS(address) | ctrl, &reg->device_regs.dcfg);
+
+	writel(FIELD_PREP(DCFG_DEVADDR_MASK, address) | ctrl, &reg->device_regs.dcfg);
 
 	dwc2_udc_ep0_zlp(dev);
 
@@ -790,10 +792,10 @@ static inline void dwc2_udc_ep0_set_stall(struct dwc2_ep *ep)
 	ep_ctrl = readl(&reg->device_regs.in_endp[EP0_CON].diepctl);
 
 	/* set the disable and stall bits */
-	if (ep_ctrl & DEPCTL_EPENA)
-		ep_ctrl |= DEPCTL_EPDIS;
+	if (ep_ctrl & DXEPCTL_EPENA)
+		ep_ctrl |= DXEPCTL_EPDIS;
 
-	ep_ctrl |= DEPCTL_STALL;
+	ep_ctrl |= DXEPCTL_STALL;
 
 	writel(ep_ctrl, &reg->device_regs.in_endp[EP0_CON].diepctl);
 
@@ -939,11 +941,11 @@ static int dwc2_udc_get_status(struct dwc2_udc *dev,
 			   ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE));
 
 	writel(phys_to_bus(usb_ctrl_dma_addr), &reg->device_regs.in_endp[EP0_CON].diepdma);
-	writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
+	writel(FIELD_PREP(DXEPTSIZ_PKTCNT_MASK, 1) | FIELD_PREP(DXEPTSIZ_XFERSIZE_MASK, 2),
 	       &reg->device_regs.in_endp[EP0_CON].dieptsiz);
 
 	ep_ctrl = readl(&reg->device_regs.in_endp[EP0_CON].diepctl);
-	writel(ep_ctrl | DEPCTL_EPENA | DEPCTL_CNAK,
+	writel(ep_ctrl | DXEPCTL_EPENA | DXEPCTL_CNAK,
 	       &reg->device_regs.in_endp[EP0_CON].diepctl);
 	dev->ep0state = WAIT_FOR_NULL_COMPLETE;
 
@@ -960,13 +962,13 @@ static void dwc2_udc_set_nak(struct dwc2_ep *ep)
 
 	if (ep_is_in(ep)) {
 		ep_ctrl = readl(&reg->device_regs.in_endp[ep_num].diepctl);
-		ep_ctrl |= DEPCTL_SNAK;
+		ep_ctrl |= DXEPCTL_SNAK;
 		writel(ep_ctrl, &reg->device_regs.in_endp[ep_num].diepctl);
 		debug("%s: set NAK, DIEPCTL%d = 0x%x\n",
 			__func__, ep_num, readl(&reg->device_regs.in_endp[ep_num].diepctl));
 	} else {
 		ep_ctrl = readl(&reg->device_regs.out_endp[ep_num].doepctl);
-		ep_ctrl |= DEPCTL_SNAK;
+		ep_ctrl |= DXEPCTL_SNAK;
 		writel(ep_ctrl, &reg->device_regs.out_endp[ep_num].doepctl);
 		debug("%s: set NAK, DOEPCTL%d = 0x%x\n",
 		      __func__, ep_num, readl(&reg->device_regs.out_endp[ep_num].doepctl));
@@ -987,10 +989,10 @@ static void dwc2_udc_ep_set_stall(struct dwc2_ep *ep)
 		ep_ctrl = readl(&reg->device_regs.in_endp[ep_num].diepctl);
 
 		/* set the disable and stall bits */
-		if (ep_ctrl & DEPCTL_EPENA)
-			ep_ctrl |= DEPCTL_EPDIS;
+		if (ep_ctrl & DXEPCTL_EPENA)
+			ep_ctrl |= DXEPCTL_EPDIS;
 
-		ep_ctrl |= DEPCTL_STALL;
+		ep_ctrl |= DXEPCTL_STALL;
 
 		writel(ep_ctrl, &reg->device_regs.in_endp[ep_num].diepctl);
 		debug("%s: set stall, DIEPCTL%d = 0x%x\n",
@@ -1000,7 +1002,7 @@ static void dwc2_udc_ep_set_stall(struct dwc2_ep *ep)
 		ep_ctrl = readl(&reg->device_regs.out_endp[ep_num].doepctl);
 
 		/* set the stall bit */
-		ep_ctrl |= DEPCTL_STALL;
+		ep_ctrl |= DXEPCTL_STALL;
 
 		writel(ep_ctrl, &reg->device_regs.out_endp[ep_num].doepctl);
 		debug("%s: set stall, DOEPCTL%d = 0x%x\n",
@@ -1022,7 +1024,7 @@ static void dwc2_udc_ep_clear_stall(struct dwc2_ep *ep)
 		ep_ctrl = readl(&reg->device_regs.in_endp[ep_num].diepctl);
 
 		/* clear stall bit */
-		ep_ctrl &= ~DEPCTL_STALL;
+		ep_ctrl &= ~DXEPCTL_STALL;
 
 		/*
 		 * USB Spec 9.4.5: For endpoints using data toggle, regardless
@@ -1032,7 +1034,7 @@ static void dwc2_udc_ep_clear_stall(struct dwc2_ep *ep)
 		 */
 		if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
 		    || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
-			ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
+			ep_ctrl |= DXEPCTL_SETD0PID; /* DATA0 */
 		}
 
 		writel(ep_ctrl, &reg->device_regs.in_endp[ep_num].diepctl);
@@ -1043,11 +1045,11 @@ static void dwc2_udc_ep_clear_stall(struct dwc2_ep *ep)
 		ep_ctrl = readl(&reg->device_regs.out_endp[ep_num].doepctl);
 
 		/* clear stall bit */
-		ep_ctrl &= ~DEPCTL_STALL;
+		ep_ctrl &= ~DXEPCTL_STALL;
 
 		if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
 		    || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
-			ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
+			ep_ctrl |= DXEPCTL_SETD0PID; /* DATA0 */
 		}
 
 		writel(ep_ctrl, &reg->device_regs.out_endp[ep_num].doepctl);
@@ -1126,12 +1128,12 @@ static void dwc2_udc_ep_activate(struct dwc2_ep *ep)
 
 	/* If the EP is already active don't change the EP Control
 	 * register. */
-	if (!(ep_ctrl & DEPCTL_USBACTEP)) {
-		ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) |
-			FIELD_PREP(DEPCTL_TYPE_MASK, ep->bmAttributes);
-		ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) |
-			FIELD_PREP(DEPCTL_MPS_MASK, ep->ep.maxpacket);
-		ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK);
+	if (!(ep_ctrl & DXEPCTL_USBACTEP)) {
+		ep_ctrl = (ep_ctrl & ~DXEPCTL_EPTYPE_MASK) |
+			FIELD_PREP(DXEPCTL_EPTYPE_MASK, ep->bmAttributes);
+		ep_ctrl = (ep_ctrl & ~DXEPCTL_MPS_MASK) |
+			FIELD_PREP(DXEPCTL_MPS_MASK, ep->ep.maxpacket);
+		ep_ctrl |= (DXEPCTL_SETD0PID | DXEPCTL_USBACTEP | DXEPCTL_SNAK);
 
 		if (ep_is_in(ep)) {
 			writel(ep_ctrl, &reg->device_regs.in_endp[ep_num].diepctl);