usb: dwc2: Extract macro definitions to common header

Some macros are shared between host and gadget code, causing duplicated
definitions. Move DWC2 macro definitions from host and gadget code into a
common header to reduce duplication.

Signed-off-by: Kongyang Liu <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Tested-by: Peter Robinson <[email protected]>
Signed-off-by: Junhui Liu <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mattijs Korpershoek <[email protected]>

1 files changed, 0 insertions, 291 deletions

diff --git a/drivers/usb/host/dwc2.h b/drivers/usb/host/dwc2.h
index a01edc5eff3..f0bb2949649 100644
--- a/drivers/usb/host/dwc2.h
+++ b/drivers/usb/host/dwc2.h
@@ -6,297 +6,6 @@
 #ifndef __DWC2_H__
 #define __DWC2_H__
 
-#include <linux/bitops.h>
-
-#define GOTGCTL_CHIRPEN				BIT(27)
-#define GOTGCTL_MULT_VALID_BC_MASK		GENMASK(26, 22)
-#define GOTGCTL_CURMODE_HOST			BIT(21)
-#define GOTGCTL_OTGVER				BIT(20)
-#define GOTGCTL_BSESVLD				BIT(19)
-#define GOTGCTL_ASESVLD				BIT(18)
-#define GOTGCTL_DBNC_SHORT			BIT(17)
-#define GOTGCTL_CONID_B				BIT(16)
-#define GOTGCTL_DBNCE_FLTR_BYPASS		BIT(15)
-#define GOTGCTL_DEVHNPEN			BIT(11)
-#define GOTGCTL_HSTSETHNPEN			BIT(10)
-#define GOTGCTL_HNPREQ				BIT(9)
-#define GOTGCTL_HSTNEGSCS			BIT(8)
-#define GOTGCTL_BVALOVAL			BIT(7)
-#define GOTGCTL_BVALOEN				BIT(6)
-#define GOTGCTL_AVALOVAL			BIT(5)
-#define GOTGCTL_AVALOEN				BIT(4)
-#define GOTGCTL_VBVALOVAL			BIT(3)
-#define GOTGCTL_VBVALOEN			BIT(2)
-#define GOTGCTL_SESREQ				BIT(1)
-#define GOTGCTL_SESREQSCS			BIT(0)
-
-#define GOTGINT_DBNCE_DONE			BIT(19)
-#define GOTGINT_A_DEV_TOUT_CHG			BIT(18)
-#define GOTGINT_HST_NEG_DET			BIT(17)
-#define GOTGINT_HST_NEG_SUC_STS_CHNG		BIT(9)
-#define GOTGINT_SES_REQ_SUC_STS_CHNG		BIT(8)
-#define GOTGINT_SES_END_DET			BIT(2)
-
-#define GAHBCFG_AHB_SINGLE			BIT(23)
-#define GAHBCFG_NOTI_ALL_DMA_WRIT		BIT(22)
-#define GAHBCFG_REM_MEM_SUPP			BIT(21)
-#define GAHBCFG_P_TXF_EMP_LVL			BIT(8)
-#define GAHBCFG_NP_TXF_EMP_LVL			BIT(7)
-#define GAHBCFG_DMA_EN				BIT(5)
-#define GAHBCFG_HBSTLEN_MASK			GENMASK(4, 1)
-#define GAHBCFG_HBSTLEN_SINGLE			0
-#define GAHBCFG_HBSTLEN_INCR			1
-#define GAHBCFG_HBSTLEN_INCR4			3
-#define GAHBCFG_HBSTLEN_INCR8			5
-#define GAHBCFG_HBSTLEN_INCR16			7
-#define GAHBCFG_GLBL_INTR_EN			BIT(0)
-#define GAHBCFG_CTRL_MASK			(GAHBCFG_P_TXF_EMP_LVL | \
-						 GAHBCFG_NP_TXF_EMP_LVL | \
-						 GAHBCFG_DMA_EN | \
-						 GAHBCFG_GLBL_INTR_EN)
-
-#define GUSBCFG_FORCEDEVMODE			BIT(30)
-#define GUSBCFG_FORCEHOSTMODE			BIT(29)
-#define GUSBCFG_TXENDDELAY			BIT(28)
-#define GUSBCFG_ICTRAFFICPULLREMOVE		BIT(27)
-#define GUSBCFG_ICUSBCAP			BIT(26)
-#define GUSBCFG_ULPI_INT_PROT_DIS		BIT(25)
-#define GUSBCFG_INDICATORPASSTHROUGH		BIT(24)
-#define GUSBCFG_INDICATORCOMPLEMENT		BIT(23)
-#define GUSBCFG_TERMSELDLPULSE			BIT(22)
-#define GUSBCFG_ULPI_INT_VBUS_IND		BIT(21)
-#define GUSBCFG_ULPI_EXT_VBUS_DRV		BIT(20)
-#define GUSBCFG_ULPI_CLK_SUSP_M			BIT(19)
-#define GUSBCFG_ULPI_AUTO_RES			BIT(18)
-#define GUSBCFG_ULPI_FS_LS			BIT(17)
-#define GUSBCFG_OTG_UTMI_FS_SEL			BIT(16)
-#define GUSBCFG_PHY_LP_CLK_SEL			BIT(15)
-#define GUSBCFG_USBTRDTIM_MASK			GENMASK(14, 10)
-#define GUSBCFG_HNPCAP				BIT(9)
-#define GUSBCFG_SRPCAP				BIT(8)
-#define GUSBCFG_DDRSEL				BIT(7)
-#define GUSBCFG_PHYSEL				BIT(6)
-#define GUSBCFG_FSINTF				BIT(5)
-#define GUSBCFG_ULPI_UTMI_SEL			BIT(4)
-#define GUSBCFG_PHYIF16				BIT(3)
-#define GUSBCFG_TOUTCAL_MASK			GENMASK(2, 0)
-
-#define GRSTCTL_AHBIDLE				BIT(31)
-#define GRSTCTL_DMAREQ				BIT(30)
-#define GRSTCTL_CSFTRST_DONE			BIT(29)
-#define GRSTCTL_TXFNUM_MASK			GENMASK(10, 6)
-#define GRSTCTL_TXFFLSH				BIT(5)
-#define GRSTCTL_RXFFLSH				BIT(4)
-#define GRSTCTL_IN_TKNQ_FLSH			BIT(3)
-#define GRSTCTL_FRMCNTRRST			BIT(2)
-#define GRSTCTL_HSFTRST				BIT(1)
-#define GRSTCTL_CSFTRST				BIT(0)
-#define GRSTCTL_TXFNUM_ALL			0x10
-
-#define GINTSTS_WKUPINT				BIT(31)
-#define GINTSTS_SESSREQINT			BIT(30)
-#define GINTSTS_DISCONNINT			BIT(29)
-#define GINTSTS_CONIDSTSCHNG			BIT(28)
-#define GINTSTS_LPMTRANRCVD			BIT(27)
-#define GINTSTS_PTXFEMP				BIT(26)
-#define GINTSTS_HCHINT				BIT(25)
-#define GINTSTS_PRTINT				BIT(24)
-#define GINTSTS_RESETDET			BIT(23)
-#define GINTSTS_FET_SUSP			BIT(22)
-#define GINTSTS_INCOMPL_IP			BIT(21)
-#define GINTSTS_INCOMPL_SOOUT			BIT(21)
-#define GINTSTS_INCOMPL_SOIN			BIT(20)
-#define GINTSTS_OEPINT				BIT(19)
-#define GINTSTS_IEPINT				BIT(18)
-#define GINTSTS_EPMIS				BIT(17)
-#define GINTSTS_RESTOREDONE			BIT(16)
-#define GINTSTS_EOPF				BIT(15)
-#define GINTSTS_ISOUTDROP			BIT(14)
-#define GINTSTS_ENUMDONE			BIT(13)
-#define GINTSTS_USBRST				BIT(12)
-#define GINTSTS_USBSUSP				BIT(11)
-#define GINTSTS_ERLYSUSP			BIT(10)
-#define GINTSTS_I2CINT				BIT(9)
-#define GINTSTS_ULPI_CK_INT			BIT(8)
-#define GINTSTS_GOUTNAKEFF			BIT(7)
-#define GINTSTS_GINNAKEFF			BIT(6)
-#define GINTSTS_NPTXFEMP			BIT(5)
-#define GINTSTS_RXFLVL				BIT(4)
-#define GINTSTS_SOF				BIT(3)
-#define GINTSTS_OTGINT				BIT(2)
-#define GINTSTS_MODEMIS				BIT(1)
-#define GINTSTS_CURMODE_HOST			BIT(0)
-
-#define FIFOSIZE_DEPTH_MASK			GENMASK(31, 16)
-#define FIFOSIZE_STARTADDR_MASK			GENMASK(15, 0)
-
-#define GI2CCTL_BSYDNE				BIT(31)
-#define GI2CCTL_RW				BIT(30)
-#define GI2CCTL_I2CDATSE0			BIT(28)
-#define GI2CCTL_I2CDEVADDR_MASK			GENMASK(27, 26)
-#define GI2CCTL_I2CSUSPCTL			BIT(25)
-#define GI2CCTL_ACK				BIT(24)
-#define GI2CCTL_I2CEN				BIT(23)
-#define GI2CCTL_ADDR_MASK			GENMASK(22, 16)
-#define GI2CCTL_REGADDR_MASK			GENMASK(15, 8)
-#define GI2CCTL_RWDATA_MASK			GENMASK(7, 0)
-
-#define GHWCFG2_OTG_ENABLE_IC_USB		BIT(31)
-#define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK		GENMASK(30, 26)
-#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK	GENMASK(25, 24)
-#define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK	GENMASK(23, 22)
-#define GHWCFG2_MULTI_PROC_INT			BIT(20)
-#define GHWCFG2_DYNAMIC_FIFO			BIT(19)
-#define GHWCFG2_PERIO_EP_SUPPORTED		BIT(18)
-#define GHWCFG2_NUM_HOST_CHAN_MASK		GENMASK(17, 14)
-#define GHWCFG2_NUM_DEV_EP_MASK			GENMASK(13, 10)
-#define GHWCFG2_FS_PHY_TYPE_MASK		GENMASK(9, 8)
-#define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED	0
-#define GHWCFG2_FS_PHY_TYPE_DEDICATED		1
-#define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI		2
-#define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI		3
-#define GHWCFG2_HS_PHY_TYPE_MASK		GENMASK(7, 6)
-#define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED	0
-#define GHWCFG2_HS_PHY_TYPE_UTMI		1
-#define GHWCFG2_HS_PHY_TYPE_ULPI		2
-#define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI		3
-#define GHWCFG2_POINT2POINT			BIT(5)
-#define GHWCFG2_ARCHITECTURE_MASK		GENMASK(4, 3)
-#define GHWCFG2_SLAVE_ONLY_ARCH			0
-#define GHWCFG2_EXT_DMA_ARCH			1
-#define GHWCFG2_INT_DMA_ARCH			2
-#define GHWCFG2_OP_MODE_MASK			GENMASK(2, 0)
-#define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE		0
-#define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE	1
-#define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE	2
-#define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE	3
-#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE	4
-#define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST	5
-#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST	6
-#define GHWCFG2_OP_MODE_UNDEFINED		7
-
-#define GHWCFG4_DESC_DMA_DYN			BIT(31)
-#define GHWCFG4_DESC_DMA			BIT(30)
-#define GHWCFG4_NUM_IN_EPS_MASK			GENMASK(29, 26)
-#define GHWCFG4_DED_FIFO_EN			BIT(25)
-#define GHWCFG4_SESSION_END_FILT_EN		BIT(24)
-#define GHWCFG4_B_VALID_FILT_EN			BIT(23)
-#define GHWCFG4_A_VALID_FILT_EN			BIT(22)
-#define GHWCFG4_VBUS_VALID_FILT_EN		BIT(21)
-#define GHWCFG4_IDDIG_FILT_EN			BIT(20)
-#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK	GENMASK(19, 16)
-#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK	GENMASK(15, 14)
-#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8		0
-#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16		1
-#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16	2
-#define GHWCFG4_ACG_SUPPORTED			BIT(12)
-#define GHWCFG4_IPG_ISOC_SUPPORTED		BIT(11)
-#define GHWCFG4_SERVICE_INTERVAL_SUPPORTED      BIT(10)
-#define GHWCFG4_XHIBER				BIT(7)
-#define GHWCFG4_HIBER				BIT(6)
-#define GHWCFG4_MIN_AHB_FREQ			BIT(5)
-#define GHWCFG4_POWER_OPTIMIZ			BIT(4)
-#define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK	GENMASK(3, 0)
-
-#define HCFG_MODECHTIMEN			BIT(31)
-#define HCFG_PERSCHEDENA			BIT(26)
-#define HCFG_FRLISTEN_MASK			GENMASK(25, 24)
-#define HCFG_FRLISTEN_8				0
-#define HCFG_FRLISTEN_16			1
-#define HCFG_FRLISTEN_32			2
-#define HCFG_FRLISTEN_64			3
-#define HCFG_DESCDMA				BIT(23)
-#define HCFG_RESVALID_MASK			GENMASK(15, 8)
-#define HCFG_ENA32KHZ				BIT(7)
-#define HCFG_FSLSSUPP				BIT(2)
-#define HCFG_FSLSPCLKSEL_MASK			GENMASK(2, 0)
-#define HCFG_FSLSPCLKSEL_30_60_MHZ		0
-#define HCFG_FSLSPCLKSEL_48_MHZ			1
-#define HCFG_FSLSPCLKSEL_6_MHZ			2
-
-#define HFIR_FRINT_MASK				GENMASK(15, 0)
-#define HFIR_RLDCTRL				BIT(16)
-
-#define HFNUM_FRREM_MASK			GENMASK(31, 16)
-#define HFNUM_FRNUM_MASK			GENMASK(15, 0)
-
-#define HPRT0_SPD_MASK				GENMASK(18, 17)
-#define HPRT0_SPD_HIGH_SPEED			0
-#define HPRT0_SPD_FULL_SPEED			1
-#define HPRT0_SPD_LOW_SPEED			2
-#define HPRT0_TSTCTL_MASK			GENMASK(16, 13)
-#define HPRT0_PWR				BIT(12)
-#define HPRT0_LNSTS_MASK			GENMASK(11, 10)
-#define HPRT0_RST				BIT(8)
-#define HPRT0_SUSP				BIT(7)
-#define HPRT0_RES				BIT(6)
-#define HPRT0_OVRCURRCHG			BIT(5)
-#define HPRT0_OVRCURRACT			BIT(4)
-#define HPRT0_ENACHG				BIT(3)
-#define HPRT0_ENA				BIT(2)
-#define HPRT0_CONNDET				BIT(1)
-#define HPRT0_CONNSTS				BIT(0)
-#define HPRT0_W1C_MASK				(HPRT0_CONNDET | \
-						 HPRT0_ENA | \
-						 HPRT0_ENACHG | \
-						 HPRT0_OVRCURRCHG)
-
-#define HCCHAR_CHENA				BIT(31)
-#define HCCHAR_CHDIS				BIT(30)
-#define HCCHAR_ODDFRM				BIT(29)
-#define HCCHAR_DEVADDR_MASK			GENMASK(28, 22)
-#define HCCHAR_MULTICNT_MASK			GENMASK(21, 20)
-#define HCCHAR_EPTYPE_MASK			GENMASK(19, 18)
-#define HCCHAR_EPTYPE_CONTROL			0
-#define HCCHAR_EPTYPE_ISOC			1
-#define HCCHAR_EPTYPE_BULK			2
-#define HCCHAR_EPTYPE_INTR			3
-#define HCCHAR_LSPDDEV				BIT(17)
-#define HCCHAR_EPDIR				BIT(15)
-#define HCCHAR_EPNUM_MASK			GENMASK(14, 11)
-#define HCCHAR_MPS_MASK				GENMASK(10, 0)
-
-#define HCSPLT_SPLTENA				BIT(31)
-#define HCSPLT_COMPSPLT				BIT(16)
-#define HCSPLT_XACTPOS_MASK			GENMASK(15, 14)
-#define HCSPLT_XACTPOS_MID			0
-#define HCSPLT_XACTPOS_END			1
-#define HCSPLT_XACTPOS_BEGIN			2
-#define HCSPLT_XACTPOS_ALL			3
-#define HCSPLT_HUBADDR_MASK			GENMASK(13, 7)
-#define HCSPLT_PRTADDR_MASK			GENMASK(6, 0)
-
-#define HCINTMSK_FRM_LIST_ROLL			BIT(13)
-#define HCINTMSK_XCS_XACT			BIT(12)
-#define HCINTMSK_BNA				BIT(11)
-#define HCINTMSK_DATATGLERR			BIT(10)
-#define HCINTMSK_FRMOVRUN			BIT(9)
-#define HCINTMSK_BBLERR				BIT(8)
-#define HCINTMSK_XACTERR			BIT(7)
-#define HCINTMSK_NYET				BIT(6)
-#define HCINTMSK_ACK				BIT(5)
-#define HCINTMSK_NAK				BIT(4)
-#define HCINTMSK_STALL				BIT(3)
-#define HCINTMSK_AHBERR				BIT(2)
-#define HCINTMSK_CHHLTD				BIT(1)
-#define HCINTMSK_XFERCOMPL			BIT(0)
-
-#define TSIZ_DOPNG				BIT(31)
-#define TSIZ_SC_MC_PID_MASK			GENMASK(30, 29)
-#define TSIZ_SC_MC_PID_DATA0			0
-#define TSIZ_SC_MC_PID_DATA2			1
-#define TSIZ_SC_MC_PID_DATA1			2
-#define TSIZ_SC_MC_PID_MDATA			3
-#define TSIZ_SC_MC_PID_SETUP			3
-#define TSIZ_PKTCNT_MASK			GENMASK(28, 19)
-#define TSIZ_NTD_MASK				GENMASK(15, 8)
-#define TSIZ_SCHINFO_MASK			GENMASK(7, 0)
-#define TSIZ_XFERSIZE_MASK			GENMASK(18, 0)
-
-#define GSNPSID_ID_MASK				GENMASK(31, 16)
-#define GSNPSID_OTG_ID				0x4f54
-#define GSNPSID_VER_MASK			GENMASK(15, 0)
-
 /* Host controller specific */
 #define DWC2_HC_PID_DATA0		0
 #define DWC2_HC_PID_DATA2		1