diff options
| author | Svyatoslav Ryhel <[email protected]> | 2025-04-18 09:12:03 +0300 |
|---|---|---|
| committer | Svyatoslav Ryhel <[email protected]> | 2025-08-01 08:44:28 +0300 |
| commit | aa291c5f8bfbb761c2f2c84a501cf6eb4b655b2e (patch) | |
| tree | 7e14031766150aa749f8688e52d697d0e9c36f6b /drivers/video | |
| parent | d564f395bcf933d5986723b4a02783338114977c (diff) | |
video: tegra: parametrize PCLK and DE polarity
Configure pixel clock and data enable polarity according to panel flags.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Diffstat (limited to 'drivers/video')
| -rw-r--r-- | drivers/video/tegra/dc.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/video/tegra/dc.c b/drivers/video/tegra/dc.c index f0e3d2c993f..ced49718834 100644 --- a/drivers/video/tegra/dc.c +++ b/drivers/video/tegra/dc.c @@ -238,8 +238,24 @@ static void rgb_enable(struct tegra_lcd_priv *priv) else value &= ~LVS_OUTPUT_POLARITY_LOW; + /* configure pixel data signal polarity */ + if (dt->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE) + value &= ~LSC0_OUTPUT_POLARITY_LOW; + else + value |= LSC0_OUTPUT_POLARITY_LOW; + writel(value, &com->pin_output_polarity[1]); + /* configure data enable signal polarity */ + value = readl(&com->pin_output_polarity[3]); + + if (dt->flags & DISPLAY_FLAGS_DE_LOW) + value |= LSPI_OUTPUT_POLARITY_LOW; + else + value &= ~LSPI_OUTPUT_POLARITY_LOW; + + writel(value, &com->pin_output_polarity[3]); + for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++) writel(rgb_sel_tab[i], &com->pin_output_sel[i]); } |