diff options
| author | Patrice Chotard <[email protected]> | 2018-02-07 10:44:48 +0100 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2018-03-13 21:45:37 -0400 |
| commit | 09b335a6753f5c6ad418ca5eb0cdc599857272cc (patch) | |
| tree | 47340e60fb8b3636fa2ac08ad38f4e9e4971c9a1 /drivers | |
| parent | b43679482b06d476d908033b176f64c156f69b5e (diff) | |
clk: clk_stm32h7: Fix prescaler for Domain 3
d1cfgr register was used to calculate the domain 3
prescaler value instead of d3cfgr.
Signed-off-by: Patrice Chotard <[email protected]>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/clk_stm32h7.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/clk/clk_stm32h7.c b/drivers/clk/clk_stm32h7.c index 92db71431e4..9ee2e2e999a 100644 --- a/drivers/clk/clk_stm32h7.c +++ b/drivers/clk/clk_stm32h7.c @@ -635,7 +635,7 @@ static ulong stm32_clk_get_rate(struct clk *clk) struct stm32_rcc_regs *regs = priv->rcc_base; ulong sysclk = 0; u32 gate_offset; - u32 d1cfgr; + u32 d1cfgr, d3cfgr; /* prescaler table lookups for clock computation */ u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512}; u8 source, idx; @@ -712,9 +712,10 @@ static ulong stm32_clk_get_rate(struct clk *clk) break; case RCC_APB4ENR: - if (d1cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) { + d3cfgr = readl(®s->d3cfgr); + if (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) { /* get D3 domain APB4 prescaler */ - idx = (d1cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >> + idx = (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >> RCC_D3CFGR_D3PPRE_SHIFT; sysclk = sysclk / prescaler_table[idx]; } |