diff options
| author | Richard Genoud <[email protected]> | 2026-01-23 12:44:49 +0100 |
|---|---|---|
| committer | Michael Trimarchi <[email protected]> | 2026-02-03 21:44:56 +0100 |
| commit | 0b0f13d503e854086da5d0bf5f015d5a5b0e974f (patch) | |
| tree | 0fb15263877d77c83f8bd11bf9c8540089598865 /drivers | |
| parent | 9edd503aadac826a279b2b36cd537cfeb6a8296e (diff) | |
mtd: rawnand: sunxi_spl: add per SoC capabilities
Introduce per SoC capabilities in sunxi_nand_spl.c
Prepare for the H616 support that has quite a lot of differences in
registers offset and capabilities.
Start with the 512 bytes ECC capability.
No functional change.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mtd/nand/raw/sunxi_nand_spl.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/drivers/mtd/nand/raw/sunxi_nand_spl.c b/drivers/mtd/nand/raw/sunxi_nand_spl.c index 909c846e020..035b224bb43 100644 --- a/drivers/mtd/nand/raw/sunxi_nand_spl.c +++ b/drivers/mtd/nand/raw/sunxi_nand_spl.c @@ -27,6 +27,7 @@ struct nfc_config { int nseeds; bool randomize; bool valid; + const struct sunxi_nfc_caps *caps; }; /* minimal "boot0" style NAND support for Allwinner A20 */ @@ -51,6 +52,10 @@ const uint16_t random_seed[128] = { 0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db, }; +__maybe_unused static const struct sunxi_nfc_caps sunxi_nfc_a10_caps = { + .has_ecc_block_512 = true, +}; + #define DEFAULT_TIMEOUT_US 100000 static int check_value_inner(int offset, int expected_bits, @@ -220,12 +225,16 @@ static int nand_read_page(const struct nfc_config *conf, u32 offs, int data_off = i * conf->ecc_size; int oob_off = conf->page_size + (i * oob_chunk_sz); u8 *data = dest + data_off; + u32 ecc512_bit = 0; + + if (conf->caps->has_ecc_block_512 && conf->ecc_size == 512) + ecc512_bit = NFC_ECC_BLOCK_512; /* Clear ECC status and restart ECC engine */ writel(0, SUNXI_NFC_BASE + NFC_REG_ECC_ST); writel((rand_seed << 16) | (conf->ecc_strength << 12) | (conf->randomize ? NFC_RANDOM_EN : 0) | - (conf->ecc_size == 512 ? NFC_ECC_BLOCK_512 : 0) | + ecc512_bit | NFC_ECC_EN | NFC_ECC_EXCEPTION, SUNXI_NFC_BASE + NFC_REG_ECC_CTL); @@ -389,6 +398,8 @@ static int nand_detect_config(struct nfc_config *conf, u32 offs, void *dest) if (conf->valid) return 0; + conf->caps = &sunxi_nfc_a10_caps; + /* * Modern NANDs are more likely than legacy ones, so we start testing * with 5 address cycles. |