diff options
| author | Tom Rini <[email protected]> | 2024-09-19 11:26:18 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2024-09-19 11:26:18 -0600 |
| commit | 146be6f0362e16b112e72bdbb5c2d359dc65c890 (patch) | |
| tree | 4cc19ab8c9363553d9ba697a7380aa043d1cda51 /drivers | |
| parent | 2ac0a302ada6b1d0d9a2a137fd790ccd4f8d2090 (diff) | |
| parent | effe934e50f03c92ba6febecfe132c9cb34ecf59 (diff) | |
Merge tag 'u-boot-imx-next-20240919' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/22363
- Several updates to i.MX9 SOC and i.MX93 EVK.
- Power domain fixes.
- TRDC cleanup and update.
- MAC address layout update.
- Add support for the i.MX9301/9302 variants.
- Add runtime detection of voltage mode.
- Generalize some code for i.MX8M and i.MX9.
- Add support for Comvetia imx6q-lxr board.
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/cpu/imx8_cpu.c | 4 | ||||
| -rw-r--r-- | drivers/ddr/imx/phy/ddrphy_utils.c | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 60deca963a6..6c0a8c0cbe4 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -60,6 +60,10 @@ static const char *get_imx_type_str(u32 imxtype) return "93(12)";/* iMX93 9x9 Dual core without NPU */ case MXC_CPU_IMX9311: return "93(11)";/* iMX93 9x9 Single core without NPU */ + case MXC_CPU_IMX9302: + return "93(02)";/* iMX93 900Mhz Low performance Dual core without NPU */ + case MXC_CPU_IMX9301: + return "93(01)";/* iMX93 900Mhz Low performance Single core without NPU */ default: return "??"; } diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c index cf5bdad7abe..14278f5ad8f 100644 --- a/drivers/ddr/imx/phy/ddrphy_utils.c +++ b/drivers/ddr/imx/phy/ddrphy_utils.c @@ -148,6 +148,10 @@ void ddrphy_init_set_dfi_clk(unsigned int drate) dram_pll_init(MHZ(266)); dram_disable_bypass(); break; + case 933: + dram_pll_init(MHZ(233)); + dram_disable_bypass(); + break; case 667: dram_pll_init(MHZ(167)); dram_disable_bypass(); |