Merge tag 'ti-v2021.10-next-v2' of https://source.denx.de/u-boot/custodians/u-boot-ti into next

- HSM re-architecture support for all K3 platforms
- AM64 USB support
- Driver model support for Davinci RTC

20 files changed, 2089 insertions, 66 deletions

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 53e7be764d3..3d2344f009e 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -241,6 +241,15 @@ static int clk_set_default_parents(struct udevice *dev, int stage)
 
 		ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
 					      index, &clk);
+		/*
+		 * If the clock provider is not ready yet, let it handle
+		 * the re-programming later.
+		 */
+		if (ret == -EPROBE_DEFER) {
+			ret = 0;
+			continue;
+		}
+
 		if (ret) {
 			debug("%s: could not get assigned clock %d for %s\n",
 			      __func__, index, dev_read_name(dev));
@@ -309,6 +318,15 @@ static int clk_set_default_rates(struct udevice *dev, int stage)
 
 		ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
 					      index, &clk);
+		/*
+		 * If the clock provider is not ready yet, let it handle
+		 * the re-programming later.
+		 */
+		if (ret == -EPROBE_DEFER) {
+			ret = 0;
+			continue;
+		}
+
 		if (ret) {
 			dev_dbg(dev,
 				"could not get assigned clock %d (err = %d)\n",
@@ -502,6 +520,8 @@ struct clk *clk_get_parent(struct clk *clk)
 		return NULL;
 
 	pdev = dev_get_parent(clk->dev);
+	if (!pdev)
+		return ERR_PTR(-ENODEV);
 	pclk = dev_get_clk_ptr(pdev);
 	if (!pclk)
 		return ERR_PTR(-ENODEV);
@@ -548,6 +568,22 @@ ulong clk_round_rate(struct clk *clk, ulong rate)
 	return ops->round_rate(clk, rate);
 }
 
+static void clk_clean_rate_cache(struct clk *clk)
+{
+	struct udevice *child_dev;
+	struct clk *clkp;
+
+	if (!clk)
+		return;
+
+	clk->rate = 0;
+
+	list_for_each_entry(child_dev, &clk->dev->child_head, sibling_node) {
+		clkp = dev_get_clk_ptr(child_dev);
+		clk_clean_rate_cache(clkp);
+	}
+}
+
 ulong clk_set_rate(struct clk *clk, ulong rate)
 {
 	const struct clk_ops *ops;
@@ -560,6 +596,9 @@ ulong clk_set_rate(struct clk *clk, ulong rate)
 	if (!ops->set_rate)
 		return -ENOSYS;
 
+	/* Clean up cached rates for us and all child clocks */
+	clk_clean_rate_cache(clk);
+
 	return ops->set_rate(clk, rate);
 }
 
diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
index 09f9ef26a42..325a9b2dcfb 100644
--- a/drivers/clk/clk_fixed_rate.c
+++ b/drivers/clk/clk_fixed_rate.c
@@ -9,6 +9,9 @@
 #include <dm/device-internal.h>
 #include <linux/clk-provider.h>
 
+#define UBOOT_DM_CLK_FIXED_RATE "fixed_rate_clock"
+#define UBOOT_DM_CLK_FIXED_RATE_RAW "fixed_rate_raw_clock"
+
 static ulong clk_fixed_rate_get_rate(struct clk *clk)
 {
 	return to_clk_fixed_rate(clk->dev)->fixed_rate;
@@ -40,6 +43,15 @@ void clk_fixed_rate_ofdata_to_plat_(struct udevice *dev,
 	clk->enable_count = 0;
 }
 
+static ulong clk_fixed_rate_raw_get_rate(struct clk *clk)
+{
+	return container_of(clk, struct clk_fixed_rate, clk)->fixed_rate;
+}
+
+const struct clk_ops clk_fixed_rate_raw_ops = {
+	.get_rate = clk_fixed_rate_raw_get_rate,
+};
+
 static int clk_fixed_rate_of_to_plat(struct udevice *dev)
 {
 	clk_fixed_rate_ofdata_to_plat_(dev, to_clk_fixed_rate(dev));
@@ -47,6 +59,32 @@ static int clk_fixed_rate_of_to_plat(struct udevice *dev)
 	return 0;
 }
 
+#if CONFIG_IS_ENABLED(CLK_CCF)
+struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
+				    ulong rate)
+{
+	struct clk *clk;
+	struct clk_fixed_rate *fixed;
+	int ret;
+
+	fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
+	if (!fixed)
+		return ERR_PTR(-ENOMEM);
+
+	fixed->fixed_rate = rate;
+
+	clk = &fixed->clk;
+
+	ret = clk_register(clk, UBOOT_DM_CLK_FIXED_RATE_RAW, name, NULL);
+	if (ret) {
+		kfree(fixed);
+		return ERR_PTR(ret);
+	}
+
+	return clk;
+}
+#endif
+
 static const struct udevice_id clk_fixed_rate_match[] = {
 	{
 		.compatible = "fixed-clock",
@@ -63,3 +101,10 @@ U_BOOT_DRIVER(fixed_clock) = {
 	.ops = &clk_fixed_rate_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
+
+U_BOOT_DRIVER(clk_fixed_rate_raw) = {
+	.name = UBOOT_DM_CLK_FIXED_RATE_RAW,
+	.id = UCLASS_CLK,
+	.ops = &clk_fixed_rate_raw_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig
index 2dc86d44a98..fbcdefd889a 100644
--- a/drivers/clk/ti/Kconfig
+++ b/drivers/clk/ti/Kconfig
@@ -41,3 +41,27 @@ config CLK_TI_SCI
 	  This enables the clock driver support over TI System Control Interface
 	  available on some new TI's SoCs. If you wish to use clock resources
 	  managed by the TI System Controller, say Y here. Otherwise, say N.
+
+config CLK_K3_PLL
+	bool "PLL clock support for K3 SoC family of devices"
+	depends on CLK && LIB_RATIONAL
+	help
+	  Enables PLL clock support for K3 SoC family of devices.
+
+config SPL_CLK_K3_PLL
+	bool "PLL clock support for K3 SoC family of devices"
+	depends on CLK && LIB_RATIONAL && SPL
+	help
+	  Enables PLL clock support for K3 SoC family of devices.
+
+config CLK_K3
+	bool "Clock support for K3 SoC family of devices"
+	depends on CLK
+	help
+	  Enables the clock translation layer from DT to device clocks.
+
+config SPL_CLK_K3
+	bool "Clock support for K3 SoC family of devices"
+	depends on CLK && SPL
+	help
+	  Enables the clock translation layer from DT to device clocks.
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 9f56b477360..07aa9a53e08 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -11,3 +11,5 @@ obj-$(CONFIG_CLK_TI_DIVIDER) += clk-divider.o
 obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o
 obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
 obj-$(CONFIG_CLK_TI_SCI) += clk-sci.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_K3_PLL) += clk-k3-pll.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_K3) += clk-k3.o
diff --git a/drivers/clk/ti/clk-k3-pll.c b/drivers/clk/ti/clk-k3-pll.c
new file mode 100644
index 00000000000..bf2407a020a
--- /dev/null
+++ b/drivers/clk/ti/clk-k3-pll.c
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments K3 SoC PLL clock driver
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ *	Tero Kristo <[email protected]>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <div64.h>
+#include <errno.h>
+#include <clk-uclass.h>
+#include <linux/clk-provider.h>
+#include "k3-clk.h"
+#include <linux/rational.h>
+
+/* 16FFT register offsets */
+#define PLL_16FFT_CFG			0x08
+#define PLL_KICK0			0x10
+#define PLL_KICK1			0x14
+#define PLL_16FFT_CTRL			0x20
+#define PLL_16FFT_STAT			0x24
+#define PLL_16FFT_FREQ_CTRL0		0x30
+#define PLL_16FFT_FREQ_CTRL1		0x34
+#define PLL_16FFT_DIV_CTRL		0x38
+
+/* CTRL register bits */
+#define PLL_16FFT_CTRL_BYPASS_EN	BIT(31)
+#define PLL_16FFT_CTRL_PLL_EN		BIT(15)
+#define PLL_16FFT_CTRL_DSM_EN		BIT(1)
+
+/* STAT register bits */
+#define PLL_16FFT_STAT_LOCK		BIT(0)
+
+/* FREQ_CTRL0 bits */
+#define PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK	0xfff
+
+/* DIV CTRL register bits */
+#define PLL_16FFT_DIV_CTRL_REF_DIV_MASK		0x3f
+
+#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS	24
+#define PLL_16FFT_HSDIV_CTRL_CLKOUT_EN          BIT(15)
+
+/* KICK register magic values */
+#define PLL_KICK0_VALUE				0x68ef3490
+#define PLL_KICK1_VALUE				0xd172bc5a
+
+/**
+ * struct ti_pll_clk - TI PLL clock data info structure
+ * @clk: core clock structure
+ * @reg: memory address of the PLL controller
+ */
+struct ti_pll_clk {
+	struct clk	clk;
+	void __iomem	*reg;
+};
+
+#define to_clk_pll(_clk) container_of(_clk, struct ti_pll_clk, clk)
+
+static int ti_pll_wait_for_lock(struct clk *clk)
+{
+	struct ti_pll_clk *pll = to_clk_pll(clk);
+	u32 stat;
+	int i;
+
+	for (i = 0; i < 100000; i++) {
+		stat = readl(pll->reg + PLL_16FFT_STAT);
+		if (stat & PLL_16FFT_STAT_LOCK)
+			return 0;
+	}
+
+	printf("%s: pll (%s) failed to lock\n", __func__,
+	       clk->dev->name);
+
+	return -EBUSY;
+}
+
+static ulong ti_pll_clk_get_rate(struct clk *clk)
+{
+	struct ti_pll_clk *pll = to_clk_pll(clk);
+	u64 current_freq;
+	u64 parent_freq = clk_get_parent_rate(clk);
+	u32 pllm;
+	u32 plld;
+	u32 pllfm;
+	u32 ctrl;
+
+	/* Check if we are in bypass */
+	ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+	if (ctrl & PLL_16FFT_CTRL_BYPASS_EN)
+		return parent_freq;
+
+	pllm = readl(pll->reg + PLL_16FFT_FREQ_CTRL0);
+	pllfm = readl(pll->reg + PLL_16FFT_FREQ_CTRL1);
+
+	plld = readl(pll->reg + PLL_16FFT_DIV_CTRL) &
+		PLL_16FFT_DIV_CTRL_REF_DIV_MASK;
+
+	current_freq = parent_freq * pllm / plld;
+
+	if (pllfm) {
+		u64 tmp;
+
+		tmp = parent_freq * pllfm;
+		do_div(tmp, plld);
+		tmp >>= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS;
+		current_freq += tmp;
+	}
+
+	return current_freq;
+}
+
+static ulong ti_pll_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct ti_pll_clk *pll = to_clk_pll(clk);
+	u64 current_freq;
+	u64 parent_freq = clk_get_parent_rate(clk);
+	int ret;
+	u32 ctrl;
+	unsigned long pllm;
+	u32 pllfm = 0;
+	unsigned long plld;
+	u32 rem;
+	int shift;
+
+	debug("%s(clk=%p, rate=%u)\n", __func__, clk, (u32)rate);
+
+	if (ti_pll_clk_get_rate(clk) == rate)
+		return rate;
+
+	if (rate != parent_freq)
+		/*
+		 * Attempt with higher max multiplier value first to give
+		 * some space for fractional divider to kick in.
+		 */
+		for (shift = 8; shift >= 0; shift -= 8) {
+			rational_best_approximation(rate, parent_freq,
+				((PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK + 1) << shift) - 1,
+				PLL_16FFT_DIV_CTRL_REF_DIV_MASK, &pllm, &plld);
+			if (pllm / plld <= PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK)
+				break;
+		}
+
+	/* Put PLL to bypass mode */
+	ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+	ctrl |= PLL_16FFT_CTRL_BYPASS_EN;
+	writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+
+	if (rate == parent_freq) {
+		debug("%s: put %s to bypass\n", __func__, clk->dev->name);
+		return rate;
+	}
+
+	debug("%s: pre-frac-calc: rate=%u, parent_freq=%u, plld=%u, pllm=%u\n",
+	      __func__, (u32)rate, (u32)parent_freq, (u32)plld, (u32)pllm);
+
+	/* Check if we need fractional config */
+	if (plld > 1) {
+		pllfm = pllm % plld;
+		pllfm <<= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS;
+		rem = pllfm % plld;
+		pllfm /= plld;
+		if (rem)
+			pllfm++;
+		pllm /= plld;
+		plld = 1;
+	}
+
+	if (pllfm)
+		ctrl |= PLL_16FFT_CTRL_DSM_EN;
+	else
+		ctrl &= ~PLL_16FFT_CTRL_DSM_EN;
+
+	writel(pllm, pll->reg + PLL_16FFT_FREQ_CTRL0);
+	writel(pllfm, pll->reg + PLL_16FFT_FREQ_CTRL1);
+	writel(plld, pll->reg + PLL_16FFT_DIV_CTRL);
+
+	ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN;
+	ctrl |= PLL_16FFT_CTRL_PLL_EN;
+	writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+
+	ret = ti_pll_wait_for_lock(clk);
+	if (ret)
+		return ret;
+
+	debug("%s: pllm=%u, plld=%u, pllfm=%u, parent_freq=%u\n",
+	      __func__, (u32)pllm, (u32)plld, (u32)pllfm, (u32)parent_freq);
+
+	current_freq = parent_freq * pllm / plld;
+
+	if (pllfm) {
+		u64 tmp;
+
+		tmp = parent_freq * pllfm;
+		do_div(tmp, plld);
+		tmp >>= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS;
+		current_freq += tmp;
+	}
+
+	return current_freq;
+}
+
+static int ti_pll_clk_enable(struct clk *clk)
+{
+	struct ti_pll_clk *pll = to_clk_pll(clk);
+	u32 ctrl;
+
+	ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+	ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN;
+	ctrl |= PLL_16FFT_CTRL_PLL_EN;
+	writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+
+	return ti_pll_wait_for_lock(clk);
+}
+
+static int ti_pll_clk_disable(struct clk *clk)
+{
+	struct ti_pll_clk *pll = to_clk_pll(clk);
+	u32 ctrl;
+
+	ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+	ctrl |= PLL_16FFT_CTRL_BYPASS_EN;
+	writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+
+	return 0;
+}
+
+static const struct clk_ops ti_pll_clk_ops = {
+	.get_rate = ti_pll_clk_get_rate,
+	.set_rate = ti_pll_clk_set_rate,
+	.enable = ti_pll_clk_enable,
+	.disable = ti_pll_clk_disable,
+};
+
+struct clk *clk_register_ti_pll(const char *name, const char *parent_name,
+				void __iomem *reg)
+{
+	struct ti_pll_clk *pll;
+	int ret;
+	int i;
+	u32 cfg, ctrl, hsdiv_presence_bit, hsdiv_ctrl_offs;
+
+	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+	if (!pll)
+		return ERR_PTR(-ENOMEM);
+
+	pll->reg = reg;
+
+	ret = clk_register(&pll->clk, "ti-pll-clk", name, parent_name);
+	if (ret) {
+		printf("%s: failed to register: %d\n", __func__, ret);
+		kfree(pll);
+		return ERR_PTR(ret);
+	}
+
+	/* Unlock the PLL registers */
+	writel(PLL_KICK0_VALUE, pll->reg + PLL_KICK0);
+	writel(PLL_KICK1_VALUE, pll->reg + PLL_KICK1);
+
+	/* Enable all HSDIV outputs */
+	cfg = readl(pll->reg + PLL_16FFT_CFG);
+	for (i = 0; i < 16; i++) {
+		hsdiv_presence_bit = BIT(16 + i);
+		hsdiv_ctrl_offs = 0x80 + (i * 4);
+		/* Enable HSDIV output if present */
+		if ((hsdiv_presence_bit & cfg) != 0UL) {
+			ctrl = readl(pll->reg + hsdiv_ctrl_offs);
+			ctrl |= PLL_16FFT_HSDIV_CTRL_CLKOUT_EN;
+			writel(ctrl, pll->reg + hsdiv_ctrl_offs);
+		}
+	}
+
+	return &pll->clk;
+}
+
+U_BOOT_DRIVER(ti_pll_clk) = {
+	.name = "ti-pll-clk",
+	.id = UCLASS_CLK,
+	.ops = &ti_pll_clk_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c
new file mode 100644
index 00000000000..e921894e7a2
--- /dev/null
+++ b/drivers/clk/ti/clk-k3.c
@@ -0,0 +1,374 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments K3 clock driver
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ *	Tero Kristo <[email protected]>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <soc.h>
+#include <clk-uclass.h>
+#include "k3-clk.h"
+
+#define PLL_MIN_FREQ	800000000
+#define PLL_MAX_FREQ	3200000000UL
+#define PLL_MAX_DIV	127
+
+/**
+ * struct clk_map - mapping from dev/clk id tuples towards physical clocks
+ * @dev_id: device ID for the clock
+ * @clk_id: clock ID for the clock
+ * @clk: pointer to the registered clock entry for the mapping
+ */
+struct clk_map {
+	u16 dev_id;
+	u32 clk_id;
+	struct clk *clk;
+};
+
+/**
+ * struct ti_clk_data - clock controller information structure
+ * @map: mapping from dev/clk id tuples to physical clock entries
+ * @size: number of entries in the map
+ */
+struct ti_clk_data {
+	struct clk_map *map;
+	int size;
+};
+
+static ulong osc_freq;
+
+static void clk_add_map(struct ti_clk_data *data, struct clk *clk,
+			u32 dev_id, u32 clk_id)
+{
+	struct clk_map *map;
+
+	debug("%s: added clk=%p, data=%p, dev=%d, clk=%d\n", __func__,
+	      clk, data, dev_id, clk_id);
+	if (!clk)
+		return;
+
+	map = data->map + data->size++;
+
+	map->dev_id = dev_id;
+	map->clk_id = clk_id;
+	map->clk = clk;
+}
+
+static const struct soc_attr ti_k3_soc_clk_data[] = {
+#if IS_ENABLED(CONFIG_SOC_K3_J721E)
+	{
+		.family = "J721E",
+		.data = &j721e_clk_platdata,
+	},
+	{
+		.family = "J7200",
+		.data = &j7200_clk_platdata,
+	},
+#endif
+	{ /* sentinel */ }
+};
+
+static int ti_clk_probe(struct udevice *dev)
+{
+	struct ti_clk_data *data = dev_get_priv(dev);
+	struct clk *clk;
+	const char *name;
+	const struct clk_data *ti_clk_data;
+	int i, j;
+	const struct soc_attr *soc_match_data;
+	const struct ti_k3_clk_platdata *pdata;
+
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	soc_match_data = soc_device_match(ti_k3_soc_clk_data);
+	if (!soc_match_data)
+		return -ENODEV;
+
+	pdata = (const struct ti_k3_clk_platdata *)soc_match_data->data;
+
+	data->map = kcalloc(pdata->soc_dev_clk_data_cnt, sizeof(*data->map),
+			    GFP_KERNEL);
+	data->size = 0;
+
+	for (i = 0; i < pdata->clk_list_cnt; i++) {
+		ti_clk_data = &pdata->clk_list[i];
+
+		switch (ti_clk_data->type) {
+		case CLK_TYPE_FIXED_RATE:
+			name = ti_clk_data->clk.fixed_rate.name;
+			clk = clk_register_fixed_rate(NULL,
+						      name,
+						      ti_clk_data->clk.fixed_rate.rate);
+			break;
+		case CLK_TYPE_DIV:
+			name = ti_clk_data->clk.div.name;
+			clk = clk_register_divider(NULL, name,
+						   ti_clk_data->clk.div.parent,
+						   ti_clk_data->clk.div.flags,
+						   map_physmem(ti_clk_data->clk.div.reg, 0, MAP_NOCACHE),
+						   ti_clk_data->clk.div.shift,
+						   ti_clk_data->clk.div.width,
+						   0);
+			break;
+		case CLK_TYPE_MUX:
+			name = ti_clk_data->clk.mux.name;
+			clk = clk_register_mux(NULL, name,
+					       ti_clk_data->clk.mux.parents,
+					       ti_clk_data->clk.mux.num_parents,
+					       ti_clk_data->clk.mux.flags,
+					       map_physmem(ti_clk_data->clk.mux.reg, 0, MAP_NOCACHE),
+					       ti_clk_data->clk.mux.shift,
+					       ti_clk_data->clk.mux.width,
+					       0);
+			break;
+		case CLK_TYPE_PLL:
+			name = ti_clk_data->clk.pll.name;
+			clk = clk_register_ti_pll(name,
+						  ti_clk_data->clk.pll.parent,
+						  map_physmem(ti_clk_data->clk.pll.reg, 0, MAP_NOCACHE));
+
+			if (!osc_freq)
+				osc_freq = clk_get_rate(clk_get_parent(clk));
+			break;
+		default:
+			name = NULL;
+			clk = NULL;
+			printf("WARNING: %s has encountered unknown clk type %d\n",
+			       __func__, ti_clk_data->type);
+		}
+
+		if (clk && ti_clk_data->default_freq)
+			clk_set_rate(clk, ti_clk_data->default_freq);
+
+		if (clk && name) {
+			for (j = 0; j < pdata->soc_dev_clk_data_cnt; j++) {
+				if (!strcmp(name, pdata->soc_dev_clk_data[j].clk_name)) {
+					clk_add_map(data, clk, pdata->soc_dev_clk_data[j].dev_id,
+						    pdata->soc_dev_clk_data[j].clk_id);
+				}
+			}
+		}
+	}
+
+	return 0;
+}
+
+static int _clk_cmp(u32 dev_id, u32 clk_id, const struct clk_map *map)
+{
+	if (map->dev_id == dev_id && map->clk_id == clk_id)
+		return 0;
+	if (map->dev_id > dev_id ||
+	    (map->dev_id == dev_id && map->clk_id > clk_id))
+		return -1;
+	return 1;
+}
+
+static int bsearch(u32 dev_id, u32 clk_id, struct clk_map *map, int num)
+{
+	int result;
+	int idx;
+
+	for (idx = 0; idx < num; idx++) {
+		result = _clk_cmp(dev_id, clk_id, &map[idx]);
+
+		if (result == 0)
+			return idx;
+	}
+
+	return -ENOENT;
+}
+
+static int ti_clk_of_xlate(struct clk *clk,
+			   struct ofnode_phandle_args *args)
+{
+	struct ti_clk_data *data = dev_get_priv(clk->dev);
+	int idx;
+
+	debug("%s(clk=%p, args_count=%d [0]=%d [1]=%d)\n", __func__, clk,
+	      args->args_count, args->args[0], args->args[1]);
+
+	if (args->args_count != 2) {
+		debug("Invalid args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	if (!data->size)
+		return -EPROBE_DEFER;
+
+	idx = bsearch(args->args[0], args->args[1], data->map, data->size);
+	if (idx < 0)
+		return idx;
+
+	clk->id = idx;
+
+	return 0;
+}
+
+static ulong ti_clk_get_rate(struct clk *clk)
+{
+	struct ti_clk_data *data = dev_get_priv(clk->dev);
+	struct clk *clkp = data->map[clk->id].clk;
+
+	return clk_get_rate(clkp);
+}
+
+static ulong ti_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct ti_clk_data *data = dev_get_priv(clk->dev);
+	struct clk *clkp = data->map[clk->id].clk;
+	int div = 1;
+	ulong child_rate;
+	const struct clk_ops *ops;
+	ulong new_rate, rem;
+	ulong diff, new_diff;
+
+	/*
+	 * We must propagate rate change to parent if current clock type
+	 * does not allow setting it.
+	 */
+	while (clkp) {
+		ops = clkp->dev->driver->ops;
+		if (ops->set_rate)
+			break;
+
+		/*
+		 * Store child rate so we can calculate the clock rate
+		 * that must be passed to parent
+		 */
+		child_rate = clk_get_rate(clkp);
+		clkp = clk_get_parent(clkp);
+		if (clkp) {
+			debug("%s: propagating rate change to parent %s, rate=%u.\n",
+			      __func__, clkp->dev->name, (u32)rate / div);
+			div *= clk_get_rate(clkp) / child_rate;
+		}
+	}
+
+	if (!clkp)
+		return -ENOSYS;
+
+	child_rate = clk_get_rate(clkp);
+
+	new_rate = clk_set_rate(clkp, rate / div);
+
+	diff = abs(new_rate - rate / div);
+
+	debug("%s: clk=%s, div=%d, rate=%u, new_rate=%u, diff=%u\n", __func__,
+	      clkp->dev->name, div, (u32)rate, (u32)new_rate, (u32)diff);
+
+	/*
+	 * If the new rate differs by 50% of the target,
+	 * modify parent. This handles typical cases where we have a hsdiv
+	 * following directly a PLL
+	 */
+
+	if (diff > rate / div / 2) {
+		ulong pll_tgt;
+		int pll_div = 0;
+
+		clk = clkp;
+
+		debug("%s: propagating rate change to parent, rate=%u.\n",
+		      __func__, (u32)rate / div);
+
+		clkp = clk_get_parent(clkp);
+
+		if (rate > osc_freq) {
+			if (rate > PLL_MAX_FREQ / 2 && rate < PLL_MAX_FREQ) {
+				pll_tgt = rate;
+				pll_div = 1;
+			} else {
+				for (pll_div = 2; pll_div < PLL_MAX_DIV; pll_div++) {
+					pll_tgt = rate / div * pll_div;
+					if (pll_tgt >= PLL_MIN_FREQ && pll_tgt <= PLL_MAX_FREQ)
+						break;
+				}
+			}
+		} else {
+			pll_tgt = osc_freq;
+			pll_div = rate / div / osc_freq;
+		}
+
+		debug("%s: pll_tgt=%u, rate=%u, div=%u\n", __func__,
+		      (u32)pll_tgt, (u32)rate, pll_div);
+
+		clk_set_rate(clkp, pll_tgt);
+
+		return clk_set_rate(clk, rate / div) * div;
+	}
+
+	/*
+	 * If the new rate differs by at least 5% of the target,
+	 * we must check for rounding error in a divider, so try
+	 * set rate with rate + (parent_freq % rate).
+	 */
+
+	if (diff > rate / div / 20) {
+		u64 parent_freq = clk_get_parent_rate(clkp);
+
+		rem = parent_freq % rate;
+		new_rate = clk_set_rate(clkp, (rate / div) + rem);
+		new_diff = abs(new_rate - rate / div);
+
+		if (new_diff > diff) {
+			new_rate = clk_set_rate(clkp, rate / div);
+		} else {
+			debug("%s: Using better rate %lu that gives diff %lu\n",
+			      __func__, new_rate, new_diff);
+		}
+	}
+
+	return new_rate;
+}
+
+static int ti_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct ti_clk_data *data = dev_get_priv(clk->dev);
+	struct clk *clkp = data->map[clk->id].clk;
+	struct clk *parentp = data->map[parent->id].clk;
+
+	return clk_set_parent(clkp, parentp);
+}
+
+static int ti_clk_enable(struct clk *clk)
+{
+	struct ti_clk_data *data = dev_get_priv(clk->dev);
+	struct clk *clkp = data->map[clk->id].clk;
+
+	return clk_enable(clkp);
+}
+
+static int ti_clk_disable(struct clk *clk)
+{
+	struct ti_clk_data *data = dev_get_priv(clk->dev);
+	struct clk *clkp = data->map[clk->id].clk;
+
+	return clk_disable(clkp);
+}
+
+static const struct udevice_id ti_clk_of_match[] = {
+	{ .compatible = "ti,k2g-sci-clk" },
+	{ /* sentinel */ },
+};
+
+static const struct clk_ops ti_clk_ops = {
+	.of_xlate = ti_clk_of_xlate,
+	.set_rate = ti_clk_set_rate,
+	.get_rate = ti_clk_get_rate,
+	.enable = ti_clk_enable,
+	.disable = ti_clk_disable,
+	.set_parent = ti_clk_set_parent,
+};
+
+U_BOOT_DRIVER(ti_clk) = {
+	.name = "ti-clk",
+	.id = UCLASS_CLK,
+	.of_match = ti_clk_of_match,
+	.probe = ti_clk_probe,
+	.priv_auto = sizeof(struct ti_clk_data),
+	.ops = &ti_clk_ops,
+};
diff --git a/drivers/clk/ti/clk-sci.c b/drivers/clk/ti/clk-sci.c
index 6f0fdaa111c..acb9eadf03c 100644
--- a/drivers/clk/ti/clk-sci.c
+++ b/drivers/clk/ti/clk-sci.c
@@ -111,10 +111,12 @@ static ulong ti_sci_clk_set_rate(struct clk *clk, ulong rate)
 #endif
 
 	ret = cops->set_freq(sci, clk->id, clk->data, 0, rate, ULONG_MAX);
-	if (ret)
+	if (ret) {
 		dev_err(clk->dev, "%s: set_freq failed (%d)\n", __func__, ret);
+		return ret;
+	}
 
-	return ret;
+	return rate;
 }
 
 static int ti_sci_clk_set_parent(struct clk *clk, struct clk *parent)
diff --git a/drivers/dma/ti/k3-udma-u-boot.c b/drivers/dma/ti/k3-udma-u-boot.c
new file mode 100644
index 00000000000..3e04f551e29
--- /dev/null
+++ b/drivers/dma/ti/k3-udma-u-boot.c
@@ -0,0 +1,177 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+#define UDMA_RCHAN_RFLOW_RNG_FLOWID_CNT_SHIFT	(16)
+
+/* How SRC/DST tag should be updated by UDMA in the descriptor's Word 3 */
+#define UDMA_RFLOW_SRCTAG_NONE		0
+#define UDMA_RFLOW_SRCTAG_CFG_TAG	1
+#define UDMA_RFLOW_SRCTAG_FLOW_ID	2
+#define UDMA_RFLOW_SRCTAG_SRC_TAG	4
+
+#define UDMA_RFLOW_DSTTAG_NONE		0
+#define UDMA_RFLOW_DSTTAG_CFG_TAG	1
+#define UDMA_RFLOW_DSTTAG_FLOW_ID	2
+#define UDMA_RFLOW_DSTTAG_DST_TAG_LO	4
+#define UDMA_RFLOW_DSTTAG_DST_TAG_HI	5
+
+#define UDMA_RFLOW_RFC_DEFAULT	\
+	((UDMA_RFLOW_SRCTAG_NONE <<  UDMA_RFLOW_RFC_SRC_TAG_HI_SEL_SHIFT) | \
+	 (UDMA_RFLOW_SRCTAG_SRC_TAG << UDMA_RFLOW_RFC_SRC_TAG_LO_SEL_SHIFT) | \
+	 (UDMA_RFLOW_DSTTAG_DST_TAG_HI << UDMA_RFLOW_RFC_DST_TAG_HI_SEL_SHIFT) | \
+	 (UDMA_RFLOW_DSTTAG_DST_TAG_LO << UDMA_RFLOW_RFC_DST_TAG_LO_SE_SHIFT))
+
+#define UDMA_RFLOW_RFx_REG_FDQ_SIZE_SHIFT	(16)
+
+/* TCHAN */
+static inline u32 udma_tchan_read(struct udma_tchan *tchan, int reg)
+{
+	if (!tchan)
+		return 0;
+	return udma_read(tchan->reg_chan, reg);
+}
+
+static inline void udma_tchan_write(struct udma_tchan *tchan, int reg, u32 val)
+{
+	if (!tchan)
+		return;
+	udma_write(tchan->reg_chan, reg, val);
+}
+
+static inline void udma_tchan_update_bits(struct udma_tchan *tchan, int reg,
+					  u32 mask, u32 val)
+{
+	if (!tchan)
+		return;
+	udma_update_bits(tchan->reg_chan, reg, mask, val);
+}
+
+/* RCHAN */
+static inline u32 udma_rchan_read(struct udma_rchan *rchan, int reg)
+{
+	if (!rchan)
+		return 0;
+	return udma_read(rchan->reg_chan, reg);
+}
+
+static inline void udma_rchan_write(struct udma_rchan *rchan, int reg, u32 val)
+{
+	if (!rchan)
+		return;
+	udma_write(rchan->reg_chan, reg, val);
+}
+
+static inline void udma_rchan_update_bits(struct udma_rchan *rchan, int reg,
+					  u32 mask, u32 val)
+{
+	if (!rchan)
+		return;
+	udma_update_bits(rchan->reg_chan, reg, mask, val);
+}
+
+/* RFLOW */
+static inline u32 udma_rflow_read(struct udma_rflow *rflow, int reg)
+{
+	if (!rflow)
+		return 0;
+	return udma_read(rflow->reg_rflow, reg);
+}
+
+static inline void udma_rflow_write(struct udma_rflow *rflow, int reg, u32 val)
+{
+	if (!rflow)
+		return;
+	udma_write(rflow->reg_rflow, reg, val);
+}
+
+static inline void udma_rflow_update_bits(struct udma_rflow *rflow, int reg,
+					  u32 mask, u32 val)
+{
+	if (!rflow)
+		return;
+	udma_update_bits(rflow->reg_rflow, reg, mask, val);
+}
+
+static void udma_alloc_tchan_raw(struct udma_chan *uc)
+{
+	u32 mode, fetch_size;
+
+	if (uc->config.pkt_mode)
+		mode = UDMA_CHAN_CFG_CHAN_TYPE_PACKET_PBRR;
+	else
+		mode = UDMA_CHAN_CFG_CHAN_TYPE_3RDP_BC_PBRR;
+
+	udma_tchan_update_bits(uc->tchan, UDMA_TCHAN_TCFG_REG,
+			       UDMA_CHAN_CFG_CHAN_TYPE_MASK, mode);
+
+	if (uc->config.dir == DMA_MEM_TO_MEM)
+		fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2;
+	else
+		fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib,
+						   uc->config.psd_size, 0) >> 2;
+
+	udma_tchan_update_bits(uc->tchan, UDMA_TCHAN_TCFG_REG,
+			       UDMA_CHAN_CFG_FETCH_SIZE_MASK, fetch_size);
+	udma_tchan_write(uc->tchan, UDMA_TCHAN_TCQ_REG,
+			 k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring));
+}
+
+static void udma_alloc_rchan_raw(struct udma_chan *uc)
+{
+	struct udma_dev *ud = uc->ud;
+	int fd_ring = k3_nav_ringacc_get_ring_id(uc->rflow->fd_ring);
+	int rx_ring = k3_nav_ringacc_get_ring_id(uc->rflow->r_ring);
+	int tc_ring = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
+	u32 rx_einfo_present = 0, rx_psinfo_present = 0;
+	u32 mode, fetch_size, rxcq_num;
+
+	if (uc->config.pkt_mode)
+		mode = UDMA_CHAN_CFG_CHAN_TYPE_PACKET_PBRR;
+	else
+		mode = UDMA_CHAN_CFG_CHAN_TYPE_3RDP_BC_PBRR;
+
+	udma_rchan_update_bits(uc->rchan, UDMA_RCHAN_RCFG_REG,
+			       UDMA_CHAN_CFG_CHAN_TYPE_MASK, mode);
+
+	if (uc->config.dir == DMA_MEM_TO_MEM) {
+		fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2;
+		rxcq_num = tc_ring;
+	} else {
+		fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib,
+						   uc->config.psd_size, 0) >> 2;
+		rxcq_num = rx_ring;
+	}
+
+	udma_rchan_update_bits(uc->rchan, UDMA_RCHAN_RCFG_REG,
+			       UDMA_CHAN_CFG_FETCH_SIZE_MASK, fetch_size);
+	udma_rchan_write(uc->rchan, UDMA_RCHAN_RCQ_REG, rxcq_num);
+
+	if (uc->config.dir == DMA_MEM_TO_MEM)
+		return;
+
+	if (ud->match_data->type == DMA_TYPE_UDMA &&
+	    uc->rflow->id != uc->rchan->id &&
+	    uc->config.dir != DMA_MEM_TO_MEM)
+		udma_rchan_write(uc->rchan, UDMA_RCHAN_RFLOW_RNG_REG, uc->rflow->id |
+				 1 << UDMA_RCHAN_RFLOW_RNG_FLOWID_CNT_SHIFT);
+
+	if (uc->config.needs_epib)
+		rx_einfo_present = UDMA_RFLOW_RFA_EINFO;
+
+	if (uc->config.psd_size)
+		rx_psinfo_present = UDMA_RFLOW_RFA_PSINFO;
+
+	udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(A),
+			 rx_einfo_present | rx_psinfo_present | rxcq_num);
+
+	udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(C), UDMA_RFLOW_RFC_DEFAULT);
+	udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(D),
+			 fd_ring | fd_ring << UDMA_RFLOW_RFx_REG_FDQ_SIZE_SHIFT);
+	udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(E),
+			 fd_ring | fd_ring << UDMA_RFLOW_RFx_REG_FDQ_SIZE_SHIFT);
+	udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(G), fd_ring);
+	udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(H),
+			 fd_ring | fd_ring << UDMA_RFLOW_RFx_REG_FDQ_SIZE_SHIFT);
+}
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index 601868d7fc8..411edef3a76 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -48,6 +48,9 @@ enum udma_mmr {
 	MMR_BCHANRT,
 	MMR_RCHANRT,
 	MMR_TCHANRT,
+	MMR_RCHAN,
+	MMR_TCHAN,
+	MMR_RFLOW,
 	MMR_LAST,
 };
 
@@ -56,9 +59,13 @@ static const char * const mmr_names[] = {
 	[MMR_BCHANRT] = "bchanrt",
 	[MMR_RCHANRT] = "rchanrt",
 	[MMR_TCHANRT] = "tchanrt",
+	[MMR_RCHAN] = "rchan",
+	[MMR_TCHAN] = "tchan",
+	[MMR_RFLOW] = "rflow",
 };
 
 struct udma_tchan {
+	void __iomem *reg_chan;
 	void __iomem *reg_rt;
 
 	int id;
@@ -71,12 +78,14 @@ struct udma_tchan {
 #define udma_bchan udma_tchan
 
 struct udma_rflow {
+	void __iomem *reg_rflow;
 	int id;
 	struct k3_nav_ring *fd_ring; /* Free Descriptor ring */
 	struct k3_nav_ring *r_ring; /* Receive ring */
 };
 
 struct udma_rchan {
+	void __iomem *reg_chan;
 	void __iomem *reg_rt;
 
 	int id;
@@ -335,6 +344,8 @@ static inline char *udma_get_dir_text(enum dma_direction dir)
 	return "invalid";
 }
 
+#include "k3-udma-u-boot.c"
+
 static void udma_reset_uchan(struct udma_chan *uc)
 {
 	memset(&uc->config, 0, sizeof(uc->config));
@@ -1014,10 +1025,20 @@ static int udma_alloc_tchan_sci_req(struct udma_chan *uc)
 	req.txcq_qnum = tc_ring;
 
 	ret = tisci_rm->tisci_udmap_ops->tx_ch_cfg(tisci_rm->tisci, &req);
-	if (ret)
+	if (ret) {
 		dev_err(ud->dev, "tisci tx alloc failed %d\n", ret);
+		return ret;
+	}
 
-	return ret;
+	/*
+	 * Above TI SCI call handles firewall configuration, cfg
+	 * register configuration still has to be done locally in
+	 * absence of RM services.
+	 */
+	if (IS_ENABLED(CONFIG_K3_DM_FW))
+		udma_alloc_tchan_raw(uc);
+
+	return 0;
 }
 
 static int udma_alloc_rchan_sci_req(struct udma_chan *uc)
@@ -1114,11 +1135,21 @@ static int udma_alloc_rchan_sci_req(struct udma_chan *uc)
 
 	ret = tisci_rm->tisci_udmap_ops->rx_flow_cfg(tisci_rm->tisci,
 						     &flow_req);
-	if (ret)
+	if (ret) {
 		dev_err(ud->dev, "tisci rx %u flow %u cfg failed %d\n",
 			uc->rchan->id, uc->rflow->id, ret);
+		return ret;
+	}
 
-	return ret;
+	/*
+	 * Above TI SCI call handles firewall configuration, cfg
+	 * register configuration still has to be done locally in
+	 * absence of RM services.
+	 */
+	if (IS_ENABLED(CONFIG_K3_DM_FW))
+		udma_alloc_rchan_raw(uc);
+
+	return 0;
 }
 
 static int udma_alloc_chan_resources(struct udma_chan *uc)
@@ -1751,6 +1782,7 @@ static int udma_probe(struct udevice *dev)
 		struct udma_tchan *tchan = &ud->tchans[i];
 
 		tchan->id = i;
+		tchan->reg_chan = ud->mmrs[MMR_TCHAN] + UDMA_CH_100(i);
 		tchan->reg_rt = ud->mmrs[MMR_TCHANRT] + UDMA_CH_1000(i);
 	}
 
@@ -1758,6 +1790,7 @@ static int udma_probe(struct udevice *dev)
 		struct udma_rchan *rchan = &ud->rchans[i];
 
 		rchan->id = i;
+		rchan->reg_chan = ud->mmrs[MMR_RCHAN] + UDMA_CH_100(i);
 		rchan->reg_rt = ud->mmrs[MMR_RCHANRT] + UDMA_CH_1000(i);
 	}
 
@@ -1765,6 +1798,7 @@ static int udma_probe(struct udevice *dev)
 		struct udma_rflow *rflow = &ud->rflows[i];
 
 		rflow->id = i;
+		rflow->reg_rflow = ud->mmrs[MMR_RFLOW] + UDMA_CH_40(i);
 	}
 
 	for (i = 0; i < ud->ch_count; i++) {
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index 4671a5e3a8a..0b6ba35b596 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -23,6 +23,7 @@
 #include <linux/soc/ti/ti_sci_protocol.h>
 
 #include "ti_sci.h"
+#include "ti_sci_static_data.h"
 
 /* List of all TI SCI devices active in system */
 static LIST_HEAD(ti_sci_list);
@@ -1668,6 +1669,34 @@ fail:
 	return ret;
 }
 
+static int __maybe_unused
+ti_sci_cmd_get_resource_range_static(const struct ti_sci_handle *handle,
+				     u32 dev_id, u8 subtype,
+				     u16 *range_start, u16 *range_num)
+{
+	struct ti_sci_resource_static_data *data;
+	int i = 0;
+
+	while (1) {
+		data = &rm_static_data[i];
+
+		if (!data->dev_id)
+			return -EINVAL;
+
+		if (data->dev_id != dev_id || data->subtype != subtype) {
+			i++;
+			continue;
+		}
+
+		*range_start = data->range_start;
+		*range_num = data->range_num;
+
+		return 0;
+	}
+
+	return -EINVAL;
+}
+
 /**
  * ti_sci_cmd_get_resource_range - Get a range of resources assigned to host
  *				   that is same as ti sci interface host.
@@ -3016,6 +3045,58 @@ static int ti_sci_probe(struct udevice *dev)
 	return ret;
 }
 
+/**
+ * ti_sci_dm_probe() - Basic probe for DM to TIFS SCI
+ * @dev:	corresponding system controller interface device
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static __maybe_unused int ti_sci_dm_probe(struct udevice *dev)
+{
+	struct ti_sci_rm_core_ops *rm_core_ops;
+	struct ti_sci_rm_udmap_ops *udmap_ops;
+	struct ti_sci_rm_ringacc_ops *rops;
+	struct ti_sci_rm_psil_ops *psilops;
+	struct ti_sci_ops *ops;
+	struct ti_sci_info *info;
+	int ret;
+
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	info = dev_get_priv(dev);
+	info->desc = (void *)dev_get_driver_data(dev);
+
+	ret = ti_sci_of_to_info(dev, info);
+	if (ret) {
+		dev_err(dev, "%s: Probe failed with error %d\n", __func__, ret);
+		return ret;
+	}
+
+	info->dev = dev;
+	info->seq = 0xA;
+
+	list_add_tail(&info->list, &ti_sci_list);
+
+	ops = &info->handle.ops;
+
+	rm_core_ops = &ops->rm_core_ops;
+	rm_core_ops->get_range = ti_sci_cmd_get_resource_range_static;
+
+	rops = &ops->rm_ring_ops;
+	rops->config = ti_sci_cmd_ring_config;
+
+	psilops = &ops->rm_psil_ops;
+	psilops->pair = ti_sci_cmd_rm_psil_pair;
+	psilops->unpair = ti_sci_cmd_rm_psil_unpair;
+
+	udmap_ops = &ops->rm_udmap_ops;
+	udmap_ops->tx_ch_cfg = ti_sci_cmd_rm_udmap_tx_ch_cfg;
+	udmap_ops->rx_ch_cfg = ti_sci_cmd_rm_udmap_rx_ch_cfg;
+	udmap_ops->rx_flow_cfg = ti_sci_cmd_rm_udmap_rx_flow_cfg;
+
+	return ret;
+}
+
 /*
  * ti_sci_get_free_resource() - Get a free resource from TISCI resource.
  * @res:	Pointer to the TISCI resource
@@ -3153,6 +3234,14 @@ static const struct ti_sci_desc ti_sci_pmmc_am654_desc = {
 	.max_msg_size = 60,
 };
 
+/* Description for J721e DM to DMSC communication */
+static const struct ti_sci_desc ti_sci_dm_j721e_desc = {
+	.default_host_id = 3,
+	.max_rx_timeout_ms = 10000,
+	.max_msgs = 20,
+	.max_msg_size = 60,
+};
+
 static const struct udevice_id ti_sci_ids[] = {
 	{
 		.compatible = "ti,k2g-sci",
@@ -3165,6 +3254,14 @@ static const struct udevice_id ti_sci_ids[] = {
 	{ /* Sentinel */ },
 };
 
+static __maybe_unused const struct udevice_id ti_sci_dm_ids[] = {
+	{
+		.compatible = "ti,j721e-dm-sci",
+		.data = (ulong)&ti_sci_dm_j721e_desc
+	},
+	{ /* Sentinel */ },
+};
+
 U_BOOT_DRIVER(ti_sci) = {
 	.name = "ti_sci",
 	.id = UCLASS_FIRMWARE,
@@ -3172,3 +3269,13 @@ U_BOOT_DRIVER(ti_sci) = {
 	.probe = ti_sci_probe,
 	.priv_auto	= sizeof(struct ti_sci_info),
 };
+
+#if IS_ENABLED(CONFIG_K3_DM_FW)
+U_BOOT_DRIVER(ti_sci_dm) = {
+	.name = "ti_sci_dm",
+	.id = UCLASS_FIRMWARE,
+	.of_match = ti_sci_dm_ids,
+	.probe = ti_sci_dm_probe,
+	.priv_auto = sizeof(struct ti_sci_info),
+};
+#endif
diff --git a/drivers/firmware/ti_sci_static_data.h b/drivers/firmware/ti_sci_static_data.h
new file mode 100644
index 00000000000..3c506e667ac
--- /dev/null
+++ b/drivers/firmware/ti_sci_static_data.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (C)  2021 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ */
+
+#ifndef __TI_SCI_STATIC_DATA_H
+#define __TI_SCI_STATIC_DATA_H
+
+struct ti_sci_resource_static_data {
+	u32 dev_id;
+	u16 range_start;
+	u16 range_num;
+	u8 subtype;
+};
+
+#if IS_ENABLED(CONFIG_K3_DM_FW)
+
+#if IS_ENABLED(CONFIG_TARGET_J721E_R5_EVM)
+static struct ti_sci_resource_static_data rm_static_data[] = {
+	/* Free rings */
+	{
+		.dev_id = 235,
+		.subtype = 1,
+		.range_start = 124,
+		.range_num = 32,
+	},
+	/* TX channels */
+	{
+		.dev_id = 236,
+		.subtype = 13,
+		.range_start = 6,
+		.range_num = 2,
+	},
+	/* RX channels */
+	{
+		.dev_id = 236,
+		.subtype = 10,
+		.range_start = 6,
+		.range_num = 2,
+	},
+	/* RX Free flows */
+	{
+		.dev_id = 236,
+		.subtype = 0,
+		.range_start = 60,
+		.range_num = 8,
+	},
+	{ },
+};
+#endif /* CONFIG_TARGET_J721E_R5_EVM */
+
+#if IS_ENABLED(CONFIG_TARGET_J7200_R5_EVM)
+static struct ti_sci_resource_static_data rm_static_data[] = {
+	/* Free rings */
+	{
+		.dev_id = 235,
+		.subtype = 1,
+		.range_start = 144,
+		.range_num = 32,
+	},
+	/* TX channels */
+	{
+		.dev_id = 236,
+		.subtype = 13,
+		.range_start = 7,
+		.range_num = 2,
+	},
+	/* RX channels */
+	{
+		.dev_id = 236,
+		.subtype = 10,
+		.range_start = 7,
+		.range_num = 2,
+	},
+	/* RX Free flows */
+	{
+		.dev_id = 236,
+		.subtype = 0,
+		.range_start = 60,
+		.range_num = 8,
+	},
+	{ },
+};
+#endif /* CONFIG_TARGET_J7200_R5_EVM */
+
+#else
+static struct ti_sci_resource_static_data rm_static_data[] = {
+	{ },
+};
+#endif /* CONFIG_K3_DM_FW */
+#endif /* __TI_SCI_STATIC_DATA_H */
diff --git a/drivers/mailbox/k3-sec-proxy.c b/drivers/mailbox/k3-sec-proxy.c
index 88f320515ae..20fdb09f314 100644
--- a/drivers/mailbox/k3-sec-proxy.c
+++ b/drivers/mailbox/k3-sec-proxy.c
@@ -409,7 +409,7 @@ static int k3_sec_proxy_remove(struct udevice *dev)
 	return 0;
 }
 
-static const u32 am6x_valid_threads[] = { 0, 1, 4, 5, 6, 7, 8, 9, 11, 12, 13 };
+static const u32 am6x_valid_threads[] = { 0, 1, 4, 5, 6, 7, 8, 9, 11, 12, 13, 20, 21, 22, 23 };
 
 static const struct k3_sec_proxy_desc am654_desc = {
 	.thread_count = 90,
diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index a0fd9807529..99b3f9ae71b 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -72,4 +72,11 @@ config TI_SCI_POWER_DOMAIN
 	help
 	  Generic power domain implementation for TI devices implementing the
 	  TI SCI protocol.
+
+config TI_POWER_DOMAIN
+	bool "Enable the TI K3 Power domain driver"
+	depends on POWER_DOMAIN && ARCH_K3
+	help
+	  Generic power domain implementation for TI K3 devices.
+
 endmenu
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index 45bf9f63834..3d1e5f073cb 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o
 obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
 obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o
 obj-$(CONFIG_TI_SCI_POWER_DOMAIN) += ti-sci-power-domain.o
+obj-$(CONFIG_TI_POWER_DOMAIN) += ti-power-domain.o
diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c
new file mode 100644
index 00000000000..b45e9b82453
--- /dev/null
+++ b/drivers/power/domain/ti-power-domain.c
@@ -0,0 +1,368 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments power domain driver
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ *	Tero Kristo <[email protected]>
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <power-domain-uclass.h>
+#include <soc.h>
+#include <k3-dev.h>
+#include <linux/iopoll.h>
+
+#define PSC_PTCMD		0x120
+#define PSC_PTSTAT		0x128
+#define PSC_PDSTAT		0x200
+#define PSC_PDCTL		0x300
+#define PSC_MDSTAT		0x800
+#define PSC_MDCTL		0xa00
+
+#define PDCTL_STATE_MASK		0x1
+#define PDCTL_STATE_OFF			0x0
+#define PDCTL_STATE_ON			0x1
+
+#define MDSTAT_STATE_MASK		0x3f
+#define MDSTAT_BUSY_MASK		0x30
+#define MDSTAT_STATE_SWRSTDISABLE	0x0
+#define MDSTAT_STATE_ENABLE		0x3
+
+#define LPSC_TIMEOUT		1000
+#define PD_TIMEOUT		1000
+
+static u32 psc_read(struct ti_psc *psc, u32 reg)
+{
+	u32 val;
+
+	val = readl(psc->base + reg);
+	debug("%s: 0x%x from %p\n", __func__, val, psc->base + reg);
+	return val;
+}
+
+static void psc_write(u32 val, struct ti_psc *psc, u32 reg)
+{
+	debug("%s: 0x%x to %p\n", __func__, val, psc->base + reg);
+	writel(val, psc->base + reg);
+}
+
+static u32 pd_read(struct ti_pd *pd, u32 reg)
+{
+	return psc_read(pd->psc, reg + 4 * pd->id);
+}
+
+static void pd_write(u32 val, struct ti_pd *pd, u32 reg)
+{
+	psc_write(val, pd->psc, reg + 4 * pd->id);
+}
+
+static u32 lpsc_read(struct ti_lpsc *lpsc, u32 reg)
+{
+	return psc_read(lpsc->psc, reg + 4 * lpsc->id);
+}
+
+static void lpsc_write(u32 val, struct ti_lpsc *lpsc, u32 reg)
+{
+	psc_write(val, lpsc->psc, reg + 4 * lpsc->id);
+}
+
+static const struct soc_attr ti_k3_soc_pd_data[] = {
+#if IS_ENABLED(CONFIG_SOC_K3_J721E)
+	{
+		.family = "J721E",
+		.data = &j721e_pd_platdata,
+	},
+	{
+		.family = "J7200",
+		.data = &j7200_pd_platdata,
+	},
+#endif
+	{ /* sentinel */ }
+};
+
+static int ti_power_domain_probe(struct udevice *dev)
+{
+	struct ti_k3_pd_platdata *data = dev_get_priv(dev);
+	const struct soc_attr *soc_match_data;
+	const struct ti_k3_pd_platdata *pdata;
+
+	printf("%s(dev=%p)\n", __func__, dev);
+
+	if (!data)
+		return -ENOMEM;
+
+	soc_match_data = soc_device_match(ti_k3_soc_pd_data);
+	if (!soc_match_data)
+		return -ENODEV;
+
+	pdata = (const struct ti_k3_pd_platdata *)soc_match_data->data;
+
+	data->psc = pdata->psc;
+	data->pd = pdata->pd;
+	data->lpsc = pdata->lpsc;
+	data->devs = pdata->devs;
+	data->num_psc = pdata->num_psc;
+	data->num_pd = pdata->num_pd;
+	data->num_lpsc = pdata->num_lpsc;
+	data->num_devs = pdata->num_devs;
+
+	return 0;
+}
+
+static int ti_pd_wait(struct ti_pd *pd)
+{
+	u32 ptstat;
+	int ret;
+
+	ret = readl_poll_timeout(pd->psc->base + PSC_PTSTAT, ptstat,
+				 !(ptstat & BIT(pd->id)), PD_TIMEOUT);
+
+	if (ret)
+		printf("%s: psc%d, pd%d failed to transition.\n", __func__,
+		       pd->psc->id, pd->id);
+
+	return ret;
+}
+
+static void ti_pd_transition(struct ti_pd *pd)
+{
+	psc_write(BIT(pd->id), pd->psc, PSC_PTCMD);
+}
+
+u8 ti_pd_state(struct ti_pd *pd)
+{
+	return pd_read(pd, PSC_PDCTL) & PDCTL_STATE_MASK;
+}
+
+static int ti_pd_get(struct ti_pd *pd)
+{
+	u32 pdctl;
+	int ret;
+
+	pd->usecount++;
+
+	if (pd->usecount > 1)
+		return 0;
+
+	if (pd->depend) {
+		ret = ti_pd_get(pd->depend);
+		if (ret)
+			return ret;
+		ti_pd_transition(pd->depend);
+		ret = ti_pd_wait(pd->depend);
+		if (ret)
+			return ret;
+	}
+
+	pdctl = pd_read(pd, PSC_PDCTL);
+
+	if ((pdctl & PDCTL_STATE_MASK) == PDCTL_STATE_ON)
+		return 0;
+
+	debug("%s: enabling psc:%d, pd:%d\n", __func__, pd->psc->id, pd->id);
+
+	pdctl &= ~PDCTL_STATE_MASK;
+	pdctl |= PDCTL_STATE_ON;
+
+	pd_write(pdctl, pd, PSC_PDCTL);
+
+	return 0;
+}
+
+static int ti_pd_put(struct ti_pd *pd)
+{
+	u32 pdctl;
+	int ret;
+
+	pd->usecount--;
+
+	if (pd->usecount > 0)
+		return 0;
+
+	pdctl = pd_read(pd, PSC_PDCTL);
+	if ((pdctl & PDCTL_STATE_MASK) == PDCTL_STATE_OFF)
+		return 0;
+
+	pdctl &= ~PDCTL_STATE_MASK;
+	pdctl |= PDCTL_STATE_OFF;
+
+	debug("%s: disabling psc:%d, pd:%d\n", __func__, pd->psc->id, pd->id);
+
+	pd_write(pdctl, pd, PSC_PDCTL);
+
+	if (pd->depend) {
+		ti_pd_transition(pd);
+		ret = ti_pd_wait(pd);
+		if (ret)
+			return ret;
+
+		ret = ti_pd_put(pd->depend);
+		if (ret)
+			return ret;
+		ti_pd_transition(pd->depend);
+		ret = ti_pd_wait(pd->depend);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int ti_lpsc_wait(struct ti_lpsc *lpsc)
+{
+	u32 mdstat;
+	int ret;
+
+	ret = readl_poll_timeout(lpsc->psc->base + PSC_MDSTAT + lpsc->id * 4,
+				 mdstat,
+				 !(mdstat & MDSTAT_BUSY_MASK), LPSC_TIMEOUT);
+
+	if (ret)
+		printf("%s: module %d failed to transition.\n", __func__,
+		       lpsc->id);
+
+	return ret;
+}
+
+u8 lpsc_get_state(struct ti_lpsc *lpsc)
+{
+	return lpsc_read(lpsc, PSC_MDCTL) & MDSTAT_STATE_MASK;
+}
+
+int ti_lpsc_transition(struct ti_lpsc *lpsc, u8 state)
+{
+	struct ti_pd *psc_pd;
+	int ret;
+	u32 mdctl;
+
+	psc_pd = lpsc->pd;
+
+	if (state == MDSTAT_STATE_ENABLE) {
+		lpsc->usecount++;
+		if (lpsc->usecount > 1)
+			return 0;
+	} else {
+		lpsc->usecount--;
+		if (lpsc->usecount >= 1)
+			return 0;
+	}
+
+	debug("%s: transitioning psc:%d, lpsc:%d to %x\n", __func__,
+	      lpsc->psc->id, lpsc->id, state);
+
+	if (lpsc->depend)
+		ti_lpsc_transition(lpsc->depend, state);
+
+	mdctl = lpsc_read(lpsc, PSC_MDCTL);
+	if ((mdctl & MDSTAT_STATE_MASK) == state)
+		return 0;
+
+	if (state == MDSTAT_STATE_ENABLE)
+		ti_pd_get(psc_pd);
+	else
+		ti_pd_put(psc_pd);
+
+	mdctl &= ~MDSTAT_STATE_MASK;
+	mdctl |= state;
+
+	lpsc_write(mdctl, lpsc, PSC_MDCTL);
+
+	ti_pd_transition(psc_pd);
+	ret = ti_pd_wait(psc_pd);
+	if (ret)
+		return ret;
+
+	return ti_lpsc_wait(lpsc);
+}
+
+static int ti_power_domain_transition(struct power_domain *pd, u8 state)
+{
+	struct ti_lpsc *lpsc = pd->priv;
+
+	return ti_lpsc_transition(lpsc, state);
+}
+
+static int ti_power_domain_on(struct power_domain *pd)
+{
+	debug("%s(pd=%p, id=%lu)\n", __func__, pd, pd->id);
+
+	return ti_power_domain_transition(pd, MDSTAT_STATE_ENABLE);
+}
+
+static int ti_power_domain_off(struct power_domain *pd)
+{
+	debug("%s(pd=%p, id=%lu)\n", __func__, pd, pd->id);
+
+	return ti_power_domain_transition(pd, MDSTAT_STATE_SWRSTDISABLE);
+}
+
+static struct ti_lpsc *lpsc_lookup(struct ti_k3_pd_platdata *data, int id)
+{
+	int idx;
+
+	for (idx = 0; idx < data->num_devs; idx++)
+		if (data->devs[idx].id == id)
+			return data->devs[idx].lpsc;
+
+	return NULL;
+}
+
+static int ti_power_domain_of_xlate(struct power_domain *pd,
+				    struct ofnode_phandle_args *args)
+{
+	struct ti_k3_pd_platdata *data = dev_get_priv(pd->dev);
+	struct ti_lpsc *lpsc;
+
+	debug("%s(power_domain=%p, id=%d)\n", __func__, pd, args->args[0]);
+
+	if (args->args_count < 1) {
+		printf("Invalid args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	lpsc = lpsc_lookup(data, args->args[0]);
+	if (!lpsc) {
+		printf("%s: invalid dev-id: %d\n", __func__, args->args[0]);
+		return -ENOENT;
+	}
+
+	pd->id = lpsc->id;
+	pd->priv = lpsc;
+
+	return 0;
+}
+
+static int ti_power_domain_request(struct power_domain *pd)
+{
+	return 0;
+}
+
+static int ti_power_domain_free(struct power_domain *pd)
+{
+	return 0;
+}
+
+static const struct udevice_id ti_power_domain_of_match[] = {
+	{ .compatible = "ti,sci-pm-domain" },
+	{ /* sentinel */ }
+};
+
+static struct power_domain_ops ti_power_domain_ops = {
+	.on = ti_power_domain_on,
+	.off = ti_power_domain_off,
+	.of_xlate = ti_power_domain_of_xlate,
+	.request = ti_power_domain_request,
+	.rfree = ti_power_domain_free,
+};
+
+U_BOOT_DRIVER(ti_pm_domains) = {
+	.name = "ti-pm-domains",
+	.id = UCLASS_POWER_DOMAIN,
+	.of_match = ti_power_domain_of_match,
+	.probe = ti_power_domain_probe,
+	.priv_auto = sizeof(struct ti_k3_pd_platdata),
+	.ops = &ti_power_domain_ops,
+};
diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c
index 3c569a3b7b6..6f3e12d915e 100644
--- a/drivers/remoteproc/ti_k3_r5f_rproc.c
+++ b/drivers/remoteproc/ti_k3_r5f_rproc.c
@@ -804,19 +804,27 @@ static int k3_r5f_probe(struct udevice *dev)
 		return ret;
 	}
 
-	ret = core->tsp.sci->ops.dev_ops.is_on(core->tsp.sci, core->tsp.dev_id,
-					       &r_state, &core->in_use);
-	if (ret)
-		return ret;
+	/*
+	 * The PM functionality is not supported by the firmware during
+	 * SPL execution with the separated DM firmware image. The following
+	 * piece of code is not compiled in that case.
+	 */
+	if (!IS_ENABLED(CONFIG_K3_DM_FW)) {
+		ret = core->tsp.sci->ops.dev_ops.is_on(core->tsp.sci,
+						       core->tsp.dev_id,
+						       &r_state, &core->in_use);
+		if (ret)
+			return ret;
 
-	if (core->in_use) {
-		dev_info(dev, "Core %d is already in use. No rproc commands work\n",
-			 core->tsp.proc_id);
-		return 0;
-	}
+		if (core->in_use) {
+			dev_info(dev, "Core %d is already in use. No rproc commands work\n",
+				 core->tsp.proc_id);
+			return 0;
+		}
 
-	/* Make sure Local reset is asserted. Redundant? */
-	reset_assert(&core->reset);
+		/* Make sure Local reset is asserted. Redundant? */
+		reset_assert(&core->reset);
+	}
 
 	ret = k3_r5f_rproc_configure(core);
 	if (ret) {
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index c84a9d2b27b..cbdfddb80f6 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -188,4 +188,11 @@ config RTC_ABX80X
 	  families of ultra-low-power  battery- and capacitor-backed real-time
 	  clock chips.
 
+config RTC_DAVINCI
+	bool "Enable TI OMAP RTC driver"
+	depends on ARCH_DAVINCI || ARCH_OMAP2PLUS
+	help
+	  Say "yes" here to support the on chip real time clock
+	  present on TI OMAP1, AM33xx, DA8xx/OMAP-L13x, AM43xx and DRA7xx.
+
 endmenu
diff --git a/drivers/rtc/davinci.c b/drivers/rtc/davinci.c
index c446e7a735f..c7ce41bbf5c 100644
--- a/drivers/rtc/davinci.c
+++ b/drivers/rtc/davinci.c
@@ -2,81 +2,443 @@
 /*
  * (C) Copyright 2011 DENX Software Engineering GmbH
  * Heiko Schocher <[email protected]>
+ * Copyright (C) 2021 Dario Binacchi <[email protected]>
  */
 #include <common.h>
 #include <command.h>
+#include <dm.h>
+#include <clk.h>
 #include <log.h>
 #include <rtc.h>
 #include <asm/io.h>
-#include <asm/davinci_rtc.h>
+#include <dm/device_compat.h>
 #include <linux/delay.h>
 
-int rtc_get(struct rtc_time *tmp)
+/* RTC registers */
+#define OMAP_RTC_SECONDS_REG		0x00
+#define OMAP_RTC_MINUTES_REG		0x04
+#define OMAP_RTC_HOURS_REG		0x08
+#define OMAP_RTC_DAYS_REG		0x0C
+#define OMAP_RTC_MONTHS_REG		0x10
+#define OMAP_RTC_YEARS_REG		0x14
+#define OMAP_RTC_WEEKS_REG		0x18
+
+#define OMAP_RTC_CTRL_REG		0x40
+#define OMAP_RTC_STATUS_REG		0x44
+#define OMAP_RTC_INTERRUPTS_REG		0x48
+
+#define OMAP_RTC_OSC_REG		0x54
+
+#define OMAP_RTC_SCRATCH0_REG		0x60
+#define OMAP_RTC_SCRATCH1_REG		0x64
+#define OMAP_RTC_SCRATCH2_REG		0x68
+
+#define OMAP_RTC_KICK0_REG		0x6c
+#define OMAP_RTC_KICK1_REG		0x70
+
+#define OMAP_RTC_PMIC_REG		0x98
+
+/* OMAP_RTC_CTRL_REG bit fields: */
+#define OMAP_RTC_CTRL_SPLIT		BIT(7)
+#define OMAP_RTC_CTRL_DISABLE		BIT(6)
+#define OMAP_RTC_CTRL_SET_32_COUNTER	BIT(5)
+#define OMAP_RTC_CTRL_TEST		BIT(4)
+#define OMAP_RTC_CTRL_MODE_12_24	BIT(3)
+#define OMAP_RTC_CTRL_AUTO_COMP		BIT(2)
+#define OMAP_RTC_CTRL_ROUND_30S		BIT(1)
+#define OMAP_RTC_CTRL_STOP		BIT(0)
+
+/* OMAP_RTC_STATUS_REG bit fields */
+#define OMAP_RTC_STATUS_POWER_UP	BIT(7)
+#define OMAP_RTC_STATUS_ALARM2		BIT(7)
+#define OMAP_RTC_STATUS_ALARM		BIT(6)
+#define OMAP_RTC_STATUS_1D_EVENT	BIT(5)
+#define OMAP_RTC_STATUS_1H_EVENT	BIT(4)
+#define OMAP_RTC_STATUS_1M_EVENT	BIT(3)
+#define OMAP_RTC_STATUS_1S_EVENT	BIT(2)
+#define OMAP_RTC_STATUS_RUN		BIT(1)
+#define OMAP_RTC_STATUS_BUSY		BIT(0)
+
+/* OMAP_RTC_OSC_REG bit fields */
+#define OMAP_RTC_OSC_32KCLK_EN		BIT(6)
+#define OMAP_RTC_OSC_SEL_32KCLK_SRC	BIT(3)
+#define OMAP_RTC_OSC_OSC32K_GZ_DISABLE	BIT(4)
+
+/* OMAP_RTC_KICKER values */
+#define	OMAP_RTC_KICK0_VALUE		0x83e70b13
+#define	OMAP_RTC_KICK1_VALUE		0x95a4f1e0
+
+struct omap_rtc_device_type {
+	bool has_32kclk_en;
+	bool has_irqwakeen;
+	bool has_pmic_mode;
+	bool has_power_up_reset;
+};
+
+struct omap_rtc_priv {
+	fdt_addr_t base;
+	u8 max_reg;
+	struct udevice *dev;
+	struct clk clk;
+	bool has_ext_clk;
+	const struct omap_rtc_device_type *type;
+};
+
+static inline u8 omap_rtc_readb(struct omap_rtc_priv *priv, unsigned int reg)
 {
-	struct davinci_rtc *rtc = (struct davinci_rtc *)DAVINCI_RTC_BASE;
-	unsigned long sec, min, hour, mday, wday, mon_cent, year;
-	unsigned long status;
+	return readb(priv->base + reg);
+}
+
+static inline u32 omap_rtc_readl(struct omap_rtc_priv *priv, unsigned int reg)
+{
+	return readl(priv->base + reg);
+}
+
+static inline void omap_rtc_writeb(struct omap_rtc_priv *priv, unsigned int reg,
+				   u8 val)
+{
+	writeb(val, priv->base + reg);
+}
+
+static inline void omap_rtc_writel(struct omap_rtc_priv *priv, unsigned int reg,
+				   u32 val)
+{
+	writel(val, priv->base + reg);
+}
+
+static inline void omap_rtc_unlock(struct omap_rtc_priv *priv)
+{
+	omap_rtc_writel(priv, OMAP_RTC_KICK0_REG, OMAP_RTC_KICK0_VALUE);
+	omap_rtc_writel(priv, OMAP_RTC_KICK1_REG, OMAP_RTC_KICK1_VALUE);
+}
+
+static inline void omap_rtc_lock(struct omap_rtc_priv *priv)
+{
+	omap_rtc_writel(priv, OMAP_RTC_KICK0_REG, 0);
+	omap_rtc_writel(priv, OMAP_RTC_KICK1_REG, 0);
+}
 
-	status = readl(&rtc->status);
-	if ((status & RTC_STATE_RUN) != RTC_STATE_RUN) {
+static int omap_rtc_wait_not_busy(struct omap_rtc_priv *priv)
+{
+	int count;
+	u8 status;
+
+	status = omap_rtc_readb(priv, OMAP_RTC_STATUS_REG);
+	if ((status & OMAP_RTC_STATUS_RUN) != OMAP_RTC_STATUS_RUN) {
 		printf("RTC doesn't run\n");
 		return -1;
 	}
-	if ((status & RTC_STATE_BUSY) == RTC_STATE_BUSY)
-		udelay(20);
 
-	sec	= readl(&rtc->second);
-	min	= readl(&rtc->minutes);
-	hour	= readl(&rtc->hours);
-	mday	= readl(&rtc->day);
-	wday	= readl(&rtc->dotw);
-	mon_cent = readl(&rtc->month);
-	year	= readl(&rtc->year);
+	/* BUSY may stay active for 1/32768 second (~30 usec) */
+	for (count = 0; count < 50; count++) {
+		if (!(status & OMAP_RTC_STATUS_BUSY))
+			break;
+
+		udelay(1);
+		status = omap_rtc_readb(priv, OMAP_RTC_STATUS_REG);
+	}
+
+	/* now we have ~15 usec to read/write various registers */
+	return 0;
+}
+
+static int omap_rtc_reset(struct udevice *dev)
+{
+	struct omap_rtc_priv *priv = dev_get_priv(dev);
+
+	/* run RTC counter */
+	omap_rtc_writeb(priv, OMAP_RTC_CTRL_REG, 0x01);
+	return 0;
+}
+
+static int omap_rtc_set(struct udevice *dev, const struct rtc_time *tm)
+{
+	struct omap_rtc_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = omap_rtc_wait_not_busy(priv);
+	if (ret)
+		return ret;
+
+	omap_rtc_unlock(priv);
+	omap_rtc_writeb(priv, OMAP_RTC_YEARS_REG, bin2bcd(tm->tm_year % 100));
+	omap_rtc_writeb(priv, OMAP_RTC_MONTHS_REG, bin2bcd(tm->tm_mon));
+	omap_rtc_writeb(priv, OMAP_RTC_WEEKS_REG, bin2bcd(tm->tm_wday));
+	omap_rtc_writeb(priv, OMAP_RTC_DAYS_REG, bin2bcd(tm->tm_mday));
+	omap_rtc_writeb(priv, OMAP_RTC_HOURS_REG, bin2bcd(tm->tm_hour));
+	omap_rtc_writeb(priv, OMAP_RTC_MINUTES_REG, bin2bcd(tm->tm_min));
+	omap_rtc_writeb(priv, OMAP_RTC_SECONDS_REG, bin2bcd(tm->tm_sec));
+	omap_rtc_lock(priv);
+
+	dev_dbg(dev, "Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+		tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, tm->tm_hour,
+		tm->tm_min, tm->tm_sec);
+
+	return 0;
+}
 
-	debug("Get RTC year: %02lx mon/cent: %02lx mday: %02lx wday: %02lx "
+static int omap_rtc_get(struct udevice *dev, struct rtc_time *tm)
+{
+	struct omap_rtc_priv *priv = dev_get_priv(dev);
+	unsigned long sec, min, hour, mday, wday, mon_cent, year;
+	int ret;
+
+	ret = omap_rtc_wait_not_busy(priv);
+	if (ret)
+		return ret;
+
+	sec = omap_rtc_readb(priv, OMAP_RTC_SECONDS_REG);
+	min = omap_rtc_readb(priv, OMAP_RTC_MINUTES_REG);
+	hour = omap_rtc_readb(priv, OMAP_RTC_HOURS_REG);
+	mday = omap_rtc_readb(priv, OMAP_RTC_DAYS_REG);
+	wday = omap_rtc_readb(priv, OMAP_RTC_WEEKS_REG);
+	mon_cent = omap_rtc_readb(priv, OMAP_RTC_MONTHS_REG);
+	year = omap_rtc_readb(priv, OMAP_RTC_YEARS_REG);
+
+	dev_dbg(dev,
+		"Get RTC year: %02lx mon/cent: %02lx mday: %02lx wday: %02lx "
 		"hr: %02lx min: %02lx sec: %02lx\n",
 		year, mon_cent, mday, wday,
 		hour, min, sec);
 
-	tmp->tm_sec  = bcd2bin(sec  & 0x7F);
-	tmp->tm_min  = bcd2bin(min  & 0x7F);
-	tmp->tm_hour = bcd2bin(hour & 0x3F);
-	tmp->tm_mday = bcd2bin(mday & 0x3F);
-	tmp->tm_mon  = bcd2bin(mon_cent & 0x1F);
-	tmp->tm_year = bcd2bin(year) + 2000;
-	tmp->tm_wday = bcd2bin(wday & 0x07);
-	tmp->tm_yday = 0;
-	tmp->tm_isdst = 0;
+	tm->tm_sec  = bcd2bin(sec  & 0x7F);
+	tm->tm_min  = bcd2bin(min  & 0x7F);
+	tm->tm_hour = bcd2bin(hour & 0x3F);
+	tm->tm_mday = bcd2bin(mday & 0x3F);
+	tm->tm_mon  = bcd2bin(mon_cent & 0x1F);
+	tm->tm_year = bcd2bin(year) + 2000;
+	tm->tm_wday = bcd2bin(wday & 0x07);
+	tm->tm_yday = 0;
+	tm->tm_isdst = 0;
+
+	dev_dbg(dev, "Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+		tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, tm->tm_hour,
+		tm->tm_min, tm->tm_sec);
+
+	return 0;
+}
+
+static int omap_rtc_scratch_read(struct udevice *dev, uint offset,
+				 u8 *buffer, uint len)
+{
+	struct omap_rtc_priv *priv = dev_get_priv(dev);
+	u32 *val = (u32 *)buffer;
+	unsigned int reg;
+	int i;
 
-	debug("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
-		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
-		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+	if (len & 3)
+		return -EFAULT;
+
+	for (i = 0; i < len / 4; i++) {
+		reg = OMAP_RTC_SCRATCH0_REG + offset + (i * 4);
+		if (reg >= OMAP_RTC_KICK0_REG)
+			return -EFAULT;
+
+		val[i] = omap_rtc_readl(priv, reg);
+	}
 
 	return 0;
 }
 
-int rtc_set(struct rtc_time *tmp)
+static int omap_rtc_scratch_write(struct udevice *dev, uint offset,
+				  const u8 *buffer, uint len)
 {
-	struct davinci_rtc *rtc = (struct davinci_rtc *)DAVINCI_RTC_BASE;
+	struct omap_rtc_priv *priv = dev_get_priv(dev);
+	u32 *val = (u32 *)buffer;
+	unsigned int reg;
+	int i;
+
+	if (len & 3)
+		return -EFAULT;
 
-	debug("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
-		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
-		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
-	writel(bin2bcd(tmp->tm_year % 100), &rtc->year);
-	writel(bin2bcd(tmp->tm_mon), &rtc->month);
+	omap_rtc_unlock(priv);
+	for (i = 0; i < len / 4; i++) {
+		reg = OMAP_RTC_SCRATCH0_REG + offset + (i * 4);
+		if (reg >= OMAP_RTC_KICK0_REG)
+			return -EFAULT;
+
+		omap_rtc_writel(priv, reg, val[i]);
+	}
+	omap_rtc_lock(priv);
 
-	writel(bin2bcd(tmp->tm_wday), &rtc->dotw);
-	writel(bin2bcd(tmp->tm_mday), &rtc->day);
-	writel(bin2bcd(tmp->tm_hour), &rtc->hours);
-	writel(bin2bcd(tmp->tm_min), &rtc->minutes);
-	writel(bin2bcd(tmp->tm_sec), &rtc->second);
 	return 0;
 }
 
-void rtc_reset(void)
+static int omap_rtc_remove(struct udevice *dev)
 {
-	struct davinci_rtc *rtc = (struct davinci_rtc *)DAVINCI_RTC_BASE;
+	struct omap_rtc_priv *priv = dev_get_priv(dev);
+	u8 reg;
 
-	/* run RTC counter */
-	writel(0x01, &rtc->ctrl);
+	if (priv->clk.dev)
+		clk_disable(&priv->clk);
+
+	omap_rtc_unlock(priv);
+
+	/* leave rtc running, but disable irqs */
+	omap_rtc_writeb(priv, OMAP_RTC_INTERRUPTS_REG, 0);
+
+	if (priv->has_ext_clk) {
+		reg = omap_rtc_readb(priv, OMAP_RTC_OSC_REG);
+		reg &= ~OMAP_RTC_OSC_SEL_32KCLK_SRC;
+		omap_rtc_writeb(priv, OMAP_RTC_OSC_REG, reg);
+	}
+
+	omap_rtc_lock(priv);
+	return 0;
 }
+
+static int omap_rtc_probe(struct udevice *dev)
+{
+	struct omap_rtc_priv *priv = dev_get_priv(dev);
+	struct rtc_time tm;
+	u8 reg, mask, new_ctrl;
+
+	priv->dev = dev;
+	priv->type = (struct omap_rtc_device_type *)dev_get_driver_data(dev);
+	priv->max_reg = OMAP_RTC_PMIC_REG;
+
+	if (!clk_get_by_name(dev, "ext-clk", &priv->clk))
+		priv->has_ext_clk = true;
+	else
+		clk_get_by_name(dev, "int-clk", &priv->clk);
+
+	if (priv->clk.dev)
+		clk_enable(&priv->clk);
+	else
+		dev_warn(dev, "missing clock\n");
+
+	omap_rtc_unlock(priv);
+
+	/*
+	 * disable interrupts
+	 *
+	 * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used
+	 */
+	omap_rtc_writel(priv, OMAP_RTC_INTERRUPTS_REG, 0);
+
+	if (priv->type->has_32kclk_en) {
+		reg = omap_rtc_readb(priv, OMAP_RTC_OSC_REG);
+		omap_rtc_writeb(priv, OMAP_RTC_OSC_REG,
+				reg | OMAP_RTC_OSC_32KCLK_EN);
+	}
+
+	/* clear old status */
+	reg = omap_rtc_readb(priv, OMAP_RTC_STATUS_REG);
+
+	mask = OMAP_RTC_STATUS_ALARM;
+
+	if (priv->type->has_pmic_mode)
+		mask |= OMAP_RTC_STATUS_ALARM2;
+
+	if (priv->type->has_power_up_reset) {
+		mask |= OMAP_RTC_STATUS_POWER_UP;
+		if (reg & OMAP_RTC_STATUS_POWER_UP)
+			dev_info(dev, "RTC power up reset detected\n");
+	}
+
+	if (reg & mask)
+		omap_rtc_writeb(priv, OMAP_RTC_STATUS_REG, reg & mask);
+
+	/* On boards with split power, RTC_ON_NOFF won't reset the RTC */
+	reg = omap_rtc_readb(priv, OMAP_RTC_CTRL_REG);
+	if (reg & OMAP_RTC_CTRL_STOP)
+		dev_info(dev, "already running\n");
+
+	/* force to 24 hour mode */
+	new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP);
+	new_ctrl |= OMAP_RTC_CTRL_STOP;
+
+	/*
+	 * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
+	 *
+	 *  - Device wake-up capability setting should come through chip
+	 *    init logic. OMAP1 boards should initialize the "wakeup capable"
+	 *    flag in the platform device if the board is wired right for
+	 *    being woken up by RTC alarm. For OMAP-L138, this capability
+	 *    is built into the SoC by the "Deep Sleep" capability.
+	 *
+	 *  - Boards wired so RTC_ON_nOFF is used as the reset signal,
+	 *    rather than nPWRON_RESET, should forcibly enable split
+	 *    power mode.  (Some chip errata report that RTC_CTRL_SPLIT
+	 *    is write-only, and always reads as zero...)
+	 */
+
+	if (new_ctrl & OMAP_RTC_CTRL_SPLIT)
+		dev_info(dev, "split power mode\n");
+
+	if (reg != new_ctrl)
+		omap_rtc_writeb(priv, OMAP_RTC_CTRL_REG, new_ctrl);
+
+	/*
+	 * If we have the external clock then switch to it so we can keep
+	 * ticking across suspend.
+	 */
+	if (priv->has_ext_clk) {
+		reg = omap_rtc_readb(priv, OMAP_RTC_OSC_REG);
+		reg &= ~OMAP_RTC_OSC_OSC32K_GZ_DISABLE;
+		reg |= OMAP_RTC_OSC_32KCLK_EN | OMAP_RTC_OSC_SEL_32KCLK_SRC;
+		omap_rtc_writeb(priv, OMAP_RTC_OSC_REG, reg);
+	}
+
+	omap_rtc_lock(priv);
+
+	if (omap_rtc_get(dev, &tm)) {
+		dev_err(dev, "failed to get datetime\n");
+	} else if (tm.tm_year == 2000 && tm.tm_mon == 1 && tm.tm_mday == 1 &&
+		   tm.tm_wday == 0) {
+		tm.tm_wday = 6;
+		omap_rtc_set(dev, &tm);
+	}
+
+	return 0;
+}
+
+static int omap_rtc_of_to_plat(struct udevice *dev)
+{
+	struct omap_rtc_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_read_addr(dev);
+	if (priv->base == FDT_ADDR_T_NONE) {
+		dev_err(dev, "invalid address\n");
+		return -EINVAL;
+	}
+
+	dev_dbg(dev, "base=%pa\n", &priv->base);
+	return 0;
+}
+
+static const struct rtc_ops omap_rtc_ops = {
+	.get = omap_rtc_get,
+	.set = omap_rtc_set,
+	.reset = omap_rtc_reset,
+	.read = omap_rtc_scratch_read,
+	.write = omap_rtc_scratch_write,
+};
+
+static const struct omap_rtc_device_type omap_rtc_am3352_type = {
+	.has_32kclk_en	= true,
+	.has_irqwakeen	= true,
+	.has_pmic_mode	= true,
+};
+
+static const struct omap_rtc_device_type omap_rtc_da830_type = {
+	.has_32kclk_en	= false,
+	.has_irqwakeen	= false,
+	.has_pmic_mode	= false,
+};
+
+static const struct udevice_id omap_rtc_ids[] = {
+	{.compatible = "ti,am3352-rtc", .data = (ulong)&omap_rtc_am3352_type},
+	{.compatible = "ti,da830-rtc", .data = (ulong)&omap_rtc_da830_type }
+};
+
+U_BOOT_DRIVER(omap_rtc) = {
+	.name = "omap_rtc",
+	.id = UCLASS_RTC,
+	.of_match = omap_rtc_ids,
+	.ops = &omap_rtc_ops,
+	.of_to_plat = omap_rtc_of_to_plat,
+	.probe = omap_rtc_probe,
+	.remove = omap_rtc_remove,
+	.priv_auto = sizeof(struct omap_rtc_priv),
+};
diff --git a/drivers/soc/ti/k3-navss-ringacc-u-boot.c b/drivers/soc/ti/k3-navss-ringacc-u-boot.c
new file mode 100644
index 00000000000..f958239c2af
--- /dev/null
+++ b/drivers/soc/ti/k3-navss-ringacc-u-boot.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot specific helpers for TI K3 AM65x NAVSS Ring accelerator
+ * Manager (RA) subsystem driver
+ *
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+struct k3_nav_ring_cfg_regs {
+	u32	resv_64[16];
+	u32	ba_lo;		/* Ring Base Address Lo Register */
+	u32	ba_hi;		/* Ring Base Address Hi Register */
+	u32	size;		/* Ring Size Register */
+	u32	event;		/* Ring Event Register */
+	u32	orderid;	/* Ring OrderID Register */
+};
+
+#define KNAV_RINGACC_CFG_REGS_STEP	0x100
+
+#define KNAV_RINGACC_CFG_RING_BA_HI_ADDR_HI_MASK	GENMASK(15, 0)
+
+#define KNAV_RINGACC_CFG_RING_SIZE_QMODE_MASK		GENMASK(31, 30)
+#define KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT		(30)
+
+#define KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_MASK		GENMASK(26, 24)
+#define KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_SHIFT		(24)
+
+static void k3_ringacc_ring_reset_raw(struct k3_nav_ring *ring)
+{
+	writel(0, &ring->cfg->size);
+}
+
+static void k3_ringacc_ring_reconfig_qmode_raw(struct k3_nav_ring *ring, enum k3_nav_ring_mode mode)
+{
+	u32 val;
+
+	val = readl(&ring->cfg->size);
+	val &= KNAV_RINGACC_CFG_RING_SIZE_QMODE_MASK;
+	val |= mode << KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT;
+	writel(val, &ring->cfg->size);
+}
+
+static void k3_ringacc_ring_free_raw(struct k3_nav_ring *ring)
+{
+	writel(0, &ring->cfg->ba_hi);
+	writel(0, &ring->cfg->ba_lo);
+	writel(0, &ring->cfg->size);
+}
+
+static void k3_nav_ringacc_ring_cfg_raw(struct k3_nav_ring *ring)
+{
+	u32 val;
+
+	writel(lower_32_bits(ring->ring_mem_dma), &ring->cfg->ba_lo);
+	writel(upper_32_bits(ring->ring_mem_dma), &ring->cfg->ba_hi);
+
+	val = ring->mode << KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT |
+	      ring->elm_size << KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_SHIFT |
+	      ring->size;
+	writel(val, &ring->cfg->size);
+}
diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c
index b5a5c9da98a..f110d78ce10 100644
--- a/drivers/soc/ti/k3-navss-ringacc.c
+++ b/drivers/soc/ti/k3-navss-ringacc.c
@@ -124,6 +124,7 @@ struct k3_nav_ring_state {
 /**
  * struct k3_nav_ring - RA Ring descriptor
  *
+ * @cfg - Ring configuration registers
  * @rt - Ring control/status registers
  * @fifos - Ring queues registers
  * @ring_mem_dma - Ring buffer dma address
@@ -138,6 +139,7 @@ struct k3_nav_ring_state {
  * @use_count - Use count for shared rings
  */
 struct k3_nav_ring {
+	struct k3_nav_ring_cfg_regs __iomem *cfg;
 	struct k3_nav_ring_rt_regs __iomem *rt;
 	struct k3_nav_ring_fifo_regs __iomem *fifos;
 	dma_addr_t	ring_mem_dma;
@@ -195,6 +197,8 @@ struct k3_nav_ringacc {
 	bool dual_ring;
 };
 
+#include "k3-navss-ringacc-u-boot.c"
+
 static int k3_nav_ringacc_ring_read_occ(struct k3_nav_ring *ring)
 {
 	return readl(&ring->rt->occ) & KNAV_RINGACC_RT_OCC_MASK;
@@ -330,6 +334,9 @@ static void k3_ringacc_ring_reset_sci(struct k3_nav_ring *ring)
 	struct k3_nav_ringacc *ringacc = ring->parent;
 	int ret;
 
+	if (IS_ENABLED(CONFIG_K3_DM_FW))
+		return k3_ringacc_ring_reset_raw(ring);
+
 	ret = ringacc->tisci_ring_ops->config(
 			ringacc->tisci,
 			TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID,
@@ -362,6 +369,9 @@ static void k3_ringacc_ring_reconfig_qmode_sci(struct k3_nav_ring *ring,
 	struct k3_nav_ringacc *ringacc = ring->parent;
 	int ret;
 
+	if (IS_ENABLED(CONFIG_K3_DM_FW))
+		return k3_ringacc_ring_reconfig_qmode_raw(ring, mode);
+
 	ret = ringacc->tisci_ring_ops->config(
 			ringacc->tisci,
 			TI_SCI_MSG_VALUE_RM_RING_MODE_VALID,
@@ -442,6 +452,9 @@ static void k3_ringacc_ring_free_sci(struct k3_nav_ring *ring)
 	struct k3_nav_ringacc *ringacc = ring->parent;
 	int ret;
 
+	if (IS_ENABLED(CONFIG_K3_DM_FW))
+		return k3_ringacc_ring_free_raw(ring);
+
 	ret = ringacc->tisci_ring_ops->config(
 			ringacc->tisci,
 			TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER,
@@ -531,11 +544,21 @@ static int k3_nav_ringacc_ring_cfg_sci(struct k3_nav_ring *ring)
 			ring->mode,
 			ring->elm_size,
 			0);
-	if (ret)
+	if (ret) {
 		dev_err(ringacc->dev, "TISCI config ring fail (%d) ring_idx %d\n",
 			ret, ring_idx);
+		return ret;
+	}
 
-	return ret;
+	/*
+	 * Above TI SCI call handles firewall configuration, cfg
+	 * register configuration still has to be done locally in
+	 * absence of RM services.
+	 */
+	if (IS_ENABLED(CONFIG_K3_DM_FW))
+		k3_nav_ringacc_ring_cfg_raw(ring);
+
+	return 0;
 }
 
 static int k3_dmaring_ring_cfg(struct k3_nav_ring *ring, struct k3_nav_ring_cfg *cfg)
@@ -951,13 +974,18 @@ static int k3_nav_ringacc_probe_dt(struct k3_nav_ringacc *ringacc)
 
 static int k3_nav_ringacc_init(struct udevice *dev, struct k3_nav_ringacc *ringacc)
 {
-	void __iomem *base_rt;
+	void __iomem *base_cfg, *base_rt;
 	int ret, i;
 
 	ret = k3_nav_ringacc_probe_dt(ringacc);
 	if (ret)
 		return ret;
 
+	base_cfg = dev_remap_addr_name(dev, "cfg");
+	pr_debug("cfg %p\n", base_cfg);
+	if (!base_cfg)
+		return -EINVAL;
+
 	base_rt = (uint32_t *)devfdt_get_addr_name(dev, "rt");
 	pr_debug("rt %p\n", base_rt);
 	if (IS_ERR(base_rt))
@@ -975,6 +1003,8 @@ static int k3_nav_ringacc_init(struct udevice *dev, struct k3_nav_ringacc *ringa
 		return -ENOMEM;
 
 	for (i = 0; i < ringacc->num_rings; i++) {
+		ringacc->rings[i].cfg = base_cfg +
+					KNAV_RINGACC_CFG_REGS_STEP * i;
 		ringacc->rings[i].rt = base_rt +
 				       KNAV_RINGACC_RT_REGS_STEP * i;
 		ringacc->rings[i].parent = ringacc;