diff options
| author | Sam Protsenko <[email protected]> | 2025-10-25 20:06:56 -0500 |
|---|---|---|
| committer | Peng Fan <[email protected]> | 2025-11-07 09:28:29 +0800 |
| commit | 1e665e543c51d665f3fe1f8dc428f86198812ead (patch) | |
| tree | 0ad2cf29b8cdeac8a2cbc54f5f95fcba1fd008cb /drivers | |
| parent | 6f0845fcb2ca687e346b74caae62c5ad418b1879 (diff) | |
mmc: exynos_dw_mmc: Add quirk for disabling FMP
Add DWMCI_QUIRK_DISABLE_FMP which disables Flash Memory Protector (FMP)
during driver's init. It's usually done by early bootloaders, but in
some cases (like USB boot) the FMP may be left unconfigured. The issue
was observed on Exynos850 SoC (the E850-96 board). Enabling this quirk
makes eMMC functional even in such cases.
No functional change, as this feature is only added here but not enabled
for any chips yet.
Signed-off-by: Sam Protsenko <[email protected]>
Reviewed-by: Anand Moon <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mmc/exynos_dw_mmc.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 51867a55249..be17bc4692c 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -35,8 +35,16 @@ * * %DWMCI_QUIRK_DISABLE_SMU: DW MMC block has Security Management Unit (SMU) * which has to be configured in non-encryption mode during driver's init. + * + * %DWMCI_QUIRK_DISABLE_FMP: DW MMC block has Flash Memory Protector (FMP) which + * has to be disabled during driver's init. This flag disables FMP encryption + * and lets external non-secure main CPUs access the SFR (peripheral memory + * region, i.e. registers) in MMC core. Although it's usually done by early + * bootloaders (before U-Boot), in some cases like during USB boot the FMP might + * be left unconfigured. */ #define DWMCI_QUIRK_DISABLE_SMU BIT(0) +#define DWMCI_QUIRK_DISABLE_FMP BIT(1) #ifdef CONFIG_DM_MMC #include <dm.h> @@ -225,6 +233,18 @@ static void exynos_dwmci_board_init(struct dwmci_host *host) MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID); } + if (priv->chip->quirks & DWMCI_QUIRK_DISABLE_FMP) { + u32 reg; + + reg = dwmci_readl(host, EMMCP_MPSECURITY); + if (reg & MPSECURITY_FMP_ON || + reg & MPSECURITY_MMC_SFR_PROT_ON) { + reg &= ~MPSECURITY_FMP_ON; + reg &= ~MPSECURITY_MMC_SFR_PROT_ON; + dwmci_writel(host, EMMCP_MPSECURITY, reg); + } + } + if (priv->sdr_timing) exynos_dwmci_clksel(host); } |