diff options
| author | Svyatoslav Ryhel <[email protected]> | 2023-02-14 19:35:28 +0200 |
|---|---|---|
| committer | Tom <[email protected]> | 2023-02-23 12:55:36 -0700 |
| commit | 23d24df34cdd8157d10d302dbba798cd0b518451 (patch) | |
| tree | ca3a22a2a0c544666bfe65fbaadbe2a984fe0b2c /drivers | |
| parent | 678157e212ea9871e03896adf3297ebb61c912db (diff) | |
ARM: tegra: Fix Tegra PWM parent clock
Default parent clock for the PWM on Tegra is a 32kHz clock and
is unable to support the requested PWM period.
Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by
updating the parent clock for the PWM to be the PLL_P.
This commit is equivalent to Linux kernel commit:
https://lore.kernel.org/all/[email protected]/
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS TF T30
Tested-by: Robert Eckelmann <[email protected]> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <[email protected]> # ASUS TF201 T30
Tested-by: Thierry Reding <[email protected]> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Signed-off-by: Tom <[email protected]>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/pwm/tegra_pwm.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/pwm/tegra_pwm.c b/drivers/pwm/tegra_pwm.c index 36c35c608b2..95fc26458b8 100644 --- a/drivers/pwm/tegra_pwm.c +++ b/drivers/pwm/tegra_pwm.c @@ -20,19 +20,21 @@ static int tegra_pwm_set_config(struct udevice *dev, uint channel, { struct tegra_pwm_priv *priv = dev_get_priv(dev); struct pwm_ctlr *regs = priv->regs; + const u32 pwm_max_freq = dev_get_driver_data(dev); uint pulse_width; u32 reg; if (channel >= 4) return -EINVAL; debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel); - /* We ignore the period here and just use 32KHz */ - clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, 32768); + + clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_PERIPH, pwm_max_freq); pulse_width = duty_ns * 255 / period_ns; reg = pulse_width << PWM_WIDTH_SHIFT; reg |= 1 << PWM_DIVIDER_SHIFT; + reg |= PWM_ENABLE_MASK; writel(reg, ®s[channel].control); debug("%s: pulse_width=%u\n", __func__, pulse_width); @@ -68,8 +70,8 @@ static const struct pwm_ops tegra_pwm_ops = { }; static const struct udevice_id tegra_pwm_ids[] = { - { .compatible = "nvidia,tegra124-pwm" }, - { .compatible = "nvidia,tegra20-pwm" }, + { .compatible = "nvidia,tegra20-pwm", .data = 48 * 1000000 }, + { .compatible = "nvidia,tegra114-pwm", .data = 408 * 1000000 }, { } }; |