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authorJonas Karlman <[email protected]>2024-05-01 16:22:19 +0000
committerKever Yang <[email protected]>2024-05-07 15:56:08 +0800
commit24463b15831cafb61868e7a1b079892bd1bb33b2 (patch)
tree1170db5c054fba62c89e6cf1cd59672bb6b5fbb3 /drivers
parentfc4572ae753f62fc26fa8361d5269d9c33505850 (diff)
clk: rockchip: rk3399: Add dummy support for ACLK_VDU clock
rk3399.dtsi from linux v5.19 and newer try to set VDU clock rate to 400 MHz using an assigned-clock-rates prop of the CRU node. U-Boot does not use or need this clock so add dummy support for getting and setting ACLK_VDU clock rate to allow CRU driver to be loaded with an updated rk3399.dtsi. Signed-off-by: Jonas Karlman <[email protected]> Reviewed-by: Kever Yang <[email protected]>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/rockchip/clk_rk3399.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index f0ce54067f8..5934771b409 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -971,6 +971,7 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
case ACLK_HDCP:
case ACLK_GIC_PRE:
case PCLK_DDR:
+ case ACLK_VDU:
break;
case PCLK_ALIVE:
case PCLK_WDT:
@@ -1061,6 +1062,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
case ACLK_HDCP:
case ACLK_GIC_PRE:
case PCLK_DDR:
+ case ACLK_VDU:
return 0;
default:
log_debug("Unknown clock %lu\n", clk->id);