diff options
| author | Christoph Muellner <[email protected]> | 2019-05-07 10:58:44 +0200 |
|---|---|---|
| committer | Kever Yang <[email protected]> | 2019-05-30 18:22:35 +0800 |
| commit | 24615436321894867cb7d4c0bd4e6b928150c112 (patch) | |
| tree | 4d51cd9723bf6be7a3d17804d188939e2d5caa37 /drivers | |
| parent | 78a1ac33cb9621f3fde31fa747a4b03ae0772d7f (diff) | |
rockchip: clk: rk3399: allow requests for all UART clocks
This patch adds the rate for UART1 and UART3 the same way
as already implemented for UART0 and UART2.
This is required for boards, which have their console output
on these UARTs.
Signed-off-by: Christoph Muellner <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3399.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 93a652e5ff4..aa6a8ad1c9c 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -912,7 +912,9 @@ static ulong rk3399_clk_get_rate(struct clk *clk) rate = rk3399_spi_get_clk(priv->cru, clk->id); break; case SCLK_UART0: + case SCLK_UART1: case SCLK_UART2: + case SCLK_UART3: return 24000000; break; case PCLK_HDMI_CTRL: |