Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

- Add lx2162 soc, lx2162qds support.
- Bug-fixes related ls102x-usb, ifc, bootcmd, secure-boot header,
- rgmii, vid, fdt, env variable, pci for Layerscape products

11 files changed, 102 insertions, 23 deletions

diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index f75d97b15c4..5f62489a90f 100644
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -47,6 +47,7 @@ config SYS_NUM_DDR_CTLRS
 			ARCH_P5020	|| \
 			ARCH_P5040	|| \
 			ARCH_LX2160A	|| \
+			ARCH_LX2162A	|| \
 			ARCH_T4160
 	default 1
 
diff --git a/drivers/net/fsl-mc/Kconfig b/drivers/net/fsl-mc/Kconfig
index 2cf651d3b3e..ae4c35799bf 100644
--- a/drivers/net/fsl-mc/Kconfig
+++ b/drivers/net/fsl-mc/Kconfig
@@ -4,7 +4,7 @@
 
 menuconfig FSL_MC_ENET
 	bool "NXP Management Complex"
-	depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
+	depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A || ARCH_LX2162A
 	default y
 	select RESV_RAM
 	help
@@ -17,7 +17,7 @@ if FSL_MC_ENET
 config SYS_MC_RSV_MEM_ALIGN
 	hex "Management Complex reserved memory alignment"
 	depends on RESV_RAM
-	default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
+	default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A || ARCH_LX2162A
 	help
 	  Reserved memory needs to be aligned for MC to use. Default value
 	  is 512MB.
diff --git a/drivers/net/ldpaa_eth/Makefile b/drivers/net/ldpaa_eth/Makefile
index 1d85b2cfa8a..52ab828f0b8 100644
--- a/drivers/net/ldpaa_eth/Makefile
+++ b/drivers/net/ldpaa_eth/Makefile
@@ -7,3 +7,4 @@ obj-y += ldpaa_eth.o
 obj-$(CONFIG_ARCH_LS2080A) += ls2080a.o
 obj-$(CONFIG_ARCH_LS1088A) += ls1088a.o
 obj-$(CONFIG_ARCH_LX2160A) += lx2160a.o
+obj-$(CONFIG_ARCH_LX2162A) += lx2160a.o
diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c
index d414c750d42..41999e176d4 100644
--- a/drivers/net/pfe_eth/pfe_firmware.c
+++ b/drivers/net/pfe_eth/pfe_firmware.c
@@ -10,6 +10,8 @@
  * files.
  */
 
+#include <dm.h>
+#include <dm/device-internal.h>
 #include <image.h>
 #include <log.h>
 #include <malloc.h>
@@ -24,6 +26,9 @@
 #define PFE_FIRMWARE_FIT_CNF_NAME	"config@1"
 
 static const void *pfe_fit_addr;
+#ifdef CONFIG_CHAIN_OF_TRUST
+static const void *pfe_esbc_hdr_addr;
+#endif
 
 /*
  * PFE elf firmware loader.
@@ -169,7 +174,7 @@ int pfe_spi_flash_init(void)
 	struct spi_flash *pfe_flash;
 	struct udevice *new;
 	int ret = 0;
-	void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+	void *addr = malloc(CONFIG_SYS_LS_PFE_FW_LENGTH);
 
 	if (!addr)
 		return -ENOMEM;
@@ -179,21 +184,56 @@ int pfe_spi_flash_init(void)
 				     CONFIG_ENV_SPI_MAX_HZ,
 				     CONFIG_ENV_SPI_MODE,
 				     &new);
+	if (ret) {
+		printf("SF: failed to probe spi\n");
+		free(addr);
+		device_remove(new, DM_REMOVE_NORMAL);
+		return ret;
+	}
+
 
 	pfe_flash = dev_get_uclass_priv(new);
 	if (!pfe_flash) {
 		printf("SF: probe for pfe failed\n");
 		free(addr);
+		device_remove(new, DM_REMOVE_NORMAL);
 		return -ENODEV;
 	}
 
 	ret = spi_flash_read(pfe_flash,
 			     CONFIG_SYS_LS_PFE_FW_ADDR,
-			     CONFIG_SYS_QE_FMAN_FW_LENGTH,
+			     CONFIG_SYS_LS_PFE_FW_LENGTH,
 			     addr);
-	if (ret)
+	if (ret) {
 		printf("SF: read for pfe failed\n");
+		free(addr);
+		spi_flash_free(pfe_flash);
+		return ret;
+	}
 
+#ifdef CONFIG_CHAIN_OF_TRUST
+	void *hdr_addr = malloc(CONFIG_SYS_LS_PFE_ESBC_LENGTH);
+
+	if (!hdr_addr) {
+		free(addr);
+		spi_flash_free(pfe_flash);
+		return -ENOMEM;
+	}
+
+	ret = spi_flash_read(pfe_flash,
+			     CONFIG_SYS_LS_PFE_ESBC_ADDR,
+			     CONFIG_SYS_LS_PFE_ESBC_LENGTH,
+			     hdr_addr);
+	if (ret) {
+		printf("SF: failed to read pfe esbc header\n");
+		free(addr);
+		free(hdr_addr);
+		spi_flash_free(pfe_flash);
+		return ret;
+	}
+
+	pfe_esbc_hdr_addr = hdr_addr;
+#endif
 	pfe_fit_addr = addr;
 	spi_flash_free(pfe_flash);
 
@@ -233,7 +273,7 @@ int pfe_firmware_init(void)
 		goto err;
 
 #ifdef CONFIG_CHAIN_OF_TRUST
-	pfe_esbc_hdr = CONFIG_SYS_LS_PFE_ESBC_ADDR;
+	pfe_esbc_hdr = (uintptr_t)pfe_esbc_hdr_addr;
 	pfe_img_addr = (uintptr_t)pfe_fit_addr;
 	if (fsl_check_boot_mode_secure() != 0) {
 		/*
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 4e1a93be221..51733dd1237 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -100,6 +100,15 @@ config PHY_BROADCOM
 config PHY_CORTINA
 	bool "Cortina Ethernet PHYs support"
 
+config SYS_CORTINA_NO_FW_UPLOAD
+	bool "Cortina firmware loading support"
+	default n
+	depends on PHY_CORTINA
+	help
+		Cortina phy has provision to store phy firmware in attached dedicated
+		EEPROM. And boards designed with such EEPROM does not require firmware
+		upload.
+
 choice
 	prompt "Location of the Cortina firmware"
 	default SYS_CORTINA_FW_IN_NOR
diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c
index dbc20b14051..b381a431fd9 100644
--- a/drivers/net/phy/cortina.c
+++ b/drivers/net/phy/cortina.c
@@ -3,7 +3,7 @@
  * Cortina CS4315/CS4340 10G PHY drivers
  *
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018, 2020 NXP
  *
  */
 
@@ -29,7 +29,7 @@
 #error The Cortina PHY needs 10G support
 #endif
 
-#ifndef CORTINA_NO_FW_UPLOAD
+#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
 struct cortina_reg_config cortina_reg_cfg[] = {
 	/* CS4315_enable_sr_mode */
 	{VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
@@ -227,7 +227,7 @@ void cs4340_upload_firmware(struct phy_device *phydev)
 
 int cs4340_phy_init(struct phy_device *phydev)
 {
-#ifndef CORTINA_NO_FW_UPLOAD
+#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
 	int timeout = 100;  /* 100ms */
 #endif
 	int reg_value;
@@ -238,7 +238,7 @@ int cs4340_phy_init(struct phy_device *phydev)
 	 * Boards designed with EEPROM attached to Cortina
 	 * does not require FW upload.
 	 */
-#ifndef CORTINA_NO_FW_UPLOAD
+#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
 	/* step1: BIST test */
 	phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL,     0x0004);
 	phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000);
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index af927849508..65498bce1d9 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -219,7 +219,7 @@ config FSL_PCIE_COMPAT
 	default "fsl,ls1046a-pcie" if ARCH_LS1046A
 	default "fsl,ls2080a-pcie" if ARCH_LS2080A
 	default "fsl,ls1088a-pcie" if ARCH_LS1088A
-	default "fsl,lx2160a-pcie" if ARCH_LX2160A
+	default "fsl,lx2160a-pcie" if ARCH_LX2160A || ARCH_LX2162A
 	default "fsl,ls1021a-pcie" if ARCH_LS1021A
 	help
 	  This compatible is used to find pci controller node in Kernel DT
@@ -228,7 +228,7 @@ config FSL_PCIE_COMPAT
 config FSL_PCIE_EP_COMPAT
 	string "PCIe EP compatible of Kernel DT"
 	depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4
-	default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A
+	default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A || ARCH_LX2162A
 	default "fsl,ls-pcie-ep"
 	help
 	  This compatible is used to find pci controller ep node in Kernel DT
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index eba230e3a5f..d7d4a44b228 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <asm/arch/fsl_serdes.h>
 #include <dm.h>
 #include <dm/devres.h>
 #include <errno.h>
@@ -272,7 +273,9 @@ static int ls_pcie_ep_probe(struct udevice *dev)
 
 	svr = SVR_SOC_VER(get_svr());
 
-	if (svr == SVR_LX2160A)
+	if (svr == SVR_LX2160A || svr == SVR_LX2162A ||
+	    svr == SVR_LX2120A || svr == SVR_LX2080A ||
+	    svr == SVR_LX2122A || svr == SVR_LX2082A)
 		pcie_ep->pf1_offset = LX2160_PCIE_PF1_OFFSET;
 	else
 		pcie_ep->pf1_offset = LS_PCIE_PF1_OFFSET;
@@ -294,7 +297,8 @@ static int ls_pcie_ep_probe(struct udevice *dev)
 	pcie_ep->num_ob_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 					      "num-ob-windows", 8);
 
-	printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
+	printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+	       "Endpoint");
 	ls_pcie_setup_ep(pcie_ep);
 
 	if (!ls_pcie_link_up(pcie)) {
diff --git a/drivers/pci/pcie_layerscape_fixup_common.c b/drivers/pci/pcie_layerscape_fixup_common.c
index 0a42997696b..40f0ef10ac4 100644
--- a/drivers/pci/pcie_layerscape_fixup_common.c
+++ b/drivers/pci/pcie_layerscape_fixup_common.c
@@ -99,6 +99,8 @@ int lx2_board_fix_fdt(void *fdt)
 		if (!prop) {
 			printf("%s: Failed to fixup PCIe EP node @0x%x\n",
 			       __func__, off);
+			off = fdt_node_offset_by_compatible(fdt, off,
+							    "fsl,lx2160a-pcie-ep");
 			continue;
 		}
 
@@ -121,13 +123,16 @@ int pcie_board_fix_fdt(void *fdt)
 
 	svr = SVR_SOC_VER(get_svr());
 
-	if (svr == SVR_LX2160A && IS_SVR_REV(get_svr(), 2, 0))
+	if ((svr == SVR_LX2160A || svr == SVR_LX2162A ||
+	     svr == SVR_LX2120A || svr == SVR_LX2080A ||
+	     svr == SVR_LX2122A || svr == SVR_LX2082A) &&
+	     IS_SVR_REV(get_svr(), 2, 0))
 		return lx2_board_fix_fdt(fdt);
 
 	return 0;
 }
 
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 /* returns the next available streamid for pcie, -errno if failed */
 int pcie_next_streamid(int currentid, int idx)
 {
diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c
index 428bfcab09f..6e71173621f 100644
--- a/drivers/pci/pcie_layerscape_gen4.c
+++ b/drivers/pci/pcie_layerscape_gen4.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2020 NXP
  *
  * PCIe Gen4 driver for NXP Layerscape SoCs
  * Author: Hou Zhiqiang <[email protected]>
@@ -455,6 +455,7 @@ static int ls_pcie_g4_probe(struct udevice *dev)
 	u32 link_ctrl_sta;
 	u32 val;
 	int ret;
+	fdt_size_t cfg_size;
 
 	pcie->bus = dev;
 
@@ -472,7 +473,8 @@ static int ls_pcie_g4_probe(struct udevice *dev)
 
 	pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
 	if (!pcie->enabled) {
-		printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
+		printf("PCIe%d: %s disabled\n", PCIE_SRDS_PRTCL(pcie->idx),
+		       dev->name);
 		return 0;
 	}
 
@@ -487,6 +489,13 @@ static int ls_pcie_g4_probe(struct udevice *dev)
 		return ret;
 	}
 
+	cfg_size = fdt_resource_size(&pcie->cfg_res);
+	if (cfg_size < SZ_4K) {
+		printf("PCIe%d: %s Invalid size(0x%llx) for resource \"config\",expected minimum 0x%x\n",
+		       PCIE_SRDS_PRTCL(pcie->idx), dev->name, cfg_size, SZ_4K);
+		return 0;
+	}
+
 	pcie->cfg = map_physmem(pcie->cfg_res.start,
 				fdt_resource_size(&pcie->cfg_res),
 				MAP_NOCACHE);
@@ -522,10 +531,12 @@ static int ls_pcie_g4_probe(struct udevice *dev)
 	pcie->mode = readb(pcie->ccsr + PCI_HEADER_TYPE) & 0x7f;
 
 	if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
-		printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
+		printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+		       "Endpoint");
 		ls_pcie_g4_setup_ep(pcie);
 	} else {
-		printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
+		printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+		       "Root Complex");
 		ls_pcie_g4_setup_ctrl(pcie);
 	}
 
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
index 25c6ddebce0..cdfcad6b0be 100644
--- a/drivers/pci/pcie_layerscape_rc.c
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -273,7 +273,8 @@ static int ls_pcie_probe(struct udevice *dev)
 
 	pcie_rc->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
 	if (!pcie_rc->enabled) {
-		printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
+		printf("PCIe%d: %s disabled\n", PCIE_SRDS_PRTCL(pcie->idx),
+		       dev->name);
 		return 0;
 	}
 
@@ -313,6 +314,13 @@ static int ls_pcie_probe(struct udevice *dev)
 		return ret;
 	}
 
+	cfg_size = fdt_resource_size(&pcie_rc->cfg_res);
+	if (cfg_size < SZ_8K) {
+		printf("PCIe%d: %s Invalid size(0x%llx) for resource \"config\",expected minimum 0x%x\n",
+		       PCIE_SRDS_PRTCL(pcie->idx), dev->name, (u64)cfg_size, SZ_8K);
+		return 0;
+	}
+
 	/*
 	 * Fix the pcie memory map address and PF control registers address
 	 * for LS2088A series SoCs
@@ -322,7 +330,6 @@ static int ls_pcie_probe(struct udevice *dev)
 	if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
 	    svr == SVR_LS2048A || svr == SVR_LS2044A ||
 	    svr == SVR_LS2081A || svr == SVR_LS2041A) {
-		cfg_size = fdt_resource_size(&pcie_rc->cfg_res);
 		pcie_rc->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
 					 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
 		pcie_rc->cfg_res.end = pcie_rc->cfg_res.start + cfg_size;
@@ -342,7 +349,8 @@ static int ls_pcie_probe(struct udevice *dev)
 	      (unsigned long)pcie->ctrl, (unsigned long)pcie_rc->cfg0,
 	      pcie->big_endian);
 
-	printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
+	printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+	       "Root Complex");
 	ls_pcie_setup_ctrl(pcie_rc);
 
 	if (!ls_pcie_link_up(pcie)) {