diff options
| author | Michal Simek <[email protected]> | 2025-11-10 13:33:32 +0100 |
|---|---|---|
| committer | Michal Simek <[email protected]> | 2025-12-19 08:25:26 +0100 |
| commit | 2b7255cfa06ccd967583b035622476a42043131e (patch) | |
| tree | 02a89109ccf105bb64505286213cf618c2cd0bb8 /drivers | |
| parent | 16f0332b180321c1c0a2f8decc6005e37202bcc9 (diff) | |
clk: versal: Add support for CLK_AUTO_ID
When CLK_AUTO_ID is enabled 8 higher bits of clk->id is unique clock
identifier in clk uclass that's why it is necessary to mask lower bits
which are clock ID.
Also check that ID not bigger then maximum supported clock.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/647f1d2c7d274c1106558a655386ef92e0baf2c8.1762778011.git.michal.simek@amd.com
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/clk_versal.c | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index 0c754943ded..ddaff07de0f 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -712,10 +712,13 @@ static int versal_clk_probe(struct udevice *dev) static ulong versal_clk_get_rate(struct clk *clk) { struct versal_clk_priv *priv = dev_get_priv(clk->dev); - u32 id = clk->id; + u32 id = clk_get_id(clk); u32 clk_id; u64 clk_rate = 0; + if (id >= clock_max_idx) + return -ENODEV; + debug("%s\n", __func__); clk_id = priv->clk[id].clk_id; @@ -728,7 +731,7 @@ static ulong versal_clk_get_rate(struct clk *clk) static ulong versal_clk_set_rate(struct clk *clk, ulong rate) { struct versal_clk_priv *priv = dev_get_priv(clk->dev); - u32 id = clk->id; + u32 id = clk_get_id(clk); u32 clk_id; u64 clk_rate = 0; u32 div; @@ -736,6 +739,9 @@ static ulong versal_clk_set_rate(struct clk *clk, ulong rate) debug("%s\n", __func__); + if (id >= clock_max_idx) + return -ENODEV; + clk_id = priv->clk[id].clk_id; ret = versal_clock_get_rate(clk_id, &clk_rate); @@ -766,9 +772,13 @@ static ulong versal_clk_set_rate(struct clk *clk, ulong rate) static int versal_clk_enable(struct clk *clk) { struct versal_clk_priv *priv = dev_get_priv(clk->dev); + u32 id = clk_get_id(clk); u32 clk_id; - clk_id = priv->clk[clk->id].clk_id; + if (id >= clock_max_idx) + return -ENODEV; + + clk_id = priv->clk[id].clk_id; if (versal_clock_gate(clk_id)) { return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, |