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authorJonas Schwöbel <[email protected]>2025-03-11 23:11:47 +0100
committerSvyatoslav Ryhel <[email protected]>2026-03-22 14:43:26 +0200
commit2fcb08a2b477667741f194b8b8a8a08a711dc974 (patch)
tree57bebbbd761c0075b91d48c71620c31ac666091d /drivers
parent0623b8512e2d9128100949ca80ede990ed80f741 (diff)
pwm: tegra: fix pulse_width calculation
The pulse_width is expressed as N/256. A 100% duty cycle is only possible when multiplied by 256 instead of 255. Signed-off-by: Jonas Schwöbel <[email protected]> Signed-off-by: Svyatoslav Ryhel <[email protected]>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pwm/tegra_pwm.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pwm/tegra_pwm.c b/drivers/pwm/tegra_pwm.c
index 4b57751f73f..4bbfeba8d98 100644
--- a/drivers/pwm/tegra_pwm.c
+++ b/drivers/pwm/tegra_pwm.c
@@ -40,7 +40,7 @@ static int tegra_pwm_set_config(struct udevice *dev, uint channel,
return -EINVAL;
debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel);
- pulse_width = duty_ns * 255 / period_ns;
+ pulse_width = duty_ns * 256 / period_ns;
if (priv->polarity & BIT(channel))
pulse_width = 256 - pulse_width;