Merge tag 'net-next-20260603' of https://source.denx.de/u-boot/custodians/u-boot-net into next

Pull request net-next-20260603

- eth, phy: Convert several drivers to use the dev APIs
- Guard SYS_RX_ETH_BUFFER with NET
- phy: Kconfig: use bool instead of tristate

16 files changed, 90 insertions, 74 deletions

diff --git a/drivers/net/calxedaxgmac.c b/drivers/net/calxedaxgmac.c
index 92990fa6d47..df0ed820e06 100644
--- a/drivers/net/calxedaxgmac.c
+++ b/drivers/net/calxedaxgmac.c
@@ -555,7 +555,7 @@ static int xgmac_ofdata_to_platdata(struct udevice *dev)
 		return -ENOMEM;
 	dev_set_priv(dev, priv);
 
-	pdata->iobase = devfdt_get_addr(dev);
+	pdata->iobase = dev_read_addr(dev);
 	if (pdata->iobase == FDT_ADDR_T_NONE) {
 		printf("%s: Cannot find XGMAC base address\n", __func__);
 		return -EINVAL;
diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c
index 8fa549280aa..2a21eceac57 100644
--- a/drivers/net/dc2114x.c
+++ b/drivers/net/dc2114x.c
@@ -653,7 +653,7 @@ static int dc2114x_of_to_plat(struct udevice *dev)
 	struct eth_pdata *plat = dev_get_plat(dev);
 	struct dc2114x_priv *priv = dev_get_priv(dev);
 
-	plat->iobase = (phys_addr_t)map_physmem((phys_addr_t)devfdt_get_addr(dev), 0, MAP_NOCACHE);
+	plat->iobase = (phys_addr_t)dev_remap_addr(dev);
 	priv->iobase = (void *)plat->iobase;
 
 	return 0;
diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c
index dc7e6f1929f..87b2b3426c8 100644
--- a/drivers/net/ethoc.c
+++ b/drivers/net/ethoc.c
@@ -686,7 +686,7 @@ static int ethoc_of_to_plat(struct udevice *dev)
 	fdt_addr_t addr;
 
 	pdata->eth_pdata.iobase = dev_read_addr(dev);
-	addr = devfdt_get_addr_index(dev, 1);
+	addr = dev_read_addr_index(dev, 1);
 	if (addr != FDT_ADDR_T_NONE)
 		pdata->packet_base = addr;
 	return 0;
diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index f9e979c4d58..fc137df14c4 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -4731,33 +4731,32 @@ static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
 
 static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
 {
-	int port_node = dev_of_offset(dev);
-	int phy_node;
+	ofnode port_node = dev_ofnode(dev);
+	ofnode phy_node;
 	u32 id;
 	int phyaddr = 0;
-	int fixed_link = 0;
+	ofnode fixed_link;
 	int ret;
 
-	phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
-	fixed_link = fdt_subnode_offset(gd->fdt_blob, port_node, "fixed-link");
+	phy_node = ofnode_parse_phandle(port_node, "phy", 0);
+	fixed_link = ofnode_find_subnode(port_node, "fixed-link");
 
-	if (phy_node > 0) {
-		int parent;
+	if (ofnode_valid(phy_node)) {
+		ofnode parent;
 
-		if (fixed_link != -FDT_ERR_NOTFOUND) {
+		if (ofnode_valid(fixed_link)) {
 			/* phy_addr is set to invalid value for fixed links */
 			phyaddr = PHY_MAX_ADDR;
 		} else {
-			phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node,
-						 "reg", 0);
+			phyaddr = ofnode_read_s32_default(phy_node, "reg", 0);
 			if (phyaddr < 0) {
 				dev_err(dev, "could not find phy address\n");
 				return -1;
 			}
 		}
-		parent = fdt_parent_offset(gd->fdt_blob, phy_node);
-		ret = uclass_get_device_by_of_offset(UCLASS_MDIO, parent,
-						     &port->mdio_dev);
+		parent = ofnode_get_parent(phy_node);
+		ret = uclass_get_device_by_ofnode(UCLASS_MDIO, parent,
+						  &port->mdio_dev);
 		if (ret)
 			return ret;
 	} else {
@@ -4771,7 +4770,7 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
 		return -EINVAL;
 	}
 
-	id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1);
+	id = dev_read_s32_default(dev, "port-id", -1);
 	if (id == -1) {
 		dev_err(dev, "missing port-id value\n");
 		return -EINVAL;
@@ -4812,7 +4811,7 @@ static void mvpp2_gpio_init(struct mvpp2_port *port)
 /* Ports initialization */
 static int mvpp2_port_probe(struct udevice *dev,
 			    struct mvpp2_port *port,
-			    int port_node,
+			    ofnode port_node,
 			    struct mvpp2 *priv)
 {
 	int err;
@@ -5296,16 +5295,16 @@ static int mvpp2_base_probe(struct udevice *dev)
 	}
 
 	/* Save base addresses for later use */
-	priv->base = devfdt_get_addr_index_ptr(dev, 0);
+	priv->base = dev_read_addr_index_ptr(dev, 0);
 	if (!priv->base)
 		return -EINVAL;
 
 	if (priv->hw_version == MVPP21) {
-		priv->lms_base = devfdt_get_addr_index_ptr(dev, 1);
+		priv->lms_base = dev_read_addr_index_ptr(dev, 1);
 		if (!priv->lms_base)
 			return -EINVAL;
 	} else {
-		priv->iface_base = devfdt_get_addr_index_ptr(dev, 1);
+		priv->iface_base = dev_read_addr_index_ptr(dev, 1);
 		if (!priv->iface_base)
 			return -EINVAL;
 
@@ -5346,13 +5345,11 @@ static int mvpp2_probe(struct udevice *dev)
 	if (priv->hw_version == MVPP21) {
 		int priv_common_regs_num = 2;
 
-		port->base = devfdt_get_addr_index_ptr(
-			dev->parent, priv_common_regs_num + port->id);
+		port->base = dev_read_addr_index_ptr(dev->parent, priv_common_regs_num + port->id);
 		if (!port->base)
 			return -EINVAL;
 	} else {
-		port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-					      "gop-port-id", -1);
+		port->gop_id = ofnode_read_s32_default(dev_ofnode(dev), "gop-port-id", -1);
 		if (port->gop_id == -1) {
 			dev_err(dev, "missing gop-port-id value\n");
 			return -EINVAL;
@@ -5376,7 +5373,7 @@ static int mvpp2_probe(struct udevice *dev)
 		priv->probe_done = 1;
 	}
 
-	err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
+	err = mvpp2_port_probe(dev, port, dev_ofnode(dev), priv);
 	if (err)
 		return err;
 
@@ -5437,13 +5434,11 @@ static struct driver mvpp2_driver = {
  */
 static int mvpp2_base_bind(struct udevice *parent)
 {
-	const void *blob = gd->fdt_blob;
-	int node = dev_of_offset(parent);
 	struct uclass_driver *drv;
 	struct udevice *dev;
 	struct eth_pdata *plat;
 	char *name;
-	int subnode;
+	ofnode subnode;
 	u32 id;
 	int base_id_add;
 
@@ -5456,19 +5451,19 @@ static int mvpp2_base_bind(struct udevice *parent)
 
 	base_id_add = base_id;
 
-	fdt_for_each_subnode(subnode, blob, node) {
+	dev_for_each_subnode(subnode, parent) {
 		/* Increment base_id for all subnodes, also the disabled ones */
 		base_id++;
 
 		/* Skip disabled ports */
-		if (!fdtdec_get_is_enabled(blob, subnode))
+		if (!ofnode_is_enabled(subnode))
 			continue;
 
 		plat = calloc(1, sizeof(*plat));
 		if (!plat)
 			return -ENOMEM;
 
-		id = fdtdec_get_int(blob, subnode, "port-id", -1);
+		id = ofnode_read_s32_default(subnode, "port-id", -1);
 		id += base_id_add;
 
 		name = calloc(1, 16);
@@ -5479,8 +5474,7 @@ static int mvpp2_base_bind(struct udevice *parent)
 		sprintf(name, "mvpp2-%d", id);
 
 		/* Create child device UCLASS_ETH and bind it */
-		device_bind(parent, &mvpp2_driver, name, plat,
-			    offset_to_ofnode(subnode), &dev);
+		device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev);
 	}
 
 	return 0;
diff --git a/drivers/net/qe/dm_qe_uec.c b/drivers/net/qe/dm_qe_uec.c
index ac3aedd8b49..f9bc5d49c8f 100644
--- a/drivers/net/qe/dm_qe_uec.c
+++ b/drivers/net/qe/dm_qe_uec.c
@@ -1133,7 +1133,7 @@ static int qe_uec_of_to_plat(struct udevice *dev)
 {
 	struct eth_pdata *pdata = dev_get_plat(dev);
 
-	pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
+	pdata->iobase = (phys_addr_t)dev_read_addr(dev);
 
 	pdata->phy_interface = dev_read_phy_mode(dev);
 	if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index bd4ebdd745a..d03368b9408 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -37,6 +37,23 @@
 		)
 #endif /* CFG_TSEC_TBICR_SETTINGS */
 
+struct tsec_private {
+	struct txbd8 __iomem txbd[TX_BUF_CNT];
+	struct rxbd8 __iomem rxbd[PKTBUFSRX];
+	struct tsec __iomem *regs;
+	struct tsec_mii_mng __iomem *phyregs_sgmii;
+	struct phy_device *phydev;
+	phy_interface_t interface;
+	struct mii_dev *bus;
+	uint phyaddr;
+	uint tbiaddr;
+	char mii_devname[16];
+	u32 flags;
+	uint rx_idx;	/* index of the current RX buffer */
+	uint tx_idx;	/* index of the current TX buffer */
+	struct udevice *dev;
+};
+
 /* Configure the TBI for SGMII operation */
 static void tsec_configure_serdes(struct tsec_private *priv)
 {
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 5c8ec2b146f..eafa82fe494 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -114,7 +114,7 @@ config BCM_SR_PCIE_PHY
 	  If unsure, say N.
 
 config PHY_DA8XX_USB
-	tristate "TI DA8xx USB PHY Driver"
+	bool "TI DA8xx USB PHY Driver"
 	depends on PHY && ARCH_DAVINCI
 	help
 	  Enable this to support the USB PHY on DA8xx SoCs.
@@ -138,7 +138,7 @@ config SPL_PIPE3_PHY
 	  and omap5
 
 config AM654_PHY
-	tristate "TI AM654 SERDES support"
+	bool "TI AM654 SERDES support"
 	depends on PHY && ARCH_K3
 	select REGMAP
 	select SYSCON
@@ -155,7 +155,7 @@ config STI_USB_PHY
 	  STiH407 SoC families.
 
 config PHY_RCAR_GEN2
-	tristate "Renesas R-Car Gen2 USB PHY"
+	bool "Renesas R-Car Gen2 USB PHY"
 	depends on PHY && RCAR_GEN2
 	help
 	  Support for the Renesas R-Car Gen2 USB PHY. This driver operates the
@@ -163,7 +163,7 @@ config PHY_RCAR_GEN2
 	  allows configuring the module multiplexing.
 
 config PHY_RCAR_GEN3
-	tristate "Renesas R-Car Gen3 USB PHY"
+	bool "Renesas R-Car Gen3 USB PHY"
 	depends on PHY && CLK && DM_REGULATOR && (RCAR_GEN3 || RZG2L)
 	default y if (RCAR_GEN3 || RZG2L)
 	help
@@ -171,7 +171,7 @@ config PHY_RCAR_GEN3
 	  PHY connected to EHCI USB module and controls USB OTG operation.
 
 config PHY_STM32_USBPHYC
-	tristate "STMicroelectronics STM32 SoC USB HS PHY driver"
+	bool "STMicroelectronics STM32 SoC USB HS PHY driver"
 	depends on PHY && ARCH_STM32MP
 	help
 	  Enable this to support the High-Speed USB transceiver that is part of
@@ -283,7 +283,7 @@ config PHY_MTK_TPHY
 	  so you can easily distinguish them by banks layout.
 
 config PHY_MTK_UFS
-	tristate "MediaTek UFS M-PHY driver"
+	bool "MediaTek UFS M-PHY driver"
 	depends on ARCH_MEDIATEK
 	depends on PHY
 	help
@@ -337,7 +337,7 @@ config PHY_IMX8M_PCIE
 	  This PHY is found on i.MX8M devices supporting PCIe.
 
 config PHY_XILINX_ZYNQMP
-	tristate "Xilinx ZynqMP PHY driver"
+	bool "Xilinx ZynqMP PHY driver"
 	depends on PHY && ARCH_ZYNQMP
 	help
 	  Enable this to support ZynqMP High Speed Gigabit Transceiver
diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
index 8c0ab80fbbc..f5f096889fe 100644
--- a/drivers/phy/cadence/Kconfig
+++ b/drivers/phy/cadence/Kconfig
@@ -1,11 +1,11 @@
 config PHY_CADENCE_SIERRA
-	tristate "Cadence Sierra PHY Driver"
+	bool "Cadence Sierra PHY Driver"
 	depends on DM_RESET
 	help
 	  Enable this to support the Cadence Sierra PHY driver
 
 config PHY_CADENCE_TORRENT
-	tristate "Cadence Torrent PHY Driver"
+	bool "Cadence Torrent PHY Driver"
 	depends on DM_RESET
 	help
 	  Enable this to support the Cadence Torrent PHY driver
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index bd7ab9d1b77..9f8a6d8d43d 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -1068,12 +1068,12 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
 
 	sp->dev = dev;
 
-	sp->base =  devfdt_remap_addr_index(dev, 0);
+	sp->base = dev_remap_addr_index(dev, 0);
 	if (!sp->base) {
 		dev_err(dev, "unable to map regs\n");
 		return -ENOMEM;
 	}
-	devfdt_get_addr_size_index(dev, 0, (fdt_size_t *)&sp->size);
+	dev_read_addr_size_index(dev, 0, (fdt_size_t *)&sp->size);
 
 	/* Get init data for this PHY */
 	data = (struct cdns_sierra_data *)dev_get_driver_data(dev);
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index 933533b2b0b..814aff15070 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -791,10 +791,10 @@ static int cdns_torrent_phy_probe(struct udevice *dev)
 		return ret;
 	}
 
-	cdns_phy->sd_base = devfdt_remap_addr_index(dev, 0);
-	if (IS_ERR(cdns_phy->sd_base))
-		return PTR_ERR(cdns_phy->sd_base);
-	devfdt_get_addr_size_index(dev, 0, (fdt_size_t *)&cdns_phy->size);
+	cdns_phy->sd_base = dev_remap_addr_index(dev, 0);
+	if (!cdns_phy->sd_base)
+		return -EINVAL;
+	dev_read_addr_size_index(dev, 0, (fdt_size_t *)&cdns_phy->size);
 
 	dev_for_each_subnode(child, dev)
 		subnodes++;
diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c
index b074d58f9f6..0ab5f9a3f0a 100644
--- a/drivers/phy/marvell/comphy_core.c
+++ b/drivers/phy/marvell/comphy_core.c
@@ -84,11 +84,11 @@ static int comphy_probe(struct udevice *dev)
 	int res;
 
 	/* Save base addresses for later use */
-	chip_cfg->comphy_base_addr = devfdt_get_addr_index_ptr(dev, 0);
+	chip_cfg->comphy_base_addr = dev_read_addr_index_ptr(dev, 0);
 	if (!chip_cfg->comphy_base_addr)
 		return -EINVAL;
 
-	chip_cfg->hpipe3_base_addr = devfdt_get_addr_index_ptr(dev, 1);
+	chip_cfg->hpipe3_base_addr = dev_read_addr_index_ptr(dev, 1);
 	if (!chip_cfg->hpipe3_base_addr)
 		return -EINVAL;
 
diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig
index 49f830abf01..7094903d869 100644
--- a/drivers/phy/qcom/Kconfig
+++ b/drivers/phy/qcom/Kconfig
@@ -7,7 +7,7 @@ config MSM8916_USB_PHY
 	  This PHY is found on qualcomm dragonboard410c development board.
 
 config PHY_QCOM_IPQ4019_USB
-	tristate "Qualcomm IPQ4019 USB PHY driver"
+	bool "Qualcomm IPQ4019 USB PHY driver"
 	depends on PHY && ARCH_IPQ40XX
 	help
 	  Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
@@ -21,26 +21,26 @@ config PHY_QCOM_QMP_COMBO
 	  PHY (USB3 + DisplayPort). Currently only USB3 mode is supported.
 
 config PHY_QCOM_QMP_PCIE
-	tristate "Qualcomm QMP PCIe PHY driver"
+	bool "Qualcomm QMP PCIe PHY driver"
 	depends on PHY && ARCH_SNAPDRAGON
 	help
 	  Enable this to support the PCIe QMP PHY on various Qualcomm chipsets.
 
 config PHY_QCOM_QMP_UFS
-	tristate "Qualcomm QMP UFS PHY driver"
+	bool "Qualcomm QMP UFS PHY driver"
 	depends on PHY && ARCH_SNAPDRAGON
 	help
 	  Enable this to support the UFS QMP PHY on various Qualcomm chipsets.
 
 config PHY_QCOM_QUSB2
-	tristate "Qualcomm USB QUSB2 PHY driver"
+	bool "Qualcomm USB QUSB2 PHY driver"
 	depends on PHY && ARCH_SNAPDRAGON
 	help
 	  Enable this to support the Super-Speed USB transceiver on various
 	  Qualcomm chipsets.
 
 config PHY_QCOM_USB_SNPS_FEMTO_V2
-	tristate "Qualcomm SNPS FEMTO USB HS PHY v2"
+	bool "Qualcomm SNPS FEMTO USB HS PHY v2"
 	depends on PHY && ARCH_SNAPDRAGON
 	help
 	  Enable this to support the Qualcomm Synopsys DesignWare Core 7nm
@@ -48,7 +48,7 @@ config PHY_QCOM_USB_SNPS_FEMTO_V2
 	  is usually paired with Synopsys DWC3 USB IPs on MSM SOCs.
 
 config PHY_QCOM_SNPS_EUSB2
-	tristate "Qualcomm Synopsys eUSB2 High-Speed PHY"
+	bool "Qualcomm Synopsys eUSB2 High-Speed PHY"
 	depends on PHY && ARCH_SNAPDRAGON
 	help
 	  Enable this to support the Qualcomm Synopsys DesignWare eUSB2
@@ -56,7 +56,7 @@ config PHY_QCOM_SNPS_EUSB2
 	  is usually paired with Synopsys DWC3 USB IPs on MSM SOCs.
 
 config PHY_QCOM_USB_HS_28NM
-	tristate "Qualcomm 28nm High-Speed PHY"
+	bool "Qualcomm 28nm High-Speed PHY"
 	depends on PHY && ARCH_SNAPDRAGON
 	help
 	  Enable this to support the Qualcomm Synopsys DesignWare Core 28nm
@@ -65,7 +65,7 @@ config PHY_QCOM_USB_HS_28NM
 	  IPs on MSM SOCs.
 
 config PHY_QCOM_USB_SS
-	tristate "Qualcomm USB Super-Speed PHY driver"
+	bool "Qualcomm USB Super-Speed PHY driver"
 	depends on PHY && ARCH_SNAPDRAGON
 	help
 	  Enable this to support the Super-Speed USB transceiver on various
diff --git a/drivers/phy/renesas/Kconfig b/drivers/phy/renesas/Kconfig
index affbee0500c..3358d454e59 100644
--- a/drivers/phy/renesas/Kconfig
+++ b/drivers/phy/renesas/Kconfig
@@ -3,19 +3,19 @@
 # Phy drivers for Renesas platforms
 
 config PHY_R8A779F0_ETHERNET_SERDES
-	tristate "Renesas R-Car S4-8 Ethernet SERDES driver"
+	bool "Renesas R-Car S4-8 Ethernet SERDES driver"
 	depends on RCAR_64 && PHY
 	help
 	  Support for Ethernet SERDES found on Renesas R-Car S4-8 SoCs.
 
 config PHY_R8A78000_ETHERNET_PCS
-	tristate "Renesas R-Car X5H Ethernet PCS driver"
+	bool "Renesas R-Car X5H Ethernet PCS driver"
 	depends on RCAR_64 && PHY
 	help
 	  Support for Ethernet PCS found on Renesas R-Car X5H SoCs.
 
 config PHY_R8A78000_MP_PHY
-	tristate "Renesas R-Car X5H Multi-Protocol PHY driver"
+	bool "Renesas R-Car X5H Multi-Protocol PHY driver"
 	depends on RCAR_64 && PHY
 	help
 	  Support for Multi-Protocol PHY on Renesas R-Car X5H SoCs.
diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index 80128335d52..6f3d7ebe29e 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -49,7 +49,7 @@ config PHY_ROCKCHIP_SNPS_PCIE3
 	  also be able splited into multiple combinations of lanes.
 
 config PHY_ROCKCHIP_USBDP
-	tristate "Rockchip USBDP COMBO PHY Driver"
+	bool "Rockchip USBDP COMBO PHY Driver"
 	depends on ARCH_ROCKCHIP
 	select PHY
 	help
diff --git a/drivers/phy/ti-pipe3-phy.c b/drivers/phy/ti-pipe3-phy.c
index 62f6cc2bfbf..080016ba417 100644
--- a/drivers/phy/ti-pipe3-phy.c
+++ b/drivers/phy/ti-pipe3-phy.c
@@ -6,6 +6,7 @@
 
 #include <dm.h>
 #include <dm/device.h>
+#include <dm/device_compat.h>
 #include <generic-phy.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
@@ -428,10 +429,10 @@ static int pipe3_exit(struct phy *phy)
 
 static void *get_reg(struct udevice *dev, const char *name)
 {
+	struct ofnode_phandle_args phandle;
 	struct udevice *syscon;
 	struct regmap *regmap;
-	const fdt32_t *cell;
-	int len, err;
+	int err;
 	void *base;
 
 	err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
@@ -449,10 +450,14 @@ static void *get_reg(struct udevice *dev, const char *name)
 		return NULL;
 	}
 
-	cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), name,
-			   &len);
-	if (len < 2*sizeof(fdt32_t)) {
-		pr_err("offset not available for %s\n", name);
+	err = dev_read_phandle_with_args(dev, name, NULL, 0, 0, &phandle);
+	if (err) {
+		dev_err(dev, "parse %s failed: %d\n", name, err);
+		return NULL;
+	}
+
+	if (phandle.args_count < 1) {
+		dev_err(dev, "%s: missing args\n", name);
 		return NULL;
 	}
 
@@ -460,7 +465,7 @@ static void *get_reg(struct udevice *dev, const char *name)
 	if (!base)
 		return NULL;
 
-	return fdtdec_get_number(cell + 1, 1) + base;
+	return base + phandle.args[0];
 }
 
 static int pipe3_phy_probe(struct udevice *dev)
@@ -471,7 +476,7 @@ static int pipe3_phy_probe(struct udevice *dev)
 	struct pipe3_data *data;
 
 	/* PHY_RX */
-	addr = devfdt_get_addr_size_index(dev, 0, &sz);
+	addr = dev_read_addr_size_index(dev, 0, &sz);
 	if (addr == FDT_ADDR_T_NONE) {
 		pr_err("missing phy_rx address\n");
 		return -EINVAL;
@@ -484,7 +489,7 @@ static int pipe3_phy_probe(struct udevice *dev)
 	}
 
 	/* PLLCTRL */
-	addr = devfdt_get_addr_size_index(dev, 2, &sz);
+	addr = dev_read_addr_size_index(dev, 2, &sz);
 	if (addr == FDT_ADDR_T_NONE) {
 		pr_err("missing pll ctrl address\n");
 		return -EINVAL;
diff --git a/drivers/phy/ti/Kconfig b/drivers/phy/ti/Kconfig
index df750b26d66..fe96eb6806f 100644
--- a/drivers/phy/ti/Kconfig
+++ b/drivers/phy/ti/Kconfig
@@ -1,5 +1,5 @@
 config PHY_J721E_WIZ
-	tristate "TI J721E WIZ (SERDES Wrapper) support"
+	bool "TI J721E WIZ (SERDES Wrapper) support"
 	depends on ARCH_K3
 	help
 	  This option enables support for WIZ module present in TI's J721E