Merge tag 'u-boot-at91-2022.07-b' of https://source.denx.de/u-boot/custodians/u-boot-at91

Second set of u-boot-at91 features for the 2022.07 cycle:

This feature set includes the new driver for the AT91 reset controller,
a new board called sam9x60 curiosity, and several other fixes and
clean-ups (sama7g5ek qspi clock, impedance; remove unused code,
introduce Kconfig symbols for SPL timers)

6 files changed, 110 insertions, 2 deletions

diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
index 098298336da..cb64119f972 100644
--- a/drivers/spi/atmel-quadspi.c
+++ b/drivers/spi/atmel-quadspi.c
@@ -438,6 +438,9 @@ static bool atmel_qspi_supports_op(struct spi_slave *slave,
 {
 	struct atmel_qspi *aq = dev_get_priv(slave->dev->parent);
 
+	if (!spi_mem_default_supports_op(slave, op))
+		return false;
+
 	if (aq->caps->octal) {
 		if (atmel_qspi_sama7g5_find_mode(op) < 0)
 			return false;
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index f6d60038b89..25dd02c7049 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -77,6 +77,21 @@ config SYSRESET_OCTEON
 	  This enables the system reset driver support for Marvell Octeon
 	  SoCs.
 
+config SYSRESET_AT91
+	bool "Enable support for Microchip/Atmel reset driver"
+	depends on ARCH_AT91
+	select SYSRESET_SPL_AT91 if SPL && SPL_SYSRESET
+	help
+	  This enables the system reset driver support for Microchip/Atmel
+	  SoCs.
+
+config SYSRESET_SPL_AT91
+	bool "Enable support for Microchip/Atmel reset driver in SPL"
+	depends on ARCH_AT91
+	help
+	  This enables the system reset driver support for Microchip/Atmel
+	  SoCs in SPL.
+
 config SYSRESET_PSCI
 	bool "Enable support for PSCI System Reset"
 	depends on ARM_PSCI_FW
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 8e00be07794..0ed3bbf356a 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -20,5 +20,6 @@ obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o
 obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
 obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
 obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o
+obj-$(CONFIG_SYSRESET_$(SPL_TPL_)AT91) += sysreset_at91.o
 obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o
 obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
diff --git a/drivers/sysreset/sysreset_at91.c b/drivers/sysreset/sysreset_at91.c
new file mode 100644
index 00000000000..24b87ee987d
--- /dev/null
+++ b/drivers/sysreset/sysreset_at91.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
+ */
+
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/at91_rstc.h>
+#include <clk.h>
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/device-internal.h>
+#include <sysreset.h>
+
+static int at91_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+	at91_rstc_t *rstc = (at91_rstc_t *)dev_get_priv(dev);
+
+	writel(AT91_RSTC_KEY
+		| AT91_RSTC_CR_PROCRST  /* Processor Reset */
+		| AT91_RSTC_CR_PERRST   /* Peripheral Reset */
+#ifdef CONFIG_AT91RESET_EXTRST
+		| AT91_RSTC_CR_EXTRST   /* External Reset (assert nRST pin) */
+#endif
+		, &rstc->cr);
+
+	return -EINPROGRESS;
+}
+
+static int at91_sysreset_probe(struct udevice *dev)
+{
+	struct clk slck;
+	void *priv;
+	int ret;
+
+	priv = dev_remap_addr(dev);
+	if (!priv)
+		return -EINVAL;
+
+	dev_set_priv(dev, priv);
+
+	ret = clk_get_by_index(dev, 0, &slck);
+	if (ret)
+		return ret;
+
+	ret = clk_prepare_enable(&slck);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static struct sysreset_ops at91_sysreset = {
+	.request = at91_sysreset_request,
+};
+
+static const struct udevice_id a91_sysreset_ids[] = {
+	{ .compatible = "atmel,sama5d3-rstc" },
+	{ .compatible = "microchip,sam9x60-rstc" },
+	{ }
+};
+
+U_BOOT_DRIVER(sysreset_at91) = {
+	.id	= UCLASS_SYSRESET,
+	.name	= "at91_reset",
+	.ops	= &at91_sysreset,
+	.probe  = at91_sysreset_probe,
+	.of_match = a91_sysreset_ids,
+};
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 672746a1816..92050179c28 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -90,6 +90,15 @@ config ATMEL_PIT_TIMER
 	  it is designed to offer maximum accuracy and efficient management,
 	  even for systems with long response time.
 
+config SPL_ATMEL_PIT_TIMER
+	bool "Atmel periodic interval timer support in SPL"
+	depends on SPL_TIMER
+	help
+	  Select this to enable a periodic interval timer for Atmel devices,
+	  it is designed to offer maximum accuracy and efficient management,
+	  even for systems with long response time.
+	  Select this to be available in SPL.
+
 config ATMEL_TCB_TIMER
 	bool "Atmel timer counter support"
 	depends on TIMER
@@ -98,6 +107,14 @@ config ATMEL_TCB_TIMER
 	  Select this to enable the use of the timer counter as a monotonic
 	  counter.
 
+config SPL_ATMEL_TCB_TIMER
+	bool "Atmel timer counter support in SPL"
+	depends on SPL_TIMER
+	depends on ARCH_AT91
+	help
+	  Select this to enable the use of the timer counter as a monotonic
+	  counter in SPL.
+
 config CADENCE_TTC_TIMER
 	bool "Cadence TTC (Triple Timer Counter)"
 	depends on TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index 17f9f1d0441..35cc490db1e 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -7,8 +7,9 @@ obj-$(CONFIG_ALTERA_TIMER)	+= altera_timer.o
 obj-$(CONFIG_ANDES_PLMT_TIMER) += andes_plmt_timer.o
 obj-$(CONFIG_ARC_TIMER)	+= arc_timer.o
 obj-$(CONFIG_AST_TIMER)	+= ast_timer.o
-obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o
-obj-$(CONFIG_ATMEL_TCB_TIMER) += atmel_tcb_timer.o
+obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o
+obj-$(CONFIG_$(SPL_)ATMEL_PIT_TIMER) += atmel_pit_timer.o
+obj-$(CONFIG_$(SPL_)ATMEL_TCB_TIMER) += atmel_tcb_timer.o
 obj-$(CONFIG_CADENCE_TTC_TIMER)	+= cadence-ttc.o
 obj-$(CONFIG_DESIGNWARE_APB_TIMER)	+= dw-apb-timer.o
 obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o