diff options
| author | Richard Genoud <[email protected]> | 2026-01-23 12:44:56 +0100 |
|---|---|---|
| committer | Michael Trimarchi <[email protected]> | 2026-02-03 21:45:14 +0100 |
| commit | 4a611a82e5158d5789cb7bbf6feabaadc9d6b796 (patch) | |
| tree | 6c014d15bb958db1693360986c8eb00ad80870f3 /drivers | |
| parent | 25cbc335b47c30f2cc5c08e9610b47bccead3c2a (diff) | |
clk: sunxi: Add MBUS Master Clock Gating Register
Add MBUS Master Clock Gating Register for H6 and H616
For H6/H616, the NAND controller needs the MBUS NAND clock along with
CLK_NAND0/1 and CLK_BUS_NAND.
The bit locations are from H6/H616 User Manuals.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/sunxi/clk_h6.c | 2 | ||||
| -rw-r--r-- | drivers/clk/sunxi/clk_h616.c | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c index 1b7bd9dea2f..81deb5728e5 100644 --- a/drivers/clk/sunxi/clk_h6.c +++ b/drivers/clk/sunxi/clk_h6.c @@ -20,6 +20,8 @@ static struct ccu_clk_gate h6_gates[] = { [CLK_DE] = GATE(0x600, BIT(31)), [CLK_BUS_DE] = GATE(0x60c, BIT(0)), + [CLK_MBUS_NAND] = GATE(0x804, BIT(5)), + [CLK_NAND0] = GATE(0x810, BIT(31)), [CLK_NAND1] = GATE(0x814, BIT(31)), [CLK_BUS_NAND] = GATE(0x82c, BIT(0)), diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c index b1e999e18c1..3e7eea25bfe 100644 --- a/drivers/clk/sunxi/clk_h616.c +++ b/drivers/clk/sunxi/clk_h616.c @@ -19,6 +19,8 @@ static struct ccu_clk_gate h616_gates[] = { [CLK_DE] = GATE(0x600, BIT(31)), [CLK_BUS_DE] = GATE(0x60c, BIT(0)), + [CLK_MBUS_NAND] = GATE(0x804, BIT(5)), + [CLK_NAND0] = GATE(0x810, BIT(31)), [CLK_NAND1] = GATE(0x814, BIT(31)), [CLK_BUS_NAND] = GATE(0x82c, BIT(0)), |