diff options
| author | Andre Przywara <[email protected]> | 2022-10-05 17:54:19 +0100 |
|---|---|---|
| committer | Andre Przywara <[email protected]> | 2023-10-22 23:41:46 +0100 |
| commit | 4a9e89a3e390bbff31aec25f9ec6d32e29e355f5 (patch) | |
| tree | d882a9e4c251aa016cac6c5f1f767dd73c003450 /drivers | |
| parent | 452369cd0c636123321d021298b4bc35a34f4941 (diff) | |
sunxi: introduce NCAT2 generation model
Allwinner seems to typically stick to a common MMIO memory map for
several SoCs, but from time to time does some breaking changes, which
also introduce new generations of some peripherals. The last time this
happened with the H6, which apart from re-organising the base addresses
also changed the clock controller significantly. We added a
CONFIG_SUN50I_GEN_H6 symbol back then to mark SoCs sharing those traits.
Now the Allwinner D1 changes the memory map again, and also extends the
pincontroller, among other peripherals.
To mark this generation of SoCs, add a CONFIG_SUNXI_GEN_NCAT2 symbol,
this name is reportedly used in the Allwinner BSP code, and prevents us
from inventing our own name.
Add this new symbol to some guards that were already checking for the H6
generation, since many features are shared between the two (like the
renovated clock controller).
This paves the way to introduce a first user of this generation.
Signed-off-by: Andre Przywara <[email protected]>
Tested-by: Samuel Holland <[email protected]>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/i2c/mvtwsi.c | 3 | ||||
| -rw-r--r-- | drivers/mmc/sunxi_mmc.c | 7 |
2 files changed, 6 insertions, 4 deletions
diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index 14cdb0f6635..c38330f758a 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -124,7 +124,8 @@ enum mvtwsi_ctrl_register_fields { * on other platforms, it is a normal r/w bit, which is cleared by writing 0. */ -#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) +#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || \ + defined(CONFIG_SUNXI_GEN_NCAT2) #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000008 #else #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000000 diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 03e33753fcf..519ef602145 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -57,6 +57,7 @@ static bool sunxi_mmc_can_calibrate(void) return IS_ENABLED(CONFIG_MACH_SUN50I) || IS_ENABLED(CONFIG_MACH_SUN50I_H5) || IS_ENABLED(CONFIG_SUN50I_GEN_H6) || + IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) || IS_ENABLED(CONFIG_MACH_SUN8I_R40); } @@ -191,7 +192,7 @@ static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc) rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK; writel(rval, &priv->reg->clkcr); -#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) +#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2) /* A64 supports calibration of delays on MMC controller and we * have to set delay of zero before starting calibration. * Allwinner BSP driver sets a delay only in the case of @@ -544,7 +545,7 @@ struct mmc *sunxi_mmc_init(int sdc_no) /* config ahb clock */ debug("init mmc %d clock and io\n", sdc_no); -#if !defined(CONFIG_SUN50I_GEN_H6) +#if !defined(CONFIG_SUN50I_GEN_H6) && !defined(CONFIG_SUNXI_GEN_NCAT2) setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no)); #ifdef CONFIG_SUNXI_GEN_SUN6I @@ -619,7 +620,7 @@ static unsigned get_mclk_offset(void) if (IS_ENABLED(CONFIG_MACH_SUN9I_A80)) return 0x410; - if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) return 0x830; return 0x88; |