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authorViorel Suman <[email protected]>2025-04-01 15:56:35 +0800
committerFabio Estevam <[email protected]>2025-04-11 08:26:27 -0300
commit51eed1cacaa6eab780914ce9e1f6a948b60ecc34 (patch)
treeccb38d3724abbe0d8ad1bc8f02dd8da20ee59237 /drivers
parenta3139fe0572ed39db3b0be526d71e1d23cb8c467 (diff)
firmware: scmi: smt: Interrupt communication enable
i.MX95 System Manager uses interrupt driven communication which requires the caller to set Bit[0] of channel flags to 1. When transmission completes and the previous general purpose interrupt has been processed by the other core, i.MX95 System Manager will set General Purpose Interrupt Control Register (GCR). U-Boot polls General-purpose Status (GSR) to check if the operation is finished. Signed-off-by: Viorel Suman <[email protected]> Signed-off-by: Alice Guo <[email protected]> Reviewed-by: Ye Li <[email protected]> Reviewed-by: Marek Vasut <[email protected]>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/firmware/scmi/smt.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/firmware/scmi/smt.c b/drivers/firmware/scmi/smt.c
index 67d2f450024..3253f4211d6 100644
--- a/drivers/firmware/scmi/smt.c
+++ b/drivers/firmware/scmi/smt.c
@@ -20,6 +20,16 @@
#include "smt.h"
+static void scmi_smt_enable_intr(struct scmi_smt *smt, bool enable)
+{
+ struct scmi_smt_header *hdr = (void *)smt->buf;
+
+ if (enable)
+ hdr->flags |= SCMI_SHMEM_FLAG_INTR_ENABLED;
+ else
+ hdr->flags &= ~SCMI_SHMEM_FLAG_INTR_ENABLED;
+}
+
/**
* Get shared memory configuration defined by the referred DT phandle
* Return with a errno compliant value.
@@ -48,6 +58,9 @@ int scmi_dt_get_smt_buffer(struct udevice *dev, struct scmi_smt *smt)
if (!smt->buf)
return -ENOMEM;
+ if (device_is_compatible(dev, "arm,scmi") && ofnode_has_property(dev_ofnode(dev), "mboxes"))
+ scmi_smt_enable_intr(smt, true);
+
#ifdef CONFIG_ARM
if (dcache_status())
mmu_set_region_dcache_behaviour(ALIGN_DOWN((uintptr_t)smt->buf, MMU_SECTION_SIZE),