diff options
| author | Pavel Machek <[email protected]> | 2014-07-19 23:57:59 +0200 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2014-08-29 15:50:50 -0400 |
| commit | 51fb455f82b08ef1bf21b5c51181d26fef56df03 (patch) | |
| tree | 3cb202ff05ce52f7a3d32c79299916b5338aae7b /drivers | |
| parent | db993fc8ec8454cbefa16e8ab736d79b25515765 (diff) | |
socfpga: fix clock manager register definition
Structure defining clock manager hardware was wrong, leading to
wrong registers being accessed and hang in MMC init.
This fixes structure to match hardware.
Signed-off-by: Pavel Machek <[email protected]>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mmc/socfpga_dw_mmc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index bc53a5da272..417ca4c2ae6 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -24,7 +24,7 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host) unsigned int smplsel; /* Disable SDMMC clock. */ - clrbits_le32(&clock_manager_base->per_pll_en, + clrbits_le32(&clock_manager_base->per_pll.en, CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); /* Configures drv_sel and smpl_sel */ @@ -39,7 +39,7 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host) readl(&system_manager_base->sdmmcgrp_ctrl)); /* Enable SDMMC clock */ - setbits_le32(&clock_manager_base->per_pll_en, + setbits_le32(&clock_manager_base->per_pll.en, CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); } |