Merge tag 'xilinx-for-v2018.07-2' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2018.07 second pull

zynqmp:
- Show reset reason
- Remove emulation platform
- Update pmufw version
- Simplify mmc bootmode
- Remove dc2 useless configuration file
- Cleanup mini config
- Defconfig syncup
- zcu100, zcu104 and zcu111 dts fixes

xilinx:
- Use live-tree functions in some drivers
- Add support for Avnet Minized and Antminer S9

fpga:
- Add secure bitstream loading support

mmc:
- Add hs200 mode support

usb xhci:
- Header fix

9 files changed, 138 insertions, 32 deletions

diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index 55bdf9e7cf2..7e8bd7eae88 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -217,6 +217,35 @@ int fpga_fsload(int devnum, const void *buf, size_t size,
 }
 #endif
 
+#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
+int fpga_loads(int devnum, const void *buf, size_t size,
+	       struct fpga_secure_info *fpga_sec_info)
+{
+	int ret_val = FPGA_FAIL;
+
+	const fpga_desc *desc = fpga_validate(devnum, buf, size,
+					      (char *)__func__);
+
+	if (desc) {
+		switch (desc->devtype) {
+		case fpga_xilinx:
+#if defined(CONFIG_FPGA_XILINX)
+			ret_val = xilinx_loads(desc->devdesc, buf, size,
+					       fpga_sec_info);
+#else
+			fpga_no_sup((char *)__func__, "Xilinx devices");
+#endif
+			break;
+		default:
+			printf("%s: Invalid or unsupported device type %d\n",
+			       __func__, desc->devtype);
+		}
+	}
+
+	return ret_val;
+}
+#endif
+
 /*
  * Generic multiplexing code
  */
diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c
index 724304a5451..f5135504eeb 100644
--- a/drivers/fpga/xilinx.c
+++ b/drivers/fpga/xilinx.c
@@ -171,6 +171,24 @@ int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
 }
 #endif
 
+#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
+int xilinx_loads(xilinx_desc *desc, const void *buf, size_t bsize,
+		 struct fpga_secure_info *fpga_sec_info)
+{
+	if (!xilinx_validate(desc, (char *)__func__)) {
+		printf("%s: Invalid device descriptor\n", __func__);
+		return FPGA_FAIL;
+	}
+
+	if (!desc->operations || !desc->operations->loads) {
+		printf("%s: Missing loads operation\n", __func__);
+		return FPGA_FAIL;
+	}
+
+	return desc->operations->loads(desc, buf, bsize, fpga_sec_info);
+}
+#endif
+
 int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index b57623b6a75..03ffa8c11f2 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -223,6 +223,51 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
 	return ret;
 }
 
+#if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD)
+static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
+			struct fpga_secure_info *fpga_sec_info)
+{
+	int ret;
+	u32 buf_lo, buf_hi;
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	u8 flag = 0;
+
+	flush_dcache_range((ulong)buf, (ulong)buf +
+			   ALIGN(bsize, CONFIG_SYS_CACHELINE_SIZE));
+
+	if (!fpga_sec_info->encflag)
+		flag |= BIT(ZYNQMP_FPGA_BIT_ENC_DEV_KEY);
+
+	if (fpga_sec_info->userkey_addr &&
+	    fpga_sec_info->encflag == FPGA_ENC_USR_KEY) {
+		flush_dcache_range((ulong)fpga_sec_info->userkey_addr,
+				   (ulong)fpga_sec_info->userkey_addr +
+				   ALIGN(KEY_PTR_LEN,
+					 CONFIG_SYS_CACHELINE_SIZE));
+		flag |= BIT(ZYNQMP_FPGA_BIT_ENC_USR_KEY);
+	}
+
+	if (!fpga_sec_info->authflag)
+		flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_OCM);
+
+	if (fpga_sec_info->authflag == ZYNQMP_FPGA_AUTH_DDR)
+		flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_DDR);
+
+	buf_lo = lower_32_bits((ulong)buf);
+	buf_hi = upper_32_bits((ulong)buf);
+
+	ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
+			 (u32)(uintptr_t)fpga_sec_info->userkey_addr,
+			 flag, ret_payload);
+	if (ret)
+		puts("PL FPGA LOAD fail\n");
+	else
+		puts("Bitstream successfully loaded\n");
+
+	return ret;
+}
+#endif
+
 static int zynqmp_pcap_info(xilinx_desc *desc)
 {
 	int ret;
@@ -238,5 +283,8 @@ static int zynqmp_pcap_info(xilinx_desc *desc)
 
 struct xilinx_fpga_op zynqmp_op = {
 	.load = zynqmp_load,
+#if defined CONFIG_CMD_FPGA_LOAD_SECURE
+	.loads = zynqmp_loads,
+#endif
 	.info = zynqmp_pcap_info,
 };
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 400f87e134d..40e28abda67 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -161,7 +161,8 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 	/* We shouldn't wait for data inihibit for stop commands, even
 	   though they might use busy signaling */
 	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
-	    cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK)
+	    cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
+	    cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
 		mask &= ~SDHCI_DATA_INHIBIT;
 
 	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
@@ -183,7 +184,8 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 
 	mask = SDHCI_INT_RESPONSE;
-	if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
+	if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
+	    cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
 		mask = SDHCI_INT_DATA_AVAIL;
 
 	if (!(cmd->resp_type & MMC_RSP_PRESENT))
@@ -201,7 +203,8 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 		flags |= SDHCI_CMD_CRC;
 	if (cmd->resp_type & MMC_RSP_OPCODE)
 		flags |= SDHCI_CMD_INDEX;
-	if (data || cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK)
+	if (data || cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK ||
+	    cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
 		flags |= SDHCI_CMD_DATA;
 
 	/* Set Transfer mode regarding to data flag */
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index f99731fb1ff..5b6d5256084 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -32,12 +32,21 @@ struct arasan_sdhci_priv {
 };
 
 #if defined(CONFIG_ARCH_ZYNQMP)
+#define MMC_HS200_BUS_SPEED	5
+
 static const u8 mode2timing[] = {
-	     [UHS_SDR12] = UHS_SDR12_BUS_SPEED,
-	     [UHS_SDR25] = UHS_SDR25_BUS_SPEED,
-	     [UHS_SDR50] = UHS_SDR50_BUS_SPEED,
-	     [UHS_SDR104] = UHS_SDR104_BUS_SPEED,
-	     [UHS_DDR50] = UHS_DDR50_BUS_SPEED,
+	[MMC_LEGACY] = UHS_SDR12_BUS_SPEED,
+	[SD_LEGACY] = UHS_SDR12_BUS_SPEED,
+	[MMC_HS] = HIGH_SPEED_BUS_SPEED,
+	[SD_HS] = HIGH_SPEED_BUS_SPEED,
+	[MMC_HS_52] = HIGH_SPEED_BUS_SPEED,
+	[MMC_DDR_52] = HIGH_SPEED_BUS_SPEED,
+	[UHS_SDR12] = UHS_SDR12_BUS_SPEED,
+	[UHS_SDR25] = UHS_SDR25_BUS_SPEED,
+	[UHS_SDR50] = UHS_SDR50_BUS_SPEED,
+	[UHS_DDR50] = UHS_DDR50_BUS_SPEED,
+	[UHS_SDR104] = UHS_SDR104_BUS_SPEED,
+	[MMC_HS_200] = MMC_HS200_BUS_SPEED,
 };
 
 #define SDHCI_HOST_CTRL2	0x3E
@@ -160,9 +169,6 @@ static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
 	struct mmc *mmc = (struct mmc *)host->mmc;
 	u8 uhsmode;
 
-	if (!IS_SD(mmc))
-		return;
-
 	uhsmode = mode2timing[mmc->selected_mode];
 
 	if (uhsmode >= UHS_SDR25_BUS_SPEED)
@@ -175,6 +181,9 @@ static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
 	struct mmc *mmc = (struct mmc *)host->mmc;
 	u32 reg;
 
+	if (!IS_SD(mmc))
+		return;
+
 	if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
 		reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
 		reg |= SDHCI_18V_SIGNAL;
@@ -283,25 +292,21 @@ static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
 		return -1;
 
 	priv->host->name = dev->name;
-	priv->host->ioaddr = (void *)devfdt_get_addr(dev);
-
-	priv->deviceid = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-					"xlnx,device_id", -1);
-	priv->bank = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-				    "xlnx,mio_bank", -1);
-	if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev),
-			     "no-1-8-v", NULL))
-		priv->no_1p8 = 1;
-	else
-		priv->no_1p8 = 0;
 
 #if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP)
 	priv->host->ops = &arasan_ops;
 #endif
 
-	plat->f_max = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-				"max-frequency", CONFIG_ZYNQ_SDHCI_MAX_FREQ);
+	priv->host->ioaddr = (void *)dev_read_addr(dev);
+	if (IS_ERR(priv->host->ioaddr))
+		return PTR_ERR(priv->host->ioaddr);
+
+	priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
+	priv->bank = dev_read_u32_default(dev, "xlnx,mio_bank", -1);
+	priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
 
+	plat->f_max = dev_read_u32_default(dev, "max-frequency",
+					   CONFIG_ZYNQ_SDHCI_MAX_FREQ);
 	return 0;
 }
 
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
index 06f0a48e670..3650af21573 100644
--- a/drivers/serial/serial_zynq.c
+++ b/drivers/serial/serial_zynq.c
@@ -175,7 +175,9 @@ static int zynq_serial_ofdata_to_platdata(struct udevice *dev)
 {
 	struct zynq_uart_priv *priv = dev_get_priv(dev);
 
-	priv->regs = (struct uart_zynq *)devfdt_get_addr(dev);
+	priv->regs = (struct uart_zynq *)dev_read_addr(dev);
+	if (IS_ERR(priv->regs))
+		return PTR_ERR(priv->regs);
 
 	return 0;
 }
diff --git a/drivers/timer/cadence-ttc.c b/drivers/timer/cadence-ttc.c
index 5b91c8a90b3..3541e5c8412 100644
--- a/drivers/timer/cadence-ttc.c
+++ b/drivers/timer/cadence-ttc.c
@@ -64,8 +64,10 @@ static int cadence_ttc_ofdata_to_platdata(struct udevice *dev)
 {
 	struct cadence_ttc_priv *priv = dev_get_priv(dev);
 
-	priv->regs = map_physmem(devfdt_get_addr(dev),
+	priv->regs = map_physmem(dev_read_addr(dev),
 				 sizeof(struct cadence_ttc_regs), MAP_NOCACHE);
+	if (IS_ERR(priv->regs))
+		return PTR_ERR(priv->regs);
 
 	return 0;
 }
diff --git a/drivers/usb/host/xhci-zynqmp.c b/drivers/usb/host/xhci-zynqmp.c
index 7fe54281c3c..e44e1ae1d91 100644
--- a/drivers/usb/host/xhci-zynqmp.c
+++ b/drivers/usb/host/xhci-zynqmp.c
@@ -13,7 +13,7 @@
 #include <dm.h>
 #include <usb.h>
 #include <linux/errno.h>
-#include <asm/arch-zynqmp/hardware.h>
+#include <asm/arch/hardware.h>
 #include <linux/compat.h>
 #include <linux/usb/dwc3.h>
 #include "xhci.h"
diff --git a/drivers/watchdog/cdns_wdt.c b/drivers/watchdog/cdns_wdt.c
index 9a07fa10fd9..f7618f86da1 100644
--- a/drivers/watchdog/cdns_wdt.c
+++ b/drivers/watchdog/cdns_wdt.c
@@ -231,17 +231,16 @@ static int cdns_wdt_probe(struct udevice *dev)
 
 static int cdns_wdt_ofdata_to_platdata(struct udevice *dev)
 {
-	int node = dev_of_offset(dev);
 	struct cdns_wdt_priv *priv = dev_get_priv(dev);
 
-	priv->regs = devfdt_get_addr_ptr(dev);
+	priv->regs = (struct cdns_regs *)dev_read_addr(dev);
 	if (IS_ERR(priv->regs))
 		return PTR_ERR(priv->regs);
 
-	priv->timeout = fdtdec_get_int(gd->fdt_blob, node, "timeout-sec",
-				       CDNS_WDT_DEFAULT_TIMEOUT);
+	priv->timeout = dev_read_u32_default(dev, "timeout-sec",
+					     CDNS_WDT_DEFAULT_TIMEOUT);
 
-	priv->rst = fdtdec_get_bool(gd->fdt_blob, node, "reset-on-timeout");
+	priv->rst = dev_read_bool(dev, "reset-on-timeout");
 
 	debug("%s: timeout %d, reset %d\n", __func__, priv->timeout, priv->rst);