diff options
| author | Jonas Schwöbel <[email protected]> | 2025-03-11 23:01:20 +0100 |
|---|---|---|
| committer | Svyatoslav Ryhel <[email protected]> | 2026-03-22 14:43:19 +0200 |
| commit | 5dcdbcf7833ae762866c43cbd872ba910576d228 (patch) | |
| tree | 8c33f54f01843dca3284b47564728cf856ba84a5 /drivers | |
| parent | 1f32eff8cedc0baf1d595ebf247772bccb950cc7 (diff) | |
pwm: tegra: add probe function
When PWM config was updated the clock was restarted which caused loss of
previous configuration of other channels. Further this fixes a bug/hang
that can happen when set_enable was called before set_config.
Signed-off-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/pwm/tegra_pwm.c | 21 |
1 files changed, 18 insertions, 3 deletions
diff --git a/drivers/pwm/tegra_pwm.c b/drivers/pwm/tegra_pwm.c index e3f1417f2ad..919728b821f 100644 --- a/drivers/pwm/tegra_pwm.c +++ b/drivers/pwm/tegra_pwm.c @@ -4,6 +4,7 @@ */ #include <dm.h> +#include <clk.h> #include <log.h> #include <pwm.h> #include <asm/io.h> @@ -19,7 +20,6 @@ static int tegra_pwm_set_config(struct udevice *dev, uint channel, { struct tegra_pwm_priv *priv = dev_get_priv(dev); struct pwm_ctlr *regs = priv->regs; - const u32 pwm_max_freq = dev_get_driver_data(dev); uint pulse_width; u32 reg; @@ -27,8 +27,6 @@ static int tegra_pwm_set_config(struct udevice *dev, uint channel, return -EINVAL; debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel); - clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_PERIPH, pwm_max_freq); - pulse_width = duty_ns * 255 / period_ns; reg = pulse_width << PWM_WIDTH_SHIFT; @@ -63,6 +61,22 @@ static int tegra_pwm_of_to_plat(struct udevice *dev) return 0; } +static int tegra_pwm_probe(struct udevice *dev) +{ + const u32 pwm_max_freq = dev_get_driver_data(dev); + struct clk *clk; + + clk = devm_clk_get(dev, NULL); + if (IS_ERR(clk)) { + debug("%s: Could not get PWM clock: %ld\n", __func__, PTR_ERR(clk)); + return PTR_ERR(clk); + } + + clock_start_periph_pll(clk->id, CLOCK_ID_PERIPH, pwm_max_freq); + + return 0; +} + static const struct pwm_ops tegra_pwm_ops = { .set_config = tegra_pwm_set_config, .set_enable = tegra_pwm_set_enable, @@ -80,5 +94,6 @@ U_BOOT_DRIVER(tegra_pwm) = { .of_match = tegra_pwm_ids, .ops = &tegra_pwm_ops, .of_to_plat = tegra_pwm_of_to_plat, + .probe = tegra_pwm_probe, .priv_auto = sizeof(struct tegra_pwm_priv), }; |