Merge branch '2020-08-05-misc-fixes'

- A large number of assorted fixes and minor improvements

5 files changed, 45 insertions, 14 deletions

diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c
index 23cf807591c..7d2e49fd3e3 100644
--- a/drivers/firmware/psci.c
+++ b/drivers/firmware/psci.c
@@ -25,7 +25,11 @@
 #define PSCI_METHOD_HVC 1
 #define PSCI_METHOD_SMC 2
 
+#if CONFIG_IS_ENABLED(EFI_LOADER)
 int __efi_runtime_data psci_method;
+#else
+int psci_method __attribute__ ((section(".data")));
+#endif
 
 unsigned long __efi_runtime invoke_psci_fn
 		(unsigned long function_id, unsigned long arg0,
diff --git a/drivers/mtd/nand/bbt.c b/drivers/mtd/nand/bbt.c
index 84d60b86521..294daee7b22 100644
--- a/drivers/mtd/nand/bbt.c
+++ b/drivers/mtd/nand/bbt.c
@@ -127,7 +127,7 @@ int nanddev_bbt_set_block_status(struct nand_device *nand, unsigned int entry,
 		unsigned int rbits = bits_per_block + offs - BITS_PER_LONG;
 
 		pos[1] &= ~GENMASK(rbits - 1, 0);
-		pos[1] |= val >> rbits;
+		pos[1] |= val >> (bits_per_block - rbits);
 	}
 
 	return 0;
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 15030b81651..ecd779d979e 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -156,9 +156,30 @@ config DWC_ETH_QOS
 	help
 	  This driver supports the Synopsys Designware Ethernet QOS (Quality
 	  Of Service) IP block. The IP supports many options for bus type,
-	  clocking/reset structure, and feature list. This driver currently
-	  supports the specific configuration used in NVIDIA's Tegra186 chip,
-	  but should be extensible to other combinations quite easily.
+	  clocking/reset structure, and feature list.
+
+config DWC_ETH_QOS_IMX
+	bool "Synopsys DWC Ethernet QOS device support for IMX"
+	depends on DWC_ETH_QOS
+	help
+	  The Synopsys Designware Ethernet QOS IP block with the specific
+	  configuration used in IMX soc.
+
+config DWC_ETH_QOS_STM32
+	bool "Synopsys DWC Ethernet QOS device support for STM32"
+	depends on DWC_ETH_QOS
+	default y if ARCH_STM32MP
+	help
+	  The Synopsys Designware Ethernet QOS IP block with the specific
+	  configuration used in STM32MP soc.
+
+config DWC_ETH_QOS_TEGRA186
+	bool "Synopsys DWC Ethernet QOS device support for TEGRA186"
+	depends on DWC_ETH_QOS
+	default y if TEGRA186
+	help
+	  The Synopsys Designware Ethernet QOS IP block with specific
+	  configuration used in NVIDIA's Tegra186 chip.
 
 config E1000
 	bool "Intel PRO/1000 Gigabit Ethernet support"
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 1d9eefbb3e8..810a2b95b19 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -2100,7 +2100,7 @@ static struct eqos_ops eqos_tegra186_ops = {
 	.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186
 };
 
-static const struct eqos_config eqos_tegra186_config = {
+static const struct eqos_config __maybe_unused eqos_tegra186_config = {
 	.reg_access_always_ok = false,
 	.mdio_wait = 10,
 	.swr_wait = 10,
@@ -2127,7 +2127,7 @@ static struct eqos_ops eqos_stm32_ops = {
 	.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
 };
 
-static const struct eqos_config eqos_stm32_config = {
+static const struct eqos_config __maybe_unused eqos_stm32_config = {
 	.reg_access_always_ok = false,
 	.mdio_wait = 10000,
 	.swr_wait = 50,
@@ -2154,7 +2154,7 @@ static struct eqos_ops eqos_imx_ops = {
 	.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx
 };
 
-struct eqos_config eqos_imx_config = {
+struct eqos_config __maybe_unused eqos_imx_config = {
 	.reg_access_always_ok = false,
 	.mdio_wait = 10000,
 	.swr_wait = 50,
@@ -2165,18 +2165,24 @@ struct eqos_config eqos_imx_config = {
 };
 
 static const struct udevice_id eqos_ids[] = {
+#if IS_ENABLED(CONFIG_DWC_ETH_QOS_TEGRA186)
 	{
 		.compatible = "nvidia,tegra186-eqos",
 		.data = (ulong)&eqos_tegra186_config
 	},
+#endif
+#if IS_ENABLED(CONFIG_DWC_ETH_QOS_STM32)
 	{
 		.compatible = "st,stm32mp1-dwmac",
 		.data = (ulong)&eqos_stm32_config
 	},
+#endif
+#if IS_ENABLED(CONFIG_DWC_ETH_QOS_IMX)
 	{
 		.compatible = "fsl,imx-eqos",
 		.data = (ulong)&eqos_imx_config
 	},
+#endif
 
 	{ }
 };
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index bd2061b765b..cdbccfd285a 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -276,13 +276,13 @@ config SPL_PINCTRL_STMFX
 	  See the help of PINCTRL_STMFX for details.
 
 config ASPEED_AST2500_PINCTRL
-  bool "Aspeed AST2500 pin control driver"
-  depends on DM && PINCTRL_GENERIC && ASPEED_AST2500
-  default y
-  help
-    Support pin multiplexing control on Aspeed ast2500 SoC. The driver uses
-	Generic Pinctrl framework and is compatible with the Linux driver,
-	i.e. it uses the same device tree configuration.
+	bool "Aspeed AST2500 pin control driver"
+	depends on DM && PINCTRL_GENERIC && ASPEED_AST2500
+	default y
+	help
+	  Support pin multiplexing control on Aspeed ast2500 SoC. The driver
+	  uses Generic Pinctrl framework and is compatible with the Linux
+	  driver, i.e. it uses the same device tree configuration.
 
 endif