diff options
| author | Naresh Kumar Ravulapalli <[email protected]> | 2025-08-08 02:42:42 -0700 |
|---|---|---|
| committer | Tien Fong Chee <[email protected]> | 2025-09-30 14:29:53 +0800 |
| commit | 63ef1c7a7391e7440bdfbffedd2cc5d9007707cd (patch) | |
| tree | 2294b89db6cfe03fe527c41b7daab6b047cad94b /drivers | |
| parent | 5d2ef97c66f0a432c859cfdf64ef696017619ad6 (diff) | |
drivers: ddr: altera: Correct DDR calibration status check
Bit 3 of the seq2core register is no longer set to indicate
calibration completion. Instead, added polling of the seq2core
register until it reads 0b00000111, signaling that the Nios
processor has started the calibration process.
Signed-off-by: Naresh Kumar Ravulapalli <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ddr/altera/sdram_soc64.c | 6 | ||||
| -rw-r--r-- | drivers/ddr/altera/sdram_soc64.h | 2 |
2 files changed, 4 insertions, 4 deletions
diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index f8fc92060db..2d0093c591c 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -85,11 +85,11 @@ int emif_reset(struct altera_sdram_plat *plat) debug("DDR: Triggerring emif reset\n"); hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL); - /* if seq2core[3] = 0, we are good */ + /* if seq2core[2:0] = 0b0000_0111, we are good */ ret = wait_for_bit_le32((const void *)(plat->hmc + RSTHANDSHAKESTAT), - DDR_HMC_SEQ2CORE_INT_RESP_MASK, - false, 1000, false); + DDR_HMC_SEQ2CORE_INT_REQ_ACK_MASK, + true, 1000, false); if (ret) { printf("DDR: failed to get ack from EMIF\n"); return ret; diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 6031cef560e..6fe0653922c 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -77,7 +77,7 @@ struct altera_sdram_plat { #define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0) #define DDR_HMC_RSTHANDSHAKE_MASK 0x0000000f #define DDR_HMC_CORE2SEQ_INT_REQ 0x0000000f -#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3) +#define DDR_HMC_SEQ2CORE_INT_REQ_ACK_MASK GENMASK(2, 0) #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f #define DDR_HMC_ERRINTEN_INTMASK \ |