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authorJim Liu <[email protected]>2023-11-14 16:51:58 +0800
committerTom Rini <[email protected]>2023-11-22 19:10:04 -0500
commit65660bfe853059e8f6a012c3e8912088dc379089 (patch)
tree167c72f273ea1e81370da1b2438d99e16e3c7ab8 /drivers
parent1504813eb84b9baa043a527ce70575428e8d9f34 (diff)
serial: npcm: support skip uart clock setting
Skip the uart clock setting if CONFIG_SYS_SKIP_UART_INIT is enabled. Fix divisor error. Signed-off-by: Jim Liu <[email protected]>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/serial/serial_npcm.c39
1 files changed, 24 insertions, 15 deletions
diff --git a/drivers/serial/serial_npcm.c b/drivers/serial/serial_npcm.c
index 76ac7cb80db..6bf3a943a2f 100644
--- a/drivers/serial/serial_npcm.c
+++ b/drivers/serial/serial_npcm.c
@@ -83,8 +83,11 @@ static int npcm_serial_setbrg(struct udevice *dev, int baudrate)
struct npcm_uart *uart = plat->reg;
u16 divisor;
+ if (IS_ENABLED(CONFIG_SYS_SKIP_UART_INIT))
+ return 0;
+
/* BaudOut = UART Clock / (16 * [Divisor + 2]) */
- divisor = DIV_ROUND_CLOSEST(plat->uart_clk, 16 * baudrate + 2) - 2;
+ divisor = DIV_ROUND_CLOSEST(plat->uart_clk, 16 * baudrate) - 2;
setbits_8(&uart->lcr, LCR_DLAB);
writeb(divisor & 0xff, &uart->dll);
@@ -97,29 +100,35 @@ static int npcm_serial_setbrg(struct udevice *dev, int baudrate)
static int npcm_serial_probe(struct udevice *dev)
{
struct npcm_serial_plat *plat = dev_get_plat(dev);
- struct npcm_uart *uart = plat->reg;
+ struct npcm_uart *uart;
struct clk clk, parent;
u32 freq;
int ret;
plat->reg = dev_read_addr_ptr(dev);
- freq = dev_read_u32_default(dev, "clock-frequency", 0);
+ uart = plat->reg;
- ret = clk_get_by_index(dev, 0, &clk);
- if (ret < 0)
- return ret;
+ if (!IS_ENABLED(CONFIG_SYS_SKIP_UART_INIT)) {
+ freq = dev_read_u32_default(dev, "clock-frequency", 24000000);
- ret = clk_get_by_index(dev, 1, &parent);
- if (!ret) {
- ret = clk_set_parent(&clk, &parent);
- if (ret)
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0)
return ret;
- }
- ret = clk_set_rate(&clk, freq);
- if (ret < 0)
- return ret;
- plat->uart_clk = ret;
+ ret = clk_get_by_index(dev, 1, &parent);
+ if (!ret) {
+ ret = clk_set_parent(&clk, &parent);
+ if (ret)
+ return ret;
+ }
+
+ if (freq) {
+ ret = clk_set_rate(&clk, freq);
+ if (ret < 0)
+ return ret;
+ }
+ plat->uart_clk = clk_get_rate(&clk);
+ }
/* Disable all interrupt */
writeb(0, &uart->ier);