Merge branch '2021-10-01-assorted-removal-and-migration' into next

- Remove the last non-CONFIG_DM boards, and their related unused code.
- Finish a few partial migrations to Kconfig, and remove some redundant
  serial related code.

14 files changed, 12 insertions, 214 deletions

diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 18917488c21..a9dc546a20b 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -23,7 +23,6 @@ obj-$(CONFIG_IPROC_GPIO)	+= iproc_gpio.o
 obj-$(CONFIG_KIRKWOOD_GPIO)	+= kw_gpio.o
 obj-$(CONFIG_KONA_GPIO)	+= kona_gpio.o
 obj-$(CONFIG_MARVELL_GPIO)	+= mvgpio.o
-obj-$(CONFIG_MARVELL_MFP)	+= mvmfp.o
 obj-$(CONFIG_MCP230XX_GPIO)	+= mcp230xx_gpio.o
 obj-$(CONFIG_MXC_GPIO)	+= mxc_gpio.o
 obj-$(CONFIG_MXS_GPIO)	+= mxs_gpio.o
diff --git a/drivers/gpio/mvmfp.c b/drivers/gpio/mvmfp.c
deleted file mode 100644
index 511042c1990..00000000000
--- a/drivers/gpio/mvmfp.c
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <[email protected]>,
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <mvmfp.h>
-#include <asm/arch/mfp.h>
-
-/*
- * mfp_config
- *
- * On most of Marvell SoCs (ex. ARMADA100) there is Multi-Funtion-Pin
- * configuration registers to configure each GPIO/Function pin on the
- * SoC.
- *
- * This function reads the array of values for
- * MFPR_X registers and programms them into respective
- * Multi-Function Pin registers.
- * It supports - Alternate Function Selection programming.
- *
- * Whereas,
- * The Configureation value is constructed using MFP()
- * array consists of 32bit values as defined in MFP(xx,xx..) macro
- */
-void mfp_config(u32 *mfp_cfgs)
-{
-	u32 *p_mfpr = NULL;
-	u32 cfg_val, val;
-
-	do {
-		cfg_val = *mfp_cfgs++;
-		/* exit if End of configuration table detected */
-		if (cfg_val == MFP_EOC)
-			break;
-
-		p_mfpr = (u32 *)(MV_MFPR_BASE
-				+ MFP_REG_GET_OFFSET(cfg_val));
-
-		/* Write a mfg register as per configuration */
-		val = 0;
-		if (cfg_val & MFP_VALUE_MASK)
-			val |= cfg_val & MFP_VALUE_MASK;
-
-		writel(val, p_mfpr);
-	} while (1);
-	/*
-	 * perform a read-back of any MFPR register to make sure the
-	 * previous writings are finished
-	 */
-	readl(p_mfpr);
-}
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index 06e6b2279f6..03471db9e80 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -44,7 +44,7 @@ static unsigned long gpio_ports[] = {
 	[0] = GPIO1_BASE_ADDR,
 	[1] = GPIO2_BASE_ADDR,
 	[2] = GPIO3_BASE_ADDR,
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
+#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
 		defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
 		defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
 		defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
@@ -352,7 +352,7 @@ static const struct mxc_gpio_plat mxc_plat[] = {
 	{ 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
 	{ 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
 	{ 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
+#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
 		defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
 		defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
 	{ 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
@@ -376,7 +376,7 @@ U_BOOT_DRVINFOS(mxc_gpios) = {
 	{ "gpio_mxc", &mxc_plat[0] },
 	{ "gpio_mxc", &mxc_plat[1] },
 	{ "gpio_mxc", &mxc_plat[2] },
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
+#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
 		defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
 		defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
 	{ "gpio_mxc", &mxc_plat[3] },
diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c
index 591137f50e3..336ebf14102 100644
--- a/drivers/mmc/mv_sdhci.c
+++ b/drivers/mmc/mv_sdhci.c
@@ -44,29 +44,6 @@ static void sdhci_mvebu_mbus_config(void __iomem *base)
 
 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 static struct sdhci_ops mv_ops;
-
-#if defined(CONFIG_SHEEVA_88SV331xV5)
-#define SD_CE_ATA_2	0xEA
-#define  MMC_CARD	0x1000
-#define  MMC_WIDTH	0x0100
-static inline void mv_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
-{
-	struct mmc *mmc = host->mmc;
-	u32 ata = (unsigned long)host->ioaddr + SD_CE_ATA_2;
-
-	if (!IS_SD(mmc) && reg == SDHCI_HOST_CONTROL) {
-		if (mmc->bus_width == 8)
-			writew(readw(ata) | (MMC_CARD | MMC_WIDTH), ata);
-		else
-			writew(readw(ata) & ~(MMC_CARD | MMC_WIDTH), ata);
-	}
-
-	writeb(val, host->ioaddr + reg);
-}
-
-#else
-#define mv_sdhci_writeb	NULL
-#endif /* CONFIG_SHEEVA_88SV331xV5 */
 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
 
 int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks)
@@ -84,7 +61,6 @@ int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks)
 	host->max_clk = max_clk;
 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 	memset(&mv_ops, 0, sizeof(struct sdhci_ops));
-	mv_ops.write_b = mv_sdhci_writeb;
 	host->ops = &mv_ops;
 #endif
 
diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c
index 59cef205754..c38f286e61d 100644
--- a/drivers/mtd/nand/raw/mxc_nand.c
+++ b/drivers/mtd/nand/raw/mxc_nand.c
@@ -11,7 +11,7 @@
 #include <linux/delay.h>
 #include <linux/err.h>
 #include <asm/io.h>
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
+#if defined(CONFIG_MX27) || \
 	defined(CONFIG_MX51) || defined(CONFIG_MX53)
 #include <asm/arch/imx-regs.h>
 #endif
diff --git a/drivers/mtd/nand/raw/mxc_nand.h b/drivers/mtd/nand/raw/mxc_nand.h
index 1c7f3a2e227..771f61e2491 100644
--- a/drivers/mtd/nand/raw/mxc_nand.h
+++ b/drivers/mtd/nand/raw/mxc_nand.h
@@ -29,11 +29,6 @@
 #define is_mxc_nfc_1()		1
 #define is_mxc_nfc_21()		0
 #define is_mxc_nfc_32()		0
-#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
-#define MXC_NFC_V2_1
-#define is_mxc_nfc_1()		0
-#define is_mxc_nfc_21()		1
-#define is_mxc_nfc_32()		0
 #elif defined(CONFIG_MX51) || defined(CONFIG_MX53)
 #define MXC_NFC_V3
 #define MXC_NFC_V3_2
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 9bb42e5ca90..40a86a3e12f 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -521,7 +521,7 @@ static int fec_open(struct eth_device *edev)
 	       &fec->eth->ecntrl);
 #endif
 
-#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
 	udelay(100);
 
 	/* setup the MII gasket for RMII mode */
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 62b55ef3959..1c0d0e5b8f8 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -128,7 +128,7 @@ struct ethernet_regs {
 
 	uint32_t res14[7];		/* MBAR_ETH + 0x2E4-2FC */
 
-#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
 	uint16_t miigsk_cfgr;		/* MBAR_ETH + 0x300 */
 	uint16_t res15[3];		/* MBAR_ETH + 0x302-306 */
 	uint16_t miigsk_enr;		/* MBAR_ETH + 0x308 */
@@ -196,7 +196,7 @@ struct ethernet_regs {
 #define FEC_X_DES_ACTIVE_TDAR		0x01000000
 #define FEC_R_DES_ACTIVE_RDAR		0x01000000
 
-#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
 /* defines for MIIGSK */
 /* RMII frequency control: 0=50MHz, 1=5MHz */
 #define MIIGSK_CFGR_FRCONT		(1 << 6)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 36ee43210a9..3bb5b02eabb 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -645,8 +645,7 @@ config MCFUART
 
 config MXC_UART
 	bool "IMX serial port support"
-	depends on ARCH_MX25 || ARCH_MX31 || TARGET_FLEA3 \
-		|| MX5 || MX6 || MX7 || IMX8M
+	depends on ARCH_MX31 || MX5 || MX6 || MX7 || IMX8M
 	help
 	  If you have a machine based on a Motorola IMX CPU you
 	  can enable its onboard serial port by enabling this option.
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 8171b17faf8..57a78484415 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -27,10 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE;
 
-#if !CONFIG_VAL(SYS_MALLOC_F_LEN)
-#error "Serial is required before relocation - define CONFIG_$(SPL_)SYS_MALLOC_F_LEN to make this work"
-#endif
-
 #if CONFIG_IS_ENABLED(SERIAL_PRESENT)
 static int serial_check_stdout(const void *blob, struct udevice **devp)
 {
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index a80c3e737db..3c53de165dd 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -23,7 +23,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* MX35 and older is CSPI */
-#if defined(CONFIG_MX25) || defined(CONFIG_MX31) || defined(CONFIG_MX35)
+#if defined(CONFIG_MX31)
 #define MXC_CSPI
 struct cspi_regs {
 	u32 rxdata;
@@ -48,17 +48,10 @@ struct cspi_regs {
 #define MXC_CSPICTRL_RXOVF		BIT(6)
 #define MXC_CSPIPERIOD_32KHZ		BIT(15)
 #define MAX_SPI_BYTES			4
-#if defined(CONFIG_MX25) || defined(CONFIG_MX35)
-#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
-#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
-#define MXC_CSPICTRL_TC			BIT(7)
-#define MXC_CSPICTRL_MAXBITS		0xfff
-#else	/* MX31 */
 #define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 24)
 #define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0x1f) << 8)
 #define MXC_CSPICTRL_TC			BIT(8)
 #define MXC_CSPICTRL_MAXBITS		0x1f
-#endif
 
 #else	/* MX51 and newer is ECSPI */
 #define MXC_ECSPI
@@ -211,9 +204,6 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
 		MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
 		MXC_CSPICTRL_DATARATE(div) |
 		MXC_CSPICTRL_EN |
-#ifdef CONFIG_MX35
-		MXC_CSPICTRL_SSCTL |
-#endif
 		MXC_CSPICTRL_MODE;
 
 	if (mode & SPI_CPHA)
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index d0b7ac512e8..1fb685e58d8 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -67,56 +67,7 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
 	unsigned int v;
 
 	v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
-#if defined(CONFIG_MX25)
-	switch (port) {
-	case 0:	/* OTG port */
-		v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
-				MX25_OTG_OCPOL_BIT);
-		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
-
-		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-			v |= MX25_OTG_PM_BIT;
-
-		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
-			v |= MX25_OTG_PP_BIT;
-
-		if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
-			v |= MX25_OTG_OCPOL_BIT;
-
-		break;
-	case 1: /* H1 port */
-		v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
-				MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT |
-				MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT |
-				MX25_H1_IPPUE_UP_BIT);
-		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
-
-		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-			v |= MX25_H1_PM_BIT;
-
-		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
-			v |= MX25_H1_PP_BIT;
-
-		if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
-			v |= MX25_H1_OCPOL_BIT;
-
-		if (!(flags & MXC_EHCI_TTL_ENABLED))
-			v |= MX25_H1_TLL_BIT;
-
-		if (flags & MXC_EHCI_INTERNAL_PHY)
-			v |= MX25_H1_USBTE_BIT;
-
-		if (flags & MXC_EHCI_IPPUE_DOWN)
-			v |= MX25_H1_IPPUE_DOWN_BIT;
-
-		if (flags & MXC_EHCI_IPPUE_UP)
-			v |= MX25_H1_IPPUE_UP_BIT;
-
-		break;
-	default:
-		return -EINVAL;
-	}
-#elif defined(CONFIG_MX31)
+#if defined(CONFIG_MX31)
 	switch (port) {
 	case 0:	/* OTG port */
 		v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
@@ -151,55 +102,6 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
 	default:
 		return -EINVAL;
 	}
-#elif defined(CONFIG_MX35)
-	switch (port) {
-	case 0:	/* OTG port */
-		v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |
-				MX35_OTG_OCPOL_BIT);
-		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
-
-		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-			v |= MX35_OTG_PM_BIT;
-
-		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
-			v |= MX35_OTG_PP_BIT;
-
-		if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
-			v |= MX35_OTG_OCPOL_BIT;
-
-		break;
-	case 1: /* H1 port */
-		v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT |
-				MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT |
-				MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT |
-				MX35_H1_IPPUE_UP_BIT);
-		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
-
-		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-			v |= MX35_H1_PM_BIT;
-
-		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
-			v |= MX35_H1_PP_BIT;
-
-		if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
-			v |= MX35_H1_OCPOL_BIT;
-
-		if (!(flags & MXC_EHCI_TTL_ENABLED))
-			v |= MX35_H1_TLL_BIT;
-
-		if (flags & MXC_EHCI_INTERNAL_PHY)
-			v |= MX35_H1_USBTE_BIT;
-
-		if (flags & MXC_EHCI_IPPUE_DOWN)
-			v |= MX35_H1_IPPUE_DOWN_BIT;
-
-		if (flags & MXC_EHCI_IPPUE_UP)
-			v |= MX35_H1_IPPUE_UP_BIT;
-
-		break;
-	default:
-		return -EINVAL;
-	}
 #else
 #error MXC EHCI USB driver not supported on this platform
 #endif
@@ -230,10 +132,6 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 	setbits_le32(&ehci->usbmode, CM_HOST);
 	__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
 	mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
-#ifdef CONFIG_MX35
-	/* Workaround for ENGcm11601 */
-	__raw_writel(0, &ehci->sbuscfg);
-#endif
 
 	udelay(10000);
 
diff --git a/drivers/w1/Kconfig b/drivers/w1/Kconfig
index a2c51083b15..0ffc1b6444b 100644
--- a/drivers/w1/Kconfig
+++ b/drivers/w1/Kconfig
@@ -20,7 +20,7 @@ config W1_GPIO
 
 config W1_MXC
 	bool "Enable 1-wire controller on i.MX processors"
-	depends on ARCH_MX25 || ARCH_MX31 || ARCH_MX5
+	depends on ARCH_MX31 || ARCH_MX5
 	help
 	  Support the one wire controller found in some members of the NXP
 	  i.MX SoC family.
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 6fbb5c1b6d5..eaa6f16f5c9 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -24,7 +24,7 @@ config WATCHDOG_AUTOSTART
 
 config WATCHDOG_TIMEOUT_MSECS
 	int "Watchdog timeout in msec"
-	default 128000 if ARCH_MX25 || ARCH_MX31 || ARCH_MX5 || ARCH_MX6
+	default 128000 if ARCH_MX31 || ARCH_MX5 || ARCH_MX6
 	default 128000 if ARCH_MX7 || ARCH_VF610
 	default 30000 if ARCH_SOCFPGA
 	default 60000