diff options
| author | Moti Buskila <[email protected]> | 2021-02-19 17:11:09 +0100 |
|---|---|---|
| committer | Stefan Roese <[email protected]> | 2021-02-26 10:22:29 +0100 |
| commit | 69f084f5c613942ff100fe2cc6db82337a87cc49 (patch) | |
| tree | 7a31ef4ed2464dcc7901ed640e105c1e630ef378 /drivers | |
| parent | 2ca5b190c34cda1e2d8ef1733a497839c5341db9 (diff) | |
ddr: marvell: a38x: fix write leveling suplementary algo
commit ce62bef8fac559e27245259882e45f19cdc293ad upstream.
- fix JIRA A7K8K-5056
- remove TEST_PATTERN write at the load patern stage earlier to WL SUP stage
- the WL SUP stage already writes this pattern to the memory, if the pattern exist at the memory
then the algorithm will fail, since it think that there are no phase to correct
Signed-off-by: Moti Buskila <[email protected]>
Reviewed-by: Kostya Porotchkin <[email protected]>
Signed-off-by: Marek Behún <[email protected]>
Tested-by: Chris Packham <[email protected]>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c index 979f3530b79..5fd9a052fa0 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c @@ -864,8 +864,11 @@ int ddr3_tip_load_all_pattern_to_mem(u32 dev_num) DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3))); } - for (pattern = 0; pattern < PATTERN_LAST; pattern++) + for (pattern = 0; pattern < PATTERN_LAST; pattern++) { + if (pattern == PATTERN_TEST) + continue; ddr3_tip_load_pattern_to_mem(dev_num, pattern); + } return MV_OK; } |