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authorManikandan Muralidharan <[email protected]>2025-09-23 15:28:18 +0530
committerEugen Hristev <[email protected]>2025-10-17 12:33:46 +0300
commit7885969610a415c7445aa19a759affa31bfba93e (patch)
tree3ecb1dd56ab5f5b465f4387309845d17361f491b /drivers
parent57d88e78a814d40efee09c8b147c304ec927e889 (diff)
clk: at91: remove default values for PMC_PLL_ACR
Remove default values for PMC PLL Analog Control Register(ACR) as the values are specific for each SoC and PLL, so load them from PLL characteristics structure Signed-off-by: Manikandan Muralidharan <[email protected]> Signed-off-by: Varshini Rajendran <[email protected]>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/at91/clk-sam9x60-pll.c7
1 files changed, 2 insertions, 5 deletions
diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
index 65be2775ac3..66f01472739 100644
--- a/drivers/clk/at91/clk-sam9x60-pll.c
+++ b/drivers/clk/at91/clk-sam9x60-pll.c
@@ -183,11 +183,8 @@ static int sam9x60_frac_pll_enable(struct clk *clk)
AT91_PMC_PLL_UPDT_ID_MSK,
AT91_PMC_PLL_UPDT_STUPTIM(0x3f) | pll->id);
- /* Recommended value for AT91_PMC_PLL_ACR */
- if (pll->characteristics->upll)
- val = AT91_PMC_PLL_ACR_DEFAULT_UPLL;
- else
- val = AT91_PMC_PLL_ACR_DEFAULT_PLLA;
+ /* Load recommended value for PMC_PLL_ACR */
+ val = pll->characteristics->acr;
pmc_write(base, AT91_PMC_PLL_ACR, val);
if (pll->characteristics->upll) {