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authorJonas Karlman <[email protected]>2024-04-22 06:28:39 +0000
committerKever Yang <[email protected]>2024-04-26 15:47:04 +0800
commit80274d1b642bbe2fc6f58552fe3d76bfe65ba084 (patch)
treebd35126ecc5b66a77a62ad2bc9c3847dec9c720e /drivers
parent19bf563304f2024451d5d04d4a7f0e8b73eabd7d (diff)
clk: rockchip: rk3588: Add REF_CLK_USB3OTGx support
The REF_CLK_USB3OTGx clocks is used as reference clock for USB3 block. Add simple support to get rate of REF_CLK_USB3OTGx clocks to fix reference clock period configuration. Signed-off-by: Jonas Karlman <[email protected]> Reviewed-by: Quentin Schulz <[email protected]> Acked-by: Sean Anderson <[email protected]> Reviewed-by: Kever Yang <[email protected]>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/rockchip/clk_rk3588.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c
index 8f33843179b..4c611a39049 100644
--- a/drivers/clk/rockchip/clk_rk3588.c
+++ b/drivers/clk/rockchip/clk_rk3588.c
@@ -1569,6 +1569,9 @@ static ulong rk3588_clk_get_rate(struct clk *clk)
case DCLK_DECOM:
rate = rk3588_mmc_get_clk(priv, clk->id);
break;
+ case REF_CLK_USB3OTG0:
+ case REF_CLK_USB3OTG1:
+ case REF_CLK_USB3OTG2:
case TMCLK_EMMC:
case TCLK_WDT0:
rate = OSC_HZ;
@@ -1734,6 +1737,9 @@ static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate)
case DCLK_DECOM:
ret = rk3588_mmc_set_clk(priv, clk->id, rate);
break;
+ case REF_CLK_USB3OTG0:
+ case REF_CLK_USB3OTG1:
+ case REF_CLK_USB3OTG2:
case TMCLK_EMMC:
case TCLK_WDT0:
ret = OSC_HZ;