diff options
| author | Neal Liu <[email protected]> | 2022-02-15 18:14:40 +0800 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2022-02-21 08:35:40 -0500 |
| commit | 829b41171b181e083fc984b72bb8acb31c1fb952 (patch) | |
| tree | 052eb6ef742e65f43d8f77ce9e410846d3527f6e /drivers | |
| parent | 5d90836cb51de553cf3a83143f99cd60cae26578 (diff) | |
crypto: aspeed: fix polling RSA status wrong issue
Check interrupt status to see if RSA engine is completed. After completion
of the task, write-clear the status to finish operation.
Add missing register base for completion.
Fixes: 89c36cca0b6 ("crypto: aspeed: Add AST2600 ACRY support")
Signed-off-by: Neal Liu <[email protected]>
Reviewed-by: Chia-Wei Wang <[email protected]>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/crypto/aspeed/aspeed_acry.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/crypto/aspeed/aspeed_acry.c b/drivers/crypto/aspeed/aspeed_acry.c index c28cdf374b6..47a007f633a 100644 --- a/drivers/crypto/aspeed/aspeed_acry.c +++ b/drivers/crypto/aspeed/aspeed_acry.c @@ -103,7 +103,7 @@ static int aspeed_acry_mod_exp(struct udevice *dev, const uint8_t *sig, uint32_t while (1) { reg = readl(acry->base + ACRY_RSA_INT_STS); if ((reg & ACRY_RSA_INT_STS_RSA_READY) && (reg & ACRY_RSA_INT_STS_RSA_CMPLT)) { - writel(reg, ACRY_RSA_INT_STS); + writel(reg, acry->base + ACRY_RSA_INT_STS); break; } udelay(20); |