diff options
| author | Tom Rini <[email protected]> | 2026-04-06 12:16:57 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2026-04-06 12:16:57 -0600 |
| commit | 93f84ee022a8401421cdaab84fe7d106d83fdb4a (patch) | |
| tree | fb15a4af876e8faf9893fd86c1c0e127265dbe9a /drivers | |
| parent | 88dc2788777babfd6322fa655df549a019aa1e69 (diff) | |
| parent | e2138cf1e6088f12ffa874e87cc8f4b198378635 (diff) | |
Merge branch 'next'
Diffstat (limited to 'drivers')
330 files changed, 25604 insertions, 6691 deletions
diff --git a/drivers/Makefile b/drivers/Makefile index de993ae42ac..43d0ba33281 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -73,6 +73,7 @@ obj-$(CONFIG_SPL_USB_HOST) += usb/host/ obj-$(CONFIG_SPL_SATA) += ata/ scsi/ obj-$(CONFIG_SPL_LEGACY_BLOCK) += block/ obj-$(CONFIG_SPL_THERMAL) += thermal/ +obj-$(CONFIG_SPL_UFS_SUPPORT) += scsi/ ufs/ endif endif diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 461b5a9fc83..adf338ab00c 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -106,8 +106,9 @@ config EFI_MEDIA For sandbox there is a test driver. config SPL_BLK_FS - bool "Load images from filesystems on block devices" - depends on SPL_BLK && SPL_FS_LOADER + bool + depends on SPL_BLK + select SPL_FS_LOADER help Use generic support to load images from fat/ext filesystems on different types of block devices such as NVMe. diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c index 9cb27561a97..4b3de0529ce 100644 --- a/drivers/block/sandbox.c +++ b/drivers/block/sandbox.c @@ -10,13 +10,10 @@ #include <os.h> #include <malloc.h> #include <sandbox_host.h> -#include <asm/global_data.h> #include <dm/device_compat.h> #include <dm/device-internal.h> #include <linux/errno.h> -DECLARE_GLOBAL_DATA_PTR; - static unsigned long host_block_read(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *buffer) diff --git a/drivers/bootcount/bootcount.c b/drivers/bootcount/bootcount.c index 343b8a34414..2c0114d9705 100644 --- a/drivers/bootcount/bootcount.c +++ b/drivers/bootcount/bootcount.c @@ -19,7 +19,8 @@ __weak void bootcount_store(ulong a) uintptr_t flush_end; #if defined(CONFIG_SYS_BOOTCOUNT_SINGLEWORD) - raw_bootcount_store(reg, (CONFIG_SYS_BOOTCOUNT_MAGIC & 0xffff0000) | a); + raw_bootcount_store(reg, (CONFIG_SYS_BOOTCOUNT_MAGIC & BOOTCOUNT_MAGIC_MASK) + | (a & BOOTCOUNT_COUNT_MASK)); flush_end = roundup(CONFIG_SYS_BOOTCOUNT_ADDR + 4, CONFIG_SYS_CACHELINE_SIZE); @@ -40,10 +41,10 @@ __weak ulong bootcount_load(void) #if defined(CONFIG_SYS_BOOTCOUNT_SINGLEWORD) u32 tmp = raw_bootcount_load(reg); - if ((tmp & 0xffff0000) != (CONFIG_SYS_BOOTCOUNT_MAGIC & 0xffff0000)) + if ((tmp & BOOTCOUNT_MAGIC_MASK) != (CONFIG_SYS_BOOTCOUNT_MAGIC & BOOTCOUNT_MAGIC_MASK)) return 0; else - return (tmp & 0x0000ffff); + return (tmp & BOOTCOUNT_COUNT_MASK); #else if (raw_bootcount_load(reg + 4) != CONFIG_SYS_BOOTCOUNT_MAGIC) return 0; @@ -74,10 +75,10 @@ static int bootcount_mem_get(struct udevice *dev, u32 *a) if (priv->singleword) { u32 tmp = raw_bootcount_load(reg); - if ((tmp & 0xffff0000) != (magic & 0xffff0000)) + if ((tmp & BOOTCOUNT_MAGIC_MASK) != (magic & BOOTCOUNT_MAGIC_MASK)) return -ENODEV; - *a = (tmp & 0x0000ffff); + *a = (tmp & BOOTCOUNT_COUNT_MASK); } else { if (raw_bootcount_load(reg + 4) != magic) return -ENODEV; @@ -98,7 +99,8 @@ static int bootcount_mem_set(struct udevice *dev, const u32 a) uintptr_t flush_end; if (priv->singleword) { - raw_bootcount_store(reg, (magic & 0xffff0000) | a); + raw_bootcount_store(reg, (magic & BOOTCOUNT_MAGIC_MASK) + | (a & BOOTCOUNT_COUNT_MASK)); flush_end = roundup(priv->base + 4, CONFIG_SYS_CACHELINE_SIZE); } else { diff --git a/drivers/bootcount/bootcount_at91.c b/drivers/bootcount/bootcount_at91.c index 1a06db1fb74..1322abe921e 100644 --- a/drivers/bootcount/bootcount_at91.c +++ b/drivers/bootcount/bootcount_at91.c @@ -3,6 +3,7 @@ #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/at91_gpbr.h> +#include <bootcount.h> /* * We combine the CONFIG_SYS_BOOTCOUNT_MAGIC and bootcount in one 32-bit @@ -13,7 +14,7 @@ void bootcount_store(ulong a) { at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; - writel((CONFIG_SYS_BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff), + writel((CONFIG_SYS_BOOTCOUNT_MAGIC & BOOTCOUNT_MAGIC_MASK) | (a & BOOTCOUNT_COUNT_MASK), &gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]); } @@ -22,8 +23,8 @@ ulong bootcount_load(void) at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; ulong val = readl(&gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]); - if ((val & 0xffff0000) != (CONFIG_SYS_BOOTCOUNT_MAGIC & 0xffff0000)) + if ((val & BOOTCOUNT_MAGIC_MASK) != (CONFIG_SYS_BOOTCOUNT_MAGIC & BOOTCOUNT_MAGIC_MASK)) return 0; else - return val & 0x0000ffff; + return val & BOOTCOUNT_COUNT_MASK; } diff --git a/drivers/bootcount/bootcount_davinci.c b/drivers/bootcount/bootcount_davinci.c index 6326957d7b0..a03d160a4cd 100644 --- a/drivers/bootcount/bootcount_davinci.c +++ b/drivers/bootcount/bootcount_davinci.c @@ -24,7 +24,7 @@ void bootcount_store(ulong a) writel(RTC_KICK0R_WE, ®->kick0r); writel(RTC_KICK1R_WE, ®->kick1r); raw_bootcount_store(®->scratch2, - (CONFIG_SYS_BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff)); + (CONFIG_SYS_BOOTCOUNT_MAGIC & BOOTCOUNT_MAGIC_MASK) | (a & BOOTCOUNT_COUNT_MASK)); } ulong bootcount_load(void) @@ -34,8 +34,8 @@ ulong bootcount_load(void) (struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR; val = raw_bootcount_load(®->scratch2); - if ((val & 0xffff0000) != (CONFIG_SYS_BOOTCOUNT_MAGIC & 0xffff0000)) + if ((val & BOOTCOUNT_MAGIC_MASK) != (CONFIG_SYS_BOOTCOUNT_MAGIC & BOOTCOUNT_MAGIC_MASK)) return 0; else - return val & 0x0000ffff; + return val & BOOTCOUNT_COUNT_MASK; } diff --git a/drivers/bootcount/bootcount_dm_i2c.c b/drivers/bootcount/bootcount_dm_i2c.c index e27034cbeb0..07359ecfa6c 100644 --- a/drivers/bootcount/bootcount_dm_i2c.c +++ b/drivers/bootcount/bootcount_dm_i2c.c @@ -15,6 +15,7 @@ struct bootcount_i2c_priv { struct udevice *bcdev; unsigned int offset; + unsigned int size; }; static int bootcount_i2c_set(struct udevice *dev, const u32 val) @@ -22,13 +23,22 @@ static int bootcount_i2c_set(struct udevice *dev, const u32 val) int ret; struct bootcount_i2c_priv *priv = dev_get_priv(dev); - ret = dm_i2c_reg_write(priv->bcdev, priv->offset, BC_MAGIC); - if (ret < 0) - goto err_exit; - - ret = dm_i2c_reg_write(priv->bcdev, priv->offset + 1, val & 0xff); - if (ret < 0) - goto err_exit; + if (priv->size == 4) { + u32 bc = (CONFIG_SYS_BOOTCOUNT_MAGIC & BOOTCOUNT_MAGIC_MASK) + | (val & BOOTCOUNT_COUNT_MASK); + + ret = dm_i2c_write(priv->bcdev, priv->offset, (uint8_t *)&bc, sizeof(bc)); + if (ret < 0) + goto err_exit; + } else { + ret = dm_i2c_reg_write(priv->bcdev, priv->offset, BC_MAGIC); + if (ret < 0) + goto err_exit; + + ret = dm_i2c_reg_write(priv->bcdev, priv->offset + 1, val & 0xff); + if (ret < 0) + goto err_exit; + } return 0; @@ -42,21 +52,39 @@ static int bootcount_i2c_get(struct udevice *dev, u32 *val) int ret; struct bootcount_i2c_priv *priv = dev_get_priv(dev); - ret = dm_i2c_reg_read(priv->bcdev, priv->offset); - if (ret < 0) - goto err_exit; - - if ((ret & 0xff) != BC_MAGIC) { - log_debug("%s: Invalid Magic, reset bootcounter.\n", __func__); - *val = 0; - return bootcount_i2c_set(dev, 0); + if (priv->size == 4) { + u32 bc; + + ret = dm_i2c_read(priv->bcdev, priv->offset, (uint8_t *)&bc, sizeof(bc)); + if (ret < 0) + goto err_exit; + + if ((bc & BOOTCOUNT_MAGIC_MASK) != + (CONFIG_SYS_BOOTCOUNT_MAGIC & BOOTCOUNT_MAGIC_MASK)) { + log_debug("%s: Invalid Magic, reset bootcounter.\n", __func__); + *val = 0; + return bootcount_i2c_set(dev, 0); + } + + *val = (bc & BOOTCOUNT_COUNT_MASK); + } else { + ret = dm_i2c_reg_read(priv->bcdev, priv->offset); + if (ret < 0) + goto err_exit; + + if ((ret & 0xff) != BC_MAGIC) { + log_debug("%s: Invalid Magic, reset bootcounter.\n", __func__); + *val = 0; + return bootcount_i2c_set(dev, 0); + } + + ret = dm_i2c_reg_read(priv->bcdev, priv->offset + 1); + if (ret < 0) + goto err_exit; + + *val = ret; } - ret = dm_i2c_reg_read(priv->bcdev, priv->offset + 1); - if (ret < 0) - goto err_exit; - - *val = ret; return 0; err_exit: @@ -73,6 +101,12 @@ static int bootcount_i2c_probe(struct udevice *dev) if (ret) goto exit; + priv->size = dev_read_u32_default(dev, "size", 2); + if (priv->size != 2 && priv->size != 4) { + ret = -EINVAL; + goto exit; + } + ret = i2c_get_chip_by_phandle(dev, "i2cbcdev", &priv->bcdev); exit: diff --git a/drivers/bootcount/i2c-eeprom.c b/drivers/bootcount/i2c-eeprom.c index 12c430465c9..f54515f451e 100644 --- a/drivers/bootcount/i2c-eeprom.c +++ b/drivers/bootcount/i2c-eeprom.c @@ -85,7 +85,7 @@ static const struct udevice_id bootcount_i2c_eeprom_ids[] = { { } }; -U_BOOT_DRIVER(bootcount_spi_flash) = { +U_BOOT_DRIVER(bootcount_i2c_eeprom) = { .name = "bootcount-i2c-eeprom", .id = UCLASS_BOOTCOUNT, .priv_auto = sizeof(struct bootcount_i2c_eeprom_priv), diff --git a/drivers/bootcount/pmic_pfuze100.c b/drivers/bootcount/pmic_pfuze100.c index 8c529f5592b..dd11344322b 100644 --- a/drivers/bootcount/pmic_pfuze100.c +++ b/drivers/bootcount/pmic_pfuze100.c @@ -13,8 +13,6 @@ #include <power/pmic.h> #include <power/pfuze100_pmic.h> -DECLARE_GLOBAL_DATA_PTR; - #define PFUZE_BC_MAGIC 0xdead struct bootcount_pmic_priv { diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index f5bcd406a50..3bf5c7f5dbf 100644 --- a/drivers/cache/Kconfig +++ b/drivers/cache/Kconfig @@ -46,11 +46,5 @@ config SIFIVE_CCACHE This driver is for SiFive Composable L2/L3 cache. It enables cache ways of composable cache. -config SIFIVE_PL2 - bool "SiFive private L2 cache" - select CACHE - help - This driver is for SiFive Private L2 cache. It configures registers - to enable the clock gating feature. endmenu diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile index 2f683866b87..05ad7d8a33e 100644 --- a/drivers/cache/Makefile +++ b/drivers/cache/Makefile @@ -5,4 +5,3 @@ obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o obj-$(CONFIG_ANDES_L2_CACHE) += cache-andes-l2.o obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o -obj-$(CONFIG_SIFIVE_PL2) += cache-sifive-pl2.o diff --git a/drivers/cache/sandbox_cache.c b/drivers/cache/sandbox_cache.c index 375892fafb0..b27960f1bfa 100644 --- a/drivers/cache/sandbox_cache.c +++ b/drivers/cache/sandbox_cache.c @@ -6,9 +6,6 @@ #include <cache.h> #include <dm.h> #include <errno.h> -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; static int sandbox_get_info(struct udevice *dev, struct cache_info *info) { diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c88931c8ec4..c2da7b3938b 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -185,6 +185,7 @@ config SANDBOX_CLK_CCF bool "Sandbox Common Clock Framework [CCF] support" depends on SANDBOX select CLK_CCF + select CLK_COMPOSITE_CCF help Enable this option if you want to test the Linux kernel's Common Clock Framework [CCF] code in U-Boot's Sandbox clock driver. diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile index 858f828e537..693446b3d89 100644 --- a/drivers/clk/altera/Makefile +++ b/drivers/clk/altera/Makefile @@ -3,9 +3,9 @@ # Copyright (C) 2018-2021 Marek Vasut <[email protected]> # -obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o -obj-$(CONFIG_TARGET_SOCFPGA_AGILEX7M) += clk-agilex.o -obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o -obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o -obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-mem-n5x.o -obj-$(CONFIG_TARGET_SOCFPGA_AGILEX5) += clk-agilex5.o +obj-$(CONFIG_ARCH_SOCFPGA_AGILEX) += clk-agilex.o +obj-$(CONFIG_ARCH_SOCFPGA_AGILEX7M) += clk-agilex.o +obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += clk-arria10.o +obj-$(CONFIG_ARCH_SOCFPGA_N5X) += clk-n5x.o +obj-$(CONFIG_ARCH_SOCFPGA_N5X) += clk-mem-n5x.o +obj-$(CONFIG_ARCH_SOCFPGA_AGILEX5) += clk-agilex5.o diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index fdbf834bb2f..b793dbf6a42 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -6,7 +6,6 @@ #include <log.h> #include <wait_bit.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/system.h> #include <clk-uclass.h> @@ -19,8 +18,6 @@ #include <asm/arch/clock_manager.h> -DECLARE_GLOBAL_DATA_PTR; - struct socfpga_clk_plat { void __iomem *regs; int pllgrp; @@ -657,6 +654,7 @@ static int bitmask_from_clk_id(struct clk *clk) plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MAINCLK_MASK; break; case AGILEX_L4_MP_CLK: + case AGILEX_NAND_X_CLK: plat->pllgrp = CLKMGR_MAINPLL_EN; plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK; break; @@ -728,6 +726,8 @@ static int bitmask_from_clk_id(struct clk *clk) plat->pllgrp = CLKMGR_PERPLL_EN; plat->bitmask = CLKMGR_PERPLLGRP_EN_NANDCLK_MASK; break; + case AGILEX_L4_SYS_FREE_CLK: + return -EOPNOTSUPP; default: return -ENXIO; } @@ -742,6 +742,9 @@ static int socfpga_clk_enable(struct clk *clk) int ret; ret = bitmask_from_clk_id(clk); + if (ret == -EOPNOTSUPP) + return 0; + if (ret) return ret; @@ -757,6 +760,9 @@ static int socfpga_clk_disable(struct clk *clk) int ret; ret = bitmask_from_clk_id(clk); + if (ret == -EOPNOTSUPP) + return 0; + if (ret) return ret; diff --git a/drivers/clk/altera/clk-agilex5.c b/drivers/clk/altera/clk-agilex5.c index fb1e72ffc5c..92b91a9dfc8 100644 --- a/drivers/clk/altera/clk-agilex5.c +++ b/drivers/clk/altera/clk-agilex5.c @@ -12,7 +12,6 @@ #include <stdio.h> #include <time.h> #include <vsprintf.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/system.h> #include <dm/lists.h> @@ -26,8 +25,6 @@ #include <wait_bit.h> #include <clk-uclass.h> -DECLARE_GLOBAL_DATA_PTR; - #define CLKMGR_CTRL_SWCTRLBTCLKEN_MASK BIT(8) #define CLKMGR_CTRL_SWCTRLBTCLKSEL_MASK BIT(9) diff --git a/drivers/clk/altera/clk-mem-n5x.c b/drivers/clk/altera/clk-mem-n5x.c index b75f52d203b..ac59571a853 100644 --- a/drivers/clk/altera/clk-mem-n5x.c +++ b/drivers/clk/altera/clk-mem-n5x.c @@ -4,7 +4,6 @@ */ #include <asm/arch/clock_manager.h> -#include <asm/global_data.h> #include <asm/io.h> #include "clk-mem-n5x.h" #include <clk-uclass.h> @@ -13,8 +12,6 @@ #include <dm/util.h> #include <dt-bindings/clock/n5x-clock.h> -DECLARE_GLOBAL_DATA_PTR; - struct socfpga_mem_clk_plat { void __iomem *regs; }; diff --git a/drivers/clk/altera/clk-n5x.c b/drivers/clk/altera/clk-n5x.c index 9e4e7a1d908..185c9028a78 100644 --- a/drivers/clk/altera/clk-n5x.c +++ b/drivers/clk/altera/clk-n5x.c @@ -4,7 +4,6 @@ */ #include <asm/arch/clock_manager.h> -#include <asm/global_data.h> #include <asm/io.h> #include <clk-uclass.h> #include <dm.h> @@ -12,8 +11,6 @@ #include <dm/util.h> #include <dt-bindings/clock/n5x-clock.h> -DECLARE_GLOBAL_DATA_PTR; - struct socfpga_clk_plat { void __iomem *regs; }; diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index b69355cefc7..f57ac79f8ca 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -13,6 +13,21 @@ #include "clk.h" +#define SET_CLK_RATE(id, rate) \ + do { \ + struct clk *clk; \ + clk_get_by_id(id, &clk); \ + clk_set_rate(clk, rate); \ + } while (0) + +#define SET_CLK_PARENT(child_id, parent_id) \ + do { \ + struct clk *clk, *clk_parent; \ + clk_get_by_id(parent_id, &clk_parent); \ + clk_get_by_id(child_id, &clk); \ + clk_set_parent(clk, clk_parent); \ + } while (0) + static int imx6q_clk_request(struct clk *clk) { if (clk->id < IMX6QDL_CLK_DUMMY || clk->id >= IMX6QDL_CLK_END) { @@ -31,12 +46,72 @@ static struct clk_ops imx6q_clk_ops = { .disable = ccf_clk_disable, }; -static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; -static const char *const periph_sels[] = { "periph_pre", "periph_clk2", }; -static const char *const periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", - "pll2_pfd0_352m", "pll2_198m", }; -static const char *const uart_sels[] = { "pll3_80m", "osc", }; -static const char *const ecspi_sels[] = { "pll3_60m", "osc", }; +static const char *const usdhc_sels[] = { + "pll2_pfd2_396m", + "pll2_pfd0_352m", +}; +static const char *const periph_sels[] = { + "periph_pre", + "periph_clk2", +}; +static const char *periph2_sels[] = { + "periph2_pre", + "periph2_clk2", +}; +static const char *const periph_pre_sels[] = { + "pll2_bus", + "pll2_pfd2_396m", + "pll2_pfd0_352m", + "pll2_198m", +}; +static const char *const uart_sels[] = { + "pll3_80m", + "osc", +}; +static const char *const ecspi_sels[] = { + "pll3_60m", + "osc", +}; +static const char *const ipu_sels[] = { + "mmdc_ch0_axi", + "pll2_pfd2_396m", + "pll3_120m", + "pll3_pfd1_540m", +}; +static const char *const ldb_di_sels[] = { + "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", + "mmdc_ch1_axi", "pll3_usb_otg", +}; +static const char *const ipu_di_pre_sels[] = { + "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", + "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", +}; +static const char *const ipu1_di0_sels[] = { + "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", +}; +static const char *const ipu1_di1_sels[] = { + "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", +}; +static const char *const ipu2_di0_sels[] = { + "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", +}; +static const char *const ipu2_di1_sels[] = { + "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", +}; +static const char *ipu1_di0_sels_2[] = { + "ipu1_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", +}; +static const char *ipu1_di1_sels_2[] = { + "ipu1_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", +}; +static const char *ipu2_di0_sels_2[] = { + "ipu2_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", +}; +static const char *ipu2_di1_sels_2[] = { + "ipu2_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", +}; + +static unsigned int share_count_mipi_core_cfg; static int imx6q_clk_probe(struct udevice *dev) { @@ -52,15 +127,37 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3)); clk_dm(IMX6QDL_CLK_PLL3_60M, - imx_clk_fixed_factor(dev, "pll3_60m", "pll3_usb_otg", 1, 8)); + imx_clk_fixed_factor(dev, "pll3_60m", "pll3_usb_otg", 1, 8)); + clk_dm(IMX6QDL_CLK_PLL3_80M, + imx_clk_fixed_factor(dev, "pll3_80m", "pll3_usb_otg", 1, 6)); + clk_dm(IMX6QDL_CLK_PLL3_120M, + imx_clk_fixed_factor(dev, "pll3_120m", "pll3_usb_otg", 1, 4)); + clk_dm(IMX6QDL_CLK_PLL5, imx_clk_pllv3(dev, IMX_PLLV3_AV, "pll5", "osc", + base + 0xa0, 0x7f)); + clk_dm(IMX6QDL_CLK_PLL5_VIDEO, + imx_clk_gate(dev, "pll5_video", "pll5", base + 0xa0, 13)); + clk_dm(IMX6QDL_CLK_PLL6, imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", + "osc", base + 0xe0, 0x3)); + clk_dm(IMX6QDL_CLK_PLL6_ENET, + imx_clk_gate(dev, "pll6_enet", "pll6", base + 0xe0, 13)); + clk_dm(IMX6QDL_CLK_PLL2_PFD0_352M, imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0)); clk_dm(IMX6QDL_CLK_PLL2_PFD2_396M, imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2)); - clk_dm(IMX6QDL_CLK_PLL6, - imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3)); - clk_dm(IMX6QDL_CLK_PLL6_ENET, - imx_clk_gate(dev, "pll6_enet", "pll6", base + 0xe0, 13)); + clk_dm(IMX6QDL_CLK_PLL3_PFD1_540M, + imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1)); + + clk_dm(IMX6QDL_CLK_PLL2_198M, + imx_clk_fixed_factor(dev, "pll2_198m", "pll2_pfd2_396m", 1, 2)); + clk_dm(IMX6QDL_CLK_PLL5_POST_DIV, + imx_clk_fixed_factor(dev, "pll5_post_div", "pll5_video", 1, 1)); + clk_dm(IMX6QDL_CLK_PLL5_VIDEO_DIV, + imx_clk_fixed_factor(dev, "pll5_video_div", "pll5_post_div", 1, + 1)); + clk_dm(IMX6QDL_CLK_VIDEO_27M, + imx_clk_fixed_factor(dev, "video_27m", "pll3_pfd1_540m", 1, + 20)); /* CCM clocks */ base = dev_read_addr_ptr(dev); @@ -68,50 +165,253 @@ static int imx6q_clk_probe(struct udevice *dev) return -EINVAL; clk_dm(IMX6QDL_CLK_USDHC1_SEL, - imx_clk_mux(dev, "usdhc1_sel", base + 0x1c, 16, 1, - usdhc_sels, ARRAY_SIZE(usdhc_sels))); + imx_clk_mux(dev, "usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, + ARRAY_SIZE(usdhc_sels))); clk_dm(IMX6QDL_CLK_USDHC2_SEL, - imx_clk_mux(dev, "usdhc2_sel", base + 0x1c, 17, 1, - usdhc_sels, ARRAY_SIZE(usdhc_sels))); + imx_clk_mux(dev, "usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, + ARRAY_SIZE(usdhc_sels))); clk_dm(IMX6QDL_CLK_USDHC3_SEL, - imx_clk_mux(dev, "usdhc3_sel", base + 0x1c, 18, 1, - usdhc_sels, ARRAY_SIZE(usdhc_sels))); + imx_clk_mux(dev, "usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, + ARRAY_SIZE(usdhc_sels))); clk_dm(IMX6QDL_CLK_USDHC4_SEL, - imx_clk_mux(dev, "usdhc4_sel", base + 0x1c, 19, 1, - usdhc_sels, ARRAY_SIZE(usdhc_sels))); + imx_clk_mux(dev, "usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, + ARRAY_SIZE(usdhc_sels))); if (of_machine_is_compatible("fsl,imx6qp")) { clk_dm(IMX6QDL_CLK_UART_SEL, - imx_clk_mux(dev, "uart_sel", base + 0x24, 6, 1, uart_sels, - ARRAY_SIZE(uart_sels))); + imx_clk_mux(dev, "uart_sel", base + 0x24, 6, 1, + uart_sels, ARRAY_SIZE(uart_sels))); clk_dm(IMX6QDL_CLK_ECSPI_SEL, - imx_clk_mux(dev, "ecspi_sel", base + 0x38, 18, 1, ecspi_sels, - ARRAY_SIZE(ecspi_sels))); + imx_clk_mux(dev, "ecspi_sel", base + 0x38, 18, 1, + ecspi_sels, ARRAY_SIZE(ecspi_sels))); } + clk_dm(IMX6QDL_CLK_PERIPH_PRE, + imx_clk_mux(dev, "periph_pre", base + 0x18, 18, 2, + periph_pre_sels, ARRAY_SIZE(periph_pre_sels))); + clk_dm(IMX6QDL_CLK_PERIPH2_PRE, + imx_clk_mux(dev, "periph2_pre", base + 0x18, 21, 2, + periph_pre_sels, ARRAY_SIZE(periph_pre_sels))); + clk_dm(IMX6QDL_CLK_PERIPH, + imx_clk_busy_mux(dev, "periph", base + 0x14, 25, 1, base + 0x48, + 5, periph_sels, ARRAY_SIZE(periph_sels))); + clk_dm(IMX6QDL_CLK_PERIPH2, + imx_clk_busy_mux(dev, "periph2", base + 0x14, 26, 1, base + 0x48, + 3, periph2_sels, ARRAY_SIZE(periph2_sels))); + clk_dm(IMX6QDL_CLK_USDHC1_PODF, - imx_clk_divider(dev, "usdhc1_podf", "usdhc1_sel", - base + 0x24, 11, 3)); + imx_clk_divider(dev, "usdhc1_podf", "usdhc1_sel", base + 0x24, + 11, 3)); clk_dm(IMX6QDL_CLK_USDHC2_PODF, - imx_clk_divider(dev, "usdhc2_podf", "usdhc2_sel", - base + 0x24, 16, 3)); + imx_clk_divider(dev, "usdhc2_podf", "usdhc2_sel", base + 0x24, + 16, 3)); clk_dm(IMX6QDL_CLK_USDHC3_PODF, - imx_clk_divider(dev, "usdhc3_podf", "usdhc3_sel", - base + 0x24, 19, 3)); + imx_clk_divider(dev, "usdhc3_podf", "usdhc3_sel", base + 0x24, + 19, 3)); clk_dm(IMX6QDL_CLK_USDHC4_PODF, - imx_clk_divider(dev, "usdhc4_podf", "usdhc4_sel", - base + 0x24, 22, 3)); + imx_clk_divider(dev, "usdhc4_podf", "usdhc4_sel", base + 0x24, + 22, 3)); if (of_machine_is_compatible("fsl,imx6qp")) { clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF, - imx_clk_divider(dev, "uart_serial_podf", "uart_sel", base + 0x24, 0, 6)); + imx_clk_divider(dev, "uart_serial_podf", "uart_sel", + base + 0x24, 0, 6)); clk_dm(IMX6QDL_CLK_ECSPI_ROOT, - imx_clk_divider(dev, "ecspi_root", "ecspi_sel", base + 0x38, 19, 6)); + imx_clk_divider(dev, "ecspi_root", "ecspi_sel", + base + 0x38, 19, 6)); } else { clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF, - imx_clk_divider(dev, "uart_serial_podf", "pll3_80m", base + 0x24, 0, 6)); + imx_clk_divider(dev, "uart_serial_podf", "pll3_80m", + base + 0x24, 0, 6)); clk_dm(IMX6QDL_CLK_ECSPI_ROOT, - imx_clk_divider(dev, "ecspi_root", "pll3_60m", base + 0x38, 19, 6)); + imx_clk_divider(dev, "ecspi_root", "pll3_60m", + base + 0x38, 19, 6)); + } + + clk_dm(IMX6QDL_CLK_AHB, + imx_clk_busy_divider(dev, "ahb", "periph", base + 0x14, 10, 3, + base + 0x48, 1)); + clk_dm(IMX6QDL_CLK_IPG, + imx_clk_divider(dev, "ipg", "ahb", base + 0x14, 8, 2)); + clk_dm(IMX6QDL_CLK_IPG_PER, + imx_clk_divider(dev, "ipg_per", "ipg", base + 0x1c, 0, 6)); + clk_dm(IMX6QDL_CLK_UART_IPG, + imx_clk_gate2(dev, "uart_ipg", "ipg", base + 0x7c, 24)); + + if (of_machine_is_compatible("fsl,imx6qp")) { + clk_dm(IMX6QDL_CLK_MMDC_CH1_AXI_CG, + imx_clk_gate2(dev, "mmdc_ch1_axi_cg", "periph2", + base + 0x4, 18)); + clk_dm(IMX6QDL_CLK_MMDC_CH1_AXI_PODF, + imx_clk_busy_divider(dev, "mmdc_ch1_axi_podf", + "mmdc_ch1_axi_cg", base + 0x14, 3, + 3, base + 0x48, 2)); + } else { + clk_dm(IMX6QDL_CLK_MMDC_CH1_AXI_PODF, + imx_clk_busy_divider(dev, "mmdc_ch1_axi_podf", "periph2", + base + 0x14, 3, 3, base + 0x48, 2)); + } + + clk_dm(IMX6QDL_CLK_MMDC_CH0_AXI_PODF, + imx_clk_busy_divider(dev, "mmdc_ch0_axi_podf", "periph", + base + 0x14, 19, 3, base + 0x48, 4)); + + clk_dm(IMX6QDL_CLK_MMDC_CH0_AXI, + imx_clk_gate2_flags(dev, "mmdc_ch0_axi", "mmdc_ch0_axi_podf", + base + 0x74, 20, CLK_IS_CRITICAL)); + clk_dm(IMX6QDL_CLK_MMDC_CH1_AXI, + imx_clk_gate2(dev, "mmdc_ch1_axi", "mmdc_ch1_axi_podf", + base + 0x74, 22)); + + clk_dm(IMX6QDL_CLK_IPU1_SEL, + imx_clk_mux(dev, "ipu1_sel", base + 0x3c, 9, 2, ipu_sels, + ARRAY_SIZE(ipu_sels))); + clk_dm(IMX6QDL_CLK_IPU2_SEL, + imx_clk_mux(dev, "ipu2_sel", base + 0x3c, 14, 2, ipu_sels, + ARRAY_SIZE(ipu_sels))); + + if (of_machine_is_compatible("fsl,imx6qp")) { + clk_dm(IMX6QDL_CLK_LDB_DI0_SEL, + imx_clk_mux(dev, "ldb_di0_sel", base + 0x2c, 9, 3, + ldb_di_sels, ARRAY_SIZE(ldb_di_sels))); + clk_dm(IMX6QDL_CLK_LDB_DI1_SEL, + imx_clk_mux(dev, "ldb_di1_sel", base + 0x2c, 12, 3, + ldb_di_sels, ARRAY_SIZE(ldb_di_sels))); + } else { + /* + * Need to set these as read-only due to a hardware bug. + * Keeping default mux values. Fixed on the i.MX6 QuadPlus + */ + clk_dm(IMX6QDL_CLK_LDB_DI0_SEL, + imx_clk_mux_flags(dev, "ldb_di0_sel", base + 0x2c, 9, 3, + ldb_di_sels, ARRAY_SIZE(ldb_di_sels), + CLK_SET_RATE_PARENT | + CLK_MUX_READ_ONLY)); + clk_dm(IMX6QDL_CLK_LDB_DI1_SEL, + imx_clk_mux_flags(dev, "ldb_di1_sel", base + 0x2c, 12, 3, + ldb_di_sels, ARRAY_SIZE(ldb_di_sels), + CLK_SET_RATE_PARENT | + CLK_MUX_READ_ONLY)); + } + + clk_dm(IMX6QDL_CLK_IPU1_DI0_PRE_SEL, + imx_clk_mux_flags(dev, "ipu1_di0_pre_sel", base + 0x34, 6, 3, + ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_CLK_IPU1_DI1_PRE_SEL, + imx_clk_mux_flags(dev, "ipu1_di1_pre_sel", base + 0x34, 15, 3, + ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_CLK_IPU2_DI0_PRE_SEL, + imx_clk_mux_flags(dev, "ipu2_di0_pre_sel", base + 0x38, 6, 3, + ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_CLK_IPU2_DI1_PRE_SEL, + imx_clk_mux_flags(dev, "ipu2_di1_pre_sel", base + 0x38, 15, 3, + ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), + CLK_SET_RATE_PARENT)); + + if (of_machine_is_compatible("fsl,imx6qp")) { + clk_dm(IMX6QDL_CLK_LDB_DI0, + imx_clk_gate2(dev, "ldb_di0", "ldb_di0_sel", base + 0x74, + 12)); + clk_dm(IMX6QDL_CLK_LDB_DI1, + imx_clk_gate2(dev, "ldb_di1", "ldb_di1_sel", base + 0x74, + 14)); + clk_dm(IMX6QDL_CLK_LDB_DI0_DIV_3_5, + imx_clk_fixed_factor(dev, "ldb_di0_div_3_5", "ldb_di0", + 2, 7)); + clk_dm(IMX6QDL_CLK_LDB_DI1_DIV_3_5, + imx_clk_fixed_factor(dev, "ldb_di1_div_3_5", "ldb_di1", + 2, 7)); + clk_dm(IMX6QDL_CLK_LDB_DI0_PODF, + imx_clk_divider(dev, "ldb_di0_podf", "ldb_di0_div_3_5", + base + 0x20, 10, 1)); + clk_dm(IMX6QDL_CLK_LDB_DI1_PODF, + imx_clk_divider(dev, "ldb_di1_podf", "ldb_di1_div_3_5", + base + 0x20, 11, 1)); + } else { + clk_dm(IMX6QDL_CLK_LDB_DI0_DIV_3_5, + imx_clk_fixed_factor(dev, "ldb_di0_div_3_5", + "ldb_di0_sel", 2, 7)); + clk_dm(IMX6QDL_CLK_LDB_DI1_DIV_3_5, + imx_clk_fixed_factor(dev, "ldb_di1_div_3_5", + "ldb_di1_sel", 2, 7)); + clk_dm(IMX6QDL_CLK_LDB_DI0_PODF, + imx_clk_divider(dev, "ldb_di0_podf", "ldb_di0_div_3_5", + base + 0x20, 10, 1)); + clk_dm(IMX6QDL_CLK_LDB_DI1_PODF, + imx_clk_divider(dev, "ldb_di1_podf", "ldb_di1_div_3_5", + base + 0x20, 11, 1)); + clk_dm(IMX6QDL_CLK_LDB_DI0, + imx_clk_gate2(dev, "ldb_di0", "ldb_di0_podf", + base + 0x74, 12)); + clk_dm(IMX6QDL_CLK_LDB_DI1, + imx_clk_gate2(dev, "ldb_di1", "ldb_di1_podf", + base + 0x74, 14)); + } + + clk_dm(IMX6QDL_CLK_IPU1_PODF, + imx_clk_divider(dev, "ipu1_podf", "ipu1_sel", base + 0x3c, 11, + 3)); + clk_dm(IMX6QDL_CLK_IPU2_PODF, + imx_clk_divider(dev, "ipu2_podf", "ipu2_sel", base + 0x3c, 16, + 3)); + clk_dm(IMX6QDL_CLK_IPU1_DI0_PRE, + imx_clk_divider(dev, "ipu1_di0_pre", "ipu1_di0_pre_sel", + base + 0x34, 3, 3)); + clk_dm(IMX6QDL_CLK_IPU1_DI1_PRE, + imx_clk_divider(dev, "ipu1_di1_pre", "ipu1_di1_pre_sel", + base + 0x34, 12, 3)); + clk_dm(IMX6QDL_CLK_IPU2_DI0_PRE, + imx_clk_divider(dev, "ipu2_di0_pre", "ipu2_di0_pre_sel", + base + 0x38, 3, 3)); + clk_dm(IMX6QDL_CLK_IPU2_DI1_PRE, + imx_clk_divider(dev, "ipu2_di1_pre", "ipu2_di1_pre_sel", + base + 0x38, 12, 3)); + + if (of_machine_is_compatible("fsl,imx6qp")) { + clk_dm(IMX6QDL_CLK_IPU1_DI0_SEL, + imx_clk_mux_flags(dev, "ipu1_di0_sel", base + 0x34, 0, 3, + ipu1_di0_sels_2, + ARRAY_SIZE(ipu1_di0_sels_2), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_CLK_IPU1_DI1_SEL, + imx_clk_mux_flags(dev, "ipu1_di1_sel", base + 0x34, 9, 3, + ipu1_di1_sels_2, + ARRAY_SIZE(ipu1_di1_sels_2), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_CLK_IPU2_DI0_SEL, + imx_clk_mux_flags(dev, "ipu2_di0_sel", base + 0x38, 0, 3, + ipu2_di0_sels_2, + ARRAY_SIZE(ipu2_di0_sels_2), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_CLK_IPU2_DI1_SEL, + imx_clk_mux_flags(dev, "ipu2_di1_sel", base + 0x38, 9, 3, + ipu2_di1_sels_2, + ARRAY_SIZE(ipu2_di1_sels_2), + CLK_SET_RATE_PARENT)); + } else { + clk_dm(IMX6QDL_CLK_IPU1_DI0_SEL, + imx_clk_mux_flags(dev, "ipu1_di0_sel", base + 0x34, 0, 3, + ipu1_di0_sels, + ARRAY_SIZE(ipu1_di0_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_CLK_IPU1_DI1_SEL, + imx_clk_mux_flags(dev, "ipu1_di1_sel", base + 0x34, 9, 3, + ipu1_di1_sels, + ARRAY_SIZE(ipu1_di1_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_CLK_IPU2_DI0_SEL, + imx_clk_mux_flags(dev, "ipu2_di0_sel", base + 0x38, 0, 3, + ipu2_di0_sels, + ARRAY_SIZE(ipu2_di0_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_CLK_IPU2_DI1_SEL, + imx_clk_mux_flags(dev, "ipu2_di1_sel", base + 0x38, 9, 3, + ipu2_di1_sels, + ARRAY_SIZE(ipu2_di1_sels), + CLK_SET_RATE_PARENT)); } clk_dm(IMX6QDL_CLK_ECSPI1, @@ -122,10 +422,11 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_gate2(dev, "ecspi3", "ecspi_root", base + 0x6c, 4)); clk_dm(IMX6QDL_CLK_ECSPI4, imx_clk_gate2(dev, "ecspi4", "ecspi_root", base + 0x6c, 6)); - clk_dm(IMX6QDL_CLK_UART_IPG, - imx_clk_gate2(dev, "uart_ipg", "ipg", base + 0x7c, 24)); clk_dm(IMX6QDL_CLK_UART_SERIAL, - imx_clk_gate2(dev, "uart_serial", "uart_serial_podf", base + 0x7c, 26)); + imx_clk_gate2(dev, "uart_serial", "uart_serial_podf", + base + 0x7c, 26)); + clk_dm(IMX6QDL_CLK_USBOH3, + imx_clk_gate2(dev, "usboh3", "ipg", base + 0x80, 0)); clk_dm(IMX6QDL_CLK_USDHC1, imx_clk_gate2(dev, "usdhc1", "usdhc1_podf", base + 0x80, 2)); clk_dm(IMX6QDL_CLK_USDHC2, @@ -134,20 +435,6 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_gate2(dev, "usdhc3", "usdhc3_podf", base + 0x80, 6)); clk_dm(IMX6QDL_CLK_USDHC4, imx_clk_gate2(dev, "usdhc4", "usdhc4_podf", base + 0x80, 8)); - - clk_dm(IMX6QDL_CLK_PERIPH_PRE, - imx_clk_mux(dev, "periph_pre", base + 0x18, 18, 2, periph_pre_sels, - ARRAY_SIZE(periph_pre_sels))); - clk_dm(IMX6QDL_CLK_PERIPH, - imx_clk_busy_mux(dev, "periph", base + 0x14, 25, 1, base + 0x48, - 5, periph_sels, ARRAY_SIZE(periph_sels))); - clk_dm(IMX6QDL_CLK_AHB, - imx_clk_busy_divider(dev, "ahb", "periph", base + 0x14, 10, 3, - base + 0x48, 1)); - clk_dm(IMX6QDL_CLK_IPG, - imx_clk_divider(dev, "ipg", "ahb", base + 0x14, 8, 2)); - clk_dm(IMX6QDL_CLK_IPG_PER, - imx_clk_divider(dev, "ipg_per", "ipg", base + 0x1c, 0, 6)); clk_dm(IMX6QDL_CLK_I2C1, imx_clk_gate2(dev, "i2c1", "ipg_per", base + 0x70, 6)); clk_dm(IMX6QDL_CLK_I2C2, @@ -162,17 +449,44 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_gate2(dev, "pwm3", "ipg_per", base + 0x78, 20)); clk_dm(IMX6QDL_CLK_PWM4, imx_clk_gate2(dev, "pwm4", "ipg_per", base + 0x78, 22)); - - clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2(dev, "enet", "ipg", base + 0x6c, 10)); + clk_dm(IMX6QDL_CLK_ENET, + imx_clk_gate2(dev, "enet", "ipg", base + 0x6c, 10)); clk_dm(IMX6QDL_CLK_ENET_REF, imx_clk_fixed_factor(dev, "enet_ref", "pll6_enet", 1, 1)); + clk_dm(IMX6QDL_CLK_MIPI_CORE_CFG, + imx_clk_gate2_shared(dev, "mipi_core_cfg", "video_27m", + base + 0x74, 16, + &share_count_mipi_core_cfg)); + clk_dm(IMX6QDL_CLK_HDMI_IAHB, + imx_clk_gate2(dev, "hdmi_iahb", "ahb", base + 0x70, 0)); + clk_dm(IMX6QDL_CLK_HDMI_ISFR, + imx_clk_gate2(dev, "hdmi_isfr", "mipi_core_cfg", base + 0x70, + 4)); + clk_dm(IMX6QDL_CLK_IPU1, + imx_clk_gate2(dev, "ipu1", "ipu1_podf", base + 0x74, 0)); + clk_dm(IMX6QDL_CLK_IPU2, + imx_clk_gate2(dev, "ipu2", "ipu2_podf", base + 0x74, 6)); + clk_dm(IMX6QDL_CLK_IPU1_DI0, + imx_clk_gate2(dev, "ipu1_di0", "ipu1_di0_sel", base + 0x74, 2)); + clk_dm(IMX6QDL_CLK_IPU1_DI1, + imx_clk_gate2(dev, "ipu1_di1", "ipu1_di1_sel", base + 0x74, 4)); + clk_dm(IMX6QDL_CLK_IPU2_DI0, + imx_clk_gate2(dev, "ipu2_di0", "ipu2_di0_sel", base + 0x74, 8)); + clk_dm(IMX6QDL_CLK_IPU2_DI1, + imx_clk_gate2(dev, "ipu2_di1", "ipu2_di1_sel", base + 0x74, 10)); + + if (of_machine_is_compatible("fsl,imx6dl")) { + SET_CLK_RATE(IMX6QDL_CLK_PLL3_PFD1_540M, 540000000UL); + SET_CLK_PARENT(IMX6QDL_CLK_IPU1_SEL, + IMX6QDL_CLK_PLL3_PFD1_540M); + } return 0; } static const struct udevice_id imx6q_clk_ids[] = { { .compatible = "fsl,imx6q-ccm" }, - { }, + {}, }; U_BOOT_DRIVER(imx6q_clk) = { diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 7d14dbc395f..b53f35df84f 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -95,6 +95,15 @@ static inline struct clk *imx_clk_gate2(struct udevice *dev, const char *name, shift, 0x3, 0, NULL); } +static inline struct clk * +imx_clk_gate2_flags(struct udevice *dev, const char *name, const char *parent, + void __iomem *reg, u8 shift, unsigned long flags) +{ + return clk_register_gate2(dev, name, parent, + flags | CLK_SET_RATE_PARENT, reg, shift, 0x3, + 0, NULL); +} + static inline struct clk *imx_clk_gate2_shared(struct udevice *dev, const char *name, const char *parent, void __iomem *reg, u8 shift, diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 68b3d6e9610..d4cac6aaf52 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -12,6 +12,8 @@ obj-$(CONFIG_TARGET_MT7988) += clk-mt7988.o obj-$(CONFIG_TARGET_MT7987) += clk-mt7987.o obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o obj-$(CONFIG_TARGET_MT8188) += clk-mt8188.o +obj-$(CONFIG_TARGET_MT8189) += clk-mt8189.o +obj-$(CONFIG_TARGET_MT8195) += clk-mt8195.o obj-$(CONFIG_TARGET_MT8365) += clk-mt8365.o obj-$(CONFIG_TARGET_MT8512) += clk-mt8512.o obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index f73bd254579..79315912fd4 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -28,6 +28,14 @@ #define MCU_BUS_MSK GENMASK(10, 9) #define MCU_BUS_SEL(x) ((x) << 9) +enum { + CLK_PAD_CLK25M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK25M] = 25 * MHZ, +}; + /* apmixedsys */ #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ _pd_shift, _pcw_reg, _pcw_shift) { \ @@ -48,9 +56,9 @@ static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0, 21, 0x204, 24, 0x204, 0), - PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR, + PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, CLK_PLL_HAVE_RST_BAR, 21, 0x214, 24, 0x214, 0), - PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR, + PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, CLK_PLL_HAVE_RST_BAR, 7, 0x224, 24, 0x224, 14), PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0, 21, 0x300, 1, 0x304, 0), @@ -86,7 +94,7 @@ static const struct mtk_gate apmixed_cgs[] = { /* topckgen */ #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK25M, CLK_PARENT_EXT, _rate) #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -95,7 +103,7 @@ static const struct mtk_gate apmixed_cgs[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, 0) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_TO_U2_PHY, 31250000), @@ -116,8 +124,8 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR0(CLK_TOP_4MHZ, CLK_APMIXED_ETH1PLL, 1, 125), FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500), FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1), - FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024), - FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1), + FACTOR2(CLK_TOP_RTC, CLK_PAD_CLK25M, 1, 1024), + FACTOR2(CLK_TOP_MEMPLL, CLK_PAD_CLK25M, 32, 1), FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1), FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2), FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4), @@ -159,173 +167,173 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1), }; -static const int axi_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL_D7 +static const struct mtk_parent axi_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), }; -static const int mem_parents[] = { - CLK_XTAL, - CLK_TOP_DMPLL -}; +static const struct mtk_parent mem_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_DMPLL), +}; -static const int ddrphycfg_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8 +static const struct mtk_parent ddrphycfg_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; -static const int eth_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - -1, - CLK_TOP_UNIVPLL_D7 +static const struct mtk_parent eth_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + VOID_PARENT, + TOP_PARENT(CLK_TOP_UNIVPLL_D7), }; - -static const int pwm_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D4 + +static const struct mtk_parent pwm_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int f10m_ref_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL4_D16 +static const struct mtk_parent f10m_ref_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL4_D16), }; -static const int nfi_infra_parents[] = { - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_TOP_UNIVPLL2_D8, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_UNIVPLL1_D8, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_SYSPLL1_D4 +static const struct mtk_parent nfi_infra_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + EXT_PARENT(CLK_PAD_CLK25M), + EXT_PARENT(CLK_PAD_CLK25M), + EXT_PARENT(CLK_PAD_CLK25M), + EXT_PARENT(CLK_PAD_CLK25M), + EXT_PARENT(CLK_PAD_CLK25M), + EXT_PARENT(CLK_PAD_CLK25M), + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), }; -static const int flash_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL_D80_D4, - CLK_TOP_SYSPLL2_D8, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL1_D8, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D4 +static const struct mtk_parent flash_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_UNIVPLL_D80_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D8), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int uart_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent uart_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; -static const int spi0_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL3_D2, - CLK_XTAL, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL1_D8, - CLK_XTAL +static const struct mtk_parent spi0_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + EXT_PARENT(CLK_PAD_CLK25M), }; -static const int spi1_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL3_D2, - CLK_XTAL, - CLK_TOP_SYSPLL4_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL1_D8, - CLK_XTAL +static const struct mtk_parent spi1_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + EXT_PARENT(CLK_PAD_CLK25M), }; -static const int msdc30_0_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D16, - CLK_TOP_UNIV48M +static const struct mtk_parent msdc30_0_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D16), + TOP_PARENT(CLK_TOP_UNIV48M), }; -static const int a1sys_hp_parents[] = { - CLK_XTAL, - CLK_TOP_AUD1PLL, - CLK_TOP_AUD2PLL, - CLK_XTAL +static const struct mtk_parent a1sys_hp_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_AUD1PLL), + TOP_PARENT(CLK_TOP_AUD2PLL), + EXT_PARENT(CLK_PAD_CLK25M), }; -static const int intdir_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL_D2, - CLK_TOP_SGMIIPLL +static const struct mtk_parent intdir_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), + TOP_PARENT(CLK_TOP_SGMIIPLL), }; -static const int aud_intbus_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_SYSPLL3_D2 +static const struct mtk_parent aud_intbus_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), }; -static const int pmicspi_parents[] = { - CLK_XTAL, - -1, - -1, - -1, - -1, - CLK_TOP_UNIVPLL2_D16 +static const struct mtk_parent pmicspi_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + VOID_PARENT, + VOID_PARENT, + VOID_PARENT, + VOID_PARENT, + TOP_PARENT(CLK_TOP_UNIVPLL2_D16), }; -static const int atb_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5 +static const struct mtk_parent atb_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), }; -static const int audio_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_SYSPLL4_D4, - CLK_TOP_UNIVPLL1_D16 +static const struct mtk_parent audio_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D16), }; -static const int usb20_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL1_D8, - CLK_XTAL +static const struct mtk_parent usb20_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + EXT_PARENT(CLK_PAD_CLK25M), }; -static const int aud1_parents[] = { - CLK_XTAL, - CLK_TOP_AUD1PLL +static const struct mtk_parent aud1_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_AUD1PLL), }; -static const int asm_l_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL_D5, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL2_D4 +static const struct mtk_parent asm_l_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int apll1_ck_parents[] = { - CLK_TOP_AUD1_SEL, - CLK_TOP_AUD2_SEL +static const struct mtk_parent apll1_ck_parents[] = { + TOP_PARENT(CLK_TOP_AUD1_SEL), + TOP_PARENT(CLK_TOP_AUD2_SEL), }; static const struct mtk_composite top_muxes[] = { @@ -361,8 +369,7 @@ static const struct mtk_composite top_muxes[] = { /* CLK_CFG_5 */ MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7), - MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, eth_parents, 0x90, 8, 3, 15, - CLK_DOMAIN_SCPSYS), + MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, eth_parents, 0x90, 8, 3, 15, CLK_MUX_DOMAIN_SCPSYS), MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x90, 16, 2, 23), MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31), @@ -387,18 +394,16 @@ static const struct mtk_composite top_muxes[] = { }; /* infracfg */ -#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED) -#define XTAL_PARENT(_id) PARENT(_id, CLK_PARENT_XTAL) static const struct mtk_parent infra_mux1_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), APMIXED_PARENT(CLK_APMIXED_MAINPLL), APMIXED_PARENT(CLK_APMIXED_MAIN_CORE_EN), APMIXED_PARENT(CLK_APMIXED_MAINPLL), }; static const struct mtk_composite infra_muxes[] = { - MUX_MIXED(CLK_INFRA_MUX1_SEL, infra_mux1_parents, 0x000, 2, 2), + MUX(CLK_INFRA_MUX1_SEL, infra_mux1_parents, 0x000, 2, 2), }; static const struct mtk_gate_regs infra_cg_regs = { @@ -425,16 +430,13 @@ static const struct mtk_gate infra_cgs[] = { }; /* pericfg */ -static const int peribus_ck_parents[] = { - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYSPLL1_D4, +static const struct mtk_parent peribus_ck_parents[] = { + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), }; -#define PERI_MUX(_id, _parents, _reg, _shift, _width) \ - MUX_FLAGS(_id, _parents, _reg, _shift, _width, CLK_PARENT_TOPCKGEN) - static const struct mtk_composite peri_muxes[] = { - PERI_MUX(CLK_PERIBUS_SEL, peribus_ck_parents, 0x05c, 0, 1), + MUX(CLK_PERIBUS_SEL, peribus_ck_parents, 0x05c, 0, 1), }; static const struct mtk_gate_regs peri0_cg_regs = { @@ -458,8 +460,8 @@ static const struct mtk_gate_regs peri1_cg_regs = { } #define GATE_PERI0(_id, _parent, _shift) \ GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_PERI0_XTAL(_id, _parent, _shift) \ - GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) +#define GATE_PERI0_EXT(_id, _parent, _shift) \ + GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_EXT) #define GATE_PERI1(_id, _parent, _shift) { \ .id = _id, \ @@ -472,14 +474,14 @@ static const struct mtk_gate_regs peri1_cg_regs = { static const struct mtk_gate peri_cgs[] = { /* PERI0 */ GATE_PERI0(CLK_PERI_THERM_PD, CLK_TOP_AXI_SEL, 1), - GATE_PERI0_XTAL(CLK_PERI_PWM1_PD, CLK_XTAL, 2), - GATE_PERI0_XTAL(CLK_PERI_PWM2_PD, CLK_XTAL, 3), - GATE_PERI0_XTAL(CLK_PERI_PWM3_PD, CLK_XTAL, 4), - GATE_PERI0_XTAL(CLK_PERI_PWM4_PD, CLK_XTAL, 5), - GATE_PERI0_XTAL(CLK_PERI_PWM5_PD, CLK_XTAL, 6), - GATE_PERI0_XTAL(CLK_PERI_PWM6_PD, CLK_XTAL, 7), - GATE_PERI0_XTAL(CLK_PERI_PWM7_PD, CLK_XTAL, 8), - GATE_PERI0_XTAL(CLK_PERI_PWM_PD, CLK_XTAL, 9), + GATE_PERI0_EXT(CLK_PERI_PWM1_PD, CLK_PAD_CLK25M, 2), + GATE_PERI0_EXT(CLK_PERI_PWM2_PD, CLK_PAD_CLK25M, 3), + GATE_PERI0_EXT(CLK_PERI_PWM3_PD, CLK_PAD_CLK25M, 4), + GATE_PERI0_EXT(CLK_PERI_PWM4_PD, CLK_PAD_CLK25M, 5), + GATE_PERI0_EXT(CLK_PERI_PWM5_PD, CLK_PAD_CLK25M, 6), + GATE_PERI0_EXT(CLK_PERI_PWM6_PD, CLK_PAD_CLK25M, 7), + GATE_PERI0_EXT(CLK_PERI_PWM7_PD, CLK_PAD_CLK25M, 8), + GATE_PERI0_EXT(CLK_PERI_PWM_PD, CLK_PAD_CLK25M, 9), GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_AXI_SEL, 12), GATE_PERI0(CLK_PERI_MSDC30_0_PD, CLK_TOP_MSDC30_0_SEL, 13), GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1_SEL, 14), @@ -493,7 +495,7 @@ static const struct mtk_gate peri_cgs[] = { GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24), GATE_PERI0(CLK_PERI_I2C2_PD, CLK_TOP_AXI_SEL, 25), GATE_PERI0(CLK_PERI_SPI1_PD, CLK_TOP_SPI1_SEL, 26), - GATE_PERI0_XTAL(CLK_PERI_AUXADC_PD, CLK_XTAL, 27), + GATE_PERI0_EXT(CLK_PERI_AUXADC_PD, CLK_PAD_CLK25M, 27), GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI0_SEL, 28), GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_NFI_INFRA_SEL, 29), GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_AXI_SEL, 30), @@ -603,7 +605,9 @@ static const struct mtk_gate ssusb_cgs[] = { }; static const struct mtk_clk_tree mt7622_apmixed_clk_tree = { - .xtal2_rate = 25 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK25M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .plls = apmixed_plls, .gates_offs = CLK_APMIXED_MAIN_CORE_EN, .gates = apmixed_cgs, @@ -612,7 +616,8 @@ static const struct mtk_clk_tree mt7622_apmixed_clk_tree = { }; static const struct mtk_clk_tree mt7622_infra_clk_tree = { - .xtal_rate = 25 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .muxes_offs = CLK_INFRA_MUX1_SEL, .gates_offs = CLK_INFRA_DBGCLK_PD, .muxes = infra_muxes, @@ -622,7 +627,8 @@ static const struct mtk_clk_tree mt7622_infra_clk_tree = { }; static const struct mtk_clk_tree mt7622_peri_clk_tree = { - .xtal_rate = 25 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .muxes_offs = CLK_PERIBUS_SEL, .gates_offs = CLK_PERI_THERM_PD, .muxes = peri_muxes, @@ -632,7 +638,8 @@ static const struct mtk_clk_tree mt7622_peri_clk_tree = { }; static const struct mtk_clk_tree mt7622_clk_tree = { - .xtal_rate = 25 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_TO_USB3_SYS, .muxes_offs = CLK_TOP_AXI_SEL, .fclks = top_fixed_clks, diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c index 071c4cf8a84..0a302b405e2 100644 --- a/drivers/clk/mediatek/clk-mt7623.c +++ b/drivers/clk/mediatek/clk-mt7623.c @@ -24,6 +24,14 @@ #define AXI_DIV_MSK GENMASK(4, 0) #define AXI_DIV_SEL(x) (x) +enum { + CLK_PAD_CLK26M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK26M] = 26 * MHZ, +}; + /* apmixedsys */ static const int pll_id_offs_map[] = { [0 ... CLK_APMIXED_NR - 1] = -1, @@ -61,9 +69,9 @@ static const int pll_id_offs_map[] = { static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x80000001, 0, 21, 0x204, 24, 0x204, 0), - PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf0000001, HAVE_RST_BAR, + PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf0000001, CLK_PLL_HAVE_RST_BAR, 21, 0x210, 4, 0x214, 0), - PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf3000001, HAVE_RST_BAR, + PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf3000001, CLK_PLL_HAVE_RST_BAR, 7, 0x220, 4, 0x224, 14), PLL(CLK_APMIXED_MMPLL, 0x230, 0x23c, 0x00000001, 0, 21, 0x230, 4, 0x234, 0), @@ -260,7 +268,7 @@ static const int top_id_offs_map[CLK_TOP_NR + 1] = { }; #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -269,7 +277,7 @@ static const int top_id_offs_map[CLK_TOP_NR + 1] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, 0) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_DPI, 108 * MHZ), @@ -369,344 +377,342 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR0(CLK_TOP_HADDS2PLL_98M, CLK_APMIXED_HADDS2PLL, 1, 3), FACTOR0(CLK_TOP_HADDS2PLL_294M, CLK_APMIXED_HADDS2PLL, 1, 1), FACTOR0(CLK_TOP_ETHPLL_500M, CLK_APMIXED_ETHPLL, 1, 1), - FACTOR2(CLK_TOP_CLK26M_D8, CLK_XTAL, 1, 8), - FACTOR2(CLK_TOP_32K_INTERNAL, CLK_XTAL, 1, 793), + FACTOR2(CLK_TOP_CLK26M_D8, CLK_PAD_CLK26M, 1, 8), + FACTOR2(CLK_TOP_32K_INTERNAL, CLK_PAD_CLK26M, 1, 793), FACTOR1(CLK_TOP_AXISEL_D4, CLK_TOP_AXI_SEL, 1, 4), FACTOR1(CLK_TOP_8BDAC, CLK_TOP_UNIVPLL_D2, 1, 1), }; -static const int axi_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_MMPLL_D2, - CLK_TOP_DMPLL_D2 +static const struct mtk_parent axi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_MMPLL_D2), + TOP_PARENT(CLK_TOP_DMPLL_D2), }; -static const int mem_parents[] = { - CLK_XTAL, - CLK_TOP_DMPLL -}; - -static const int ddrphycfg_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8 -}; - -static const int mm_parents[] = { - CLK_XTAL, - CLK_TOP_VENCPLL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_DMPLL -}; - -static const int pwm_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_UNIVPLL1_D4 -}; - -static const int vdec_parents[] = { - CLK_XTAL, - CLK_TOP_VDECPLL, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_VENCPLL, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_MMPLL_D2 -}; - -static const int mfg_parents[] = { - CLK_XTAL, - CLK_TOP_MMPLL, - CLK_TOP_DMPLL_X2, - CLK_TOP_MSDCPLL, - CLK_XTAL, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL1_D2 -}; - -static const int camtg_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL_D26, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL3_D2, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_MMPLL_D2 -}; - -static const int uart_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D8 -}; - -static const int spi_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL3_D2, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL1_D8 -}; - -static const int usb20_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL1_D8, - CLK_TOP_UNIVPLL3_D4 -}; - -static const int msdc30_parents[] = { - CLK_XTAL, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_UNIVPLL2_D4, -}; - -static const int aud_intbus_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL3_D2, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_UNIVPLL2_D4 -}; - -static const int pmicspi_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_SYSPLL2_D8, - CLK_TOP_SYSPLL1_D16, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL_D26, - CLK_TOP_DMPLL_D2, - CLK_TOP_DMPLL_D4 -}; - -static const int scp_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_DMPLL_D2, - CLK_TOP_DMPLL_D4 -}; - -static const int dpi0_tve_parents[] = { - CLK_XTAL, - CLK_TOP_MIPIPLL, - CLK_TOP_MIPIPLL_D2, - CLK_TOP_MIPIPLL_D4, - CLK_XTAL, - CLK_TOP_TVDPLL, - CLK_TOP_TVDPLL_D2, - CLK_TOP_TVDPLL_D4 -}; - -static const int dpi1_parents[] = { - CLK_XTAL, - CLK_TOP_TVDPLL, - CLK_TOP_TVDPLL_D2, - CLK_TOP_TVDPLL_D4 -}; - -static const int hdmi_parents[] = { - CLK_XTAL, - CLK_TOP_HDMIPLL, - CLK_TOP_HDMIPLL_D2, - CLK_TOP_HDMIPLL_D3 -}; - -static const int apll_parents[] = { - CLK_XTAL, - CLK_TOP_AUDPLL, - CLK_TOP_AUDPLL_D4, - CLK_TOP_AUDPLL_D8, - CLK_TOP_AUDPLL_D16, - CLK_TOP_AUDPLL_D24, - CLK_XTAL, - CLK_XTAL -}; - -static const int rtc_parents[] = { - CLK_TOP_32K_INTERNAL, - CLK_TOP_32K_EXTERNAL, - CLK_XTAL, - CLK_TOP_UNIVPLL3_D8 -}; - -static const int nfi2x_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_SYSPLL_D7, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL4_D4, - CLK_XTAL -}; - -static const int emmc_hclk_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL2_D2 -}; - -static const int flash_parents[] = { - CLK_TOP_CLK26M_D8, - CLK_XTAL, - CLK_TOP_SYSPLL2_D8, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D4 -}; - -static const int di_parents[] = { - CLK_XTAL, - CLK_TOP_TVD2PLL, - CLK_TOP_TVD2PLL_D2, - CLK_XTAL -}; - -static const int nr_osd_parents[] = { - CLK_XTAL, - CLK_TOP_VENCPLL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_DMPLL -}; - -static const int hdmirx_bist_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL_D3, - CLK_XTAL, - CLK_TOP_SYSPLL1_D16, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_VENCPLL, - CLK_XTAL -}; - -static const int intdir_parents[] = { - CLK_XTAL, - CLK_TOP_MMPLL, - CLK_TOP_SYSPLL_D2, - CLK_TOP_UNIVPLL_D2 -}; - -static const int asm_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL_D5 -}; - -static const int ms_card_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL3_D8, - CLK_TOP_SYSPLL4_D4 -}; - -static const int ethif_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_DMPLL, - CLK_TOP_DMPLL_D2 -}; - -static const int hdmirx_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL_D52 -}; - -static const int cmsys_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL3_D2, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_SYSPLL1_D8, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL -}; - -static const int clk_8bdac_parents[] = { - CLK_TOP_32K_INTERNAL, - CLK_TOP_8BDAC, - CLK_XTAL, - CLK_XTAL -}; - -static const int aud2dvd_parents[] = { - CLK_TOP_AUD_48K_TIMING, - CLK_TOP_AUD_44K_TIMING -}; - -static const int padmclk_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL_D26, - CLK_TOP_UNIVPLL_D52, - CLK_TOP_UNIVPLL_D108, - CLK_TOP_UNIVPLL2_D8, - CLK_TOP_UNIVPLL2_D16, - CLK_TOP_UNIVPLL2_D32 -}; +static const struct mtk_parent mem_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_DMPLL), +}; + +static const struct mtk_parent ddrphycfg_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), +}; + +static const struct mtk_parent mm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_VENCPLL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_DMPLL), +}; + +static const struct mtk_parent pwm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), +}; + +static const struct mtk_parent vdec_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_VDECPLL), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_VENCPLL), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_MMPLL_D2), +}; + +static const struct mtk_parent mfg_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL), + TOP_PARENT(CLK_TOP_DMPLL_X2), + TOP_PARENT(CLK_TOP_MSDCPLL), + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), +}; + +static const struct mtk_parent camtg_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D26), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_MMPLL_D2), +}; + +static const struct mtk_parent uart_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), +}; + +static const struct mtk_parent spi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), +}; + +static const struct mtk_parent usb20_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), +}; + +static const struct mtk_parent msdc30_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), +}; + +static const struct mtk_parent aud_intbus_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), +}; + +static const struct mtk_parent pmicspi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D8), + TOP_PARENT(CLK_TOP_SYSPLL1_D16), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D26), + TOP_PARENT(CLK_TOP_DMPLL_D2), + TOP_PARENT(CLK_TOP_DMPLL_D4), +}; + +static const struct mtk_parent scp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_DMPLL_D2), + TOP_PARENT(CLK_TOP_DMPLL_D4), +}; + +static const struct mtk_parent dpi0_tve_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MIPIPLL), + TOP_PARENT(CLK_TOP_MIPIPLL_D2), + TOP_PARENT(CLK_TOP_MIPIPLL_D4), + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL), + TOP_PARENT(CLK_TOP_TVDPLL_D2), + TOP_PARENT(CLK_TOP_TVDPLL_D4), +}; + +static const struct mtk_parent dpi1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL), + TOP_PARENT(CLK_TOP_TVDPLL_D2), + TOP_PARENT(CLK_TOP_TVDPLL_D4), +}; + +static const struct mtk_parent hdmi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_HDMIPLL), + TOP_PARENT(CLK_TOP_HDMIPLL_D2), + TOP_PARENT(CLK_TOP_HDMIPLL_D3), +}; + +static const struct mtk_parent apll_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_AUDPLL), + TOP_PARENT(CLK_TOP_AUDPLL_D4), + TOP_PARENT(CLK_TOP_AUDPLL_D8), + TOP_PARENT(CLK_TOP_AUDPLL_D16), + TOP_PARENT(CLK_TOP_AUDPLL_D24), + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), +}; + +static const struct mtk_parent rtc_parents[] = { + TOP_PARENT(CLK_TOP_32K_INTERNAL), + TOP_PARENT(CLK_TOP_32K_EXTERNAL), + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D8), +}; + +static const struct mtk_parent nfi2x_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + EXT_PARENT(CLK_PAD_CLK26M), +}; + +static const struct mtk_parent emmc_hclk_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), +}; + +static const struct mtk_parent flash_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M_D8), + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL2_D8), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), +}; + +static const struct mtk_parent di_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_TVD2PLL), + TOP_PARENT(CLK_TOP_TVD2PLL_D2), + EXT_PARENT(CLK_PAD_CLK26M), +}; + +static const struct mtk_parent nr_osd_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_VENCPLL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_DMPLL), +}; + +static const struct mtk_parent hdmirx_bist_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D16), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_VENCPLL), + EXT_PARENT(CLK_PAD_CLK26M), +}; + +static const struct mtk_parent intdir_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL), + TOP_PARENT(CLK_TOP_SYSPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), +}; + +static const struct mtk_parent asm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), +}; + +static const struct mtk_parent ms_card_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D8), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), +}; + +static const struct mtk_parent ethif_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_DMPLL), + TOP_PARENT(CLK_TOP_DMPLL_D2), +}; + +static const struct mtk_parent hdmirx_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D52), +}; + +static const struct mtk_parent cmsys_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), +}; + +static const struct mtk_parent clk_8bdac_parents[] = { + TOP_PARENT(CLK_TOP_32K_INTERNAL), + TOP_PARENT(CLK_TOP_8BDAC), + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), +}; + +static const struct mtk_parent aud2dvd_parents[] = { + TOP_PARENT(CLK_TOP_AUD_48K_TIMING), + TOP_PARENT(CLK_TOP_AUD_44K_TIMING), +}; + +static const struct mtk_parent padmclk_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D26), + TOP_PARENT(CLK_TOP_UNIVPLL_D52), + TOP_PARENT(CLK_TOP_UNIVPLL_D108), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), + TOP_PARENT(CLK_TOP_UNIVPLL2_D16), + TOP_PARENT(CLK_TOP_UNIVPLL2_D32), +}; -static const int aud_mux_parents[] = { - CLK_XTAL, - CLK_TOP_AUD1PLL_98M, - CLK_TOP_AUD2PLL_90M, - CLK_TOP_HADDS2PLL_98M, - CLK_TOP_AUD_EXTCK1_DIV, - CLK_TOP_AUD_EXTCK2_DIV +static const struct mtk_parent aud_mux_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_AUD1PLL_98M), + TOP_PARENT(CLK_TOP_AUD2PLL_90M), + TOP_PARENT(CLK_TOP_HADDS2PLL_98M), + TOP_PARENT(CLK_TOP_AUD_EXTCK1_DIV), + TOP_PARENT(CLK_TOP_AUD_EXTCK2_DIV), }; -static const int aud_src_parents[] = { - CLK_TOP_AUD_MUX1_SEL, - CLK_TOP_AUD_MUX2_SEL +static const struct mtk_parent aud_src_parents[] = { + TOP_PARENT(CLK_TOP_AUD_MUX1_SEL), + TOP_PARENT(CLK_TOP_AUD_MUX2_SEL), }; static const struct mtk_composite top_muxes[] = { MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), - MUX_GATE_FLAGS(CLK_TOP_MM_SEL, mm_parents, 0x40, 24, 3, 31, - CLK_DOMAIN_SCPSYS), + MUX_GATE_FLAGS(CLK_TOP_MM_SEL, mm_parents, 0x40, 24, 3, 31, CLK_MUX_DOMAIN_SCPSYS), MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), MUX_GATE(CLK_TOP_VDEC_SEL, vdec_parents, 0x50, 8, 4, 15), - MUX_GATE_FLAGS(CLK_TOP_MFG_SEL, mfg_parents, 0x50, 16, 3, 23, - CLK_DOMAIN_SCPSYS), + MUX_GATE_FLAGS(CLK_TOP_MFG_SEL, mfg_parents, 0x50, 16, 3, 23, CLK_MUX_DOMAIN_SCPSYS), MUX_GATE(CLK_TOP_CAMTG_SEL, camtg_parents, 0x50, 24, 3, 31), MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), @@ -744,8 +750,7 @@ static const struct mtk_composite top_muxes[] = { MUX_GATE(CLK_TOP_ASM_H_SEL, asm_parents, 0xD0, 0, 2, 7), MUX_GATE(CLK_TOP_MS_CARD_SEL, ms_card_parents, 0xD0, 16, 2, 23), - MUX_GATE_FLAGS(CLK_TOP_ETHIF_SEL, ethif_parents, 0xD0, 24, 3, 31, - CLK_DOMAIN_SCPSYS), + MUX_GATE_FLAGS(CLK_TOP_ETHIF_SEL, ethif_parents, 0xD0, 24, 3, 31, CLK_MUX_DOMAIN_SCPSYS), MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, hdmirx_parents, 0xE0, 0, 1, 7), MUX_GATE(CLK_TOP_MSDC30_3_SEL, msdc30_parents, 0xE0, 8, 3, 15), @@ -786,8 +791,8 @@ static const struct mtk_gate_regs infra_cg_regs = { } #define GATE_INFRA(_id, _parent, _shift) \ GATE_INFRA_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_INFRA_XTAL(_id, _parent, _shift) \ - GATE_INFRA_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) +#define GATE_INFRA_EXT(_id, _parent, _shift) \ + GATE_INFRA_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_EXT) static const struct mtk_gate infra_cgs[] = { @@ -795,8 +800,8 @@ static const struct mtk_gate infra_cgs[] = { GATE_INFRA(CLK_INFRA_SMI, CLK_TOP_MM_SEL, 1), GATE_INFRA(CLK_INFRA_QAXI_CM4, CLK_TOP_AXI_SEL, 2), GATE_INFRA(CLK_INFRA_AUD_SPLIN_B, CLK_TOP_HADDS2PLL_294M, 4), - GATE_INFRA_XTAL(CLK_INFRA_AUDIO, CLK_XTAL, 5), - GATE_INFRA_XTAL(CLK_INFRA_EFUSE, CLK_XTAL, 6), + GATE_INFRA_EXT(CLK_INFRA_AUDIO, CLK_PAD_CLK26M, 5), + GATE_INFRA_EXT(CLK_INFRA_EFUSE, CLK_PAD_CLK26M, 6), GATE_INFRA(CLK_INFRA_L2C_SRAM, CLK_TOP_MM_SEL, 7), GATE_INFRA(CLK_INFRA_M4U, CLK_TOP_MEM_SEL, 8), GATE_INFRA(CLK_INFRA_CONNMCU, CLK_TOP_WBG_DIG_416M, 12), @@ -866,19 +871,16 @@ static const int peri_id_offs_map[] = { [CLK_PERI_FCI] = 48, }; -#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) -#define XTAL_PARENT(_id) PARENT(_id, CLK_PARENT_XTAL) - static const struct mtk_parent uart_ck_sel_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UART_SEL), }; static const struct mtk_composite peri_muxes[] = { - MUX_MIXED(CLK_PERI_UART0_SEL, uart_ck_sel_parents, 0x40C, 0, 1), - MUX_MIXED(CLK_PERI_UART1_SEL, uart_ck_sel_parents, 0x40C, 1, 1), - MUX_MIXED(CLK_PERI_UART2_SEL, uart_ck_sel_parents, 0x40C, 2, 1), - MUX_MIXED(CLK_PERI_UART3_SEL, uart_ck_sel_parents, 0x40C, 3, 1), + MUX(CLK_PERI_UART0_SEL, uart_ck_sel_parents, 0x40C, 0, 1), + MUX(CLK_PERI_UART1_SEL, uart_ck_sel_parents, 0x40C, 1, 1), + MUX(CLK_PERI_UART2_SEL, uart_ck_sel_parents, 0x40C, 2, 1), + MUX(CLK_PERI_UART3_SEL, uart_ck_sel_parents, 0x40C, 3, 1), }; static const struct mtk_gate_regs peri0_cg_regs = { @@ -902,8 +904,8 @@ static const struct mtk_gate_regs peri1_cg_regs = { } #define GATE_PERI0(_id, _parent, _shift) \ GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_PERI0_XTAL(_id, _parent, _shift) \ - GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) +#define GATE_PERI0_EXT(_id, _parent, _shift) \ + GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_EXT) #define GATE_PERI1(_id, _parent, _shift) { \ .id = _id, \ @@ -941,10 +943,10 @@ static const struct mtk_gate peri_cgs[] = { GATE_PERI0(CLK_PERI_I2C0, CLK_TOP_AXI_SEL, 24), GATE_PERI0(CLK_PERI_I2C1, CLK_TOP_AXI_SEL, 25), GATE_PERI0(CLK_PERI_I2C2, CLK_TOP_AXI_SEL, 26), - GATE_PERI0_XTAL(CLK_PERI_I2C3, CLK_XTAL, 27), - GATE_PERI0_XTAL(CLK_PERI_AUXADC, CLK_XTAL, 28), + GATE_PERI0_EXT(CLK_PERI_I2C3, CLK_PAD_CLK26M, 27), + GATE_PERI0_EXT(CLK_PERI_AUXADC, CLK_PAD_CLK26M, 28), GATE_PERI0(CLK_PERI_SPI0, CLK_TOP_SPI0_SEL, 29), - GATE_PERI0_XTAL(CLK_PERI_ETH, CLK_XTAL, 30), + GATE_PERI0_EXT(CLK_PERI_ETH, CLK_PAD_CLK26M, 30), GATE_PERI0(CLK_PERI_USB0_MCU, CLK_TOP_AXI_SEL, 31), GATE_PERI1(CLK_PERI_USB1_MCU, CLK_TOP_AXI_SEL, 0), @@ -1000,7 +1002,9 @@ static const struct mtk_gate hif_cgs[] = { }; static const struct mtk_clk_tree mt7623_apmixedsys_clk_tree = { - .xtal2_rate = 26 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .id_offs_map = pll_id_offs_map, .id_offs_map_size = ARRAY_SIZE(pll_id_offs_map), .plls = apmixed_plls, @@ -1008,7 +1012,8 @@ static const struct mtk_clk_tree mt7623_apmixedsys_clk_tree = { }; static const struct mtk_clk_tree mt7623_topckgen_clk_tree = { - .xtal_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .id_offs_map = top_id_offs_map, .id_offs_map_size = ARRAY_SIZE(top_id_offs_map), .fdivs_offs = top_id_offs_map[CLK_TOP_SYSPLL], @@ -1058,7 +1063,8 @@ static int mt7623_topckgen_probe(struct udevice *dev) } static const struct mtk_clk_tree mt7623_clk_gate_tree = { - .xtal_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; static int mt7623_infracfg_probe(struct udevice *dev) @@ -1068,6 +1074,8 @@ static int mt7623_infracfg_probe(struct udevice *dev) } static const struct mtk_clk_tree mt7623_clk_peri_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .id_offs_map = peri_id_offs_map, .id_offs_map_size = ARRAY_SIZE(peri_id_offs_map), .muxes_offs = peri_id_offs_map[CLK_PERI_UART0_SEL], @@ -1076,7 +1084,6 @@ static const struct mtk_clk_tree mt7623_clk_peri_tree = { .gates = peri_cgs, .num_muxes = ARRAY_SIZE(peri_muxes), .num_gates = ARRAY_SIZE(peri_cgs), - .xtal_rate = 26 * MHZ, }; static int mt7623_pericfg_probe(struct udevice *dev) @@ -1187,7 +1194,7 @@ U_BOOT_DRIVER(mtk_clk_pericfg) = { .id = UCLASS_CLK, .of_match = mt7623_pericfg_compat, .probe = mt7623_pericfg_probe, - .priv_auto = sizeof(struct mtk_cg_priv), + .priv_auto = sizeof(struct mtk_clk_priv), .ops = &mtk_clk_infrasys_ops, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index 582394f594b..74510ee36a9 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -28,6 +28,16 @@ #define MCU_BUS_MSK GENMASK(10, 9) #define MCU_BUS_SEL(x) ((x) << 9) +enum { + CLK_PAD_CLK40M, + CLK_PAD_CLK20M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK40M] = 40 * MHZ, + [CLK_PAD_CLK20M] = 20 * MHZ, +}; + /* apmixedsys */ #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ _pd_shift, _pcw_reg, _pcw_shift) { \ @@ -48,9 +58,9 @@ static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0, 21, 0x204, 24, 0x204, 0), - PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR, + PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, CLK_PLL_HAVE_RST_BAR, 21, 0x214, 24, 0x214, 0), - PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR, + PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, CLK_PLL_HAVE_RST_BAR, 7, 0x224, 24, 0x224, 14), PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0, 21, 0x300, 1, 0x304, 0), @@ -62,7 +72,7 @@ static const struct mtk_pll_data apmixed_plls[] = { /* topckgen */ #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK40M, CLK_PARENT_EXT, _rate) #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -71,7 +81,7 @@ static const struct mtk_pll_data apmixed_plls[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, 0) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_TO_U2_PHY, 31250000), @@ -93,11 +103,11 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500), FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1), FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1), - FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024), - FACTOR2(CLK_TOP_PWM_QTR_26M, CLK_XTAL, 1, 1), - FACTOR2(CLK_TOP_CPUM_TCK_IN, CLK_XTAL, 1, 1), - FACTOR2(CLK_TOP_TO_USB3_DA_TOP, CLK_XTAL, 1, 1), - FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1), + FACTOR2(CLK_TOP_RTC, CLK_PAD_CLK40M, 1, 1024), + FACTOR2(CLK_TOP_PWM_QTR_26M, CLK_PAD_CLK40M, 1, 1), + FACTOR2(CLK_TOP_CPUM_TCK_IN, CLK_PAD_CLK40M, 1, 1), + FACTOR2(CLK_TOP_TO_USB3_DA_TOP, CLK_PAD_CLK40M, 1, 1), + FACTOR2(CLK_TOP_MEMPLL, CLK_PAD_CLK40M, 32, 1), FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1), FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_MEMPLL, 1, 4), FACTOR1(CLK_TOP_DMPLL_D8, CLK_TOP_MEMPLL, 1, 8), @@ -133,7 +143,7 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_UNIVPLL_D80_D4, CLK_TOP_UNIVPLL, 1, 320), FACTOR1(CLK_TOP_UNIV48M, CLK_TOP_UNIVPLL, 1, 25), FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2), - FACTOR2(CLK_TOP_CLKXTAL_D4, CLK_XTAL, 1, 4), + FACTOR2(CLK_TOP_CLKXTAL_D4, CLK_PAD_CLK40M, 1, 4), FACTOR1(CLK_TOP_HD_FAXI, CLK_TOP_AXI_SEL, 1, 1), FACTOR1(CLK_TOP_FAXI, CLK_TOP_AXI_SEL, 1, 1), FACTOR1(CLK_TOP_F_FAUD_INTBUS, CLK_TOP_AUD_INTBUS_SEL, 1, 1), @@ -152,215 +162,215 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_PCIE0_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1), }; -static const int axi_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL_D7, - CLK_TOP_DMPLL -}; - -static const int mem_parents[] = { - CLK_XTAL, - CLK_TOP_DMPLL -}; - -static const int ddrphycfg_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8 -}; - -static const int eth_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_SGMIIPLL_D2, - CLK_TOP_UNIVPLL_D7, - CLK_TOP_DMPLL -}; - -static const int pwm_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D4 -}; - -static const int sgmii_ref_1_parents[] = { - CLK_XTAL, - CLK_TOP_SGMIIPLL_D2 -}; - -static const int nfi_infra_parents[] = { - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_TOP_UNIVPLL2_D8, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_UNIVPLL1_D8, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL_D7 -}; - -static const int flash_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL_D80_D4, - CLK_TOP_SYSPLL2_D8, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL1_D8, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D4 -}; - -static const int uart_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D8 -}; - -static const int spi0_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL3_D2, - CLK_XTAL, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL1_D8, - CLK_XTAL -}; - -static const int spi1_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL3_D2, - CLK_XTAL, - CLK_TOP_SYSPLL4_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL1_D8, - CLK_XTAL +static const struct mtk_parent axi_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_DMPLL), +}; + +static const struct mtk_parent mem_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_DMPLL), +}; + +static const struct mtk_parent ddrphycfg_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), +}; + +static const struct mtk_parent eth_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_SGMIIPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_DMPLL), +}; + +static const struct mtk_parent pwm_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), +}; + +static const struct mtk_parent sgmii_ref_1_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SGMIIPLL_D2), +}; + +static const struct mtk_parent nfi_infra_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + EXT_PARENT(CLK_PAD_CLK40M), + EXT_PARENT(CLK_PAD_CLK40M), + EXT_PARENT(CLK_PAD_CLK40M), + EXT_PARENT(CLK_PAD_CLK40M), + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D7), +}; + +static const struct mtk_parent flash_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_UNIVPLL_D80_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D8), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), +}; + +static const struct mtk_parent uart_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), +}; + +static const struct mtk_parent spi0_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + EXT_PARENT(CLK_PAD_CLK40M), +}; + +static const struct mtk_parent spi1_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + EXT_PARENT(CLK_PAD_CLK40M), }; -static const int msdc30_0_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D16, - CLK_TOP_UNIV48M -}; - -static const int msdc30_1_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D16, - CLK_TOP_UNIV48M, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_SYSPLL_D7, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL2_D2 +static const struct mtk_parent msdc30_0_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D16), + TOP_PARENT(CLK_TOP_UNIV48M), +}; + +static const struct mtk_parent msdc30_1_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D16), + TOP_PARENT(CLK_TOP_UNIV48M), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), }; -static const int ap2wbmcu_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIV48M, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_SYSPLL_D7, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL2_D2 +static const struct mtk_parent ap2wbmcu_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIV48M), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), }; -static const int audio_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_SYSPLL4_D4, - CLK_TOP_SYSPLL1_D16 +static const struct mtk_parent audio_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D16), }; -static const int aud_intbus_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_DMPLL_D4 -}; +static const struct mtk_parent aud_intbus_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_DMPLL_D4), +}; -static const int pmicspi_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_SYSPLL1_D16, - CLK_TOP_UNIVPLL3_D4, - CLK_XTAL, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_DMPLL_D8 +static const struct mtk_parent pmicspi_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D16), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_DMPLL_D8), }; -static const int scp_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL2_D4 +static const struct mtk_parent scp_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int atb_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5 +static const struct mtk_parent atb_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), }; -static const int hif_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - -1, - CLK_TOP_UNIVPLL_D7 +static const struct mtk_parent hif_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + VOID_PARENT, + TOP_PARENT(CLK_TOP_UNIVPLL_D7), }; -static const int sata_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D4 +static const struct mtk_parent sata_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int usb20_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL1_D8 +static const struct mtk_parent usb20_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; -static const int aud1_parents[] = { - CLK_XTAL +static const struct mtk_parent aud1_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), }; -static const int irrx_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL4_D16 +static const struct mtk_parent irrx_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL4_D16), }; -static const int crypto_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_SYSPLL_D5, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL_D2 +static const struct mtk_parent crypto_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2), }; -static const int gpt10m_parents[] = { - CLK_XTAL, - CLK_TOP_CLKXTAL_D4 +static const struct mtk_parent gpt10m_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_CLKXTAL_D4), }; static const struct mtk_composite top_muxes[] = { @@ -396,8 +406,7 @@ static const struct mtk_composite top_muxes[] = { /* CLK_CFG_5 */ MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7), - MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, hif_parents, 0x90, 8, 3, 15, - CLK_DOMAIN_SCPSYS), + MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, hif_parents, 0x90, 8, 3, 15, CLK_MUX_DOMAIN_SCPSYS), MUX_GATE(CLK_TOP_SATA_SEL, sata_parents, 0x90, 16, 1, 23), MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31), @@ -567,8 +576,9 @@ static const struct mtk_gate ssusb_cgs[] = { }; static const struct mtk_clk_tree mt7629_clk_tree = { - .xtal_rate = 40 * MHZ, - .xtal2_rate = 20 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK20M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_TO_USB3_SYS, .muxes_offs = CLK_TOP_AXI_SEL, .plls = apmixed_plls, @@ -582,8 +592,9 @@ static const struct mtk_clk_tree mt7629_clk_tree = { }; static const struct mtk_clk_tree mt7629_peri_clk_tree = { - .xtal_rate = 40 * MHZ, - .xtal2_rate = 20 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK20M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_TO_USB3_SYS, .muxes_offs = CLK_TOP_AXI_SEL, .plls = apmixed_plls, diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c index 09ed4d8a97f..8c2944b7fb3 100644 --- a/drivers/clk/mediatek/clk-mt7981.c +++ b/drivers/clk/mediatek/clk-mt7981.c @@ -18,8 +18,16 @@ #define MT7981_CLK_PDN 0x250 #define MT7981_CLK_PDN_EN_WRITE BIT(31) +enum { + CLK_PAD_CLK40M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK40M] = 40 * MHZ, +}; + #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK40M, CLK_PARENT_EXT, _rate) #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -139,97 +147,194 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { }; /* TOPCKGEN MUX PARENTS */ -static const int nfi1x_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_MM_D4, - CLK_TOP_NET1_D8_D2, CLK_TOP_CB_NET2_D6, - CLK_TOP_CB_M_D4, CLK_TOP_CB_MM_D8, - CLK_TOP_NET1_D8_D4, CLK_TOP_CB_M_D8 }; +static const struct mtk_parent nfi1x_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_MM_D4), + TOP_PARENT(CLK_TOP_NET1_D8_D2), + TOP_PARENT(CLK_TOP_CB_NET2_D6), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_CB_MM_D8), + TOP_PARENT(CLK_TOP_NET1_D8_D4), + TOP_PARENT(CLK_TOP_CB_M_D8), +}; -static const int spinfi_parents[] = { CLK_TOP_CKSQ_40M_D2, CLK_TOP_CB_CKSQ_40M, - CLK_TOP_NET1_D5_D4, CLK_TOP_CB_M_D4, - CLK_TOP_CB_MM_D8, CLK_TOP_NET1_D8_D4, - CLK_TOP_MM_D6_D2, CLK_TOP_CB_M_D8 }; +static const struct mtk_parent spinfi_parents[] = { + TOP_PARENT(CLK_TOP_CKSQ_40M_D2), + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_CB_MM_D8), + TOP_PARENT(CLK_TOP_NET1_D8_D4), + TOP_PARENT(CLK_TOP_MM_D6_D2), + TOP_PARENT(CLK_TOP_CB_M_D8), +}; -static const int spi_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D2, - CLK_TOP_CB_MM_D4, CLK_TOP_NET1_D8_D2, - CLK_TOP_CB_NET2_D6, CLK_TOP_NET1_D5_D4, - CLK_TOP_CB_M_D4, CLK_TOP_NET1_D8_D4 }; +static const struct mtk_parent spi_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_M_D2), + TOP_PARENT(CLK_TOP_CB_MM_D4), + TOP_PARENT(CLK_TOP_NET1_D8_D2), + TOP_PARENT(CLK_TOP_CB_NET2_D6), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_NET1_D8_D4), +}; -static const int uart_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D8, - CLK_TOP_M_D8_D2 }; +static const struct mtk_parent uart_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_M_D8), + TOP_PARENT(CLK_TOP_M_D8_D2), +}; -static const int pwm_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D8_D2, - CLK_TOP_NET1_D5_D4, CLK_TOP_CB_M_D4, - CLK_TOP_M_D8_D2, CLK_TOP_CB_RTC_32K }; +static const struct mtk_parent pwm_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D8_D2), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_M_D8_D2), + TOP_PARENT(CLK_TOP_CB_RTC_32K), +}; -static const int i2c_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D5_D4, - CLK_TOP_CB_M_D4, CLK_TOP_NET1_D8_D4 }; +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_NET1_D8_D4), +}; -static const int pextp_tl_ck_parents[] = { CLK_TOP_CB_CKSQ_40M, - CLK_TOP_NET1_D5_D4, CLK_TOP_CB_M_D4, - CLK_TOP_CB_RTC_32K }; +static const struct mtk_parent pextp_tl_ck_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_CB_RTC_32K), +}; -static const int emmc_208m_parents[] = { - CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D2, CLK_TOP_CB_NET2_D4, - CLK_TOP_CB_APLL2_196M, CLK_TOP_CB_MM_D4, CLK_TOP_NET1_D8_D2, - CLK_TOP_CB_MM_D6 +static const struct mtk_parent emmc_208m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_M_D2), + TOP_PARENT(CLK_TOP_CB_NET2_D4), + TOP_PARENT(CLK_TOP_CB_APLL2_196M), + TOP_PARENT(CLK_TOP_CB_MM_D4), + TOP_PARENT(CLK_TOP_NET1_D8_D2), + TOP_PARENT(CLK_TOP_CB_MM_D6), }; -static const int emmc_400m_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_NET2_D2, - CLK_TOP_CB_MM_D2, CLK_TOP_CB_NET2_D2 }; +static const struct mtk_parent emmc_400m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET2_D2), + TOP_PARENT(CLK_TOP_CB_MM_D2), + TOP_PARENT(CLK_TOP_CB_NET2_D2), +}; -static const int csw_f26m_parents[] = { CLK_TOP_CKSQ_40M_D2, CLK_TOP_M_D8_D2 }; +static const struct mtk_parent csw_f26m_parents[] = { + TOP_PARENT(CLK_TOP_CKSQ_40M_D2), + TOP_PARENT(CLK_TOP_M_D8_D2), +}; -static const int dramc_md32_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D2, - CLK_TOP_CB_WEDMCU_208M }; +static const struct mtk_parent dramc_md32_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_M_D2), + TOP_PARENT(CLK_TOP_CB_WEDMCU_208M), +}; -static const int sysaxi_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D8_D2 }; +static const struct mtk_parent sysaxi_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D8_D2), +}; -static const int sysapb_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_M_D3_D2 }; +static const struct mtk_parent sysapb_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_M_D3_D2), +}; -static const int arm_db_main_parents[] = { CLK_TOP_CB_CKSQ_40M, - CLK_TOP_CB_NET2_D6 }; +static const struct mtk_parent arm_db_main_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET2_D6), +}; -static const int ap2cnn_host_parents[] = { CLK_TOP_CB_CKSQ_40M, - CLK_TOP_NET1_D8_D4 }; +static const struct mtk_parent ap2cnn_host_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D8_D4), +}; -static const int netsys_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_MM_D2 }; +static const struct mtk_parent netsys_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_MM_D2), +}; -static const int netsys_500m_parents[] = { CLK_TOP_CB_CKSQ_40M, - CLK_TOP_CB_NET1_D5 }; +static const struct mtk_parent netsys_500m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET1_D5), +}; -static const int netsys_mcu_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_MM_720M, - CLK_TOP_CB_NET1_D4, CLK_TOP_CB_NET1_D5, - CLK_TOP_CB_M_416M }; +static const struct mtk_parent netsys_mcu_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_MM_720M), + TOP_PARENT(CLK_TOP_CB_NET1_D4), + TOP_PARENT(CLK_TOP_CB_NET1_D5), + TOP_PARENT(CLK_TOP_CB_M_416M), +}; -static const int netsys_2x_parents[] = { CLK_TOP_CB_CKSQ_40M, - CLK_TOP_CB_NET2_800M, - CLK_TOP_CB_MM_720M }; +static const struct mtk_parent netsys_2x_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET2_800M), + TOP_PARENT(CLK_TOP_CB_MM_720M), +}; -static const int sgm_325m_parents[] = { CLK_TOP_CB_CKSQ_40M, - CLK_TOP_CB_SGM_325M }; +static const struct mtk_parent sgm_325m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_SGM_325M), +}; -static const int sgm_reg_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_NET2_D4 }; +static const struct mtk_parent sgm_reg_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET2_D4), +}; -static const int eip97b_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_NET1_D5, - CLK_TOP_CB_M_416M, CLK_TOP_CB_MM_D2, - CLK_TOP_NET1_D5_D2 }; +static const struct mtk_parent eip97b_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET1_D5), + TOP_PARENT(CLK_TOP_CB_M_416M), + TOP_PARENT(CLK_TOP_CB_MM_D2), + TOP_PARENT(CLK_TOP_NET1_D5_D2), +}; -static const int aud_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_APLL2_196M }; +static const struct mtk_parent aud_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_APLL2_196M), +}; -static const int a1sys_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_APLL2_D4 }; +static const struct mtk_parent a1sys_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_APLL2_D4), +}; -static const int aud_l_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_APLL2_196M, - CLK_TOP_M_D8_D2 }; +static const struct mtk_parent aud_l_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_APLL2_196M), + TOP_PARENT(CLK_TOP_M_D8_D2), +}; -static const int a_tuner_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_APLL2_D4, - CLK_TOP_M_D8_D2 }; +static const struct mtk_parent a_tuner_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_APLL2_D4), + TOP_PARENT(CLK_TOP_M_D8_D2), +}; -static const int u2u3_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_M_D8_D2 }; +static const struct mtk_parent u2u3_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_M_D8_D2), +}; -static const int u2u3_sys_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D5_D4 }; +static const struct mtk_parent u2u3_sys_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D5_D4), +}; -static const int usb_frmcnt_parents[] = { CLK_TOP_CB_CKSQ_40M, - CLK_TOP_CB_MM_D3_D5 }; +static const struct mtk_parent usb_frmcnt_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_MM_D3_D5), +}; #define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ _shift, _width, _gate, _upd_ofs, _upd) \ @@ -238,9 +343,10 @@ static const int usb_frmcnt_parents[] = { CLK_TOP_CB_CKSQ_40M, .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \ .upd_shift = _upd, .mux_shift = _shift, \ .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \ - .gate_shift = _gate, .parent = _parents, \ + .gate_shift = _gate, \ + .parent = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD, \ + .flags = CLK_MUX_SETCLR_UPD, \ } /* TOPCKGEN MUX_GATE */ @@ -319,9 +425,6 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = { }; /* INFRASYS MUX PARENTS */ -#define INFRA_PARENT(_id) PARENT(_id, CLK_PARENT_INFRASYS) -#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) -#define VOID_PARENT PARENT(-1, 0) static const struct mtk_parent infra_uart0_parents[] = { TOP_PARENT(CLK_TOP_F26M_SEL), @@ -363,8 +466,9 @@ static const struct mtk_parent infra_pcie_parents[] = { .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \ .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \ .gate_shift = -1, .upd_shift = -1, \ - .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ + .parent = _parents, \ + .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_MUX_SETCLR_UPD, \ } /* INFRA MUX */ @@ -513,13 +617,16 @@ static const struct mtk_gate infracfg_gates[] = { }; static const struct mtk_clk_tree mt7981_fixed_pll_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_APMIXED_NR_CLK, - .xtal_rate = 40 * MHZ, .fclks = fixed_pll_clks, .num_fclks = ARRAY_SIZE(fixed_pll_clks), }; static const struct mtk_clk_tree mt7981_topckgen_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_CB_M_416M, .muxes_offs = CLK_TOP_NFI1X_SEL, .fclks = top_fixed_clks, @@ -528,10 +635,12 @@ static const struct mtk_clk_tree mt7981_topckgen_clk_tree = { .num_fclks = ARRAY_SIZE(top_fixed_clks), .num_fdivs = ARRAY_SIZE(top_fixed_divs), .num_muxes = ARRAY_SIZE(top_muxes), - .flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN, + .flags = CLK_PARENT_TOPCKGEN, }; static const struct mtk_clk_tree mt7981_infracfg_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_INFRA_66M_MCK, .muxes_offs = CLK_INFRA_UART0_SEL, .gates_offs = CLK_INFRA_GPT_STA, diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c index 79efbf43bc4..9c6514120a6 100644 --- a/drivers/clk/mediatek/clk-mt7986.c +++ b/drivers/clk/mediatek/clk-mt7986.c @@ -18,13 +18,16 @@ #define MT7986_CLK_PDN 0x250 #define MT7986_CLK_PDN_EN_WRITE BIT(31) -#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED) -#define INFRA_PARENT(_id) PARENT(_id, CLK_PARENT_INFRASYS) -#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) -#define VOID_PARENT PARENT(-1, 0) +enum { + CLK_PAD_CLK40M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK40M] = 40 * MHZ, +}; #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK40M, CLK_PARENT_EXT, _rate) #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -234,9 +237,10 @@ static const struct mtk_parent da_u2_refsel_parents[] = { .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \ .upd_shift = _upd, .mux_shift = _shift, \ .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \ - .gate_shift = _gate, .parent_flags = _parents, \ + .gate_shift = _gate, \ + .parent = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ + .flags = CLK_MUX_SETCLR_UPD, \ } /* TOPCKGEN MUX_GATE */ @@ -370,8 +374,9 @@ static const struct mtk_parent infra_pcie_parents[] = { .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \ .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \ .gate_shift = -1, .upd_shift = -1, \ - .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ + .parent = _parents, \ + .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_MUX_SETCLR_UPD, \ } /* INFRA MUX */ @@ -519,14 +524,17 @@ static const struct mtk_gate infracfg_gates[] = { }; static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_APMIXED_NR_CLK, - .xtal_rate = 40 * MHZ, .fclks = fixed_pll_clks, .num_fclks = ARRAY_SIZE(fixed_pll_clks), .flags = CLK_PARENT_APMIXED, }; static const struct mtk_clk_tree mt7986_topckgen_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_XTAL_D2, .muxes_offs = CLK_TOP_NFI1X_SEL, .fclks = top_fixed_clks, @@ -535,10 +543,12 @@ static const struct mtk_clk_tree mt7986_topckgen_clk_tree = { .num_fclks = ARRAY_SIZE(top_fixed_clks), .num_fdivs = ARRAY_SIZE(top_fixed_divs), .num_muxes = ARRAY_SIZE(top_muxes), - .flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN, + .flags = CLK_PARENT_TOPCKGEN, }; static const struct mtk_clk_tree mt7986_infracfg_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_INFRA_SYSAXI_D2, .muxes_offs = CLK_INFRA_UART0_SEL, .gates_offs = CLK_INFRA_GPT_STA, diff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c index 959b1c9cff6..5f102636079 100644 --- a/drivers/clk/mediatek/clk-mt7987.c +++ b/drivers/clk/mediatek/clk-mt7987.c @@ -15,15 +15,22 @@ #include "clk-mtk.h" -#define MT7987_XTAL_RATE (40 * MHZ) #define MT7987_CLK_PDN 0x250 #define MT7987_CLK_PDN_EN_WRITE BIT(31) +enum { + CLK_PAD_CLK40M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK40M] = 40 * MHZ, +}; + #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK40M, CLK_PARENT_EXT, _rate) -#define XTAL_FACTOR(_id, _name, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) +#define EXT_FACTOR(_id, _name, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -47,11 +54,12 @@ static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = { }; static const struct mtk_clk_tree mt7987_fixed_pll_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls), .fclks = apmixedsys_mtk_plls, .num_fclks = ARRAY_SIZE(apmixedsys_mtk_plls), .flags = CLK_PARENT_APMIXED, - .xtal_rate = 40 * MHZ, }; static const struct udevice_id mt7987_fixed_pll_compat[] = { @@ -104,15 +112,13 @@ static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = { PLL_FACTOR(CLK_TOP_NET2_D7_D2, "net2_d7_d2", CLK_APMIXED_NET2PLL, 1, 14), PLL_FACTOR(CLK_TOP_CB_NET2_D8, "cb_net2_d8", CLK_APMIXED_NET2PLL, 1, 8), PLL_FACTOR(CLK_TOP_MSDC_D2, "msdc_d2", CLK_APMIXED_MSDCPLL, 1, 2), - XTAL_FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", CLK_XTAL, 1, 1), + EXT_FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", CLK_PAD_CLK40M, 1, 1), TOP_FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CLK_TOP_CB_CKSQ_40M, 1, 2), TOP_FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", CLK_TOP_CB_CKSQ_40M, 1, 1250), TOP_FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CLK_TOP_CB_CKSQ_40M, 1, 1221), }; /* TOPCKGEN MUX PARENTS */ -#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED) -#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) /* CLK_TOP_NETSYS_SEL (netsys_sel) in topckgen */ static const struct mtk_parent netsys_parents[] = { @@ -341,9 +347,9 @@ static const struct mtk_parent emmc_200m_parents[] = { .upd_reg = (_upd_ofs), .upd_shift = (_upd), \ .mux_shift = (_shift), .mux_mask = BIT(_width) - 1, \ .gate_reg = (_mux_ofs), .gate_shift = (_gate), \ - .parent_flags = (_parents), \ + .parent = (_parents), \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ + .flags = CLK_MUX_SETCLR_UPD, \ } /* TOPCKGEN MUX_GATE */ @@ -443,13 +449,14 @@ static const struct mtk_composite topckgen_mtk_muxes[] = { }; static const struct mtk_clk_tree mt7987_topckgen_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .muxes_offs = CLK_TOP_NETSYS_SEL, .fdivs = topckgen_mtk_fixed_factors, .muxes = topckgen_mtk_muxes, .num_fdivs = ARRAY_SIZE(topckgen_mtk_fixed_factors), .num_muxes = ARRAY_SIZE(topckgen_mtk_muxes), - .flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN, - .xtal_rate = MT7987_XTAL_RATE, + .flags = CLK_PARENT_TOPCKGEN, }; static const struct udevice_id mt7987_topckgen_compat[] = { @@ -482,63 +489,63 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = { /* INFRASYS MUX PARENTS */ /* CLK_INFRA_MUX_UART0_SEL (infra_mux_uart0_sel) in infracfg */ -static const int infra_mux_uart0_parents[] = { - CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_UART_SEL +static const struct mtk_parent infra_mux_uart0_parents[] = { + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_UART_SEL), }; /* CLK_INFRA_MUX_UART1_SEL (infra_mux_uart1_sel) in infracfg */ -static const int infra_mux_uart1_parents[] = { - CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_UART_SEL +static const struct mtk_parent infra_mux_uart1_parents[] = { + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_UART_SEL), }; /* CLK_INFRA_MUX_UART2_SEL (infra_mux_uart2_sel) in infracfg */ -static const int infra_mux_uart2_parents[] = { - CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_UART_SEL +static const struct mtk_parent infra_mux_uart2_parents[] = { + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_UART_SEL), }; /* CLK_INFRA_MUX_SPI0_SEL (infra_mux_spi0_sel) in infracfg */ -static const int infra_mux_spi0_parents[] = { - CLK_TOP_I2C_SEL, - CLK_TOP_SPI_SEL +static const struct mtk_parent infra_mux_spi0_parents[] = { + TOP_PARENT(CLK_TOP_I2C_SEL), + TOP_PARENT(CLK_TOP_SPI_SEL), }; /* CLK_INFRA_MUX_SPI1_SEL (infra_mux_spi1_sel) in infracfg */ -static const int infra_mux_spi1_parents[] = { - CLK_TOP_I2C_SEL, - CLK_TOP_SPIM_MST_SEL +static const struct mtk_parent infra_mux_spi1_parents[] = { + TOP_PARENT(CLK_TOP_I2C_SEL), + TOP_PARENT(CLK_TOP_SPIM_MST_SEL), }; /* CLK_INFRA_MUX_SPI2_BCK_SEL (infra_mux_spi2_bck_sel) in infracfg */ -static const int infra_mux_spi2_bck_parents[] = { - CLK_TOP_I2C_SEL, - CLK_TOP_SPI_SEL +static const struct mtk_parent infra_mux_spi2_bck_parents[] = { + TOP_PARENT(CLK_TOP_I2C_SEL), + TOP_PARENT(CLK_TOP_SPI_SEL), }; /* CLK_INFRA_PWM_BCK_SEL (infra_pwm_bck_sel) in infracfg */ -static const int infra_pwm_bck_parents[] = { - CLK_TOP_CB_RTC_32P7K, - CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_SYSAXI_SEL, - CLK_TOP_PWM_SEL +static const struct mtk_parent infra_pwm_bck_parents[] = { + TOP_PARENT(CLK_TOP_CB_RTC_32P7K), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_SYSAXI_SEL), + TOP_PARENT(CLK_TOP_PWM_SEL), }; /* CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL (infra_pcie_gfmux_tl_ck_o_p0_sel) in infracfg */ -static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = { - CLK_TOP_CB_RTC_32P7K, - CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_PEXTP_TL_SEL +static const struct mtk_parent infra_pcie_gfmux_tl_ck_o_p0_parents[] = { + TOP_PARENT(CLK_TOP_CB_RTC_32P7K), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_PEXTP_TL_SEL), }; /* CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL (infra_pcie_gfmux_tl_ck_o_p1_sel) in infracfg */ -static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = { - CLK_TOP_CB_RTC_32P7K, - CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_PEXTP_TL_P1_SEL +static const struct mtk_parent infra_pcie_gfmux_tl_ck_o_p1_parents[] = { + TOP_PARENT(CLK_TOP_CB_RTC_32P7K), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_PEXTP_TL_P1_SEL), }; #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ @@ -547,8 +554,9 @@ static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = { .mux_clr_reg = (_reg) + 0x4, .mux_set_reg = (_reg) + 0x0, \ .mux_shift = (_shift), .mux_mask = BIT(_width) - 1, \ .gate_shift = -1, .upd_shift = -1, \ - .parent = (_parents), .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \ + .parent = (_parents), \ + .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_MUX_SETCLR_UPD, \ } /* INFRA MUX */ @@ -640,8 +648,8 @@ static const struct mtk_gate_regs infra_3_cg_regs = { GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) #define GATE_INFRA3_TOP(_id, _name, _parent, _shift) \ GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_INFRA3_XTAL(_id, _name, _parent, _shift) \ - GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) +#define GATE_INFRA3_EXT(_id, _name, _parent, _shift) \ + GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_EXT) /* INFRA GATE */ static const struct mtk_gate infracfg_mtk_gates[] = { @@ -742,20 +750,20 @@ static const struct mtk_gate infracfg_mtk_gates[] = { CLK_TOP_CB_CKSQ_40M, 7), GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", CLK_TOP_CKSQ_40M_D2, 9), - GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE_CK_P1, - "infra_usb_pipe_ck_p1", CLK_XTAL, 11), - GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI_CK_P1, - "infra_usb_utmi_ck_p1", CLK_XTAL, 13), + GATE_INFRA3_EXT(CLK_INFRA_USB_PIPE_CK_P1, + "infra_usb_pipe_ck_p1", CLK_PAD_CLK40M, 11), + GATE_INFRA3_EXT(CLK_INFRA_USB_UTMI_CK_P1, + "infra_usb_utmi_ck_p1", CLK_PAD_CLK40M, 13), GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", CLK_TOP_USB_XHCI_P1_SEL, 15), GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0", CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20), GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1", CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21), - GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P0, - "infra_pcie_pipe_ck_p0", CLK_XTAL, 24), - GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P1, - "infra_pcie_pipe_ck_p1", CLK_XTAL, 25), + GATE_INFRA3_EXT(CLK_INFRA_PCIE_PIPE_P0, + "infra_pcie_pipe_ck_p0", CLK_PAD_CLK40M, 24), + GATE_INFRA3_EXT(CLK_INFRA_PCIE_PIPE_P1, + "infra_pcie_pipe_ck_p1", CLK_PAD_CLK40M, 25), GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", CLK_TOP_SYSAXI_SEL, 28), GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P1, @@ -767,14 +775,14 @@ static const struct mtk_gate infracfg_mtk_gates[] = { }; static const struct mtk_clk_tree mt7987_infracfg_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .muxes_offs = CLK_INFRA_MUX_UART0_SEL, .gates_offs = CLK_INFRA_66M_GPT_BCK, .muxes = infracfg_mtk_mux, .gates = infracfg_mtk_gates, .num_muxes = ARRAY_SIZE(infracfg_mtk_mux), .num_gates = ARRAY_SIZE(infracfg_mtk_gates), - .flags = CLK_BYPASS_XTAL, - .xtal_rate = MT7987_XTAL_RATE, }; static const struct udevice_id mt7987_infracfg_compat[] = { diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c index cd8726852d7..4e19f285da0 100644 --- a/drivers/clk/mediatek/clk-mt7988.c +++ b/drivers/clk/mediatek/clk-mt7988.c @@ -21,11 +21,19 @@ #define MT7988_ETHDMA_RST_CTRL_OFS 0x34 #define MT7988_ETHWARP_RST_CTRL_OFS 0x8 +enum { + CLK_PAD_CLK40M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK40M] = 40 * MHZ, +}; + #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK40M, CLK_PARENT_EXT, _rate) -#define XTAL_FACTOR(_id, _name, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) +#define EXT_FACTOR(_id, _name, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -94,8 +102,6 @@ static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = { }; /* TOPCKGEN MUX PARENTS */ -#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED) -#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) static const struct mtk_parent netsys_parents[] = { TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D2), @@ -283,9 +289,10 @@ static const struct mtk_parent eth_mii_parents[] = { .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \ .upd_shift = _upd, .mux_shift = _shift, \ .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \ - .gate_shift = _gate, .parent_flags = _parents, \ + .gate_shift = _gate, \ + .parent = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ + .flags = CLK_MUX_SETCLR_UPD, \ } /* TOPCKGEN MUX_GATE */ @@ -446,51 +453,75 @@ static const struct mtk_composite topckgen_mtk_muxes[] = { }; /* INFRASYS MUX PARENTS */ -static const int infra_mux_uart0_parents[] = { CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_UART_SEL }; +static const struct mtk_parent infra_mux_uart0_parents[] = { + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_UART_SEL), +}; -static const int infra_mux_uart1_parents[] = { CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_UART_SEL }; +static const struct mtk_parent infra_mux_uart1_parents[] = { + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_UART_SEL), +}; -static const int infra_mux_uart2_parents[] = { CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_UART_SEL }; +static const struct mtk_parent infra_mux_uart2_parents[] = { + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_UART_SEL), +}; -static const int infra_mux_spi0_parents[] = { CLK_TOP_I2C_SEL, CLK_TOP_SPI_SEL }; +static const struct mtk_parent infra_mux_spi0_parents[] = { + TOP_PARENT(CLK_TOP_I2C_SEL), + TOP_PARENT(CLK_TOP_SPI_SEL), +}; -static const int infra_mux_spi1_parents[] = { CLK_TOP_I2C_SEL, CLK_TOP_SPIM_MST_SEL }; +static const struct mtk_parent infra_mux_spi1_parents[] = { + TOP_PARENT(CLK_TOP_I2C_SEL), + TOP_PARENT(CLK_TOP_SPIM_MST_SEL), +}; -static const int infra_pwm_bck_parents[] = { CLK_TOP_RTC_32P7K, - CLK_TOP_INFRA_F26M_SEL, CLK_TOP_SYSAXI_SEL, - CLK_TOP_PWM_SEL }; +static const struct mtk_parent infra_pwm_bck_parents[] = { + TOP_PARENT(CLK_TOP_RTC_32P7K), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_SYSAXI_SEL), + TOP_PARENT(CLK_TOP_PWM_SEL), +}; -static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = { - CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_PEXTP_TL_SEL +static const struct mtk_parent infra_pcie_gfmux_tl_ck_o_p0_parents[] = { + TOP_PARENT(CLK_TOP_RTC_32P7K), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_PEXTP_TL_SEL), }; -static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = { - CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_PEXTP_TL_P1_SEL +static const struct mtk_parent infra_pcie_gfmux_tl_ck_o_p1_parents[] = { + TOP_PARENT(CLK_TOP_RTC_32P7K), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_PEXTP_TL_P1_SEL), }; -static const int infra_pcie_gfmux_tl_ck_o_p2_parents[] = { - CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_PEXTP_TL_P2_SEL +static const struct mtk_parent infra_pcie_gfmux_tl_ck_o_p2_parents[] = { + TOP_PARENT(CLK_TOP_RTC_32P7K), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_PEXTP_TL_P2_SEL), }; -static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = { - CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_PEXTP_TL_P3_SEL +static const struct mtk_parent infra_pcie_gfmux_tl_ck_o_p3_parents[] = { + TOP_PARENT(CLK_TOP_RTC_32P7K), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_PEXTP_TL_P3_SEL), }; #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ { \ .id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0, \ .mux_clr_reg = _reg + 0x4, .mux_shift = _shift, \ - .mux_mask = BIT(_width) - 1, .parent = _parents, \ + .mux_mask = BIT(_width) - 1, \ + .parent = _parents, \ .gate_shift = -1, .upd_shift = -1, \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \ + .flags = CLK_MUX_SETCLR_UPD, \ } /* INFRA MUX */ @@ -606,8 +637,8 @@ static const struct mtk_gate_regs infra_3_cg_regs = { GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) #define GATE_INFRA3_TOP(_id, _name, _parent, _shift) \ GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_INFRA3_XTAL(_id, _name, _parent, _shift) \ - GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) +#define GATE_INFRA3_EXT(_id, _name, _parent, _shift) \ + GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_EXT) /* INFRA GATE */ static const struct mtk_gate infracfg_mtk_gates[] = { @@ -728,21 +759,18 @@ static const struct mtk_gate infracfg_mtk_gates[] = { GATE_INFRA3_TOP(CLK_INFRA_USB_SYS, "infra_usb_sys", CLK_TOP_USB_SYS_SEL, 4), GATE_INFRA3_TOP(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", CLK_TOP_USB_SYS_P1_SEL, 5), - GATE_INFRA3_XTAL(CLK_INFRA_USB_REF, "infra_usb_ref", CLK_XTAL, 6), - GATE_INFRA3_XTAL(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CLK_XTAL, - 7), + GATE_INFRA3_EXT(CLK_INFRA_USB_REF, "infra_usb_ref", CLK_PAD_CLK40M, 6), + GATE_INFRA3_EXT(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CLK_PAD_CLK40M, 7), GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", CLK_TOP_USB_FRMCNT_SEL, 8), GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", CLK_TOP_USB_FRMCNT_P1_SEL, 9), - GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE, "infra_usb_pipe", CLK_XTAL, - 10), - GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", - CLK_XTAL, 11), - GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI, "infra_usb_utmi", CLK_XTAL, - 12), - GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", - CLK_XTAL, 13), + GATE_INFRA3_EXT(CLK_INFRA_USB_PIPE, "infra_usb_pipe", CLK_PAD_CLK40M, 10), + GATE_INFRA3_EXT(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", + CLK_PAD_CLK40M, 11), + GATE_INFRA3_EXT(CLK_INFRA_USB_UTMI, "infra_usb_utmi", CLK_PAD_CLK40M, 12), + GATE_INFRA3_EXT(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", + CLK_PAD_CLK40M, 13), GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI, "infra_usb_xhci", CLK_TOP_USB_XHCI_SEL, 14), GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", @@ -755,14 +783,14 @@ static const struct mtk_gate infracfg_mtk_gates[] = { CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, 22), GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3", CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, 23), - GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", - CLK_XTAL, 24), - GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", - CLK_XTAL, 25), - GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", - CLK_XTAL, 26), - GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", - CLK_XTAL, 27), + GATE_INFRA3_EXT(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", + CLK_PAD_CLK40M, 24), + GATE_INFRA3_EXT(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", + CLK_PAD_CLK40M, 25), + GATE_INFRA3_EXT(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", + CLK_PAD_CLK40M, 26), + GATE_INFRA3_EXT(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", + CLK_PAD_CLK40M, 27), GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", CLK_TOP_SYSAXI_SEL, 28), GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", @@ -774,14 +802,17 @@ static const struct mtk_gate infracfg_mtk_gates[] = { }; static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls), .fclks = apmixedsys_mtk_plls, .num_fclks = ARRAY_SIZE(apmixedsys_mtk_plls), .flags = CLK_PARENT_APMIXED, - .xtal_rate = 40 * MHZ, }; static const struct mtk_clk_tree mt7988_topckgen_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_XTAL_D2, .muxes_offs = CLK_TOP_NETSYS_SEL, .fclks = topckgen_mtk_fixed_clks, @@ -790,19 +821,18 @@ static const struct mtk_clk_tree mt7988_topckgen_clk_tree = { .num_fclks = ARRAY_SIZE(topckgen_mtk_fixed_clks), .num_fdivs = ARRAY_SIZE(topckgen_mtk_fixed_factors), .num_muxes = ARRAY_SIZE(topckgen_mtk_muxes), - .flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN, - .xtal_rate = 40 * MHZ, + .flags = CLK_PARENT_TOPCKGEN, }; static const struct mtk_clk_tree mt7988_infracfg_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .muxes_offs = CLK_INFRA_MUX_UART0_SEL, .gates_offs = CLK_INFRA_PCIE_PERI_26M_CK_P0, .muxes = infracfg_mtk_mux, .gates = infracfg_mtk_gates, .num_muxes = ARRAY_SIZE(infracfg_mtk_mux), .num_gates = ARRAY_SIZE(infracfg_mtk_gates), - .flags = CLK_BYPASS_XTAL, - .xtal_rate = 40 * MHZ, }; static const struct udevice_id mt7988_fixed_pll_compat[] = { diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 9d9d00622db..7b2d796bc6c 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -17,6 +17,14 @@ #define MT8183_PLL_FMAX (3800UL * MHZ) #define MT8183_PLL_FMIN (1500UL * MHZ) +enum { + CLK_PAD_CLK26M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK26M] = 26 * MHZ, +}; + /* apmixedsys */ #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, \ _pcwibits, _pd_reg, _pd_shift, _pcw_reg, _pcw_shift) { \ @@ -38,24 +46,24 @@ static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL_LL, 0x0200, 0x020C, 0x00000001, - HAVE_RST_BAR, BIT(24), 22, 8, 0x0204, 24, + CLK_PLL_HAVE_RST_BAR, BIT(24), 22, 8, 0x0204, 24, 0x0204, 0), PLL(CLK_APMIXED_ARMPLL_L, 0x0210, 0x021C, 0x00000001, - HAVE_RST_BAR, BIT(24), 22, 8, 0x0214, 24, + CLK_PLL_HAVE_RST_BAR, BIT(24), 22, 8, 0x0214, 24, 0x0214, 0), PLL(CLK_APMIXED_CCIPLL, 0x0290, 0x029C, 0x00000001, - HAVE_RST_BAR, BIT(24), 22, 8, 0x0294, 24, + CLK_PLL_HAVE_RST_BAR, BIT(24), 22, 8, 0x0294, 24, 0x0294, 0), PLL(CLK_APMIXED_MAINPLL, 0x0220, 0x022C, 0x00000001, - HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, + CLK_PLL_HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0224, 0), PLL(CLK_APMIXED_UNIV2PLL, 0x0230, 0x023C, 0x00000001, - HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, + CLK_PLL_HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0234, 0), PLL(CLK_APMIXED_MSDCPLL, 0x0250, 0x025C, 0x00000001, 0, 0, 22, 8, 0x0254, 24, 0x0254, 0), PLL(CLK_APMIXED_MMPLL, 0x0270, 0x027C, 0x00000001, - HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, + CLK_PLL_HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0274, 0), PLL(CLK_APMIXED_MFGPLL, 0x0240, 0x024C, 0x00000001, 0, 0, 22, 8, 0x0244, 24, 0x0244, 0), @@ -68,7 +76,7 @@ static const struct mtk_pll_data apmixed_plls[] = { }; #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) #define FIXED_CLK1(_id, _rate) \ FIXED_CLK(_id, CLK_TOP_UNIVPLL, CLK_PARENT_TOPCKGEN, _rate) @@ -197,347 +205,347 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { 16, CLK_PARENT_TOPCKGEN), }; -static const int axi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D4, - CLK_TOP_SYSPLL_D7, - CLK_TOP_OSC_D4 -}; - -static const int mm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL_D7, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_SYSPLL_D3_D2 -}; - -static const int img_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL_D6, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_SYSPLL_D3_D2 -}; - -static const int cam_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2, - CLK_TOP_MMPLL_D6, - CLK_TOP_SYSPLL_D3, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_SYSPLL_D3_D2, - CLK_TOP_UNIVPLL_D3_D2 -}; - -static const int dsp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_SYSPLL_D3_D2 -}; - -static const int dsp1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_SYSPLL_D3_D2 -}; - -static const int dsp2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_SYSPLL_D3_D2 -}; - -static const int ipu_if_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_SYSPLL_D3_D2 -}; - -static const int mfg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MFGPLL_CK, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D3 -}; - -static const int f52m_mfg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_UNIVPLL_D3_D4, - CLK_TOP_UNIVPLL_D3_D8 -}; - -static const int camtg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVP_192M_D8, - CLK_TOP_UNIVPLL_D3_D8, - CLK_TOP_UNIVP_192M_D4, - CLK_TOP_UNIVPLL_D3_D16, - CLK_TOP_F26M_CK_D2, - CLK_TOP_UNIVP_192M_D16, - CLK_TOP_UNIVP_192M_D32 -}; - -static const int camtg2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVP_192M_D8, - CLK_TOP_UNIVPLL_D3_D8, - CLK_TOP_UNIVP_192M_D4, - CLK_TOP_UNIVPLL_D3_D16, - CLK_TOP_F26M_CK_D2, - CLK_TOP_UNIVP_192M_D16, - CLK_TOP_UNIVP_192M_D32 -}; - -static const int camtg3_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVP_192M_D8, - CLK_TOP_UNIVPLL_D3_D8, - CLK_TOP_UNIVP_192M_D4, - CLK_TOP_UNIVPLL_D3_D16, - CLK_TOP_F26M_CK_D2, - CLK_TOP_UNIVP_192M_D16, - CLK_TOP_UNIVP_192M_D32 -}; - -static const int camtg4_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVP_192M_D8, - CLK_TOP_UNIVPLL_D3_D8, - CLK_TOP_UNIVP_192M_D4, - CLK_TOP_UNIVPLL_D3_D16, - CLK_TOP_F26M_CK_D2, - CLK_TOP_UNIVP_192M_D16, - CLK_TOP_UNIVP_192M_D32 -}; - -static const int uart_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3_D8 -}; - -static const int spi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D5_D2, - CLK_TOP_SYSPLL_D3_D4, - CLK_TOP_MSDCPLL_D4 -}; - -static const int msdc50_hclk_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_SYSPLL_D3_D2 +static const struct mtk_parent axi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_OSC_D4), +}; + +static const struct mtk_parent mm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), +}; + +static const struct mtk_parent img_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), +}; + +static const struct mtk_parent cam_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), +}; + +static const struct mtk_parent dsp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), +}; + +static const struct mtk_parent dsp1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), +}; + +static const struct mtk_parent dsp2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), +}; + +static const struct mtk_parent ipu_if_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), +}; + +static const struct mtk_parent mfg_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MFGPLL_CK), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D3), +}; + +static const struct mtk_parent f52m_mfg_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D8), +}; + +static const struct mtk_parent camtg_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVP_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D8), + TOP_PARENT(CLK_TOP_UNIVP_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D16), + TOP_PARENT(CLK_TOP_F26M_CK_D2), + TOP_PARENT(CLK_TOP_UNIVP_192M_D16), + TOP_PARENT(CLK_TOP_UNIVP_192M_D32), +}; + +static const struct mtk_parent camtg2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVP_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D8), + TOP_PARENT(CLK_TOP_UNIVP_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D16), + TOP_PARENT(CLK_TOP_F26M_CK_D2), + TOP_PARENT(CLK_TOP_UNIVP_192M_D16), + TOP_PARENT(CLK_TOP_UNIVP_192M_D32), +}; + +static const struct mtk_parent camtg3_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVP_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D8), + TOP_PARENT(CLK_TOP_UNIVP_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D16), + TOP_PARENT(CLK_TOP_F26M_CK_D2), + TOP_PARENT(CLK_TOP_UNIVP_192M_D16), + TOP_PARENT(CLK_TOP_UNIVP_192M_D32), +}; + +static const struct mtk_parent camtg4_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVP_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D8), + TOP_PARENT(CLK_TOP_UNIVP_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D16), + TOP_PARENT(CLK_TOP_F26M_CK_D2), + TOP_PARENT(CLK_TOP_UNIVP_192M_D16), + TOP_PARENT(CLK_TOP_UNIVP_192M_D32), +}; + +static const struct mtk_parent uart_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D8), +}; + +static const struct mtk_parent spi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D5_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D4), + TOP_PARENT(CLK_TOP_MSDCPLL_D4), +}; + +static const struct mtk_parent msdc50_hclk_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), }; - -static const int msdc50_0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL_CK, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_UNIVPLL_D2_D4, - CLK_TOP_SYSPLL_D3_D2, - CLK_TOP_UNIVPLL_D2_D2 + +static const struct mtk_parent msdc50_0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL_CK), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), }; -static const int msdc30_1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_SYSPLL_D3_D2, - CLK_TOP_SYSPLL_D7, - CLK_TOP_MSDCPLL_D2 +static const struct mtk_parent msdc30_1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), }; -static const int msdc30_2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_SYSPLL_D3_D2, - CLK_TOP_SYSPLL_D7, - CLK_TOP_MSDCPLL_D2 +static const struct mtk_parent msdc30_2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), }; -static const int audio_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D5_D4, - CLK_TOP_SYSPLL_D7_D4, - CLK_TOP_SYSPLL_D2_D16 +static const struct mtk_parent audio_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D5_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D7_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D16), }; -static const int aud_intbus_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D4, - CLK_TOP_SYSPLL_D7_D2 +static const struct mtk_parent aud_intbus_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D7_D2), }; -static const int pmicspi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D8, - CLK_TOP_OSC_D8 +static const struct mtk_parent pmicspi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D8), + TOP_PARENT(CLK_TOP_OSC_D8), }; -static const int fpwrap_ulposc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_OSC_D16, - CLK_TOP_OSC_D4, - CLK_TOP_OSC_D8 +static const struct mtk_parent fpwrap_ulposc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D16), + TOP_PARENT(CLK_TOP_OSC_D4), + TOP_PARENT(CLK_TOP_OSC_D8), }; -static const int atb_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_SYSPLL_D5 +static const struct mtk_parent atb_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), }; -static const int sspm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2_D4, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D3 +static const struct mtk_parent sspm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3), }; -static const int dpi0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_TVDPLL_D2, - CLK_TOP_TVDPLL_D4, - CLK_TOP_TVDPLL_D8, - CLK_TOP_TVDPLL_D16, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_UNIVPLL_D3_D4, - CLK_TOP_SYSPLL_D3_D4, - CLK_TOP_UNIVPLL_D3_D8 +static const struct mtk_parent dpi0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL_D2), + TOP_PARENT(CLK_TOP_TVDPLL_D4), + TOP_PARENT(CLK_TOP_TVDPLL_D8), + TOP_PARENT(CLK_TOP_TVDPLL_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D8), }; -static const int scam_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D5_D2 +static const struct mtk_parent scam_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D5_D2), }; -static const int disppwm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3_D4, - CLK_TOP_OSC_D2, - CLK_TOP_OSC_D4, - CLK_TOP_OSC_D16 +static const struct mtk_parent disppwm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D4), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_OSC_D4), + TOP_PARENT(CLK_TOP_OSC_D16), }; -static const int usb_top_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_UNIVPLL_D3_D4, - CLK_TOP_UNIVPLL_D5_D2 +static const struct mtk_parent usb_top_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; -static const int ssusb_top_xhci_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_UNIVPLL_D3_D4, - CLK_TOP_UNIVPLL_D5_D2 +static const struct mtk_parent ssusb_top_xhci_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; -static const int spm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D8 +static const struct mtk_parent spm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D8), }; -static const int i2c_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D8, - CLK_TOP_UNIVPLL_D5_D2 +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; -static const int scp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2_D8, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent scp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D8), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int seninf_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_UNIVPLL_D2_D4 +static const struct mtk_parent seninf_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D4), }; -static const int dxcc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_SYSPLL_D2_D4, - CLK_TOP_SYSPLL_D2_D8 +static const struct mtk_parent dxcc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D8), }; -static const int aud_engen1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_D2, - CLK_TOP_APLL1_D4, - CLK_TOP_APLL1_D8 +static const struct mtk_parent aud_engen1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_D2), + TOP_PARENT(CLK_TOP_APLL1_D4), + TOP_PARENT(CLK_TOP_APLL1_D8), }; -static const int aud_engen2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_D2, - CLK_TOP_APLL2_D4, - CLK_TOP_APLL2_D8 +static const struct mtk_parent aud_engen2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_D2), + TOP_PARENT(CLK_TOP_APLL2_D4), + TOP_PARENT(CLK_TOP_APLL2_D8), }; -static const int faes_ufsfde_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_SYSPLL_D3, - CLK_TOP_SYSPLL_D2_D4, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent faes_ufsfde_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int fufs_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D4, - CLK_TOP_SYSPLL_D2_D8, - CLK_TOP_SYSPLL_D2_D16 +static const struct mtk_parent fufs_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D8), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D16), }; -static const int aud_1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_CK +static const struct mtk_parent aud_1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_CK), }; -static const int aud_2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_CK +static const struct mtk_parent aud_2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_CK), }; static const struct mtk_composite top_muxes[] = { @@ -597,8 +605,9 @@ static const struct mtk_composite top_muxes[] = { }; static const struct mtk_clk_tree mt8183_clk_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_CLK13M, .muxes_offs = CLK_TOP_MUX_AXI, .plls = apmixed_plls, diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c index 64aeaa5949f..3e413e111f1 100644 --- a/drivers/clk/mediatek/clk-mt8188.c +++ b/drivers/clk/mediatek/clk-mt8188.c @@ -19,15 +19,17 @@ #define MT8188_PLL_FMAX (3800UL * MHZ) #define MT8188_PLL_FMIN (1500UL * MHZ) -/* Missing topckgen clocks definition in dt-bindings */ -#define CLK_TOP_ADSPPLL 206 -#define CLK_TOP_CLK13M 207 -#define CLK_TOP_CLK26M 208 -#define CLK_TOP_CLK32K 209 -#define CLK_TOP_IMGPLL 210 -#define CLK_TOP_MSDCPLL 211 -#define CLK_TOP_ULPOSC1_CK1 212 -#define CLK_TOP_ULPOSC_CK1 213 +enum { + CLK_PAD_CLK32K, + CLK_PAD_CLK26M, + CLK_PAD_CLK13M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK32K] = 32000, + [CLK_PAD_CLK26M] = 26 * MHZ, + [CLK_PAD_CLK13M] = 13 * MHZ, +}; /* apmixedsys */ #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ @@ -57,13 +59,13 @@ static const struct mtk_pll_data apmixed_plls[] = { 0x0528, 0), PLL(CLK_APMIXED_TVDPLL2, 0x0534, 0x0540, 0, 0, 22, 0x0538, 24, 0x0538, 0), - PLL(CLK_APMIXED_MMPLL, 0x0544, 0x0550, 0xff000000, HAVE_RST_BAR, + PLL(CLK_APMIXED_MMPLL, 0x0544, 0x0550, 0xff000000, CLK_PLL_HAVE_RST_BAR, 22, 0x0548, 24, 0x0548, 0), - PLL(CLK_APMIXED_MAINPLL, 0x045C, 0x0468, 0xff000000, HAVE_RST_BAR, + PLL(CLK_APMIXED_MAINPLL, 0x045C, 0x0468, 0xff000000, CLK_PLL_HAVE_RST_BAR, 22, 0x0460, 24, 0x0460, 0), PLL(CLK_APMIXED_IMGPLL, 0x0554, 0x0560, 0, 0, 22, 0x0558, 24, 0x0558, 0), - PLL(CLK_APMIXED_UNIVPLL, 0x0504, 0x0510, 0xff000000, HAVE_RST_BAR, + PLL(CLK_APMIXED_UNIVPLL, 0x0504, 0x0510, 0xff000000, CLK_PLL_HAVE_RST_BAR, 22, 0x0508, 24, 0x0508, 0), PLL(CLK_APMIXED_ADSPPLL, 0x042C, 0x0438, 0, 0, 22, 0x0430, 24, 0x0430, 0), @@ -82,14 +84,15 @@ static const struct mtk_pll_data apmixed_plls[] = { }; static const struct mtk_clk_tree mt8188_apmixedsys_clk_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .plls = apmixed_plls, .num_plls = ARRAY_SIZE(apmixed_plls), }; #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_ULPOSC1, 260000000), @@ -98,8 +101,6 @@ static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_466M_FMEM, 533000000), FIXED_CLK0(CLK_TOP_PEXTP_PIPE, 250000000), FIXED_CLK0(CLK_TOP_DSI_PHY, 500000000), - FIXED_CLK0(CLK_TOP_CLK26M, 260000000), - FIXED_CLK0(CLK_TOP_CLK32K, 32000), }; #define FACTOR0(_id, _parent, _mult, _div) \ @@ -148,13 +149,13 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_UNIVPLL_192M_D10, CLK_TOP_UNIVPLL_192M, 1, 10), FACTOR1(CLK_TOP_UNIVPLL_192M_D16, CLK_TOP_UNIVPLL_192M, 1, 16), FACTOR1(CLK_TOP_UNIVPLL_192M_D32, CLK_TOP_UNIVPLL_192M, 1, 32), - FACTOR1(CLK_TOP_APLL1_D3, CLK_TOP_APLL1, 1, 3), - FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_APLL1, 1, 4), - FACTOR1(CLK_TOP_APLL2_D3, CLK_TOP_APLL2, 1, 3), - FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_APLL2, 1, 4), - FACTOR1(CLK_TOP_APLL3_D4, CLK_TOP_APLL3, 1, 4), - FACTOR1(CLK_TOP_APLL4_D4, CLK_TOP_APLL4, 1, 4), - FACTOR1(CLK_TOP_APLL5_D4, CLK_TOP_APLL5, 1, 4), + FACTOR0(CLK_TOP_APLL1_D3, CLK_APMIXED_APLL1, 1, 3), + FACTOR0(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4), + FACTOR0(CLK_TOP_APLL2_D3, CLK_APMIXED_APLL2, 1, 3), + FACTOR0(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4), + FACTOR0(CLK_TOP_APLL3_D4, CLK_APMIXED_APLL3, 1, 4), + FACTOR0(CLK_TOP_APLL4_D4, CLK_APMIXED_APLL4, 1, 4), + FACTOR0(CLK_TOP_APLL5_D4, CLK_APMIXED_APLL5, 1, 4), FACTOR0(CLK_TOP_MMPLL_D4, CLK_APMIXED_MMPLL, 1, 4), FACTOR1(CLK_TOP_MMPLL_D4_D2, CLK_TOP_MMPLL_D4, 1, 2), FACTOR0(CLK_TOP_MMPLL_D5, CLK_APMIXED_MMPLL, 1, 5), @@ -164,21 +165,20 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_MMPLL_D6_D2, CLK_TOP_MMPLL_D6, 1, 2), FACTOR0(CLK_TOP_MMPLL_D7, CLK_APMIXED_MMPLL, 1, 7), FACTOR0(CLK_TOP_MMPLL_D9, CLK_APMIXED_MMPLL, 1, 9), - FACTOR1(CLK_TOP_TVDPLL1_D2, CLK_TOP_TVDPLL1, 1, 2), - FACTOR1(CLK_TOP_TVDPLL1_D4, CLK_TOP_TVDPLL1, 1, 4), - FACTOR1(CLK_TOP_TVDPLL1_D8, CLK_TOP_TVDPLL1, 1, 8), - FACTOR1(CLK_TOP_TVDPLL1_D16, CLK_TOP_TVDPLL1, 1, 16), - FACTOR1(CLK_TOP_TVDPLL2_D2, CLK_TOP_TVDPLL2, 1, 2), - FACTOR1(CLK_TOP_TVDPLL2_D4, CLK_TOP_TVDPLL2, 1, 4), - FACTOR1(CLK_TOP_TVDPLL2_D8, CLK_TOP_TVDPLL2, 1, 8), - FACTOR1(CLK_TOP_TVDPLL2_D16, CLK_TOP_TVDPLL2, 1, 16), - FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1), + FACTOR0(CLK_TOP_TVDPLL1_D2, CLK_APMIXED_TVDPLL1, 1, 2), + FACTOR0(CLK_TOP_TVDPLL1_D4, CLK_APMIXED_TVDPLL1, 1, 4), + FACTOR0(CLK_TOP_TVDPLL1_D8, CLK_APMIXED_TVDPLL1, 1, 8), + FACTOR0(CLK_TOP_TVDPLL1_D16, CLK_APMIXED_TVDPLL1, 1, 16), + FACTOR0(CLK_TOP_TVDPLL2_D2, CLK_APMIXED_TVDPLL2, 1, 2), + FACTOR0(CLK_TOP_TVDPLL2_D4, CLK_APMIXED_TVDPLL2, 1, 4), + FACTOR0(CLK_TOP_TVDPLL2_D8, CLK_APMIXED_TVDPLL2, 1, 8), + FACTOR0(CLK_TOP_TVDPLL2_D16, CLK_APMIXED_TVDPLL2, 1, 16), FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2), FACTOR0(CLK_TOP_MSDCPLL_D16, CLK_APMIXED_MSDCPLL, 1, 16), - FACTOR1(CLK_TOP_ETHPLL_D2, CLK_TOP_ETHPLL, 1, 2), - FACTOR1(CLK_TOP_ETHPLL_D4, CLK_TOP_ETHPLL, 1, 4), - FACTOR1(CLK_TOP_ETHPLL_D8, CLK_TOP_ETHPLL, 1, 8), - FACTOR1(CLK_TOP_ETHPLL_D10, CLK_TOP_ETHPLL, 1, 10), + FACTOR0(CLK_TOP_ETHPLL_D2, CLK_APMIXED_ETHPLL, 1, 2), + FACTOR0(CLK_TOP_ETHPLL_D4, CLK_APMIXED_ETHPLL, 1, 4), + FACTOR0(CLK_TOP_ETHPLL_D8, CLK_APMIXED_ETHPLL, 1, 8), + FACTOR0(CLK_TOP_ETHPLL_D10, CLK_APMIXED_ETHPLL, 1, 10), FACTOR0(CLK_TOP_ADSPPLL_D2, CLK_APMIXED_ADSPPLL, 1, 2), FACTOR0(CLK_TOP_ADSPPLL_D4, CLK_APMIXED_ADSPPLL, 1, 4), FACTOR0(CLK_TOP_ADSPPLL_D8, CLK_APMIXED_ADSPPLL, 1, 8), @@ -190,375 +190,375 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_ULPOSC1_D16, CLK_TOP_ULPOSC1, 1, 16), }; -static const int axi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_MAINPLL_D7_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_ULPOSC1_D4 -}; - -static const int spm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_ULPOSC1_D10, - CLK_TOP_MAINPLL_D7_D4, - CLK_TOP_CLK32K -}; - -static const int scp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MAINPLL_D6, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_MAINPLL_D3 -}; - -static const int bus_aximem_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D7_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MAINPLL_D6 -}; - -static const int vpp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MMPLL_D6_D2, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D4, - CLK_TOP_MMPLL_D5, - CLK_TOP_TVDPLL1, - CLK_TOP_TVDPLL2, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4 -}; - -static const int ethdr_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MMPLL_D6_D2, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D4, - CLK_TOP_MMPLL_D5_D4, - CLK_TOP_TVDPLL1, - CLK_TOP_TVDPLL2, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4 -}; - -static const int ipe_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_IMGPLL, - CLK_TOP_MAINPLL_D4, - CLK_TOP_MMPLL_D6, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MMPLL_D6_D2, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_MAINPLL_D7 -}; - -static const int cam_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_TVDPLL1, - CLK_TOP_MAINPLL_D4, - CLK_TOP_MMPLL_D4, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_IMGPLL -}; - -static const int ccu_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MMPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_UNIVPLL_D7 -}; - -static const int ccu_ahb_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MMPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_UNIVPLL_D7 -}; - -static const int img_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_IMGPLL, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MMPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D5_D2 -}; - -static const int camtm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D6_D4 -}; - -static const int dsp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 -}; - -static const int dsp1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MMPLL_D5, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 -}; - -static const int dsp2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MMPLL_D5, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 -}; - -static const int dsp3_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MMPLL_D5, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 -}; - -static const int dsp4_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 -}; - -static const int dsp5_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 -}; - -static const int dsp6_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 -}; - -static const int dsp7_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 -}; - -static const int mfg_core_tmp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_UNIVPLL_D7 -}; - -static const int camtg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_192M_D8, - CLK_TOP_UNIVPLL_D6_D8, - CLK_TOP_UNIVPLL_192M_D4, - CLK_TOP_UNIVPLL_192M_D10, - CLK_TOP_CLK13M, - CLK_TOP_UNIVPLL_192M_D16, - CLK_TOP_UNIVPLL_192M_D32 -}; - -static const int camtg2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_192M_D8, - CLK_TOP_UNIVPLL_D6_D8, - CLK_TOP_UNIVPLL_192M_D4, - CLK_TOP_UNIVPLL_192M_D10, - CLK_TOP_CLK13M, - CLK_TOP_UNIVPLL_192M_D16, - CLK_TOP_UNIVPLL_192M_D32 -}; - -static const int camtg3_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_192M_D8, - CLK_TOP_UNIVPLL_D6_D8, - CLK_TOP_UNIVPLL_192M_D4, - CLK_TOP_UNIVPLL_192M_D10, - CLK_TOP_CLK13M, - CLK_TOP_UNIVPLL_192M_D16, - CLK_TOP_UNIVPLL_192M_D32 -}; - -static const int uart_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D8 -}; - -static const int spi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D5_D4, - CLK_TOP_MAINPLL_D6_D4, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_UNIVPLL_D5_D4 -}; - -static const int msdc5hclk_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D6_D2 -}; - -static const int msdc50_0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_UNIVPLL_D4_D2 -}; - -static const int msdc30_1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_MAINPLL_D7_D2, - CLK_TOP_MSDCPLL_D2 -}; - -static const int msdc30_2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_MAINPLL_D7_D2, - CLK_TOP_MSDCPLL_D2 -}; +static const struct mtk_parent axi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_ULPOSC1_D4), +}; + +static const struct mtk_parent spm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), + EXT_PARENT(CLK_PAD_CLK32K), +}; + +static const struct mtk_parent scp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_MAINPLL_D3), +}; + +static const struct mtk_parent bus_aximem_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), +}; + +static const struct mtk_parent vpp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D5), + TOP_PARENT(CLK_TOP_TVDPLL1), + TOP_PARENT(CLK_TOP_TVDPLL2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), +}; + +static const struct mtk_parent ethdr_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D5_D4), + TOP_PARENT(CLK_TOP_TVDPLL1), + TOP_PARENT(CLK_TOP_TVDPLL2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), +}; + +static const struct mtk_parent ipe_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_IMGPLL), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7), +}; + +static const struct mtk_parent cam_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL1), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + APMIXED_PARENT(CLK_APMIXED_IMGPLL), +}; + +static const struct mtk_parent ccu_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), +}; + +static const struct mtk_parent ccu_ahb_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), +}; + +static const struct mtk_parent img_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_IMGPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent camtm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent dsp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent dsp1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent dsp2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent dsp3_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent dsp4_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent dsp5_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent dsp6_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent dsp7_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent mfg_core_tmp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), +}; + +static const struct mtk_parent camtg_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D10), + EXT_PARENT(CLK_PAD_CLK13M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D32), +}; + +static const struct mtk_parent camtg2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D10), + EXT_PARENT(CLK_PAD_CLK13M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D32), +}; + +static const struct mtk_parent camtg3_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D10), + EXT_PARENT(CLK_PAD_CLK13M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D32), +}; + +static const struct mtk_parent uart_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), +}; + +static const struct mtk_parent spi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), +}; + +static const struct mtk_parent msdc5hclk_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), +}; + +static const struct mtk_parent msdc50_0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_MSDCPLL), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), +}; + +static const struct mtk_parent msdc30_1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), +}; + +static const struct mtk_parent msdc30_2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), +}; -static const int intdir_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D4 -}; - -static const int aud_intbus_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_MAINPLL_D7_D4 +static const struct mtk_parent intdir_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), +}; + +static const struct mtk_parent aud_intbus_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), }; -static const int audio_h_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D7, - CLK_TOP_APLL1, - CLK_TOP_APLL2 +static const struct mtk_parent audio_h_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), }; -static const int pwrap_ulposc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_ULPOSC1_D10, - CLK_TOP_ULPOSC1_D7, - CLK_TOP_ULPOSC1_D8, - CLK_TOP_ULPOSC1_D16, - CLK_TOP_MAINPLL_D4_D8, - CLK_TOP_UNIVPLL_D5_D8, - CLK_TOP_TVDPLL1_D16 +static const struct mtk_parent pwrap_ulposc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_ULPOSC1_D7), + TOP_PARENT(CLK_TOP_ULPOSC1_D8), + TOP_PARENT(CLK_TOP_ULPOSC1_D16), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D8), + TOP_PARENT(CLK_TOP_TVDPLL1_D16), }; -static const int atb_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D5_D2 +static const struct mtk_parent atb_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), }; -static const int sspm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D7_D2, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MAINPLL_D9, - CLK_TOP_MAINPLL_D4_D2 +static const struct mtk_parent sspm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D9), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), }; /* @@ -566,463 +566,463 @@ static const int sspm_parents[] = { * TVDPLL1 on eDP and TVDPLL2 on DP to avoid changing the "other" PLL rate * in dual output case, which would lead to corruption of functionality loss. */ -static const int dp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_TVDPLL2_D2, - CLK_TOP_TVDPLL2_D4, - CLK_TOP_TVDPLL2_D8, - CLK_TOP_TVDPLL2_D16 +static const struct mtk_parent dp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL2_D2), + TOP_PARENT(CLK_TOP_TVDPLL2_D4), + TOP_PARENT(CLK_TOP_TVDPLL2_D8), + TOP_PARENT(CLK_TOP_TVDPLL2_D16), }; - -static const int edp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_TVDPLL1_D2, - CLK_TOP_TVDPLL1_D4, - CLK_TOP_TVDPLL1_D8, - CLK_TOP_TVDPLL1_D16 + +static const struct mtk_parent edp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL1_D2), + TOP_PARENT(CLK_TOP_TVDPLL1_D4), + TOP_PARENT(CLK_TOP_TVDPLL1_D8), + TOP_PARENT(CLK_TOP_TVDPLL1_D16), }; - -static const int dpi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_TVDPLL1_D2, - CLK_TOP_TVDPLL2_D2, - CLK_TOP_TVDPLL1_D4, - CLK_TOP_TVDPLL2_D4, - CLK_TOP_TVDPLL1_D8, - CLK_TOP_TVDPLL2_D8, - CLK_TOP_TVDPLL1_D16, - CLK_TOP_TVDPLL2_D16 -}; - -static const int disp_pwm0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_ULPOSC1_D2, - CLK_TOP_ULPOSC1_D4, - CLK_TOP_ULPOSC1_D16, - CLK_TOP_ETHPLL_D4 -}; - -static const int disp_pwm1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_ULPOSC1_D2, - CLK_TOP_ULPOSC1_D4, - CLK_TOP_ULPOSC1_D16 -}; - -static const int usb_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D5_D2 -}; - -static const int ssusb_xhci_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D5_D2 -}; - -static const int usb_2p_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D5_D2 -}; - -static const int ssusb_xhci_2p_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D5_D2 -}; - -static const int usb_3p_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D5_D2 -}; - -static const int ssusb_xhci_3p_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D5_D2 -}; - -static const int i2c_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D8, - CLK_TOP_UNIVPLL_D5_D4 -}; - -static const int seninf_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D7, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MMPLL_D6, - CLK_TOP_UNIVPLL_D5 -}; - -static const int seninf1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D7, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MMPLL_D6, - CLK_TOP_UNIVPLL_D5 -}; - -static const int gcpu_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D6, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MMPLL_D5_D2, - CLK_TOP_UNIVPLL_D5_D2 -}; - -static const int venc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_MAINPLL_D6, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MMPLL_D6, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_MMPLL_D9, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_MAINPLL_D5 -}; - -static const int vdec_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MMPLL_D6_D2, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D5, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MMPLL_D6, - CLK_TOP_MAINPLL_D4, - CLK_TOP_TVDPLL2, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_IMGPLL, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MMPLL_D9 -}; - -static const int pwm_parents[] = { - CLK_TOP_CLK32K, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D4_D8, - CLK_TOP_UNIVPLL_D6_D4 -}; - -static const int mcupm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_MAINPLL_D7_D4 -}; - -static const int spmi_p_mst_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_CLK13M, - CLK_TOP_ULPOSC1_D8, - CLK_TOP_ULPOSC1_D10, - CLK_TOP_ULPOSC1_D16, - CLK_TOP_ULPOSC1_D7, - CLK_TOP_CLK32K, - CLK_TOP_MAINPLL_D7_D8, - CLK_TOP_MAINPLL_D6_D8, - CLK_TOP_MAINPLL_D5_D8 -}; - -static const int spmi_m_mst_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_CLK13M, - CLK_TOP_ULPOSC1_D8, - CLK_TOP_ULPOSC1_D10, - CLK_TOP_ULPOSC1_D16, - CLK_TOP_ULPOSC1_D7, - CLK_TOP_CLK32K, - CLK_TOP_MAINPLL_D7_D8, - CLK_TOP_MAINPLL_D6_D8, - CLK_TOP_MAINPLL_D5_D8 -}; - -static const int dvfsrc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_ULPOSC1_D10, - CLK_TOP_UNIVPLL_D6_D8, - CLK_TOP_MSDCPLL_D16 -}; - -static const int tl_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_MAINPLL_D4_D4 -}; - -static const int aes_msdcfde_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_UNIVPLL_D6 -}; - -static const int dsi_occ_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_UNIVPLL_D4_D2 -}; - -static const int wpe_vpp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MMPLL_D6_D2, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D5, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MAINPLL_D4, - CLK_TOP_TVDPLL1, - CLK_TOP_UNIVPLL_D4 -}; - -static const int hdcp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D4_D8, - CLK_TOP_MAINPLL_D5_D8, - CLK_TOP_UNIVPLL_D6_D4 + +static const struct mtk_parent dpi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL1_D2), + TOP_PARENT(CLK_TOP_TVDPLL2_D2), + TOP_PARENT(CLK_TOP_TVDPLL1_D4), + TOP_PARENT(CLK_TOP_TVDPLL2_D4), + TOP_PARENT(CLK_TOP_TVDPLL1_D8), + TOP_PARENT(CLK_TOP_TVDPLL2_D8), + TOP_PARENT(CLK_TOP_TVDPLL1_D16), + TOP_PARENT(CLK_TOP_TVDPLL2_D16), +}; + +static const struct mtk_parent disp_pwm0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D2), + TOP_PARENT(CLK_TOP_ULPOSC1_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D16), + TOP_PARENT(CLK_TOP_ETHPLL_D4), +}; + +static const struct mtk_parent disp_pwm1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D2), + TOP_PARENT(CLK_TOP_ULPOSC1_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D16), +}; + +static const struct mtk_parent usb_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent ssusb_xhci_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent usb_2p_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent ssusb_xhci_2p_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent usb_3p_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent ssusb_xhci_3p_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent i2c_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), +}; + +static const struct mtk_parent seninf_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), +}; + +static const struct mtk_parent seninf1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), +}; + +static const struct mtk_parent gcpu_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent venc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MMPLL_D9), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5), +}; + +static const struct mtk_parent vdec_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_TVDPLL2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + APMIXED_PARENT(CLK_APMIXED_IMGPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MMPLL_D9), +}; + +static const struct mtk_parent pwm_parents[] = { + EXT_PARENT(CLK_PAD_CLK32K), + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent mcupm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), +}; + +static const struct mtk_parent spmi_p_mst_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK13M), + TOP_PARENT(CLK_TOP_ULPOSC1_D8), + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_ULPOSC1_D16), + TOP_PARENT(CLK_TOP_ULPOSC1_D7), + EXT_PARENT(CLK_PAD_CLK32K), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D8), +}; + +static const struct mtk_parent spmi_m_mst_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK13M), + TOP_PARENT(CLK_TOP_ULPOSC1_D8), + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_ULPOSC1_D16), + TOP_PARENT(CLK_TOP_ULPOSC1_D7), + EXT_PARENT(CLK_PAD_CLK32K), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D8), +}; + +static const struct mtk_parent dvfsrc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_MSDCPLL_D16), +}; + +static const struct mtk_parent tl_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), +}; + +static const struct mtk_parent aes_msdcfde_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), +}; + +static const struct mtk_parent dsi_occ_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), +}; + +static const struct mtk_parent wpe_vpp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_TVDPLL1), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), +}; + +static const struct mtk_parent hdcp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), }; -static const int hdcp_24m_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_192M_D4, - CLK_TOP_UNIVPLL_192M_D8, - CLK_TOP_UNIVPLL_D6_D8 +static const struct mtk_parent hdcp_24m_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), }; -static const int hdmi_apb_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_MSDCPLL_D2 +static const struct mtk_parent hdmi_apb_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), }; -static const int snps_eth_250m_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_ETHPLL_D2 +static const struct mtk_parent snps_eth_250m_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D2), }; -static const int snps_eth_62p4m_ptp_parents[] = { - CLK_TOP_APLL2_D3, - CLK_TOP_APLL1_D3, - CLK_TOP_CLK26M, - CLK_TOP_ETHPLL_D8 -}; - -static const int snps_eth_50m_rmii_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_ETHPLL_D10 +static const struct mtk_parent snps_eth_62p4m_ptp_parents[] = { + TOP_PARENT(CLK_TOP_APLL2_D3), + TOP_PARENT(CLK_TOP_APLL1_D3), + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D8), +}; + +static const struct mtk_parent snps_eth_50m_rmii_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D10), }; -static const int adsp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_CLK13M, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_ULPOSC1_D2, - CLK_TOP_ULPOSC1_CK1, - CLK_TOP_ADSPPLL, - CLK_TOP_ADSPPLL_D2, - CLK_TOP_ADSPPLL_D4, - CLK_TOP_ADSPPLL_D8 +static const struct mtk_parent adsp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK13M), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D2), + TOP_PARENT(CLK_TOP_ULPOSC1), + APMIXED_PARENT(CLK_APMIXED_ADSPPLL), + TOP_PARENT(CLK_TOP_ADSPPLL_D2), + TOP_PARENT(CLK_TOP_ADSPPLL_D4), + TOP_PARENT(CLK_TOP_ADSPPLL_D8), }; -static const int audio_local_bus_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_CLK13M, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_MAINPLL_D7_D2, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D7, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_ULPOSC1_CK1, - CLK_TOP_ULPOSC1_D4, - CLK_TOP_ULPOSC1_D2 +static const struct mtk_parent audio_local_bus_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK13M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_ULPOSC1), + TOP_PARENT(CLK_TOP_ULPOSC1_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D2), }; -static const int asm_h_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D5_D2 +static const struct mtk_parent asm_h_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), }; -static const int asm_l_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D5_D2 +static const struct mtk_parent asm_l_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), }; -static const int apll1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_D4 +static const struct mtk_parent apll1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_D4), }; -static const int apll2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_D4 +static const struct mtk_parent apll2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_D4), }; -static const int apll3_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL3_D4 +static const struct mtk_parent apll3_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL3_D4), }; -static const int apll4_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL4_D4 +static const struct mtk_parent apll4_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL4_D4), }; -static const int apll5_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL5_D4 +static const struct mtk_parent apll5_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL5_D4), }; -static const int i2so1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1, - CLK_TOP_APLL2, - CLK_TOP_APLL3, - CLK_TOP_APLL4, - CLK_TOP_APLL5 +static const struct mtk_parent i2so1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL3), + TOP_PARENT(CLK_TOP_APLL4), + TOP_PARENT(CLK_TOP_APLL5), }; -static const int i2so2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1, - CLK_TOP_APLL2, - CLK_TOP_APLL3, - CLK_TOP_APLL4, - CLK_TOP_APLL5 +static const struct mtk_parent i2so2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL3), + TOP_PARENT(CLK_TOP_APLL4), + TOP_PARENT(CLK_TOP_APLL5), }; -static const int i2si1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1, - CLK_TOP_APLL2, - CLK_TOP_APLL3, - CLK_TOP_APLL4, - CLK_TOP_APLL5 +static const struct mtk_parent i2si1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL3), + TOP_PARENT(CLK_TOP_APLL4), + TOP_PARENT(CLK_TOP_APLL5), }; -static const int i2si2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1, - CLK_TOP_APLL2, - CLK_TOP_APLL3, - CLK_TOP_APLL4, - CLK_TOP_APLL5 +static const struct mtk_parent i2si2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL3), + TOP_PARENT(CLK_TOP_APLL4), + TOP_PARENT(CLK_TOP_APLL5), }; -static const int dptx_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1, - CLK_TOP_APLL2, - CLK_TOP_APLL3, - CLK_TOP_APLL4, - CLK_TOP_APLL5 +static const struct mtk_parent dptx_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL3), + TOP_PARENT(CLK_TOP_APLL4), + TOP_PARENT(CLK_TOP_APLL5), }; -static const int aud_iec_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1, - CLK_TOP_APLL2, - CLK_TOP_APLL3, - CLK_TOP_APLL4, - CLK_TOP_APLL5 +static const struct mtk_parent aud_iec_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL3), + TOP_PARENT(CLK_TOP_APLL4), + TOP_PARENT(CLK_TOP_APLL5), }; -static const int a1sys_hp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_D4 +static const struct mtk_parent a1sys_hp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_D4), }; -static const int a2sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_D4 +static const struct mtk_parent a2sys_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_D4), }; -static const int a3sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL3_D4, - CLK_TOP_APLL4_D4, - CLK_TOP_APLL5_D4 +static const struct mtk_parent a3sys_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL3_D4), + TOP_PARENT(CLK_TOP_APLL4_D4), + TOP_PARENT(CLK_TOP_APLL5_D4), }; -static const int a4sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL3_D4, - CLK_TOP_APLL4_D4, - CLK_TOP_APLL5_D4 +static const struct mtk_parent a4sys_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL3_D4), + TOP_PARENT(CLK_TOP_APLL4_D4), + TOP_PARENT(CLK_TOP_APLL5_D4), }; -static const int ecc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D6, - CLK_TOP_UNIVPLL_D6 +static const struct mtk_parent ecc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), }; -static const int spinor_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_CLK13M, - CLK_TOP_MAINPLL_D7_D8, - CLK_TOP_UNIVPLL_D6_D8 +static const struct mtk_parent spinor_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK13M), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), }; -static const int ulposc_parents[] = { - CLK_TOP_ULPOSC_CK1, - CLK_TOP_ETHPLL_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_ETHPLL_D10 +static const struct mtk_parent ulposc_parents[] = { + TOP_PARENT(CLK_TOP_ULPOSC1), + TOP_PARENT(CLK_TOP_ETHPLL_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_ETHPLL_D10), }; -static const int srck_parents[] = { - CLK_TOP_ULPOSC1_D10, - CLK_TOP_CLK26M +static const struct mtk_parent srck_parents[] = { + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + EXT_PARENT(CLK_PAD_CLK26M), }; static const struct mtk_composite top_muxes[] = { @@ -1142,236 +1142,286 @@ static const struct mtk_composite top_muxes[] = { MUX_GATE(CLK_TOP_SRCK, srck_parents, 0x0128, 16, 4, 23), }; -static const int mt8188_id_offs_map[] = { - 87, /* CLK_TOP_AXI */ - 88, /* CLK_TOP_SPM */ - 89, /* CLK_TOP_SCP */ - 90, /* CLK_TOP_BUS_AXIMEM */ - 91, /* CLK_TOP_VPP */ - 92, /* CLK_TOP_ETHDR */ - 93, /* CLK_TOP_IPE */ - 94, /* CLK_TOP_CAM */ - 95, /* CLK_TOP_CCU */ - 96, /* CLK_TOP_CCU_AHB */ - 97, /* CLK_TOP_IMG */ - 98, /* CLK_TOP_CAMTM */ - 99, /* CLK_TOP_DSP */ - 100, /* CLK_TOP_DSP1 */ - 101, /* CLK_TOP_DSP2 */ - 102, /* CLK_TOP_DSP3 */ - 103, /* CLK_TOP_DSP4 */ - 104, /* CLK_TOP_DSP5 */ - 105, /* CLK_TOP_DSP6 */ - 106, /* CLK_TOP_DSP7 */ - 107, /* CLK_TOP_MFG_CORE_TMP */ - 108, /* CLK_TOP_CAMTG */ - 109, /* CLK_TOP_CAMTG2 */ - 110, /* CLK_TOP_CAMTG3 */ - 111, /* CLK_TOP_UART */ - 112, /* CLK_TOP_SPI */ - 113, /* CLK_TOP_MSDC50_0_HCLK */ - 114, /* CLK_TOP_MSDC50_0 */ - 115, /* CLK_TOP_MSDC30_1 */ - 116, /* CLK_TOP_MSDC30_2 */ - 117, /* CLK_TOP_INTDIR */ - 118, /* CLK_TOP_AUD_INTBUS */ - 119, /* CLK_TOP_AUDIO_H */ - 120, /* CLK_TOP_PWRAP_ULPOSC */ - 121, /* CLK_TOP_ATB */ - 122, /* CLK_TOP_SSPM */ - 123, /* CLK_TOP_DP */ - 124, /* CLK_TOP_EDP */ - 125, /* CLK_TOP_DPI */ - 126, /* CLK_TOP_DISP_PWM0 */ - 127, /* CLK_TOP_DISP_PWM1 */ - 128, /* CLK_TOP_USB_TOP */ - 129, /* CLK_TOP_SSUSB_XHCI */ - 130, /* CLK_TOP_USB_TOP_2P */ - 131, /* CLK_TOP_SSUSB_XHCI_2P */ - 132, /* CLK_TOP_USB_TOP_3P */ - 133, /* CLK_TOP_SSUSB_XHCI_3P */ - 134, /* CLK_TOP_I2C */ - 135, /* CLK_TOP_SENINF */ - 136, /* CLK_TOP_SENINF1 */ - 137, /* CLK_TOP_GCPU */ - 138, /* CLK_TOP_VENC */ - 139, /* CLK_TOP_VDEC */ - 140, /* CLK_TOP_PWM */ - 141, /* CLK_TOP_MCUPM */ - 142, /* CLK_TOP_SPMI_P_MST */ - 143, /* CLK_TOP_SPMI_M_MST */ - 144, /* CLK_TOP_DVFSRC */ - 145, /* CLK_TOP_TL */ - 146, /* CLK_TOP_AES_MSDCFDE */ - 147, /* CLK_TOP_DSI_OCC */ - 148, /* CLK_TOP_WPE_VPP */ - 149, /* CLK_TOP_HDCP */ - 150, /* CLK_TOP_HDCP_24M */ - 151, /* CLK_TOP_HDMI_APB */ - 152, /* CLK_TOP_SNPS_ETH_250M */ - 153, /* CLK_TOP_SNPS_ETH_62P4M_PTP */ - 154, /* CLK_TOP_SNPS_ETH_50M_RMII */ - 155, /* CLK_TOP_ADSP */ - 156, /* CLK_TOP_AUDIO_LOCAL_BUS */ - 157, /* CLK_TOP_ASM_H */ - 158, /* CLK_TOP_ASM_L */ - 159, /* CLK_TOP_APLL1 */ - 160, /* CLK_TOP_APLL2 */ - 161, /* CLK_TOP_APLL3 */ - 162, /* CLK_TOP_APLL4 */ - 163, /* CLK_TOP_APLL5 */ - 164, /* CLK_TOP_I2SO1 */ - 165, /* CLK_TOP_I2SO2 */ - 166, /* CLK_TOP_I2SI1 */ - 167, /* CLK_TOP_I2SI2 */ - 168, /* CLK_TOP_DPTX */ - 169, /* CLK_TOP_AUD_IEC */ - 170, /* CLK_TOP_A1SYS_HP */ - 171, /* CLK_TOP_A2SYS */ - 172, /* CLK_TOP_A3SYS */ - 173, /* CLK_TOP_A4SYS */ - 174, /* CLK_TOP_ECC */ - 175, /* CLK_TOP_SPINOR */ - 176, /* CLK_TOP_ULPOSC */ - 177, /* CLK_TOP_SRCK */ - -1, /* CLK_TOP_MFG_CK_FAST_REF */ - 8, /* CLK_TOP_MAINPLL_D3 */ - 9, /* CLK_TOP_MAINPLL_D4 */ - 10, /* CLK_TOP_MAINPLL_D4_D2 */ - 11, /* CLK_TOP_MAINPLL_D4_D4 */ - 12, /* CLK_TOP_MAINPLL_D4_D8 */ - 13, /* CLK_TOP_MAINPLL_D5 */ - 14, /* CLK_TOP_MAINPLL_D5_D2 */ - 15, /* CLK_TOP_MAINPLL_D5_D4 */ - 16, /* CLK_TOP_MAINPLL_D5_D8 */ - 17, /* CLK_TOP_MAINPLL_D6 */ - 18, /* CLK_TOP_MAINPLL_D6_D2 */ - 19, /* CLK_TOP_MAINPLL_D6_D4 */ - 20, /* CLK_TOP_MAINPLL_D6_D8 */ - 21, /* CLK_TOP_MAINPLL_D7 */ - 22, /* CLK_TOP_MAINPLL_D7_D2 */ - 23, /* CLK_TOP_MAINPLL_D7_D4 */ - 24, /* CLK_TOP_MAINPLL_D7_D8 */ - 25, /* CLK_TOP_MAINPLL_D9 */ - 26, /* CLK_TOP_UNIVPLL_D2 */ - 27, /* CLK_TOP_UNIVPLL_D3 */ - 28, /* CLK_TOP_UNIVPLL_D4 */ - 29, /* CLK_TOP_UNIVPLL_D4_D2 */ - 30, /* CLK_TOP_UNIVPLL_D4_D4 */ - 31, /* CLK_TOP_UNIVPLL_D4_D8 */ - 32, /* CLK_TOP_UNIVPLL_D5 */ - 33, /* CLK_TOP_UNIVPLL_D5_D2 */ - 34, /* CLK_TOP_UNIVPLL_D5_D4 */ - 35, /* CLK_TOP_UNIVPLL_D5_D8 */ - 36, /* CLK_TOP_UNIVPLL_D6 */ - 37, /* CLK_TOP_UNIVPLL_D6_D2 */ - 38, /* CLK_TOP_UNIVPLL_D6_D4 */ - 39, /* CLK_TOP_UNIVPLL_D6_D8 */ - 40, /* CLK_TOP_UNIVPLL_D7 */ - 41, /* CLK_TOP_UNIVPLL_192M */ - 42, /* CLK_TOP_UNIVPLL_192M_D4 */ - 43, /* CLK_TOP_UNIVPLL_192M_D8 */ - 44, /* CLK_TOP_UNIVPLL_192M_D10 */ - 45, /* CLK_TOP_UNIVPLL_192M_D16 */ - 46, /* CLK_TOP_UNIVPLL_192M_D32 */ - 47, /* CLK_TOP_APLL1_D3 */ - 48, /* CLK_TOP_APLL1_D4 */ - 49, /* CLK_TOP_APLL2_D3 */ - 50, /* CLK_TOP_APLL2_D4 */ - 51, /* CLK_TOP_APLL3_D4 */ - 52, /* CLK_TOP_APLL4_D4 */ - 53, /* CLK_TOP_APLL5_D4 */ - 54, /* CLK_TOP_MMPLL_D4 */ - 55, /* CLK_TOP_MMPLL_D4_D2 */ - 56, /* CLK_TOP_MMPLL_D5 */ - 57, /* CLK_TOP_MMPLL_D5_D2 */ - 58, /* CLK_TOP_MMPLL_D5_D4 */ - 59, /* CLK_TOP_MMPLL_D6 */ - 60, /* CLK_TOP_MMPLL_D6_D2 */ - 61, /* CLK_TOP_MMPLL_D7 */ - 62, /* CLK_TOP_MMPLL_D9 */ - -1, /* CLK_TOP_TVDPLL1 */ - 63, /* CLK_TOP_TVDPLL1_D2 */ - 64, /* CLK_TOP_TVDPLL1_D4 */ - 65, /* CLK_TOP_TVDPLL1_D8 */ - 66, /* CLK_TOP_TVDPLL1_D16 */ - -1, /* CLK_TOP_TVDPLL2 */ - 67, /* CLK_TOP_TVDPLL2_D2 */ - 68, /* CLK_TOP_TVDPLL2_D4 */ - 69, /* CLK_TOP_TVDPLL2_D8 */ - 70, /* CLK_TOP_TVDPLL2_D16 */ - 72, /* CLK_TOP_MSDCPLL_D2 */ - 73, /* CLK_TOP_MSDCPLL_D16 */ - -1, /* CLK_TOP_ETHPLL */ - 74, /* CLK_TOP_ETHPLL_D2 */ - 75, /* CLK_TOP_ETHPLL_D4 */ - 76, /* CLK_TOP_ETHPLL_D8 */ - 77, /* CLK_TOP_ETHPLL_D10 */ - 78, /* CLK_TOP_ADSPPLL_D2 */ - 79, /* CLK_TOP_ADSPPLL_D4 */ - 80, /* CLK_TOP_ADSPPLL_D8 */ - 0, /* CLK_TOP_ULPOSC1 */ - 81, /* CLK_TOP_ULPOSC1_D2 */ - 82, /* CLK_TOP_ULPOSC1_D4 */ - 83, /* CLK_TOP_ULPOSC1_D8 */ - 84, /* CLK_TOP_ULPOSC1_D7 */ - 85, /* CLK_TOP_ULPOSC1_D10 */ - 86, /* CLK_TOP_ULPOSC1_D16 */ - 1, /* CLK_TOP_MPHONE_SLAVE_BCK */ - 2, /* CLK_TOP_PAD_FPC */ - 3, /* CLK_TOP_466M_FMEM */ - 4, /* CLK_TOP_PEXTP_PIPE */ - 5, /* CLK_TOP_DSI_PHY */ - -1, /* CLK_TOP_APLL12_CK_DIV0 */ - -1, /* CLK_TOP_APLL12_CK_DIV1 */ - -1, /* CLK_TOP_APLL12_CK_DIV2 */ - -1, /* CLK_TOP_APLL12_CK_DIV3 */ - -1, /* CLK_TOP_APLL12_CK_DIV4 */ - -1, /* CLK_TOP_APLL12_CK_DIV9 */ - -1, /* CLK_TOP_CFGREG_CLOCK_EN_VPP0 */ - -1, /* CLK_TOP_CFGREG_CLOCK_EN_VPP1 */ - -1, /* CLK_TOP_CFGREG_CLOCK_EN_VDO0 */ - -1, /* CLK_TOP_CFGREG_CLOCK_EN_VDO1 */ - -1, /* CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS */ - -1, /* CLK_TOP_CFGREG_F26M_VPP0 */ - -1, /* CLK_TOP_CFGREG_F26M_VPP1 */ - -1, /* CLK_TOP_CFGREG_F26M_VDO0 */ - -1, /* CLK_TOP_CFGREG_F26M_VDO1 */ - -1, /* CLK_TOP_CFGREG_AUD_F26M_AUD */ - -1, /* CLK_TOP_CFGREG_UNIPLL_SES */ - -1, /* CLK_TOP_CFGREG_F_PCIE_PHY_REF */ - -1, /* CLK_TOP_SSUSB_TOP_REF */ - -1, /* CLK_TOP_SSUSB_PHY_REF */ - -1, /* CLK_TOP_SSUSB_TOP_P1_REF */ - -1, /* CLK_TOP_SSUSB_PHY_P1_REF */ - -1, /* CLK_TOP_SSUSB_TOP_P2_REF */ - -1, /* CLK_TOP_SSUSB_PHY_P2_REF */ - -1, /* CLK_TOP_SSUSB_TOP_P3_REF */ - -1, /* CLK_TOP_SSUSB_PHY_P3_REF */ - -1, /* CLK_TOP_NR_CLK */ - -1, /* CLK_TOP_ADSPPLL */ - -1, /* CLK_TOP_CLK13M */ - 6, /* CLK_TOP_CLK26M */ - 7, /* CLK_TOP_CLK32K */ - -1, /* CLK_TOP_IMGPLL */ - 71, /* CLK_TOP_MSDCPLL */ - -1, /* CLK_TOP_ULPOSC1_CK1 */ - -1, /* CLK_TOP_ULPOSC_CK1 */ +static const int mt8188_id_top_offs_map[] = { + [0 ... CLK_TOP_NR_CLK - 1] = -1, + /* FIXED */ + [CLK_TOP_ULPOSC1] = 0, + [CLK_TOP_MPHONE_SLAVE_BCK] = 1, + [CLK_TOP_PAD_FPC] = 2, + [CLK_TOP_466M_FMEM] = 3, + [CLK_TOP_PEXTP_PIPE] = 4, + [CLK_TOP_DSI_PHY] = 5, + /* FACTOR */ + [CLK_TOP_MAINPLL_D3] = 6, + [CLK_TOP_MAINPLL_D4] = 7, + [CLK_TOP_MAINPLL_D4_D2] = 8, + [CLK_TOP_MAINPLL_D4_D4] = 9, + [CLK_TOP_MAINPLL_D4_D8] = 10, + [CLK_TOP_MAINPLL_D5] = 11, + [CLK_TOP_MAINPLL_D5_D2] = 12, + [CLK_TOP_MAINPLL_D5_D4] = 13, + [CLK_TOP_MAINPLL_D5_D8] = 14, + [CLK_TOP_MAINPLL_D6] = 15, + [CLK_TOP_MAINPLL_D6_D2] = 16, + [CLK_TOP_MAINPLL_D6_D4] = 17, + [CLK_TOP_MAINPLL_D6_D8] = 18, + [CLK_TOP_MAINPLL_D7] = 19, + [CLK_TOP_MAINPLL_D7_D2] = 20, + [CLK_TOP_MAINPLL_D7_D4] = 21, + [CLK_TOP_MAINPLL_D7_D8] = 22, + [CLK_TOP_MAINPLL_D9] = 23, + [CLK_TOP_UNIVPLL_D2] = 24, + [CLK_TOP_UNIVPLL_D3] = 25, + [CLK_TOP_UNIVPLL_D4] = 26, + [CLK_TOP_UNIVPLL_D4_D2] = 27, + [CLK_TOP_UNIVPLL_D4_D4] = 28, + [CLK_TOP_UNIVPLL_D4_D8] = 29, + [CLK_TOP_UNIVPLL_D5] = 30, + [CLK_TOP_UNIVPLL_D5_D2] = 31, + [CLK_TOP_UNIVPLL_D5_D4] = 32, + [CLK_TOP_UNIVPLL_D5_D8] = 33, + [CLK_TOP_UNIVPLL_D6] = 34, + [CLK_TOP_UNIVPLL_D6_D2] = 35, + [CLK_TOP_UNIVPLL_D6_D4] = 36, + [CLK_TOP_UNIVPLL_D6_D8] = 37, + [CLK_TOP_UNIVPLL_D7] = 38, + [CLK_TOP_UNIVPLL_192M] = 39, + [CLK_TOP_UNIVPLL_192M_D4] = 40, + [CLK_TOP_UNIVPLL_192M_D8] = 41, + [CLK_TOP_UNIVPLL_192M_D10] = 42, + [CLK_TOP_UNIVPLL_192M_D16] = 43, + [CLK_TOP_UNIVPLL_192M_D32] = 44, + [CLK_TOP_APLL1_D3] = 45, + [CLK_TOP_APLL1_D4] = 46, + [CLK_TOP_APLL2_D3] = 47, + [CLK_TOP_APLL2_D4] = 48, + [CLK_TOP_APLL3_D4] = 49, + [CLK_TOP_APLL4_D4] = 50, + [CLK_TOP_APLL5_D4] = 51, + [CLK_TOP_MMPLL_D4] = 52, + [CLK_TOP_MMPLL_D4_D2] = 53, + [CLK_TOP_MMPLL_D5] = 54, + [CLK_TOP_MMPLL_D5_D2] = 55, + [CLK_TOP_MMPLL_D5_D4] = 56, + [CLK_TOP_MMPLL_D6] = 57, + [CLK_TOP_MMPLL_D6_D2] = 58, + [CLK_TOP_MMPLL_D7] = 59, + [CLK_TOP_MMPLL_D9] = 60, + [CLK_TOP_TVDPLL1_D2] = 61, + [CLK_TOP_TVDPLL1_D4] = 62, + [CLK_TOP_TVDPLL1_D8] = 63, + [CLK_TOP_TVDPLL1_D16] = 64, + [CLK_TOP_TVDPLL2_D2] = 65, + [CLK_TOP_TVDPLL2_D4] = 66, + [CLK_TOP_TVDPLL2_D8] = 67, + [CLK_TOP_TVDPLL2_D16] = 68, + [CLK_TOP_MSDCPLL_D2] = 69, + [CLK_TOP_MSDCPLL_D16] = 70, + [CLK_TOP_ETHPLL_D2] = 71, + [CLK_TOP_ETHPLL_D4] = 72, + [CLK_TOP_ETHPLL_D8] = 73, + [CLK_TOP_ETHPLL_D10] = 74, + [CLK_TOP_ADSPPLL_D2] = 75, + [CLK_TOP_ADSPPLL_D4] = 76, + [CLK_TOP_ADSPPLL_D8] = 77, + [CLK_TOP_ULPOSC1_D2] = 78, + [CLK_TOP_ULPOSC1_D4] = 79, + [CLK_TOP_ULPOSC1_D8] = 80, + [CLK_TOP_ULPOSC1_D7] = 81, + [CLK_TOP_ULPOSC1_D10] = 82, + [CLK_TOP_ULPOSC1_D16] = 83, + /* MUX */ + [CLK_TOP_AXI] = 84, + [CLK_TOP_SPM] = 85, + [CLK_TOP_SCP] = 86, + [CLK_TOP_BUS_AXIMEM] = 87, + [CLK_TOP_VPP] = 88, + [CLK_TOP_ETHDR] = 89, + [CLK_TOP_IPE] = 90, + [CLK_TOP_CAM] = 91, + [CLK_TOP_CCU] = 92, + [CLK_TOP_CCU_AHB] = 93, + [CLK_TOP_IMG] = 94, + [CLK_TOP_CAMTM] = 95, + [CLK_TOP_DSP] = 96, + [CLK_TOP_DSP1] = 97, + [CLK_TOP_DSP2] = 98, + [CLK_TOP_DSP3] = 99, + [CLK_TOP_DSP4] = 100, + [CLK_TOP_DSP5] = 101, + [CLK_TOP_DSP6] = 102, + [CLK_TOP_DSP7] = 103, + [CLK_TOP_MFG_CORE_TMP] = 104, + [CLK_TOP_CAMTG] = 105, + [CLK_TOP_CAMTG2] = 106, + [CLK_TOP_CAMTG3] = 107, + [CLK_TOP_UART] = 108, + [CLK_TOP_SPI] = 109, + [CLK_TOP_MSDC50_0_HCLK] = 110, + [CLK_TOP_MSDC50_0] = 111, + [CLK_TOP_MSDC30_1] = 112, + [CLK_TOP_MSDC30_2] = 113, + [CLK_TOP_INTDIR] = 114, + [CLK_TOP_AUD_INTBUS] = 115, + [CLK_TOP_AUDIO_H] = 116, + [CLK_TOP_PWRAP_ULPOSC] = 117, + [CLK_TOP_ATB] = 118, + [CLK_TOP_SSPM] = 119, + [CLK_TOP_DP] = 120, + [CLK_TOP_EDP] = 121, + [CLK_TOP_DPI] = 122, + [CLK_TOP_DISP_PWM0] = 123, + [CLK_TOP_DISP_PWM1] = 124, + [CLK_TOP_USB_TOP] = 125, + [CLK_TOP_SSUSB_XHCI] = 126, + [CLK_TOP_USB_TOP_2P] = 127, + [CLK_TOP_SSUSB_XHCI_2P] = 128, + [CLK_TOP_USB_TOP_3P] = 129, + [CLK_TOP_SSUSB_XHCI_3P] = 130, + [CLK_TOP_I2C] = 131, + [CLK_TOP_SENINF] = 132, + [CLK_TOP_SENINF1] = 133, + [CLK_TOP_GCPU] = 134, + [CLK_TOP_VENC] = 135, + [CLK_TOP_VDEC] = 136, + [CLK_TOP_PWM] = 137, + [CLK_TOP_MCUPM] = 138, + [CLK_TOP_SPMI_P_MST] = 139, + [CLK_TOP_SPMI_M_MST] = 140, + [CLK_TOP_DVFSRC] = 141, + [CLK_TOP_TL] = 142, + [CLK_TOP_AES_MSDCFDE] = 143, + [CLK_TOP_DSI_OCC] = 144, + [CLK_TOP_WPE_VPP] = 145, + [CLK_TOP_HDCP] = 146, + [CLK_TOP_HDCP_24M] = 147, + [CLK_TOP_HDMI_APB] = 148, + [CLK_TOP_SNPS_ETH_250M] = 149, + [CLK_TOP_SNPS_ETH_62P4M_PTP] = 150, + [CLK_TOP_SNPS_ETH_50M_RMII] = 151, + [CLK_TOP_ADSP] = 152, + [CLK_TOP_AUDIO_LOCAL_BUS] = 153, + [CLK_TOP_ASM_H] = 154, + [CLK_TOP_ASM_L] = 155, + [CLK_TOP_APLL1] = 156, + [CLK_TOP_APLL2] = 157, + [CLK_TOP_APLL3] = 158, + [CLK_TOP_APLL4] = 159, + [CLK_TOP_APLL5] = 160, + [CLK_TOP_I2SO1] = 161, + [CLK_TOP_I2SO2] = 162, + [CLK_TOP_I2SI1] = 163, + [CLK_TOP_I2SI2] = 164, + [CLK_TOP_DPTX] = 165, + [CLK_TOP_AUD_IEC] = 166, + [CLK_TOP_A1SYS_HP] = 167, + [CLK_TOP_A2SYS] = 168, + [CLK_TOP_A3SYS] = 169, + [CLK_TOP_A4SYS] = 170, + [CLK_TOP_ECC] = 171, + [CLK_TOP_SPINOR] = 172, + [CLK_TOP_ULPOSC] = 173, + [CLK_TOP_SRCK] = 174, + /* GATE */ + [CLK_TOP_CFGREG_CLOCK_EN_VPP0] = 175, + [CLK_TOP_CFGREG_CLOCK_EN_VPP1] = 176, + [CLK_TOP_CFGREG_CLOCK_EN_VDO0] = 177, + [CLK_TOP_CFGREG_CLOCK_EN_VDO1] = 178, + [CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS] = 179, + [CLK_TOP_CFGREG_F26M_VPP0] = 180, + [CLK_TOP_CFGREG_F26M_VPP1] = 181, + [CLK_TOP_CFGREG_F26M_VDO0] = 182, + [CLK_TOP_CFGREG_F26M_VDO1] = 183, + [CLK_TOP_CFGREG_AUD_F26M_AUD] = 184, + [CLK_TOP_CFGREG_UNIPLL_SES] = 185, + [CLK_TOP_CFGREG_F_PCIE_PHY_REF] = 186, + [CLK_TOP_SSUSB_TOP_REF] = 187, + [CLK_TOP_SSUSB_PHY_REF] = 188, + [CLK_TOP_SSUSB_TOP_P1_REF] = 189, + [CLK_TOP_SSUSB_PHY_P1_REF] = 190, + [CLK_TOP_SSUSB_TOP_P2_REF] = 191, + [CLK_TOP_SSUSB_PHY_P2_REF] = 192, + [CLK_TOP_SSUSB_TOP_P3_REF] = 193, + [CLK_TOP_SSUSB_PHY_P3_REF] = 194, +}; + +static const struct mtk_gate_regs top0_cg_regs = { + .set_ofs = 0x238, + .clr_ofs = 0x238, + .sta_ofs = 0x238, +}; + +static const struct mtk_gate_regs top1_cg_regs = { + .set_ofs = 0x250, + .clr_ofs = 0x250, + .sta_ofs = 0x250, +}; + +#define GATE_TOP0(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &top0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_TOP0E(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &top0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_EXT, \ + } + +#define GATE_TOP1(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &top1_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_EXT, \ + } + +static const struct mtk_gate topckgen_cg_clks[] = { + /* TOP0 */ + GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VPP0, CLK_TOP_VPP, 0), + GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VPP1, CLK_TOP_VPP, 1), + GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO0, CLK_TOP_VPP, 2), + GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO1, CLK_TOP_VPP, 3), + GATE_TOP0(CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS, CLK_TOP_VPP, 4), + GATE_TOP0E(CLK_TOP_CFGREG_F26M_VPP0, CLK_PAD_CLK26M, 5), + GATE_TOP0E(CLK_TOP_CFGREG_F26M_VPP1, CLK_PAD_CLK26M, 6), + GATE_TOP0E(CLK_TOP_CFGREG_F26M_VDO0, CLK_PAD_CLK26M, 7), + GATE_TOP0E(CLK_TOP_CFGREG_F26M_VDO1, CLK_PAD_CLK26M, 8), + GATE_TOP0E(CLK_TOP_CFGREG_AUD_F26M_AUD, CLK_PAD_CLK26M, 9), + GATE_TOP0(CLK_TOP_CFGREG_UNIPLL_SES, CLK_TOP_UNIVPLL_D2, 15), + GATE_TOP0E(CLK_TOP_CFGREG_F_PCIE_PHY_REF, CLK_PAD_CLK26M, 18), + /* TOP1 */ + GATE_TOP1(CLK_TOP_SSUSB_TOP_REF, CLK_PAD_CLK26M, 0), + GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, CLK_PAD_CLK26M, 1), + GATE_TOP1(CLK_TOP_SSUSB_TOP_P1_REF, CLK_PAD_CLK26M, 2), + GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, CLK_PAD_CLK26M, 3), + GATE_TOP1(CLK_TOP_SSUSB_TOP_P2_REF, CLK_PAD_CLK26M, 4), + GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, CLK_PAD_CLK26M, 5), + GATE_TOP1(CLK_TOP_SSUSB_TOP_P3_REF, CLK_PAD_CLK26M, 6), + GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, CLK_PAD_CLK26M, 7), }; static const struct mtk_clk_tree mt8188_topckgen_clk_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, - .id_offs_map = mt8188_id_offs_map, - .id_offs_map_size = ARRAY_SIZE(mt8188_id_offs_map), - .fdivs_offs = 8, /* CLK_TOP_MAINPLL_D3 */ - .muxes_offs = 87, /* CLK_TOP_AXI */ + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), + .id_offs_map = mt8188_id_top_offs_map, + .id_offs_map_size = ARRAY_SIZE(mt8188_id_top_offs_map), + .fdivs_offs = mt8188_id_top_offs_map[CLK_TOP_MAINPLL_D3], + .muxes_offs = mt8188_id_top_offs_map[CLK_TOP_AXI], + .gates_offs = mt8188_id_top_offs_map[CLK_TOP_CFGREG_CLOCK_EN_VPP0], .fclks = top_fixed_clks, .fdivs = top_fixed_divs, .muxes = top_muxes, + .gates = topckgen_cg_clks, .num_fclks = ARRAY_SIZE(top_fixed_clks), .num_fdivs = ARRAY_SIZE(top_fixed_divs), .num_muxes = ARRAY_SIZE(top_muxes), + .num_gates = ARRAY_SIZE(topckgen_cg_clks), }; static const struct mtk_gate_regs infra_ao0_cg_regs = { @@ -1412,6 +1462,14 @@ static const struct mtk_gate_regs infra_ao4_cg_regs = { .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ } +#define GATE_INFRA_AO0E(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra_ao0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_EXT, \ + } + #define GATE_INFRA_AO1(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ @@ -1420,6 +1478,14 @@ static const struct mtk_gate_regs infra_ao4_cg_regs = { .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ } +#define GATE_INFRA_AO1E(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra_ao1_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_EXT, \ + } + #define GATE_INFRA_AO2(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ @@ -1428,6 +1494,14 @@ static const struct mtk_gate_regs infra_ao4_cg_regs = { .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ } +#define GATE_INFRA_AO2E(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra_ao2_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_EXT, \ + } + #define GATE_INFRA_AO3(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ @@ -1436,6 +1510,14 @@ static const struct mtk_gate_regs infra_ao4_cg_regs = { .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ } +#define GATE_INFRA_AO3E(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra_ao3_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_EXT, \ + } + #define GATE_INFRA_AO4(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ @@ -1467,24 +1549,24 @@ static const struct mtk_gate infracfg_ao_clks[] = { GATE_INFRA_AO0(CLK_INFRA_AO_UART2, CLK_TOP_UART, 24), GATE_INFRA_AO0(CLK_INFRA_AO_UART3, CLK_TOP_UART, 25), GATE_INFRA_AO0(CLK_INFRA_AO_UART4, CLK_TOP_UART, 26), - GATE_INFRA_AO0(CLK_INFRA_AO_GCE_26M, CLK_TOP_CLK26M, 27), + GATE_INFRA_AO0E(CLK_INFRA_AO_GCE_26M, CLK_PAD_CLK26M, 27), GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, CLK_TOP_PAD_FPC, 28), GATE_INFRA_AO0(CLK_INFRA_AO_UART5, CLK_TOP_UART, 29), /* INFRA_AO1 */ - GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_26M, CLK_TOP_CLK26M, 0), + GATE_INFRA_AO1E(CLK_INFRA_AO_HDMI_26M, CLK_PAD_CLK26M, 0), GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, CLK_TOP_SPI, 1), - GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, CLK_TOP_CLK26M, 2), + GATE_INFRA_AO1E(CLK_INFRA_AO_MSDC0, CLK_PAD_CLK26M, 2), GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, CLK_TOP_AXI, 4), GATE_INFRA_AO1(CLK_INFRA_AO_MSDC2, CLK_TOP_AXI, 5), GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0_SRC, CLK_TOP_MSDC50_0, 6), /* infra_ao_dvfsrc is for internal DVFS usage, should not be handled by Linux. */ - GATE_INFRA_AO1(CLK_INFRA_AO_DVFSRC, CLK_TOP_CLK26M, 7), + GATE_INFRA_AO1E(CLK_INFRA_AO_DVFSRC, CLK_PAD_CLK26M, 7), GATE_INFRA_AO1(CLK_INFRA_AO_TRNG, CLK_TOP_AXI, 9), - GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC, CLK_TOP_CLK26M, 10), + GATE_INFRA_AO1E(CLK_INFRA_AO_AUXADC, CLK_PAD_CLK26M, 10), GATE_INFRA_AO1(CLK_INFRA_AO_CPUM, CLK_TOP_AXI, 11), - GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_32K, CLK_TOP_CLK32K, 12), + GATE_INFRA_AO1E(CLK_INFRA_AO_HDMI_32K, CLK_PAD_CLK32K, 12), GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_HCLK, CLK_TOP_AXI, 13), - GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_26M, CLK_TOP_CLK26M, 15), + GATE_INFRA_AO1E(CLK_INFRA_AO_PCIE_TL_26M, CLK_PAD_CLK26M, 15), GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1_SRC, CLK_TOP_MSDC30_1, 16), GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_BCLK, CLK_TOP_AXI, 17), GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_96M, CLK_TOP_TL, 18), @@ -1493,14 +1575,14 @@ static const struct mtk_gate infracfg_ao_clks[] = { GATE_INFRA_AO1(CLK_INFRA_AO_ECC_66M_HCLK, CLK_TOP_AXI, 23), GATE_INFRA_AO1(CLK_INFRA_AO_DEBUGSYS, CLK_TOP_AXI, 24), GATE_INFRA_AO1(CLK_INFRA_AO_AUDIO, CLK_TOP_AXI, 25), - GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_32K, CLK_TOP_CLK32K, 26), + GATE_INFRA_AO1E(CLK_INFRA_AO_PCIE_TL_32K, CLK_PAD_CLK32K, 26), GATE_INFRA_AO1(CLK_INFRA_AO_DBG_TRACE, CLK_TOP_AXI, 29), - GATE_INFRA_AO1(CLK_INFRA_AO_DRAMC_F26M, CLK_TOP_CLK26M, 31), + GATE_INFRA_AO1E(CLK_INFRA_AO_DRAMC_F26M, CLK_PAD_CLK26M, 31), /* INFRA_AO2 */ GATE_INFRA_AO2(CLK_INFRA_AO_IRTX, CLK_TOP_AXI, 0), GATE_INFRA_AO2(CLK_INFRA_AO_DISP_PWM, CLK_TOP_DISP_PWM0, 2), GATE_INFRA_AO2(CLK_INFRA_AO_CLDMA_BCLK, CLK_TOP_AXI, 3), - GATE_INFRA_AO2(CLK_INFRA_AO_AUDIO_26M_BCLK, CLK_TOP_CLK26M, 4), + GATE_INFRA_AO2E(CLK_INFRA_AO_AUDIO_26M_BCLK, CLK_PAD_CLK26M, 4), GATE_INFRA_AO2(CLK_INFRA_AO_SPI1, CLK_TOP_SPI, 6), GATE_INFRA_AO2(CLK_INFRA_AO_SPI2, CLK_TOP_SPI, 9), GATE_INFRA_AO2(CLK_INFRA_AO_SPI3, CLK_TOP_SPI, 10), @@ -1519,14 +1601,14 @@ static const struct mtk_gate infracfg_ao_clks[] = { GATE_INFRA_AO3(CLK_INFRA_AO_MD_MSDC0, CLK_TOP_MSDC50_0, 8), GATE_INFRA_AO3(CLK_INFRA_AO_MSDC30_2, CLK_TOP_MSDC30_2, 9), GATE_INFRA_AO3(CLK_INFRA_AO_GCPU, CLK_TOP_GCPU, 10), - GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_PERI_26M, CLK_TOP_CLK26M, 15), + GATE_INFRA_AO3E(CLK_INFRA_AO_PCIE_PERI_26M, CLK_PAD_CLK26M, 15), GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_66M_BCLK, CLK_TOP_AXI, 16), GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_133M_BCLK, CLK_TOP_AXI, 17), GATE_INFRA_AO3(CLK_INFRA_AO_DISP_PWM1, CLK_TOP_DISP_PWM1, 20), GATE_INFRA_AO3(CLK_INFRA_AO_FBIST2FPC, CLK_TOP_MSDC50_0, 24), /* infra_ao_dapc_sync is for device access permission control module */ GATE_INFRA_AO3(CLK_INFRA_AO_DEVICE_APC_SYNC, CLK_TOP_AXI, 25), - GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_P1_PERI_26M, CLK_TOP_CLK26M, 26), + GATE_INFRA_AO3E(CLK_INFRA_AO_PCIE_P1_PERI_26M, CLK_PAD_CLK26M, 26), /* INFRA_AO4 */ /* infra_ao_133m_mclk_set/infra_ao_66m_mclk_set are main clocks of peripheral */ GATE_INFRA_AO4(CLK_INFRA_AO_133M_MCLK_CK, CLK_TOP_AXI, 0), @@ -1536,8 +1618,8 @@ static const struct mtk_gate infracfg_ao_clks[] = { }; static const struct mtk_clk_tree mt8188_infracfg_ao_clk_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; static const struct mtk_gate_regs peri_ao_cg_regs = { @@ -1554,11 +1636,19 @@ static const struct mtk_gate_regs peri_ao_cg_regs = { .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ } +#define GATE_PERI_AOE(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &peri_ao_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_EXT, \ + } + static const struct mtk_gate pericfg_ao_clks[] = { GATE_PERI_AO(CLK_PERI_AO_ETHERNET, CLK_TOP_AXI, 0), GATE_PERI_AO(CLK_PERI_AO_ETHERNET_BUS, CLK_TOP_AXI, 1), GATE_PERI_AO(CLK_PERI_AO_FLASHIF_BUS, CLK_TOP_AXI, 3), - GATE_PERI_AO(CLK_PERI_AO_FLASHIF_26M, CLK_TOP_CLK26M, 4), + GATE_PERI_AOE(CLK_PERI_AO_FLASHIF_26M, CLK_PAD_CLK26M, 4), GATE_PERI_AO(CLK_PERI_AO_FLASHIFLASHCK, CLK_TOP_SPINOR, 5), GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_BUS, CLK_TOP_USB_TOP_2P, 9), GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_XHCI, CLK_TOP_SSUSB_XHCI_2P, 10), @@ -1570,66 +1660,8 @@ static const struct mtk_gate pericfg_ao_clks[] = { }; static const struct mtk_clk_tree mt8188_pericfg_ao_clk_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, -}; - -static const struct mtk_gate_regs top0_cg_regs = { - .set_ofs = 0x238, - .clr_ofs = 0x238, - .sta_ofs = 0x238, -}; - -static const struct mtk_gate_regs top1_cg_regs = { - .set_ofs = 0x250, - .clr_ofs = 0x250, - .sta_ofs = 0x250, -}; - -#define GATE_TOP0(_id, _parent, _shift) { \ - .id = _id, \ - .parent = _parent, \ - .regs = &top0_cg_regs, \ - .shift = _shift, \ - .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \ - } - -#define GATE_TOP1(_id, _parent, _shift) { \ - .id = _id, \ - .parent = _parent, \ - .regs = &top1_cg_regs, \ - .shift = _shift, \ - .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ - } - -static const struct mtk_gate topckgen_cg_clks[] = { - /* TOP0 */ - GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VPP0, CLK_TOP_VPP, 0), - GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VPP1, CLK_TOP_VPP, 1), - GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO0, CLK_TOP_VPP, 2), - GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO1, CLK_TOP_VPP, 3), - GATE_TOP0(CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS, CLK_TOP_VPP, 4), - GATE_TOP0(CLK_TOP_CFGREG_F26M_VPP0, CLK_TOP_CLK26M, 5), - GATE_TOP0(CLK_TOP_CFGREG_F26M_VPP1, CLK_TOP_CLK26M, 6), - GATE_TOP0(CLK_TOP_CFGREG_F26M_VDO0, CLK_TOP_CLK26M, 7), - GATE_TOP0(CLK_TOP_CFGREG_F26M_VDO1, CLK_TOP_CLK26M, 8), - GATE_TOP0(CLK_TOP_CFGREG_AUD_F26M_AUD, CLK_TOP_CLK26M, 9), - GATE_TOP0(CLK_TOP_CFGREG_UNIPLL_SES, CLK_TOP_UNIVPLL_D2, 15), - GATE_TOP0(CLK_TOP_CFGREG_F_PCIE_PHY_REF, CLK_TOP_CLK26M, 18), - /* TOP1 */ - GATE_TOP1(CLK_TOP_SSUSB_TOP_REF, CLK_TOP_CLK26M, 0), - GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, CLK_TOP_CLK26M, 1), - GATE_TOP1(CLK_TOP_SSUSB_TOP_P1_REF, CLK_TOP_CLK26M, 2), - GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, CLK_TOP_CLK26M, 3), - GATE_TOP1(CLK_TOP_SSUSB_TOP_P2_REF, CLK_TOP_CLK26M, 4), - GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, CLK_TOP_CLK26M, 5), - GATE_TOP1(CLK_TOP_SSUSB_TOP_P3_REF, CLK_TOP_CLK26M, 6), - GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, CLK_TOP_CLK26M, 7), -}; - -static const struct mtk_clk_tree mt8188_topckgen_cg_clk_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; static const struct mtk_gate_regs imp_iic_wrap_cg_regs = { @@ -1663,18 +1695,18 @@ static const struct mtk_gate imp_iic_wrap_en_clks[] = { }; const struct mtk_clk_tree mt8188_imp_iic_wrap_c_clk_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; const struct mtk_clk_tree mt8188_imp_iic_wrap_w_clk_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; const struct mtk_clk_tree mt8188_imp_iic_wrap_en_clk_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; static int mt8188_apmixedsys_probe(struct udevice *dev) @@ -1687,14 +1719,6 @@ static int mt8188_topckgen_probe(struct udevice *dev) return mtk_common_clk_init(dev, &mt8188_topckgen_clk_tree); } -static int mt8188_topckgen_cg_probe(struct udevice *dev) -{ - return mtk_common_clk_gate_init(dev, &mt8188_topckgen_cg_clk_tree, - topckgen_cg_clks, - ARRAY_SIZE(topckgen_cg_clks), - CLK_TOP_CFGREG_CLOCK_EN_VPP0); -} - static int mt8188_infracfg_ao_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt8188_infracfg_ao_clk_tree, @@ -1740,11 +1764,6 @@ static const struct udevice_id mt8188_topckgen_compat[] = { { } }; -static const struct udevice_id mt8188_topckgen_cg_compat[] = { - { .compatible = "mediatek,mt8188-topckgen-cg", }, - { } -}; - static const struct udevice_id mt8188_infracfg_ao_compat[] = { { .compatible = "mediatek,mt8188-infracfg-ao", }, { } @@ -1790,16 +1809,6 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = { .flags = DM_FLAG_PRE_RELOC, }; -U_BOOT_DRIVER(mtk_clk_topckgen_cg) = { - .name = "mt8188-topckgen-cg", - .id = UCLASS_CLK, - .of_match = mt8188_topckgen_cg_compat, - .probe = mt8188_topckgen_cg_probe, - .priv_auto = sizeof(struct mtk_cg_priv), - .ops = &mtk_clk_gate_ops, - .flags = DM_FLAG_PRE_RELOC, -}; - U_BOOT_DRIVER(mtk_clk_infracfg_ao) = { .name = "mt8188-infracfg-ao", .id = UCLASS_CLK, diff --git a/drivers/clk/mediatek/clk-mt8189.c b/drivers/clk/mediatek/clk-mt8189.c new file mode 100644 index 00000000000..fec908728c0 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189.c @@ -0,0 +1,1744 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026 MediaTek Inc. + * Author: Chris Chen <[email protected]> + * Author: David Lechner <[email protected]> + */ + +#include <dm.h> +#include <dt-bindings/clock/mediatek,mt8189-clk.h> +#include <linux/kernel.h> + +#include "clk-mtk.h" + +/* TOPCK MUX SEL REG */ +#define CLK_CFG_UPDATE 0x0004 +#define CLK_CFG_UPDATE1 0x0008 +#define CLK_CFG_UPDATE2 0x000c +#define VLP_CLK_CFG_UPDATE 0x0004 +#define CLK_CFG_0 0x0010 +#define CLK_CFG_0_SET 0x0014 +#define CLK_CFG_0_CLR 0x0018 +#define CLK_CFG_1 0x0020 +#define CLK_CFG_1_SET 0x0024 +#define CLK_CFG_1_CLR 0x0028 +#define CLK_CFG_2 0x0030 +#define CLK_CFG_2_SET 0x0034 +#define CLK_CFG_2_CLR 0x0038 +#define CLK_CFG_3 0x0040 +#define CLK_CFG_3_SET 0x0044 +#define CLK_CFG_3_CLR 0x0048 +#define CLK_CFG_4 0x0050 +#define CLK_CFG_4_SET 0x0054 +#define CLK_CFG_4_CLR 0x0058 +#define CLK_CFG_5 0x0060 +#define CLK_CFG_5_SET 0x0064 +#define CLK_CFG_5_CLR 0x0068 +#define CLK_CFG_6 0x0070 +#define CLK_CFG_6_SET 0x0074 +#define CLK_CFG_6_CLR 0x0078 +#define CLK_CFG_7 0x0080 +#define CLK_CFG_7_SET 0x0084 +#define CLK_CFG_7_CLR 0x0088 +#define CLK_CFG_8 0x0090 +#define CLK_CFG_8_SET 0x0094 +#define CLK_CFG_8_CLR 0x0098 +#define CLK_CFG_9 0x00A0 +#define CLK_CFG_9_SET 0x00A4 +#define CLK_CFG_9_CLR 0x00A8 +#define CLK_CFG_10 0x00B0 +#define CLK_CFG_10_SET 0x00B4 +#define CLK_CFG_10_CLR 0x00B8 +#define CLK_CFG_11 0x00C0 +#define CLK_CFG_11_SET 0x00C4 +#define CLK_CFG_11_CLR 0x00C8 +#define CLK_CFG_12 0x00D0 +#define CLK_CFG_12_SET 0x00D4 +#define CLK_CFG_12_CLR 0x00D8 +#define CLK_CFG_13 0x00E0 +#define CLK_CFG_13_SET 0x00E4 +#define CLK_CFG_13_CLR 0x00E8 +#define CLK_CFG_14 0x00F0 +#define CLK_CFG_14_SET 0x00F4 +#define CLK_CFG_14_CLR 0x00F8 +#define CLK_CFG_15 0x0100 +#define CLK_CFG_15_SET 0x0104 +#define CLK_CFG_15_CLR 0x0108 +#define CLK_CFG_16 0x0110 +#define CLK_CFG_16_SET 0x0114 +#define CLK_CFG_16_CLR 0x0118 +#define CLK_CFG_17 0x0180 +#define CLK_CFG_17_SET 0x0184 +#define CLK_CFG_17_CLR 0x0188 +#define CLK_CFG_18 0x0190 +#define CLK_CFG_18_SET 0x0194 +#define CLK_CFG_18_CLR 0x0198 +#define CLK_CFG_19 0x0240 +#define CLK_CFG_19_SET 0x0244 +#define CLK_CFG_19_CLR 0x0248 +#define CLK_AUDDIV_0 0x0320 +#define CLK_MISC_CFG_3 0x0510 +#define CLK_MISC_CFG_3_SET 0x0514 +#define CLK_MISC_CFG_3_CLR 0x0518 +#define VLP_CLK_CFG_0 0x0008 +#define VLP_CLK_CFG_0_SET 0x000C +#define VLP_CLK_CFG_0_CLR 0x0010 +#define VLP_CLK_CFG_1 0x0014 +#define VLP_CLK_CFG_1_SET 0x0018 +#define VLP_CLK_CFG_1_CLR 0x001C +#define VLP_CLK_CFG_2 0x0020 +#define VLP_CLK_CFG_2_SET 0x0024 +#define VLP_CLK_CFG_2_CLR 0x0028 +#define VLP_CLK_CFG_3 0x002C +#define VLP_CLK_CFG_3_SET 0x0030 +#define VLP_CLK_CFG_3_CLR 0x0034 +#define VLP_CLK_CFG_4 0x0038 +#define VLP_CLK_CFG_4_SET 0x003C +#define VLP_CLK_CFG_4_CLR 0x0040 +#define VLP_CLK_CFG_5 0x0044 +#define VLP_CLK_CFG_5_SET 0x0048 +#define VLP_CLK_CFG_5_CLR 0x004C + +/* TOPCK MUX SHIFT */ +#define TOP_MUX_AXI_SHIFT 0 +#define TOP_MUX_AXI_PERI_SHIFT 1 +#define TOP_MUX_AXI_UFS_SHIFT 2 +#define TOP_MUX_BUS_AXIMEM_SHIFT 3 +#define TOP_MUX_DISP0_SHIFT 4 +#define TOP_MUX_MMINFRA_SHIFT 5 +#define TOP_MUX_UART_SHIFT 6 +#define TOP_MUX_SPI0_SHIFT 7 +#define TOP_MUX_SPI1_SHIFT 8 +#define TOP_MUX_SPI2_SHIFT 9 +#define TOP_MUX_SPI3_SHIFT 10 +#define TOP_MUX_SPI4_SHIFT 11 +#define TOP_MUX_SPI5_SHIFT 12 +#define TOP_MUX_MSDC_MACRO_0P_SHIFT 13 +#define TOP_MUX_MSDC50_0_HCLK_SHIFT 14 +#define TOP_MUX_MSDC50_0_SHIFT 15 +#define TOP_MUX_AES_MSDCFDE_SHIFT 16 +#define TOP_MUX_MSDC_MACRO_1P_SHIFT 17 +#define TOP_MUX_MSDC30_1_SHIFT 18 +#define TOP_MUX_MSDC30_1_HCLK_SHIFT 19 +#define TOP_MUX_MSDC_MACRO_2P_SHIFT 20 +#define TOP_MUX_MSDC30_2_SHIFT 21 +#define TOP_MUX_MSDC30_2_HCLK_SHIFT 22 +#define TOP_MUX_AUD_INTBUS_SHIFT 23 +#define TOP_MUX_ATB_SHIFT 24 +#define TOP_MUX_DISP_PWM_SHIFT 25 +#define TOP_MUX_USB_TOP_P0_SHIFT 26 +#define TOP_MUX_SSUSB_XHCI_P0_SHIFT 27 +#define TOP_MUX_USB_TOP_P1_SHIFT 28 +#define TOP_MUX_SSUSB_XHCI_P1_SHIFT 29 +#define TOP_MUX_USB_TOP_P2_SHIFT 30 +#define TOP_MUX_SSUSB_XHCI_P2_SHIFT 0 +#define TOP_MUX_USB_TOP_P3_SHIFT 1 +#define TOP_MUX_SSUSB_XHCI_P3_SHIFT 2 +#define TOP_MUX_USB_TOP_P4_SHIFT 3 +#define TOP_MUX_SSUSB_XHCI_P4_SHIFT 4 +#define TOP_MUX_I2C_SHIFT 5 +#define TOP_MUX_SENINF_SHIFT 6 +#define TOP_MUX_SENINF1_SHIFT 7 +#define TOP_MUX_AUD_ENGEN1_SHIFT 8 +#define TOP_MUX_AUD_ENGEN2_SHIFT 9 +#define TOP_MUX_AES_UFSFDE_SHIFT 10 +#define TOP_MUX_UFS_SHIFT 11 +#define TOP_MUX_UFS_MBIST_SHIFT 12 +#define TOP_MUX_AUD_1_SHIFT 13 +#define TOP_MUX_AUD_2_SHIFT 14 +#define TOP_MUX_VENC_SHIFT 15 +#define TOP_MUX_VDEC_SHIFT 16 +#define TOP_MUX_PWM_SHIFT 17 +#define TOP_MUX_AUDIO_H_SHIFT 18 +#define TOP_MUX_MCUPM_SHIFT 19 +#define TOP_MUX_MEM_SUB_SHIFT 20 +#define TOP_MUX_MEM_SUB_PERI_SHIFT 21 +#define TOP_MUX_MEM_SUB_UFS_SHIFT 22 +#define TOP_MUX_EMI_N_SHIFT 23 +#define TOP_MUX_DSI_OCC_SHIFT 24 +#define TOP_MUX_AP2CONN_HOST_SHIFT 25 +#define TOP_MUX_IMG1_SHIFT 26 +#define TOP_MUX_IPE_SHIFT 27 +#define TOP_MUX_CAM_SHIFT 28 +#define TOP_MUX_CAMTM_SHIFT 29 +#define TOP_MUX_DSP_SHIFT 30 +#define TOP_MUX_SR_PKA_SHIFT 0 +#define TOP_MUX_DXCC_SHIFT 1 +#define TOP_MUX_MFG_REF_SHIFT 2 +#define TOP_MUX_MDP0_SHIFT 3 +#define TOP_MUX_DP_SHIFT 4 +#define TOP_MUX_EDP_SHIFT 5 +#define TOP_MUX_EDP_FAVT_SHIFT 6 +#define TOP_MUX_SNPS_ETH_250M_SHIFT 7 +#define TOP_MUX_SNPS_ETH_62P4M_PTP_SHIFT 8 +#define TOP_MUX_SNPS_ETH_50M_RMII_SHIFT 9 +#define TOP_MUX_SFLASH_SHIFT 10 +#define TOP_MUX_GCPU_SHIFT 11 +#define TOP_MUX_PCIE_MAC_TL_SHIFT 12 +#define TOP_MUX_VDSTX_CLKDIG_CTS_SHIFT 13 +#define TOP_MUX_PLL_DPIX_SHIFT 14 +#define TOP_MUX_ECC_SHIFT 15 +#define TOP_MUX_SCP_SHIFT 0 +#define TOP_MUX_PWRAP_ULPOSC_SHIFT 1 +#define TOP_MUX_SPMI_P_MST_SHIFT 2 +#define TOP_MUX_DVFSRC_SHIFT 3 +#define TOP_MUX_PWM_VLP_SHIFT 4 +#define TOP_MUX_AXI_VLP_SHIFT 5 +#define TOP_MUX_SYSTIMER_26M_SHIFT 6 +#define TOP_MUX_SSPM_SHIFT 7 +#define TOP_MUX_SSPM_F26M_SHIFT 8 +#define TOP_MUX_SRCK_SHIFT 9 +#define TOP_MUX_SCP_SPI_SHIFT 10 +#define TOP_MUX_SCP_IIC_SHIFT 11 +#define TOP_MUX_SCP_SPI_HIGH_SPD_SHIFT 12 +#define TOP_MUX_SCP_IIC_HIGH_SPD_SHIFT 13 +#define TOP_MUX_SSPM_ULPOSC_SHIFT 14 +#define TOP_MUX_APXGPT_26M_SHIFT 15 +#define TOP_MUX_VADSP_SHIFT 16 +#define TOP_MUX_VADSP_VOWPLL_SHIFT 17 +#define TOP_MUX_VADSP_UARTHUB_BCLK_SHIFT 18 +#define TOP_MUX_CAMTG0_SHIFT 19 +#define TOP_MUX_CAMTG1_SHIFT 20 +#define TOP_MUX_CAMTG2_SHIFT 21 +#define TOP_MUX_AUD_ADC_SHIFT 22 +#define TOP_MUX_KP_IRQ_GEN_SHIFT 23 + +/* TOPCK DIVIDER REG */ +#define CLK_AUDDIV_2 0x0328 +#define CLK_AUDDIV_3 0x0334 +#define CLK_AUDDIV_5 0x033C + +/* APMIXED PLL REG */ +#define AP_PLL_CON3 0x00C +#define APLL1_TUNER_CON0 0x040 +#define APLL2_TUNER_CON0 0x044 +#define ARMPLL_LL_CON0 0x204 +#define ARMPLL_LL_CON1 0x208 +#define ARMPLL_LL_CON2 0x20C +#define ARMPLL_LL_CON3 0x210 +#define ARMPLL_BL_CON0 0x214 +#define ARMPLL_BL_CON1 0x218 +#define ARMPLL_BL_CON2 0x21C +#define ARMPLL_BL_CON3 0x220 +#define CCIPLL_CON0 0x224 +#define CCIPLL_CON1 0x228 +#define CCIPLL_CON2 0x22C +#define CCIPLL_CON3 0x230 +#define MAINPLL_CON0 0x304 +#define MAINPLL_CON1 0x308 +#define MAINPLL_CON2 0x30C +#define MAINPLL_CON3 0x310 +#define UNIVPLL_CON0 0x314 +#define UNIVPLL_CON1 0x318 +#define UNIVPLL_CON2 0x31C +#define UNIVPLL_CON3 0x320 +#define MMPLL_CON0 0x324 +#define MMPLL_CON1 0x328 +#define MMPLL_CON2 0x32C +#define MMPLL_CON3 0x330 +#define MFGPLL_CON0 0x504 +#define MFGPLL_CON1 0x508 +#define MFGPLL_CON2 0x50C +#define MFGPLL_CON3 0x510 +#define APLL1_CON0 0x404 +#define APLL1_CON1 0x408 +#define APLL1_CON2 0x40C +#define APLL1_CON3 0x410 +#define APLL1_CON4 0x414 +#define APLL2_CON0 0x418 +#define APLL2_CON1 0x41C +#define APLL2_CON2 0x420 +#define APLL2_CON3 0x424 +#define APLL2_CON4 0x428 +#define EMIPLL_CON0 0x334 +#define EMIPLL_CON1 0x338 +#define EMIPLL_CON2 0x33C +#define EMIPLL_CON3 0x340 +#define APUPLL2_CON0 0x614 +#define APUPLL2_CON1 0x618 +#define APUPLL2_CON2 0x61C +#define APUPLL2_CON3 0x620 +#define APUPLL_CON0 0x604 +#define APUPLL_CON1 0x608 +#define APUPLL_CON2 0x60C +#define APUPLL_CON3 0x610 +#define TVDPLL1_CON0 0x42C +#define TVDPLL1_CON1 0x430 +#define TVDPLL1_CON2 0x434 +#define TVDPLL1_CON3 0x438 +#define TVDPLL2_CON0 0x43C +#define TVDPLL2_CON1 0x440 +#define TVDPLL2_CON2 0x444 +#define TVDPLL2_CON3 0x448 +#define ETHPLL_CON0 0x514 +#define ETHPLL_CON1 0x518 +#define ETHPLL_CON2 0x51C +#define ETHPLL_CON3 0x520 +#define MSDCPLL_CON0 0x524 +#define MSDCPLL_CON1 0x528 +#define MSDCPLL_CON2 0x52C +#define MSDCPLL_CON3 0x530 +#define UFSPLL_CON0 0x534 +#define UFSPLL_CON1 0x538 +#define UFSPLL_CON2 0x53C +#define UFSPLL_CON3 0x540 + +enum { + CLK_PAD_CLK32K, + CLK_PAD_CLK26M, + CLK_PAD_ULPOSC, +}; + +static ulong ext_clock_rates[] = { + [CLK_PAD_CLK32K] = 32000, + [CLK_PAD_CLK26M] = 26 * MHZ, + [CLK_PAD_ULPOSC] = 260 * MHZ, +}; + +#define MT8189_PLL_FMAX (3800UL * MHZ) +#define MT8189_PLL_FMIN (1500UL * MHZ) + +#define PLL(_id, _reg, _flags, _pd_reg, _pd_shift, _pcw_reg, _pcw_shift, _pcwbits) \ + { \ + .id = _id, \ + .reg = _reg, \ + .flags = (_flags), \ + .fmax = MT8189_PLL_FMAX, \ + .fmin = MT8189_PLL_FMIN, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + .pcwbits = _pcwbits, \ + .pcwibits = 8, \ + } + +static const struct mtk_pll_data apmixed_plls[] = { + PLL(CLK_APMIXED_ARMPLL_LL, ARMPLL_LL_CON0, 0, ARMPLL_LL_CON1, 24, ARMPLL_LL_CON1, 0, 22), + PLL(CLK_APMIXED_ARMPLL_BL, ARMPLL_BL_CON0, 0, ARMPLL_BL_CON1, 24, ARMPLL_BL_CON1, 0, 22), + PLL(CLK_APMIXED_CCIPLL, CCIPLL_CON0, 0, CCIPLL_CON1, 24, CCIPLL_CON1, 0, 22), + PLL(CLK_APMIXED_MAINPLL, MAINPLL_CON0, 0, MAINPLL_CON1, 24, MAINPLL_CON1, 0, 22), + PLL(CLK_APMIXED_UNIVPLL, UNIVPLL_CON0, 0, UNIVPLL_CON1, 24, UNIVPLL_CON1, 0, 22), + PLL(CLK_APMIXED_MMPLL, MMPLL_CON0, 0, MMPLL_CON1, 24, MMPLL_CON1, 0, 22), + PLL(CLK_APMIXED_MFGPLL, MFGPLL_CON0, 0, MFGPLL_CON1, 24, MFGPLL_CON1, 0, 22), + PLL(CLK_APMIXED_APLL1, APLL1_CON0, 0, APLL1_CON1, 24, APLL1_CON2, 0, 32), + PLL(CLK_APMIXED_APLL2, APLL2_CON0, 0, APLL2_CON1, 24, APLL2_CON2, 0, 32), + PLL(CLK_APMIXED_EMIPLL, EMIPLL_CON0, 0, EMIPLL_CON1, 24, EMIPLL_CON1, 0, 22), + PLL(CLK_APMIXED_APUPLL2, APUPLL2_CON0, 0, APUPLL2_CON1, 24, APUPLL2_CON1, 0, 22), + PLL(CLK_APMIXED_APUPLL, APUPLL_CON0, 0, APUPLL_CON1, 24, APUPLL_CON1, 0, 22), + PLL(CLK_APMIXED_TVDPLL1, TVDPLL1_CON0, 0, TVDPLL1_CON1, 24, TVDPLL1_CON1, 0, 22), + PLL(CLK_APMIXED_TVDPLL2, TVDPLL2_CON0, 0, TVDPLL2_CON1, 24, TVDPLL2_CON1, 0, 22), + PLL(CLK_APMIXED_ETHPLL, ETHPLL_CON0, 0, ETHPLL_CON1, 24, ETHPLL_CON1, 0, 22), + PLL(CLK_APMIXED_MSDCPLL, MSDCPLL_CON0, 0, MSDCPLL_CON1, 24, MSDCPLL_CON1, 0, 22), + PLL(CLK_APMIXED_UFSPLL, UFSPLL_CON0, 0, UFSPLL_CON1, 24, UFSPLL_CON1, 0, 22), +}; + +#define FACTOR0(id, parent, mult, div) \ + FACTOR(id, parent, mult, div, CLK_PARENT_APMIXED) + +#define FACTOR1(id, parent, mult, div) \ + FACTOR(id, parent, mult, div, CLK_PARENT_EXT) + +static const struct mtk_fixed_factor top_fixed_divs[] = { + FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3), + FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4), + FACTOR0(CLK_TOP_MAINPLL_D4_D2, CLK_APMIXED_MAINPLL, 1, 8), + FACTOR0(CLK_TOP_MAINPLL_D4_D4, CLK_APMIXED_MAINPLL, 1, 16), + FACTOR0(CLK_TOP_MAINPLL_D4_D8, CLK_APMIXED_MAINPLL, 43, 1375), + FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5), + FACTOR0(CLK_TOP_MAINPLL_D5_D2, CLK_APMIXED_MAINPLL, 1, 10), + FACTOR0(CLK_TOP_MAINPLL_D5_D4, CLK_APMIXED_MAINPLL, 1, 20), + FACTOR0(CLK_TOP_MAINPLL_D5_D8, CLK_APMIXED_MAINPLL, 1, 40), + FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6), + FACTOR0(CLK_TOP_MAINPLL_D6_D2, CLK_APMIXED_MAINPLL, 1, 12), + FACTOR0(CLK_TOP_MAINPLL_D6_D4, CLK_APMIXED_MAINPLL, 1, 24), + FACTOR0(CLK_TOP_MAINPLL_D6_D8, CLK_APMIXED_MAINPLL, 1, 48), + FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7), + FACTOR0(CLK_TOP_MAINPLL_D7_D2, CLK_APMIXED_MAINPLL, 1, 14), + FACTOR0(CLK_TOP_MAINPLL_D7_D4, CLK_APMIXED_MAINPLL, 1, 28), + FACTOR0(CLK_TOP_MAINPLL_D7_D8, CLK_APMIXED_MAINPLL, 1, 56), + FACTOR0(CLK_TOP_MAINPLL_D9, CLK_APMIXED_MAINPLL, 1, 9), + FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2), + FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3), + FACTOR0(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4), + FACTOR0(CLK_TOP_UNIVPLL_D4_D2, CLK_APMIXED_UNIVPLL, 1, 8), + FACTOR0(CLK_TOP_UNIVPLL_D4_D4, CLK_APMIXED_UNIVPLL, 1, 16), + FACTOR0(CLK_TOP_UNIVPLL_D4_D8, CLK_APMIXED_UNIVPLL, 1, 32), + FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5), + FACTOR0(CLK_TOP_UNIVPLL_D5_D2, CLK_APMIXED_UNIVPLL, 1, 10), + FACTOR0(CLK_TOP_UNIVPLL_D5_D4, CLK_APMIXED_UNIVPLL, 1, 20), + FACTOR0(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6), + FACTOR0(CLK_TOP_UNIVPLL_D6_D2, CLK_APMIXED_UNIVPLL, 1, 12), + FACTOR0(CLK_TOP_UNIVPLL_D6_D4, CLK_APMIXED_UNIVPLL, 1, 24), + FACTOR0(CLK_TOP_UNIVPLL_D6_D8, CLK_APMIXED_UNIVPLL, 1, 48), + FACTOR0(CLK_TOP_UNIVPLL_D6_D16, CLK_APMIXED_UNIVPLL, 1, 96), + FACTOR0(CLK_TOP_UNIVPLL_D7, CLK_APMIXED_UNIVPLL, 1, 7), + FACTOR0(CLK_TOP_UNIVPLL_D7_D2, CLK_APMIXED_UNIVPLL, 1, 14), + FACTOR0(CLK_TOP_UNIVPLL_D7_D3, CLK_APMIXED_UNIVPLL, 1, 21), + FACTOR0(CLK_TOP_LVDSTX_DG_CTS, CLK_APMIXED_UNIVPLL, 1, 21), + FACTOR0(CLK_TOP_UNIVPLL_192M, CLK_APMIXED_UNIVPLL, 1, 13), + FACTOR0(CLK_TOP_UNIVPLL_192M_D2, CLK_APMIXED_UNIVPLL, 1, 26), + FACTOR0(CLK_TOP_UNIVPLL_192M_D4, CLK_APMIXED_UNIVPLL, 1, 52), + FACTOR0(CLK_TOP_UNIVPLL_192M_D8, CLK_APMIXED_UNIVPLL, 1, 104), + FACTOR0(CLK_TOP_UNIVPLL_192M_D10, CLK_APMIXED_UNIVPLL, 1, 130), + FACTOR0(CLK_TOP_UNIVPLL_192M_D16, CLK_APMIXED_UNIVPLL, 1, 208), + FACTOR0(CLK_TOP_UNIVPLL_192M_D32, CLK_APMIXED_UNIVPLL, 1, 416), + FACTOR0(CLK_TOP_APLL1_D2, CLK_APMIXED_APLL1, 1, 2), + FACTOR0(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4), + FACTOR0(CLK_TOP_APLL1_D8, CLK_APMIXED_APLL1, 1, 8), + FACTOR0(CLK_TOP_APLL1_D3, CLK_APMIXED_APLL1, 1, 3), + FACTOR0(CLK_TOP_APLL2_D2, CLK_APMIXED_APLL2, 1, 2), + FACTOR0(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4), + FACTOR0(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8), + FACTOR0(CLK_TOP_APLL2_D3, CLK_APMIXED_APLL2, 1, 3), + FACTOR0(CLK_TOP_MMPLL_D4, CLK_APMIXED_MMPLL, 1, 4), + FACTOR0(CLK_TOP_MMPLL_D4_D2, CLK_APMIXED_MMPLL, 1, 8), + FACTOR0(CLK_TOP_MMPLL_D4_D4, CLK_APMIXED_MMPLL, 1, 16), + FACTOR0(CLK_TOP_VPLL_DPIX, CLK_APMIXED_MMPLL, 1, 16), + FACTOR0(CLK_TOP_MMPLL_D5, CLK_APMIXED_MMPLL, 1, 5), + FACTOR0(CLK_TOP_MMPLL_D5_D2, CLK_APMIXED_MMPLL, 1, 10), + FACTOR0(CLK_TOP_MMPLL_D5_D4, CLK_APMIXED_MMPLL, 1, 20), + FACTOR0(CLK_TOP_MMPLL_D6, CLK_APMIXED_MMPLL, 1, 6), + FACTOR0(CLK_TOP_MMPLL_D6_D2, CLK_APMIXED_MMPLL, 1, 12), + FACTOR0(CLK_TOP_MMPLL_D7, CLK_APMIXED_MMPLL, 1, 7), + FACTOR0(CLK_TOP_MMPLL_D9, CLK_APMIXED_MMPLL, 1, 9), + FACTOR0(CLK_TOP_TVDPLL1_D2, CLK_APMIXED_TVDPLL1, 1, 2), + FACTOR0(CLK_TOP_TVDPLL1_D4, CLK_APMIXED_TVDPLL1, 1, 4), + FACTOR0(CLK_TOP_TVDPLL1_D8, CLK_APMIXED_TVDPLL1, 1, 8), + FACTOR0(CLK_TOP_TVDPLL1_D16, CLK_APMIXED_TVDPLL1, 92, 1473), + FACTOR0(CLK_TOP_TVDPLL2_D2, CLK_APMIXED_TVDPLL2, 1, 2), + FACTOR0(CLK_TOP_TVDPLL2_D4, CLK_APMIXED_TVDPLL2, 1, 4), + FACTOR0(CLK_TOP_TVDPLL2_D8, CLK_APMIXED_TVDPLL2, 1, 8), + FACTOR0(CLK_TOP_TVDPLL2_D16, CLK_APMIXED_TVDPLL2, 92, 1473), + FACTOR0(CLK_TOP_ETHPLL_D2, CLK_APMIXED_ETHPLL, 1, 2), + FACTOR0(CLK_TOP_ETHPLL_D8, CLK_APMIXED_ETHPLL, 1, 8), + FACTOR0(CLK_TOP_ETHPLL_D10, CLK_APMIXED_ETHPLL, 1, 10), + FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2), + FACTOR1(CLK_TOP_VOWPLL, CLK_PAD_CLK26M, 1, 1), + FACTOR0(CLK_TOP_UFSPLL_D2, CLK_APMIXED_UFSPLL, 1, 2), + FACTOR1(CLK_TOP_F26M_CK_D2, CLK_PAD_CLK26M, 1, 2), + FACTOR1(CLK_TOP_OSC_D2, CLK_PAD_ULPOSC, 1, 2), + FACTOR1(CLK_TOP_OSC_D4, CLK_PAD_ULPOSC, 1, 4), + FACTOR1(CLK_TOP_OSC_D8, CLK_PAD_ULPOSC, 1, 8), + FACTOR1(CLK_TOP_OSC_D16, CLK_PAD_ULPOSC, 61, 973), + FACTOR1(CLK_TOP_OSC_D3, CLK_PAD_ULPOSC, 1, 3), + FACTOR1(CLK_TOP_OSC_D7, CLK_PAD_ULPOSC, 1, 7), + FACTOR1(CLK_TOP_OSC_D10, CLK_PAD_ULPOSC, 1, 10), + FACTOR1(CLK_TOP_OSC_D20, CLK_PAD_ULPOSC, 1, 20), +}; + +static const struct mtk_parent axi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_OSC_D4), +}; + +static const struct mtk_parent axi_peri_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_OSC_D4), +}; + +static const struct mtk_parent axi_u_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), + TOP_PARENT(CLK_TOP_OSC_D8), +}; + +static const struct mtk_parent bus_aximem_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), +}; + +static const struct mtk_parent disp0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + APMIXED_PARENT(CLK_APMIXED_TVDPLL1), + APMIXED_PARENT(CLK_APMIXED_TVDPLL2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), +}; + +static const struct mtk_parent mminfra_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + APMIXED_PARENT(CLK_APMIXED_EMIPLL), +}; + +static const struct mtk_parent uart_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), +}; + +static const struct mtk_parent spi0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_192M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent spi1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_192M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent spi2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_192M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent spi3_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_192M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent spi4_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_192M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent spi5_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_192M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent msdc_macro_0p_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_MSDCPLL), + TOP_PARENT(CLK_TOP_MMPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), +}; + +static const struct mtk_parent msdc5hclk_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), +}; + +static const struct mtk_parent msdc50_0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_MSDCPLL), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), +}; + +static const struct mtk_parent aes_msdcfde_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + APMIXED_PARENT(CLK_APMIXED_MSDCPLL), +}; + +static const struct mtk_parent msdc_macro_1p_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_MSDCPLL), + TOP_PARENT(CLK_TOP_MMPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), +}; + +static const struct mtk_parent msdc30_1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), +}; + +static const struct mtk_parent msdc30_1_h_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D4), +}; + +static const struct mtk_parent msdc_macro_2p_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_MSDCPLL), + TOP_PARENT(CLK_TOP_MMPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), +}; + +static const struct mtk_parent msdc30_2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), +}; + +static const struct mtk_parent msdc30_2_h_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D4), +}; + +static const struct mtk_parent aud_intbus_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), +}; + +static const struct mtk_parent atb_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), +}; + +static const struct mtk_parent disp_pwm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_OSC_D4), + TOP_PARENT(CLK_TOP_OSC_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), +}; + +static const struct mtk_parent usb_p0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent ssusb_xhci_p0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent usb_p1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent ssusb_xhci_p1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent usb_p2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent ssusb_xhci_p2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent usb_p3_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent ssusb_xhci_p3_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent usb_p4_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent ssusb_xhci_p4_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent i2c_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), +}; + +static const struct mtk_parent seninf_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), +}; + +static const struct mtk_parent seninf1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), +}; + +static const struct mtk_parent aud_engen1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_D2), + TOP_PARENT(CLK_TOP_APLL1_D4), + TOP_PARENT(CLK_TOP_APLL1_D8), +}; + +static const struct mtk_parent aud_engen2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_D2), + TOP_PARENT(CLK_TOP_APLL2_D4), + TOP_PARENT(CLK_TOP_APLL2_D8), +}; + +static const struct mtk_parent aes_ufsfde_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), +}; + +static const struct mtk_parent ufs_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), +}; + +static const struct mtk_parent ufs_mbist_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UFSPLL_D2), +}; + +static const struct mtk_parent aud_1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_APLL1), +}; + +static const struct mtk_parent aud_2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_APLL2), +}; + +static const struct mtk_parent venc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MMPLL_D9), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5), +}; + +static const struct mtk_parent vdec_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D5_D2), +}; + +static const struct mtk_parent pwm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), +}; + +static const struct mtk_parent audio_h_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D7_D2), + APMIXED_PARENT(CLK_APMIXED_APLL1), + APMIXED_PARENT(CLK_APMIXED_APLL2), +}; + +static const struct mtk_parent mcupm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), +}; + +static const struct mtk_parent mem_sub_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), +}; + +static const struct mtk_parent mem_sub_peri_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D4), +}; + +static const struct mtk_parent mem_sub_u_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D4), +}; + +static const struct mtk_parent emi_n_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D9), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + APMIXED_PARENT(CLK_APMIXED_EMIPLL), +}; + +static const struct mtk_parent dsi_occ_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), +}; + +static const struct mtk_parent ap2conn_host_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), +}; + +static const struct mtk_parent img1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_MMPLL_D5_D2), +}; + +static const struct mtk_parent ipe_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_MMPLL_D5_D2), +}; + +static const struct mtk_parent cam_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D9), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_OSC_D2), +}; + +static const struct mtk_parent camtm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent dsp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D4), + TOP_PARENT(CLK_TOP_OSC_D3), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), +}; + +static const struct mtk_parent sr_pka_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), +}; + +static const struct mtk_parent dxcc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), +}; + +static const struct mtk_parent mfg_ref_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), +}; + +static const struct mtk_parent mdp0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + APMIXED_PARENT(CLK_APMIXED_TVDPLL1), + APMIXED_PARENT(CLK_APMIXED_TVDPLL2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), +}; + +static const struct mtk_parent dp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL1_D16), + TOP_PARENT(CLK_TOP_TVDPLL1_D8), + TOP_PARENT(CLK_TOP_TVDPLL1_D4), + TOP_PARENT(CLK_TOP_TVDPLL1_D2), +}; + +static const struct mtk_parent edp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL2_D16), + TOP_PARENT(CLK_TOP_TVDPLL2_D8), + TOP_PARENT(CLK_TOP_TVDPLL2_D4), + TOP_PARENT(CLK_TOP_TVDPLL2_D2), + TOP_PARENT(CLK_TOP_APLL1_D4), + TOP_PARENT(CLK_TOP_APLL2_D4), +}; + +static const struct mtk_parent edp_favt_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL2_D16), + TOP_PARENT(CLK_TOP_TVDPLL2_D8), + TOP_PARENT(CLK_TOP_TVDPLL2_D4), + TOP_PARENT(CLK_TOP_TVDPLL2_D2), + TOP_PARENT(CLK_TOP_APLL1_D4), + TOP_PARENT(CLK_TOP_APLL2_D4), +}; + +static const struct mtk_parent snps_eth_250m_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D2), +}; + +static const struct mtk_parent snps_eth_62p4m_ptp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D8), + TOP_PARENT(CLK_TOP_APLL1_D3), + TOP_PARENT(CLK_TOP_APLL2_D3), +}; + +static const struct mtk_parent snps_eth_50m_rmii_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D10), +}; + +static const struct mtk_parent sflash_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D7_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), +}; + +static const struct mtk_parent gcpu_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), +}; + +static const struct mtk_parent pcie_mac_tl_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), +}; + +static const struct mtk_parent vdstx_dg_cts_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_LVDSTX_DG_CTS), + TOP_PARENT(CLK_TOP_UNIVPLL_D7_D3), +}; + +static const struct mtk_parent pll_dpix_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_VPLL_DPIX), + TOP_PARENT(CLK_TOP_MMPLL_D4_D4), +}; + +static const struct mtk_parent ecc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), +}; + +#define MUX_CLR_SET_UPD(_id, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ + _shift, _width, _upd_ofs, _upd) \ + MUX_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs, \ + _mux_clr_ofs, _shift, _width, -1, _upd_ofs, \ + _upd, CLK_MUX_SETCLR_UPD) + +#define MUX_GATE_CLR_SET_UPD(_id, _parents, _mux_ofs, _mux_set_ofs, \ + _mux_clr_ofs, _shift, _width, _gate, _upd_ofs, \ + _upd) \ + MUX_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs, \ + _mux_clr_ofs, _shift, _width, _gate, \ + _upd_ofs, _upd, CLK_MUX_SETCLR_UPD) + +const struct mtk_composite top_muxes[] = { + /* CLK_CFG_0 */ + MUX_CLR_SET_UPD(CLK_TOP_AXI_SEL, axi_parents, CLK_CFG_0, CLK_CFG_0_SET, + CLK_CFG_0_CLR, 0, 3, CLK_CFG_UPDATE, TOP_MUX_AXI_SHIFT), + MUX_CLR_SET_UPD(CLK_TOP_AXI_PERI_SEL, axi_peri_parents, CLK_CFG_0, + CLK_CFG_0_SET, CLK_CFG_0_CLR, 8, 2, CLK_CFG_UPDATE, + TOP_MUX_AXI_PERI_SHIFT), + MUX_CLR_SET_UPD(CLK_TOP_AXI_U_SEL, axi_u_parents, CLK_CFG_0, + CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 2, CLK_CFG_UPDATE, + TOP_MUX_AXI_UFS_SHIFT), + MUX_CLR_SET_UPD(CLK_TOP_BUS_AXIMEM_SEL, bus_aximem_parents, CLK_CFG_0, + CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, CLK_CFG_UPDATE, + TOP_MUX_BUS_AXIMEM_SHIFT), + /* CLK_CFG_1 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP0_SEL, disp0_parents, CLK_CFG_1, + CLK_CFG_1_SET, CLK_CFG_1_CLR, 0, 4, 7, + CLK_CFG_UPDATE, TOP_MUX_DISP0_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MMINFRA_SEL, mminfra_parents, CLK_CFG_1, + CLK_CFG_1_SET, CLK_CFG_1_CLR, 8, 4, 15, + CLK_CFG_UPDATE, TOP_MUX_MMINFRA_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, uart_parents, CLK_CFG_1, + CLK_CFG_1_SET, CLK_CFG_1_CLR, 16, 1, 23, + CLK_CFG_UPDATE, TOP_MUX_UART_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI0_SEL, spi0_parents, CLK_CFG_1, + CLK_CFG_1_SET, CLK_CFG_1_CLR, 24, 3, 31, + CLK_CFG_UPDATE, TOP_MUX_SPI0_SHIFT), + /* CLK_CFG_2 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI1_SEL, spi1_parents, CLK_CFG_2, + CLK_CFG_2_SET, CLK_CFG_2_CLR, 0, 3, 7, + CLK_CFG_UPDATE, TOP_MUX_SPI1_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI2_SEL, spi2_parents, CLK_CFG_2, + CLK_CFG_2_SET, CLK_CFG_2_CLR, 8, 3, 15, + CLK_CFG_UPDATE, TOP_MUX_SPI2_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI3_SEL, spi3_parents, CLK_CFG_2, + CLK_CFG_2_SET, CLK_CFG_2_CLR, 16, 3, 23, + CLK_CFG_UPDATE, TOP_MUX_SPI3_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI4_SEL, spi4_parents, CLK_CFG_2, + CLK_CFG_2_SET, CLK_CFG_2_CLR, 24, 3, 31, + CLK_CFG_UPDATE, TOP_MUX_SPI4_SHIFT), + /* CLK_CFG_3 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI5_SEL, spi5_parents, CLK_CFG_3, + CLK_CFG_3_SET, CLK_CFG_3_CLR, 0, 3, 7, + CLK_CFG_UPDATE, TOP_MUX_SPI5_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC_MACRO_0P_SEL, msdc_macro_0p_parents, + CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 8, 2, 15, + CLK_CFG_UPDATE, TOP_MUX_MSDC_MACRO_0P_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, msdc5hclk_parents, + CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 16, 2, 23, + CLK_CFG_UPDATE, TOP_MUX_MSDC50_0_HCLK_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents, CLK_CFG_3, + CLK_CFG_3_SET, CLK_CFG_3_CLR, 24, 3, 31, + CLK_CFG_UPDATE, TOP_MUX_MSDC50_0_SHIFT), + /* CLK_CFG_4 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE_SEL, aes_msdcfde_parents, + CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 0, 3, 7, + CLK_CFG_UPDATE, TOP_MUX_AES_MSDCFDE_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC_MACRO_1P_SEL, msdc_macro_1p_parents, + CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 8, 2, 15, + CLK_CFG_UPDATE, TOP_MUX_MSDC_MACRO_1P_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, CLK_CFG_4, + CLK_CFG_4_SET, CLK_CFG_4_CLR, 16, 3, 23, + CLK_CFG_UPDATE, TOP_MUX_MSDC30_1_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_HCLK_SEL, msdc30_1_h_parents, + CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 24, 2, 31, + CLK_CFG_UPDATE, TOP_MUX_MSDC30_1_HCLK_SHIFT), + /* CLK_CFG_5 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC_MACRO_2P_SEL, msdc_macro_2p_parents, + CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 0, 2, 7, + CLK_CFG_UPDATE, TOP_MUX_MSDC_MACRO_2P_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL, msdc30_2_parents, CLK_CFG_5, + CLK_CFG_5_SET, CLK_CFG_5_CLR, 8, 3, 15, + CLK_CFG_UPDATE, TOP_MUX_MSDC30_2_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_HCLK_SEL, msdc30_2_h_parents, + CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 16, 2, 23, + CLK_CFG_UPDATE, TOP_MUX_MSDC30_2_HCLK_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, + CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 24, 2, 31, + CLK_CFG_UPDATE, TOP_MUX_AUD_INTBUS_SHIFT), + /* CLK_CFG_6 */ + MUX_CLR_SET_UPD(CLK_TOP_ATB_SEL, atb_parents, CLK_CFG_6, CLK_CFG_6_SET, + CLK_CFG_6_CLR, 0, 2, CLK_CFG_UPDATE, TOP_MUX_ATB_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, disp_pwm_parents, CLK_CFG_6, + CLK_CFG_6_SET, CLK_CFG_6_CLR, 8, 3, 15, + CLK_CFG_UPDATE, TOP_MUX_DISP_PWM_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P0_SEL, usb_p0_parents, CLK_CFG_6, + CLK_CFG_6_SET, CLK_CFG_6_CLR, 16, 2, 23, + CLK_CFG_UPDATE, TOP_MUX_USB_TOP_P0_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P0_SEL, ssusb_xhci_p0_parents, + CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 24, 2, 31, + CLK_CFG_UPDATE, TOP_MUX_SSUSB_XHCI_P0_SHIFT), + /* CLK_CFG_7 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P1_SEL, usb_p1_parents, CLK_CFG_7, + CLK_CFG_7_SET, CLK_CFG_7_CLR, 0, 2, 7, + CLK_CFG_UPDATE, TOP_MUX_USB_TOP_P1_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, ssusb_xhci_p1_parents, + CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 8, 2, 15, + CLK_CFG_UPDATE, TOP_MUX_SSUSB_XHCI_P1_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P2_SEL, usb_p2_parents, CLK_CFG_7, + CLK_CFG_7_SET, CLK_CFG_7_CLR, 16, 2, 23, + CLK_CFG_UPDATE, TOP_MUX_USB_TOP_P2_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P2_SEL, ssusb_xhci_p2_parents, + CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 24, 2, 31, + CLK_CFG_UPDATE1, TOP_MUX_SSUSB_XHCI_P2_SHIFT), + /* CLK_CFG_8 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P3_SEL, usb_p3_parents, CLK_CFG_8, + CLK_CFG_8_SET, CLK_CFG_8_CLR, 0, 2, 7, + CLK_CFG_UPDATE1, TOP_MUX_USB_TOP_P3_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P3_SEL, ssusb_xhci_p3_parents, + CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR, 8, 2, 15, + CLK_CFG_UPDATE1, TOP_MUX_SSUSB_XHCI_P3_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P4_SEL, usb_p4_parents, CLK_CFG_8, + CLK_CFG_8_SET, CLK_CFG_8_CLR, 16, 2, 23, + CLK_CFG_UPDATE1, TOP_MUX_USB_TOP_P4_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P4_SEL, ssusb_xhci_p4_parents, + CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR, 24, 2, 31, + CLK_CFG_UPDATE1, TOP_MUX_SSUSB_XHCI_P4_SHIFT), + /* CLK_CFG_9 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, i2c_parents, CLK_CFG_9, + CLK_CFG_9_SET, CLK_CFG_9_CLR, 0, 2, 7, + CLK_CFG_UPDATE1, TOP_MUX_I2C_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, seninf_parents, + CLK_CFG_9, CLK_CFG_9_SET, CLK_CFG_9_CLR, 8, 3, 15, + CLK_CFG_UPDATE1, TOP_MUX_SENINF_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1_SEL, seninf1_parents, CLK_CFG_9, + CLK_CFG_9_SET, CLK_CFG_9_CLR, 16, 3, 23, + CLK_CFG_UPDATE1, TOP_MUX_SENINF1_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, + CLK_CFG_9, CLK_CFG_9_SET, CLK_CFG_9_CLR, 24, 2, 31, + CLK_CFG_UPDATE1, TOP_MUX_AUD_ENGEN1_SHIFT), + /* CLK_CFG_10 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, + CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR, 0, 2, 7, + CLK_CFG_UPDATE1, TOP_MUX_AUD_ENGEN2_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE_SEL, aes_ufsfde_parents, + CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR, 8, 3, 15, + CLK_CFG_UPDATE1, TOP_MUX_AES_UFSFDE_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_U_SEL, ufs_parents, CLK_CFG_10, + CLK_CFG_10_SET, CLK_CFG_10_CLR, 16, 3, 23, + CLK_CFG_UPDATE1, TOP_MUX_UFS_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_U_MBIST_SEL, ufs_mbist_parents, CLK_CFG_10, + CLK_CFG_10_SET, CLK_CFG_10_CLR, 24, 2, 31, + CLK_CFG_UPDATE1, TOP_MUX_UFS_MBIST_SHIFT), + /* CLK_CFG_11 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, aud_1_parents, CLK_CFG_11, + CLK_CFG_11_SET, CLK_CFG_11_CLR, 0, 1, 7, + CLK_CFG_UPDATE1, TOP_MUX_AUD_1_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, aud_2_parents, CLK_CFG_11, + CLK_CFG_11_SET, CLK_CFG_11_CLR, 8, 1, 15, + CLK_CFG_UPDATE1, TOP_MUX_AUD_2_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, venc_parents, CLK_CFG_11, + CLK_CFG_11_SET, CLK_CFG_11_CLR, 16, 4, 23, + CLK_CFG_UPDATE1, TOP_MUX_VENC_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, vdec_parents, CLK_CFG_11, + CLK_CFG_11_SET, CLK_CFG_11_CLR, 24, 4, 31, + CLK_CFG_UPDATE1, TOP_MUX_VDEC_SHIFT), + /* CLK_CFG_12 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, pwm_parents, CLK_CFG_12, + CLK_CFG_12_SET, CLK_CFG_12_CLR, 0, 1, 7, + CLK_CFG_UPDATE1, TOP_MUX_PWM_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H_SEL, audio_h_parents, CLK_CFG_12, + CLK_CFG_12_SET, CLK_CFG_12_CLR, 8, 2, 15, + CLK_CFG_UPDATE1, TOP_MUX_AUDIO_H_SHIFT), + MUX_CLR_SET_UPD(CLK_TOP_MCUPM_SEL, mcupm_parents, CLK_CFG_12, + CLK_CFG_12_SET, CLK_CFG_12_CLR, 16, 2, CLK_CFG_UPDATE1, + TOP_MUX_MCUPM_SHIFT), + MUX_CLR_SET_UPD(CLK_TOP_MEM_SUB_SEL, mem_sub_parents, CLK_CFG_12, + CLK_CFG_12_SET, CLK_CFG_12_CLR, 24, 4, CLK_CFG_UPDATE1, + TOP_MUX_MEM_SUB_SHIFT), + /* CLK_CFG_13 */ + MUX_CLR_SET_UPD(CLK_TOP_MEM_SUB_PERI_SEL, mem_sub_peri_parents, CLK_CFG_13, + CLK_CFG_13_SET, CLK_CFG_13_CLR, 0, 3, CLK_CFG_UPDATE1, + TOP_MUX_MEM_SUB_PERI_SHIFT), + MUX_CLR_SET_UPD(CLK_TOP_MEM_SUB_U_SEL, mem_sub_u_parents, CLK_CFG_13, + CLK_CFG_13_SET, CLK_CFG_13_CLR, 8, 3, CLK_CFG_UPDATE1, + TOP_MUX_MEM_SUB_UFS_SHIFT), + MUX_CLR_SET_UPD(CLK_TOP_EMI_N_SEL, emi_n_parents, CLK_CFG_13, + CLK_CFG_13_SET, CLK_CFG_13_CLR, 16, 3, CLK_CFG_UPDATE1, + TOP_MUX_EMI_N_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC_SEL, dsi_occ_parents, CLK_CFG_13, + CLK_CFG_13_SET, CLK_CFG_13_CLR, 24, 2, 31, + CLK_CFG_UPDATE1, TOP_MUX_DSI_OCC_SHIFT), + /* CLK_CFG_14 */ + MUX_CLR_SET_UPD(CLK_TOP_AP2CONN_HOST_SEL, ap2conn_host_parents, CLK_CFG_14, + CLK_CFG_14_SET, CLK_CFG_14_CLR, 0, 1, CLK_CFG_UPDATE1, + TOP_MUX_AP2CONN_HOST_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1_SEL, img1_parents, CLK_CFG_14, + CLK_CFG_14_SET, CLK_CFG_14_CLR, 8, 4, 15, + CLK_CFG_UPDATE1, TOP_MUX_IMG1_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, ipe_parents, CLK_CFG_14, + CLK_CFG_14_SET, CLK_CFG_14_CLR, 16, 4, 23, + CLK_CFG_UPDATE1, TOP_MUX_IPE_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL, cam_parents, CLK_CFG_14, + CLK_CFG_14_SET, CLK_CFG_14_CLR, 24, 4, 31, + CLK_CFG_UPDATE1, TOP_MUX_CAM_SHIFT), + /* CLK_CFG_15 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, camtm_parents, CLK_CFG_15, + CLK_CFG_15_SET, CLK_CFG_15_CLR, 0, 2, 7, + CLK_CFG_UPDATE1, TOP_MUX_CAMTM_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, dsp_parents, CLK_CFG_15, + CLK_CFG_15_SET, CLK_CFG_15_CLR, 8, 3, 15, + CLK_CFG_UPDATE1, TOP_MUX_DSP_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SR_PKA_SEL, sr_pka_parents, CLK_CFG_15, + CLK_CFG_15_SET, CLK_CFG_15_CLR, 16, 3, 23, + CLK_CFG_UPDATE2, TOP_MUX_SR_PKA_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, dxcc_parents, CLK_CFG_15, + CLK_CFG_15_SET, CLK_CFG_15_CLR, 24, 2, 31, + CLK_CFG_UPDATE2, TOP_MUX_DXCC_SHIFT), + /* CLK_CFG_16 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, mfg_ref_parents, CLK_CFG_16, + CLK_CFG_16_SET, CLK_CFG_16_CLR, 0, 2, 7, + CLK_CFG_UPDATE2, TOP_MUX_MFG_REF_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP0_SEL, mdp0_parents, CLK_CFG_16, + CLK_CFG_16_SET, CLK_CFG_16_CLR, 8, 4, 15, + CLK_CFG_UPDATE2, TOP_MUX_MDP0_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DP_SEL, dp_parents, CLK_CFG_16, + CLK_CFG_16_SET, CLK_CFG_16_CLR, 16, 3, 23, + CLK_CFG_UPDATE2, TOP_MUX_DP_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP_SEL, edp_parents, CLK_CFG_16, + CLK_CFG_16_SET, CLK_CFG_16_CLR, 24, 3, 31, + CLK_CFG_UPDATE2, TOP_MUX_EDP_SHIFT), + /* CLK_CFG_17 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP_FAVT_SEL, edp_favt_parents, CLK_CFG_17, + CLK_CFG_17_SET, CLK_CFG_17_CLR, 0, 3, 7, + CLK_CFG_UPDATE2, TOP_MUX_EDP_FAVT_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_250M_SEL, snps_eth_250m_parents, CLK_CFG_17, + CLK_CFG_17_SET, CLK_CFG_17_CLR, 8, 1, 15, + CLK_CFG_UPDATE2, TOP_MUX_SNPS_ETH_250M_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_62P4M_PTP_SEL, + snps_eth_62p4m_ptp_parents, CLK_CFG_17, + CLK_CFG_17_SET, CLK_CFG_17_CLR, 16, 2, 23, + CLK_CFG_UPDATE2, TOP_MUX_SNPS_ETH_62P4M_PTP_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_50M_RMII_SEL, + snps_eth_50m_rmii_parents, CLK_CFG_17, + CLK_CFG_17_SET, CLK_CFG_17_CLR, 24, 1, 31, + CLK_CFG_UPDATE2, TOP_MUX_SNPS_ETH_50M_RMII_SHIFT), + /* CLK_CFG_18 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_SFLASH_SEL, sflash_parents, CLK_CFG_18, + CLK_CFG_18_SET, CLK_CFG_18_CLR, 0, 3, 7, + CLK_CFG_UPDATE2, TOP_MUX_SFLASH_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_SEL, gcpu_parents, CLK_CFG_18, + CLK_CFG_18_SET, CLK_CFG_18_CLR, 8, 3, 15, + CLK_CFG_UPDATE2, TOP_MUX_GCPU_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MAC_TL_SEL, pcie_mac_tl_parents, CLK_CFG_18, + CLK_CFG_18_SET, CLK_CFG_18_CLR, 16, 2, 23, + CLK_CFG_UPDATE2, TOP_MUX_PCIE_MAC_TL_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_VDSTX_DG_CTS_SEL, vdstx_dg_cts_parents, CLK_CFG_18, + CLK_CFG_18_SET, CLK_CFG_18_CLR, 24, 2, 31, + CLK_CFG_UPDATE2, TOP_MUX_VDSTX_CLKDIG_CTS_SHIFT), + /* CLK_CFG_19 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_PLL_DPIX_SEL, pll_dpix_parents, CLK_CFG_19, + CLK_CFG_19_SET, CLK_CFG_19_CLR, 0, 2, 7, + CLK_CFG_UPDATE2, TOP_MUX_PLL_DPIX_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC_SEL, ecc_parents, CLK_CFG_19, + CLK_CFG_19_SET, CLK_CFG_19_CLR, 8, 3, 15, + CLK_CFG_UPDATE2, TOP_MUX_ECC_SHIFT), +}; + +static const struct mtk_gate_regs top_cg_regs = { + .set_ofs = 0x514, + .clr_ofs = 0x518, + .sta_ofs = 0x510, +}; + +#define GATE_TOP(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &top_cg_regs, _shift, \ + CLK_GATE_NO_SETCLR_INV | CLK_PARENT_EXT) + +static const struct mtk_gate top_gates[] = { + GATE_TOP(CLK_TOP_USB2_PHY_RF_P0_EN, CLK_PAD_CLK26M, 7), + GATE_TOP(CLK_TOP_USB2_PHY_RF_P1_EN, CLK_PAD_CLK26M, 10), + GATE_TOP(CLK_TOP_USB2_PHY_RF_P2_EN, CLK_PAD_CLK26M, 11), + GATE_TOP(CLK_TOP_USB2_PHY_RF_P3_EN, CLK_PAD_CLK26M, 12), + GATE_TOP(CLK_TOP_USB2_PHY_RF_P4_EN, CLK_PAD_CLK26M, 13), +}; + +static const struct mtk_gate_regs perao0_cg_regs = { + .set_ofs = 0x24, + .clr_ofs = 0x28, + .sta_ofs = 0x10, +}; + +static const struct mtk_gate_regs perao1_cg_regs = { + .set_ofs = 0x2C, + .clr_ofs = 0x30, + .sta_ofs = 0x14, +}; + +static const struct mtk_gate_regs perao2_cg_regs = { + .set_ofs = 0x34, + .clr_ofs = 0x38, + .sta_ofs = 0x18, +}; + +#define GATE_PERAO0(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &perao0_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +#define GATE_PERAO0P(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &perao0_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_EXT) + +#define GATE_PERAO1(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &perao1_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +#define GATE_PERAO1P(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &perao1_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_EXT) + +#define GATE_PERAO2(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &perao2_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +#define GATE_PERAO2P(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &perao2_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_EXT) + +static const struct mtk_gate perao_clks[] = { + /* PERAO0 */ + GATE_PERAO0(CLK_PERAO_UART0, CLK_TOP_UART_SEL, 0), + GATE_PERAO0(CLK_PERAO_UART1, CLK_TOP_UART_SEL, 1), + GATE_PERAO0(CLK_PERAO_UART2, CLK_TOP_UART_SEL, 2), + GATE_PERAO0(CLK_PERAO_UART3, CLK_TOP_UART_SEL, 3), + GATE_PERAO0(CLK_PERAO_PWM_H, CLK_TOP_AXI_PERI_SEL, 4), + GATE_PERAO0(CLK_PERAO_PWM_B, CLK_TOP_PWM_SEL, 5), + GATE_PERAO0(CLK_PERAO_PWM_FB1, CLK_TOP_PWM_SEL, 6), + GATE_PERAO0(CLK_PERAO_PWM_FB2, CLK_TOP_PWM_SEL, 7), + GATE_PERAO0(CLK_PERAO_PWM_FB3, CLK_TOP_PWM_SEL, 8), + GATE_PERAO0(CLK_PERAO_PWM_FB4, CLK_TOP_PWM_SEL, 9), + GATE_PERAO0(CLK_PERAO_DISP_PWM0, CLK_TOP_DISP_PWM_SEL, 10), + GATE_PERAO0(CLK_PERAO_DISP_PWM1, CLK_TOP_DISP_PWM_SEL, 11), + GATE_PERAO0(CLK_PERAO_SPI0_B, CLK_TOP_SPI0_SEL, 12), + GATE_PERAO0(CLK_PERAO_SPI1_B, CLK_TOP_SPI1_SEL, 13), + GATE_PERAO0(CLK_PERAO_SPI2_B, CLK_TOP_SPI2_SEL, 14), + GATE_PERAO0(CLK_PERAO_SPI3_B, CLK_TOP_SPI3_SEL, 15), + GATE_PERAO0(CLK_PERAO_SPI4_B, CLK_TOP_SPI4_SEL, 16), + GATE_PERAO0(CLK_PERAO_SPI5_B, CLK_TOP_SPI5_SEL, 17), + GATE_PERAO0(CLK_PERAO_SPI0_H, CLK_TOP_AXI_PERI_SEL, 18), + GATE_PERAO0(CLK_PERAO_SPI1_H, CLK_TOP_AXI_PERI_SEL, 19), + GATE_PERAO0(CLK_PERAO_SPI2_H, CLK_TOP_AXI_PERI_SEL, 20), + GATE_PERAO0(CLK_PERAO_SPI3_H, CLK_TOP_AXI_PERI_SEL, 21), + GATE_PERAO0(CLK_PERAO_SPI4_H, CLK_TOP_AXI_PERI_SEL, 22), + GATE_PERAO0(CLK_PERAO_SPI5_H, CLK_TOP_AXI_PERI_SEL, 23), + GATE_PERAO0(CLK_PERAO_AXI, CLK_TOP_MEM_SUB_PERI_SEL, 24), + GATE_PERAO0(CLK_PERAO_AHB_APB, CLK_TOP_AXI_PERI_SEL, 25), + GATE_PERAO0(CLK_PERAO_TL, CLK_TOP_MAC_TL_SEL, 26), + GATE_PERAO0P(CLK_PERAO_REF, CLK_PAD_CLK26M, 27), + GATE_PERAO0(CLK_PERAO_I2C, CLK_TOP_AXI_PERI_SEL, 28), + GATE_PERAO0(CLK_PERAO_DMA_B, CLK_TOP_AXI_PERI_SEL, 29), + /* PERAO1 */ + GATE_PERAO1P(CLK_PERAO_SSUSB0_REF, CLK_PAD_CLK26M, 1), + GATE_PERAO1(CLK_PERAO_SSUSB0_FRMCNT, CLK_TOP_UNIVPLL_192M_D4, 2), + GATE_PERAO1(CLK_PERAO_SSUSB0_SYS, CLK_TOP_USB_TOP_P0_SEL, 4), + GATE_PERAO1(CLK_PERAO_SSUSB0_XHCI, CLK_TOP_USB_XHCI_P0_SEL, 5), + GATE_PERAO1(CLK_PERAO_SSUSB0_F, CLK_TOP_AXI_PERI_SEL, 6), + GATE_PERAO1(CLK_PERAO_SSUSB0_H, CLK_TOP_AXI_PERI_SEL, 7), + GATE_PERAO1P(CLK_PERAO_SSUSB1_REF, CLK_PAD_CLK26M, 8), + GATE_PERAO1(CLK_PERAO_SSUSB1_FRMCNT, CLK_TOP_UNIVPLL_192M_D4, 9), + GATE_PERAO1(CLK_PERAO_SSUSB1_SYS, CLK_TOP_USB_TOP_P1_SEL, 11), + GATE_PERAO1(CLK_PERAO_SSUSB1_XHCI, CLK_TOP_USB_XHCI_P1_SEL, 12), + GATE_PERAO1(CLK_PERAO_SSUSB1_F, CLK_TOP_AXI_PERI_SEL, 13), + GATE_PERAO1(CLK_PERAO_SSUSB1_H, CLK_TOP_AXI_PERI_SEL, 14), + GATE_PERAO1P(CLK_PERAO_SSUSB2_REF, CLK_PAD_CLK26M, 15), + GATE_PERAO1(CLK_PERAO_SSUSB2_FRMCNT, CLK_TOP_UNIVPLL_192M_D4, 16), + GATE_PERAO1(CLK_PERAO_SSUSB2_SYS, CLK_TOP_USB_TOP_P2_SEL, 18), + GATE_PERAO1(CLK_PERAO_SSUSB2_XHCI, CLK_TOP_USB_XHCI_P2_SEL, 19), + GATE_PERAO1(CLK_PERAO_SSUSB2_F, CLK_TOP_AXI_PERI_SEL, 20), + GATE_PERAO1(CLK_PERAO_SSUSB2_H, CLK_TOP_AXI_PERI_SEL, 21), + GATE_PERAO1P(CLK_PERAO_SSUSB3_REF, CLK_PAD_CLK26M, 23), + GATE_PERAO1(CLK_PERAO_SSUSB3_FRMCNT, CLK_TOP_UNIVPLL_192M_D4, 24), + GATE_PERAO1(CLK_PERAO_SSUSB3_SYS, CLK_TOP_USB_TOP_P3_SEL, 26), + GATE_PERAO1(CLK_PERAO_SSUSB3_XHCI, CLK_TOP_USB_XHCI_P3_SEL, 27), + GATE_PERAO1(CLK_PERAO_SSUSB3_F, CLK_TOP_AXI_PERI_SEL, 28), + GATE_PERAO1(CLK_PERAO_SSUSB3_H, CLK_TOP_AXI_PERI_SEL, 29), + /* PERAO2 */ + GATE_PERAO2P(CLK_PERAO_SSUSB4_REF, CLK_PAD_CLK26M, 0), + GATE_PERAO2(CLK_PERAO_SSUSB4_FRMCNT, CLK_TOP_UNIVPLL_192M_D4, 1), + GATE_PERAO2(CLK_PERAO_SSUSB4_SYS, CLK_TOP_USB_TOP_P4_SEL, 3), + GATE_PERAO2(CLK_PERAO_SSUSB4_XHCI, CLK_TOP_USB_XHCI_P4_SEL, 4), + GATE_PERAO2(CLK_PERAO_SSUSB4_F, CLK_TOP_AXI_PERI_SEL, 5), + GATE_PERAO2(CLK_PERAO_SSUSB4_H, CLK_TOP_AXI_PERI_SEL, 6), + GATE_PERAO2(CLK_PERAO_MSDC0, CLK_TOP_MSDC50_0_SEL, 7), + GATE_PERAO2(CLK_PERAO_MSDC0_H, CLK_TOP_MSDC50_0_HCLK_SEL, 8), + GATE_PERAO2(CLK_PERAO_MSDC0_FAES, CLK_TOP_AES_MSDCFDE_SEL, 9), + GATE_PERAO2(CLK_PERAO_MSDC0_MST_F, CLK_TOP_AXI_PERI_SEL, 10), + GATE_PERAO2(CLK_PERAO_MSDC0_SLV_H, CLK_TOP_AXI_PERI_SEL, 11), + GATE_PERAO2(CLK_PERAO_MSDC1, CLK_TOP_MSDC30_1_SEL, 12), + GATE_PERAO2(CLK_PERAO_MSDC1_H, CLK_TOP_MSDC30_1_HCLK_SEL, 13), + GATE_PERAO2(CLK_PERAO_MSDC1_MST_F, CLK_TOP_AXI_PERI_SEL, 14), + GATE_PERAO2(CLK_PERAO_MSDC1_SLV_H, CLK_TOP_AXI_PERI_SEL, 15), + GATE_PERAO2(CLK_PERAO_MSDC2, CLK_TOP_MSDC30_2_SEL, 16), + GATE_PERAO2(CLK_PERAO_MSDC2_H, CLK_TOP_MSDC30_2_HCLK_SEL, 17), + GATE_PERAO2(CLK_PERAO_MSDC2_MST_F, CLK_TOP_AXI_PERI_SEL, 18), + GATE_PERAO2(CLK_PERAO_MSDC2_SLV_H, CLK_TOP_AXI_PERI_SEL, 19), + GATE_PERAO2(CLK_PERAO_SFLASH, CLK_TOP_SFLASH_SEL, 20), + GATE_PERAO2(CLK_PERAO_SFLASH_F, CLK_TOP_AXI_PERI_SEL, 21), + GATE_PERAO2(CLK_PERAO_SFLASH_H, CLK_TOP_AXI_PERI_SEL, 22), + GATE_PERAO2(CLK_PERAO_SFLASH_P, CLK_TOP_AXI_PERI_SEL, 23), + GATE_PERAO2(CLK_PERAO_AUDIO0, CLK_TOP_AXI_PERI_SEL, 24), + GATE_PERAO2(CLK_PERAO_AUDIO1, CLK_TOP_AXI_PERI_SEL, 25), + GATE_PERAO2(CLK_PERAO_AUDIO2, CLK_TOP_AUD_INTBUS_SEL, 26), + GATE_PERAO2P(CLK_PERAO_AUXADC_26M, CLK_PAD_CLK26M, 27), +}; + +static const struct mtk_gate_regs imp_cg_regs = { + .set_ofs = 0xE08, + .clr_ofs = 0xE04, + .sta_ofs = 0xE00, +}; + +#define GATE_IMP(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &imp_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +static const struct mtk_gate imp_clks[] = { + GATE_IMP(CLK_IMPE_I2C0, CLK_TOP_I2C_SEL, 0), + GATE_IMP(CLK_IMPE_I2C1, CLK_TOP_I2C_SEL, 1), + GATE_IMP(CLK_IMPWS_I2C2, CLK_TOP_I2C_SEL, 0), + GATE_IMP(CLK_IMPS_I2C3, CLK_TOP_I2C_SEL, 0), + GATE_IMP(CLK_IMPS_I2C4, CLK_TOP_I2C_SEL, 1), + GATE_IMP(CLK_IMPS_I2C5, CLK_TOP_I2C_SEL, 2), + GATE_IMP(CLK_IMPS_I2C6, CLK_TOP_I2C_SEL, 3), + GATE_IMP(CLK_IMPEN_I2C7, CLK_TOP_I2C_SEL, 0), + GATE_IMP(CLK_IMPEN_I2C8, CLK_TOP_I2C_SEL, 1), +}; + +static const struct mtk_gate_regs mm0_cg_regs = { + .set_ofs = 0x104, + .clr_ofs = 0x108, + .sta_ofs = 0x100, +}; + +static const struct mtk_gate_regs mm1_cg_regs = { + .set_ofs = 0x114, + .clr_ofs = 0x118, + .sta_ofs = 0x110, +}; + +#define GATE_MM0(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &mm0_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +#define GATE_MM1(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &mm1_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +static const struct mtk_gate mm_clks[] = { + /* MM0 */ + GATE_MM0(CLK_MM_DISP_OVL0_4L, CLK_TOP_DISP0_SEL, 0), + GATE_MM0(CLK_MM_DISP_OVL1_4L, CLK_TOP_DISP0_SEL, 1), + GATE_MM0(CLK_MM_VPP_RSZ0, CLK_TOP_DISP0_SEL, 2), + GATE_MM0(CLK_MM_VPP_RSZ1, CLK_TOP_DISP0_SEL, 3), + GATE_MM0(CLK_MM_DISP_RDMA0, CLK_TOP_DISP0_SEL, 4), + GATE_MM0(CLK_MM_DISP_RDMA1, CLK_TOP_DISP0_SEL, 5), + GATE_MM0(CLK_MM_DISP_COLOR0, CLK_TOP_DISP0_SEL, 6), + GATE_MM0(CLK_MM_DISP_COLOR1, CLK_TOP_DISP0_SEL, 7), + GATE_MM0(CLK_MM_DISP_CCORR0, CLK_TOP_DISP0_SEL, 8), + GATE_MM0(CLK_MM_DISP_CCORR1, CLK_TOP_DISP0_SEL, 9), + GATE_MM0(CLK_MM_DISP_CCORR2, CLK_TOP_DISP0_SEL, 10), + GATE_MM0(CLK_MM_DISP_CCORR3, CLK_TOP_DISP0_SEL, 11), + GATE_MM0(CLK_MM_DISP_AAL0, CLK_TOP_DISP0_SEL, 12), + GATE_MM0(CLK_MM_DISP_AAL1, CLK_TOP_DISP0_SEL, 13), + GATE_MM0(CLK_MM_DISP_GAMMA0, CLK_TOP_DISP0_SEL, 14), + GATE_MM0(CLK_MM_DISP_GAMMA1, CLK_TOP_DISP0_SEL, 15), + GATE_MM0(CLK_MM_DISP_DITHER0, CLK_TOP_DISP0_SEL, 16), + GATE_MM0(CLK_MM_DISP_DITHER1, CLK_TOP_DISP0_SEL, 17), + GATE_MM0(CLK_MM_DISP_DSC_WRAP0, CLK_TOP_DISP0_SEL, 18), + GATE_MM0(CLK_MM_VPP_MERGE0, CLK_TOP_DISP0_SEL, 19), + GATE_MM0(CLK_MMSYS_0_DISP_DVO, CLK_TOP_DISP0_SEL, 20), + GATE_MM0(CLK_MMSYS_0_DISP_DSI0, CLK_TOP_DISP0_SEL, 21), + GATE_MM0(CLK_MM_DP_INTF0, CLK_TOP_DISP0_SEL, 22), + GATE_MM0(CLK_MM_DPI0, CLK_TOP_DISP0_SEL, 23), + GATE_MM0(CLK_MM_DISP_WDMA0, CLK_TOP_DISP0_SEL, 24), + GATE_MM0(CLK_MM_DISP_WDMA1, CLK_TOP_DISP0_SEL, 25), + GATE_MM0(CLK_MM_DISP_FAKE_ENG0, CLK_TOP_DISP0_SEL, 26), + GATE_MM0(CLK_MM_DISP_FAKE_ENG1, CLK_TOP_DISP0_SEL, 27), + GATE_MM0(CLK_MM_SMI_LARB, CLK_TOP_DISP0_SEL, 28), + GATE_MM0(CLK_MM_DISP_MUTEX0, CLK_TOP_DISP0_SEL, 29), + GATE_MM0(CLK_MM_DIPSYS_CONFIG, CLK_TOP_DISP0_SEL, 30), + GATE_MM0(CLK_MM_DUMMY, CLK_TOP_DISP0_SEL, 31), + /* MM1 */ + GATE_MM1(CLK_MMSYS_1_DISP_DSI0, CLK_TOP_DSI_OCC_SEL, 0), + GATE_MM1(CLK_MMSYS_1_LVDS_ENCODER, CLK_TOP_PLL_DPIX_SEL, 1), + GATE_MM1(CLK_MMSYS_1_DPI0, CLK_TOP_PLL_DPIX_SEL, 2), + GATE_MM1(CLK_MMSYS_1_DISP_DVO, CLK_TOP_EDP_SEL, 3), + GATE_MM1(CLK_MM_DP_INTF, CLK_TOP_DP_SEL, 4), + GATE_MM1(CLK_MMSYS_1_LVDS_ENCODER_CTS, CLK_TOP_VDSTX_DG_CTS_SEL, 5), + GATE_MM1(CLK_MMSYS_1_DISP_DVO_AVT, CLK_TOP_EDP_FAVT_SEL, 6), +}; + +static const struct mtk_gate_regs mminfra_config0_cg_regs = { + .set_ofs = 0x104, + .clr_ofs = 0x108, + .sta_ofs = 0x100, +}; + +static const struct mtk_gate_regs mminfra_config1_cg_regs = { + .set_ofs = 0x114, + .clr_ofs = 0x118, + .sta_ofs = 0x110, +}; + +#define GATE_MMINFRA_CONFIG0(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &mminfra_config0_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +#define GATE_MMINFRA_CONFIG1(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &mminfra_config1_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +static const struct mtk_gate mminfra_config_clks[] = { + GATE_MMINFRA_CONFIG0(CLK_MMINFRA_GCE_D, CLK_TOP_MMINFRA_SEL, 0), + GATE_MMINFRA_CONFIG0(CLK_MMINFRA_GCE_M, CLK_TOP_MMINFRA_SEL, 1), + GATE_MMINFRA_CONFIG0(CLK_MMINFRA_SMI, CLK_TOP_MMINFRA_SEL, 2), + GATE_MMINFRA_CONFIG1(CLK_MMINFRA_GCE_26M, CLK_TOP_MMINFRA_SEL, 17), +}; + +static const struct mtk_clk_tree mt8189_apmixedsys_clk_tree = { + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), + .plls = apmixed_plls, + .num_plls = ARRAY_SIZE(apmixed_plls), +}; + +static const struct mtk_clk_tree mt8189_topckgen_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), + .fdivs_offs = CLK_TOP_MAINPLL_D3, + .muxes_offs = CLK_TOP_AXI_SEL, + .gates_offs = CLK_TOP_USB2_PHY_RF_P0_EN, + .fdivs = top_fixed_divs, + .muxes = top_muxes, + .gates = top_gates, + .num_fdivs = ARRAY_SIZE(top_fixed_divs), + .num_muxes = ARRAY_SIZE(top_muxes), + .num_gates = ARRAY_SIZE(top_gates), +}; + +static const struct udevice_id mt8189_apmixed[] = { + { .compatible = "mediatek,mt8189-apmixedsys", }, + { } +}; + +static const struct udevice_id mt8189_topckgen_compat[] = { + { .compatible = "mediatek,mt8189-topckgen", }, + { } +}; + +struct mt8189_gate_clk_data { + const struct mtk_gate *gates; + int num_gates; +}; + +#define GATE_CLK_DATA(name) \ +static const struct mt8189_gate_clk_data name##_data = { \ + .gates = name, .num_gates = ARRAY_SIZE(name) \ +} + +GATE_CLK_DATA(perao_clks); +GATE_CLK_DATA(imp_clks); +GATE_CLK_DATA(mm_clks); +GATE_CLK_DATA(mminfra_config_clks); + +static const struct udevice_id of_match_mt8189_clk_gate[] = { + { .compatible = "mediatek,mt8189-peri-ao", .data = (ulong)&perao_clks_data }, + { .compatible = "mediatek,mt8189-iic-wrap", .data = (ulong)&imp_clks_data }, + { .compatible = "mediatek,mt8189-dispsys", .data = (ulong)&mm_clks_data }, + { .compatible = "mediatek,mt8189-mm-infra", .data = (ulong)&mminfra_config_clks_data }, + { } +}; + +static int mt8189_apmixedsys_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt8189_apmixedsys_clk_tree); +} + +static int mt8189_topckgen_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt8189_topckgen_clk_tree); +} + +static int mt8189_clk_gate_probe(struct udevice *dev) +{ + struct mt8189_gate_clk_data *data; + + data = (void *)dev_get_driver_data(dev); + + return mtk_common_clk_gate_init(dev, &mt8189_topckgen_clk_tree, + data->gates, data->num_gates, + data->gates[0].id); +} + +U_BOOT_DRIVER(mtk_clk_apmixedsys) = { + .name = "mt8189-apmixedsys", + .id = UCLASS_CLK, + .of_match = mt8189_apmixed, + .probe = mt8189_apmixedsys_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_apmixedsys_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_topckgen) = { + .name = "mt8189-topckgen", + .id = UCLASS_CLK, + .of_match = mt8189_topckgen_compat, + .probe = mt8189_topckgen_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_topckgen_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_gate) = { + .name = "mt8189-gate-clk", + .id = UCLASS_CLK, + .of_match = of_match_mt8189_clk_gate, + .probe = mt8189_clk_gate_probe, + .priv_auto = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/mediatek/clk-mt8195.c b/drivers/clk/mediatek/clk-mt8195.c new file mode 100644 index 00000000000..37cceb5f32b --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8195.c @@ -0,0 +1,1662 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026 MediaTek Inc. + * Author: Chris-qj Chen <[email protected]> + * Julien Stephan <[email protected]> + */ + +#include <asm/io.h> +#include <dm.h> +#include <dt-bindings/clock/mt8195-clk.h> +#include <linux/bitops.h> + +#include "clk-mtk.h" + +#define MT8195_PLL_FMAX (3800UL * MHZ) +#define MT8195_PLL_FMIN (1500UL * MHZ) +#define MT8195_INTEGER_BITS 8 + +enum { + CLK_PAD_CLK26M, + CLK_PAD_CLK32K, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK26M] = 26 * MHZ, + [CLK_PAD_CLK32K] = 32000, +}; + +#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, \ + _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift,\ + _pcw_reg, _pcw_shift, _pcw_chg_reg) { \ + .id = _id, \ + .reg = _reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .rst_bar_mask = _rst_bar_mask, \ + .fmax = MT8195_PLL_FMAX, \ + .fmin = MT8195_PLL_FMIN, \ + .flags = _flags, \ + .pcwbits = _pcwbits, \ + .pcwibits = MT8195_INTEGER_BITS, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + .pcw_chg_reg = _pcw_chg_reg, \ + } + +static const struct mtk_pll_data apmixed_plls[] = { + PLL(CLK_APMIXED_NNAPLL, 0x0390, 0x03a0, 0, 0, 0, 22, 0x0398, 24, + 0x0398, 0, 0x0398), + PLL(CLK_APMIXED_RESPLL, 0x0190, 0x0320, 0, 0, 0, 22, 0x0198, 24, + 0x0198, 0, 0x0198), + PLL(CLK_APMIXED_ETHPLL, 0x0360, 0x0370, 0, 0, 0, 22, 0x0368, 24, + 0x0368, 0, 0x0368), + PLL(CLK_APMIXED_MSDCPLL, 0x0710, 0x0720, 0, 0, 0, 22, 0x0718, 24, + 0x0718, 0, 0x0718), + PLL(CLK_APMIXED_TVDPLL1, 0x00a0, 0x00b0, 0, 0, 0, 22, 0x00a8, 24, + 0x00a8, 0, 0x00a8), + PLL(CLK_APMIXED_TVDPLL2, 0x00c0, 0x00d0, 0, 0, 0, 22, 0x00c8, 24, + 0x00c8, 0, 0x00c8), + PLL(CLK_APMIXED_MMPLL, 0x00e0, 0x00f0, 0xff000000, CLK_PLL_HAVE_RST_BAR, + BIT(23), 22, 0x00e8, 24, 0x00e8, 0, 0x00e8), + PLL(CLK_APMIXED_MAINPLL, 0x01d0, 0x01e0, 0xff000000, CLK_PLL_HAVE_RST_BAR, + BIT(23), 22, 0x01d8, 24, 0x01d8, 0, 0x01d8), + PLL(CLK_APMIXED_VDECPLL, 0x0890, 0x08a0, 0, 0, 0, 22, 0x0898, 24, + 0x0898, 0, 0x0898), + PLL(CLK_APMIXED_IMGPLL, 0x0100, 0x0110, 0, 0, 0, 22, 0x0108, 24, + 0x0108, 0, 0x0108), + PLL(CLK_APMIXED_UNIVPLL, 0x01f0, 0x0700, 0xff000000, CLK_PLL_HAVE_RST_BAR, + BIT(23), 22, 0x01f8, 24, 0x01f8, 0, 0x01f8), + PLL(CLK_APMIXED_HDMIPLL1, 0x08c0, 0x08d0, 0, 0, 0, 22, 0x08c8, 24, + 0x08c8, 0, 0x08c8), + PLL(CLK_APMIXED_HDMIPLL2, 0x0870, 0x0880, 0, 0, 0, 22, 0x0878, 24, + 0x0878, 0, 0x0878), + PLL(CLK_APMIXED_HDMIRX_APLL, 0x08e0, 0x0dd4, 0, 0, 0, 32, 0x08e8, 24, + 0x08ec, 0, 0x08e8), + PLL(CLK_APMIXED_USB1PLL, 0x01a0, 0x01b0, 0, 0, 0, 22, 0x01a8, 24, + 0x01a8, 0, 0x01a8), + PLL(CLK_APMIXED_ADSPPLL, 0x07e0, 0x07f0, 0, 0, 0, 22, 0x07e8, 24, + 0x07e8, 0, 0x07e8), + PLL(CLK_APMIXED_APLL1, 0x07c0, 0x0dc0, 0, 0, 0, 32, 0x07c8, 24, + 0x07cc, 0, 0x07c8), + PLL(CLK_APMIXED_APLL2, 0x0780, 0x0dc4, 0, 0, 0, 32, 0x0788, 24, + 0x078c, 0, 0x0788), + PLL(CLK_APMIXED_APLL3, 0x0760, 0x0dc8, 0, 0, 0, 32, 0x0768, 24, + 0x076c, 0, 0x0768), + PLL(CLK_APMIXED_APLL4, 0x0740, 0x0dcc, 0, 0, 0, 32, 0x0748, 24, + 0x074c, 0, 0x0748), + PLL(CLK_APMIXED_APLL5, 0x07a0, 0x0dd0, 0x100000, 0, 0, 32, 0x07a8, 24, + 0x07ac, 0, 0x07a8), + PLL(CLK_APMIXED_MFGPLL, 0x0340, 0x0350, 0, 0, 0, 22, 0x0348, 24, + 0x0348, 0, 0x0348), + PLL(CLK_APMIXED_DGIPLL, 0x0150, 0x0160, 0, 0, 0, 22, 0x0158, 24, + 0x0158, 0, 0x0158), +}; + +static const struct mtk_clk_tree mt8195_apmixedsys_clk_tree = { + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), + .plls = apmixed_plls, + .num_plls = ARRAY_SIZE(apmixed_plls), +}; + +#define FIXED_CLK0(_id, _rate) \ + FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) + +static const struct mtk_fixed_clk top_fixed_clks[] = { + FIXED_CLK0(CLK_TOP_IN_DGI, 165000000), + FIXED_CLK0(CLK_TOP_ULPOSC1, 248000000), + FIXED_CLK0(CLK_TOP_ULPOSC2, 326000000), + FIXED_CLK0(CLK_TOP_MEM_466M, 533000000), + FIXED_CLK0(CLK_TOP_MPHONE_SLAVE_B, 49152000), + FIXED_CLK0(CLK_TOP_PEXTP_PIPE, 250000000), + FIXED_CLK0(CLK_TOP_UFS_RX_SYMBOL, 166000000), + FIXED_CLK0(CLK_TOP_UFS_TX_SYMBOL, 166000000), + FIXED_CLK0(CLK_TOP_SSUSB_U3PHY_P1_P_P0, 131000000), + FIXED_CLK0(CLK_TOP_UFS_RX_SYMBOL1, 166000000), + FIXED_CLK0(CLK_TOP_FPC, 50000000), + FIXED_CLK0(CLK_TOP_HDMIRX_P, 594000000), +}; + +#define FACTOR0(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) + +#define FACTOR1(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) + +#define FACTOR2(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) + +static const struct mtk_fixed_factor top_fixed_divs[] = { + FACTOR2(CLK_TOP_CLK26M_D2, CLK_PAD_CLK26M, 1, 2), + FACTOR2(CLK_TOP_CLK26M_D52, CLK_PAD_CLK26M, 1, 52), + FACTOR1(CLK_TOP_IN_DGI_D2, CLK_TOP_IN_DGI, 1, 2), + FACTOR1(CLK_TOP_IN_DGI_D4, CLK_TOP_IN_DGI, 1, 4), + FACTOR1(CLK_TOP_IN_DGI_D6, CLK_TOP_IN_DGI, 1, 6), + FACTOR1(CLK_TOP_IN_DGI_D8, CLK_TOP_IN_DGI, 1, 8), + FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3), + FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4), + FACTOR1(CLK_TOP_MAINPLL_D4_D2, CLK_TOP_MAINPLL_D4, 1, 2), + FACTOR1(CLK_TOP_MAINPLL_D4_D4, CLK_TOP_MAINPLL_D4, 1, 4), + FACTOR1(CLK_TOP_MAINPLL_D4_D8, CLK_TOP_MAINPLL_D4, 1, 8), + FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5), + FACTOR1(CLK_TOP_MAINPLL_D5_D2, CLK_TOP_MAINPLL_D5, 1, 2), + FACTOR1(CLK_TOP_MAINPLL_D5_D4, CLK_TOP_MAINPLL_D5, 1, 4), + FACTOR1(CLK_TOP_MAINPLL_D5_D8, CLK_TOP_MAINPLL_D5, 1, 8), + FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6), + FACTOR1(CLK_TOP_MAINPLL_D6_D2, CLK_TOP_MAINPLL_D6, 1, 2), + FACTOR1(CLK_TOP_MAINPLL_D6_D4, CLK_TOP_MAINPLL_D6, 1, 4), + FACTOR1(CLK_TOP_MAINPLL_D6_D8, CLK_TOP_MAINPLL_D6, 1, 8), + FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7), + FACTOR1(CLK_TOP_MAINPLL_D7_D2, CLK_TOP_MAINPLL_D7, 1, 2), + FACTOR1(CLK_TOP_MAINPLL_D7_D4, CLK_TOP_MAINPLL_D7, 1, 4), + FACTOR1(CLK_TOP_MAINPLL_D7_D8, CLK_TOP_MAINPLL_D7, 1, 8), + FACTOR0(CLK_TOP_MAINPLL_D9, CLK_APMIXED_MAINPLL, 1, 9), + FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2), + FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3), + FACTOR0(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4), + FACTOR1(CLK_TOP_UNIVPLL_D4_D2, CLK_TOP_UNIVPLL_D4, 1, 2), + FACTOR1(CLK_TOP_UNIVPLL_D4_D4, CLK_TOP_UNIVPLL_D4, 1, 4), + FACTOR1(CLK_TOP_UNIVPLL_D4_D8, CLK_TOP_UNIVPLL_D4, 1, 8), + FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5), + FACTOR1(CLK_TOP_UNIVPLL_D5_D2, CLK_TOP_UNIVPLL_D5, 1, 2), + FACTOR1(CLK_TOP_UNIVPLL_D5_D4, CLK_TOP_UNIVPLL_D5, 1, 4), + FACTOR1(CLK_TOP_UNIVPLL_D5_D8, CLK_TOP_UNIVPLL_D5, 1, 8), + FACTOR0(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6), + FACTOR1(CLK_TOP_UNIVPLL_D6_D2, CLK_TOP_UNIVPLL_D6, 1, 2), + FACTOR1(CLK_TOP_UNIVPLL_D6_D4, CLK_TOP_UNIVPLL_D6, 1, 4), + FACTOR1(CLK_TOP_UNIVPLL_D6_D8, CLK_TOP_UNIVPLL_D6, 1, 8), + FACTOR1(CLK_TOP_UNIVPLL_D6_D16, CLK_TOP_UNIVPLL_D6, 1, 16), + FACTOR0(CLK_TOP_UNIVPLL_D7, CLK_APMIXED_UNIVPLL, 1, 7), + FACTOR0(CLK_TOP_UNIVPLL_192M, CLK_APMIXED_UNIVPLL, 1, 13), + FACTOR1(CLK_TOP_UNIVPLL_192M_D4, CLK_TOP_UNIVPLL_192M, 1, 4), + FACTOR1(CLK_TOP_UNIVPLL_192M_D8, CLK_TOP_UNIVPLL_192M, 1, 8), + FACTOR1(CLK_TOP_UNIVPLL_192M_D16, CLK_TOP_UNIVPLL_192M, 1, 16), + FACTOR1(CLK_TOP_UNIVPLL_192M_D32, CLK_TOP_UNIVPLL_192M, 1, 32), + FACTOR0(CLK_TOP_APLL1_D3, CLK_APMIXED_APLL1, 1, 3), + FACTOR0(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4), + FACTOR0(CLK_TOP_APLL2_D3, CLK_APMIXED_APLL2, 1, 3), + FACTOR0(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4), + FACTOR0(CLK_TOP_APLL3_D4, CLK_APMIXED_APLL3, 1, 4), + FACTOR0(CLK_TOP_APLL4_D4, CLK_APMIXED_APLL4, 1, 4), + FACTOR0(CLK_TOP_APLL5_D4, CLK_APMIXED_APLL5, 1, 4), + FACTOR0(CLK_TOP_HDMIRX_APLL_D3, CLK_APMIXED_HDMIRX_APLL, 1, 3), + FACTOR0(CLK_TOP_HDMIRX_APLL_D4, CLK_APMIXED_HDMIRX_APLL, 1, 4), + FACTOR0(CLK_TOP_HDMIRX_APLL_D6, CLK_APMIXED_HDMIRX_APLL, 1, 6), + FACTOR0(CLK_TOP_MMPLL_D4, CLK_APMIXED_MMPLL, 1, 4), + FACTOR1(CLK_TOP_MMPLL_D4_D2, CLK_TOP_MMPLL_D4, 1, 2), + FACTOR1(CLK_TOP_MMPLL_D4_D4, CLK_TOP_MMPLL_D4, 1, 4), + FACTOR0(CLK_TOP_MMPLL_D5, CLK_APMIXED_MMPLL, 1, 5), + FACTOR1(CLK_TOP_MMPLL_D5_D2, CLK_TOP_MMPLL_D5, 1, 2), + FACTOR1(CLK_TOP_MMPLL_D5_D4, CLK_TOP_MMPLL_D5, 1, 4), + FACTOR0(CLK_TOP_MMPLL_D6, CLK_APMIXED_MMPLL, 1, 6), + FACTOR1(CLK_TOP_MMPLL_D6_D2, CLK_TOP_MMPLL_D6, 1, 2), + FACTOR0(CLK_TOP_MMPLL_D7, CLK_APMIXED_MMPLL, 1, 7), + FACTOR0(CLK_TOP_MMPLL_D9, CLK_APMIXED_MMPLL, 1, 9), + FACTOR0(CLK_TOP_TVDPLL1_D2, CLK_APMIXED_TVDPLL1, 1, 2), + FACTOR0(CLK_TOP_TVDPLL1_D4, CLK_APMIXED_TVDPLL1, 1, 4), + FACTOR0(CLK_TOP_TVDPLL1_D8, CLK_APMIXED_TVDPLL1, 1, 8), + FACTOR0(CLK_TOP_TVDPLL1_D16, CLK_APMIXED_TVDPLL1, 1, 16), + FACTOR0(CLK_TOP_TVDPLL2_D2, CLK_APMIXED_TVDPLL2, 1, 2), + FACTOR0(CLK_TOP_TVDPLL2_D4, CLK_APMIXED_TVDPLL2, 1, 4), + FACTOR0(CLK_TOP_TVDPLL2_D8, CLK_APMIXED_TVDPLL2, 1, 8), + FACTOR0(CLK_TOP_TVDPLL2_D16, CLK_APMIXED_TVDPLL2, 1, 16), + FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2), + FACTOR0(CLK_TOP_MSDCPLL_D4, CLK_APMIXED_MSDCPLL, 1, 4), + FACTOR0(CLK_TOP_MSDCPLL_D16, CLK_APMIXED_MSDCPLL, 1, 16), + FACTOR0(CLK_TOP_ETHPLL_D2, CLK_APMIXED_ETHPLL, 1, 2), + FACTOR0(CLK_TOP_ETHPLL_D8, CLK_APMIXED_ETHPLL, 1, 8), + FACTOR0(CLK_TOP_ETHPLL_D10, CLK_APMIXED_ETHPLL, 1, 10), + FACTOR0(CLK_TOP_DGIPLL_D2, CLK_APMIXED_DGIPLL, 1, 2), + FACTOR1(CLK_TOP_ULPOSC1_D2, CLK_TOP_ULPOSC1, 1, 2), + FACTOR1(CLK_TOP_ULPOSC1_D4, CLK_TOP_ULPOSC1, 1, 4), + FACTOR1(CLK_TOP_ULPOSC1_D7, CLK_TOP_ULPOSC1, 1, 7), + FACTOR1(CLK_TOP_ULPOSC1_D8, CLK_TOP_ULPOSC1, 1, 8), + FACTOR1(CLK_TOP_ULPOSC1_D10, CLK_TOP_ULPOSC1, 1, 10), + FACTOR1(CLK_TOP_ULPOSC1_D16, CLK_TOP_ULPOSC1, 1, 16), + FACTOR0(CLK_TOP_ADSPPLL_D2, CLK_APMIXED_ADSPPLL, 1, 2), + FACTOR0(CLK_TOP_ADSPPLL_D4, CLK_APMIXED_ADSPPLL, 1, 4), + FACTOR0(CLK_TOP_ADSPPLL_D8, CLK_APMIXED_ADSPPLL, 1, 8), +}; + +static const struct mtk_parent axi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_ULPOSC1_D4), +}; + +static const struct mtk_parent spm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), + EXT_PARENT(CLK_PAD_CLK32K), +}; + +static const struct mtk_parent scp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), +}; + +static const struct mtk_parent bus_aximem_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), +}; + +static const struct mtk_parent vpp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D5), + APMIXED_PARENT(CLK_APMIXED_TVDPLL1), + APMIXED_PARENT(CLK_APMIXED_TVDPLL2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), +}; + +static const struct mtk_parent ethdr_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D5_D4), + APMIXED_PARENT(CLK_APMIXED_TVDPLL1), + APMIXED_PARENT(CLK_APMIXED_TVDPLL2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), +}; + +static const struct mtk_parent ipe_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_IMGPLL), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent cam_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + APMIXED_PARENT(CLK_APMIXED_IMGPLL), +}; + +static const struct mtk_parent ccu_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), +}; + +static const struct mtk_parent img_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_IMGPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent camtm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent dsp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent dsp1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent dsp2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent ipu_if_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), +}; + +static const struct mtk_parent mfg_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), +}; + +static const struct mtk_parent camtg_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D16), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D32), +}; + +static const struct mtk_parent uart_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), +}; + +static const struct mtk_parent spi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D4), + TOP_PARENT(CLK_TOP_MSDCPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), +}; + +static const struct mtk_parent spis_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), +}; + +static const struct mtk_parent msdc50_0_h_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), +}; + +static const struct mtk_parent msdc50_0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_MSDCPLL), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), +}; + +static const struct mtk_parent msdc30_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), +}; + +static const struct mtk_parent intdir_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), +}; + +static const struct mtk_parent aud_intbus_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), +}; + +static const struct mtk_parent audio_h_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), +}; + +static const struct mtk_parent pwrap_ulposc_parents[] = { + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ULPOSC1_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D7), + TOP_PARENT(CLK_TOP_ULPOSC1_D8), + TOP_PARENT(CLK_TOP_ULPOSC1_D16), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D8), +}; + +static const struct mtk_parent atb_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), +}; + +static const struct mtk_parent pwrmcu_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D9), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), +}; + +static const struct mtk_parent dp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL1_D2), + TOP_PARENT(CLK_TOP_TVDPLL2_D2), + TOP_PARENT(CLK_TOP_TVDPLL1_D4), + TOP_PARENT(CLK_TOP_TVDPLL2_D4), + TOP_PARENT(CLK_TOP_TVDPLL1_D8), + TOP_PARENT(CLK_TOP_TVDPLL2_D8), + TOP_PARENT(CLK_TOP_TVDPLL1_D16), + TOP_PARENT(CLK_TOP_TVDPLL2_D16), +}; + +static const struct mtk_parent disp_pwm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D2), + TOP_PARENT(CLK_TOP_ULPOSC1_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D16), +}; + +static const struct mtk_parent usb_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent i2c_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), +}; + +static const struct mtk_parent seninf_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), +}; + +static const struct mtk_parent gcpu_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent dxcc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), +}; + +static const struct mtk_parent dpmaif_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), +}; + +static const struct mtk_parent aes_fde_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), +}; + +static const struct mtk_parent ufs_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), +}; + +static const struct mtk_parent ufs_tick1us_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M_D52), + EXT_PARENT(CLK_PAD_CLK26M), +}; + +static const struct mtk_parent ufs_mp_sap_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL_D16), +}; + +static const struct mtk_parent venc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MMPLL_D9), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5), +}; + +static const struct mtk_parent vdec_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D5), + APMIXED_PARENT(CLK_APMIXED_VDECPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MMPLL_D9), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D4), +}; + +static const struct mtk_parent pwm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), +}; + +static const struct mtk_parent mcupm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), +}; + +static const struct mtk_parent spmi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_ULPOSC1_D8), + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_ULPOSC1_D16), + TOP_PARENT(CLK_TOP_ULPOSC1_D7), + EXT_PARENT(CLK_PAD_CLK32K), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D8), +}; + +static const struct mtk_parent dvfsrc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_MSDCPLL_D16), +}; + +static const struct mtk_parent tl_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), +}; + +static const struct mtk_parent dsi_occ_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), +}; + +static const struct mtk_parent wpe_vpp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + APMIXED_PARENT(CLK_APMIXED_TVDPLL1), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), +}; + +static const struct mtk_parent hdcp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent hdcp_24m_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), +}; + +static const struct mtk_parent hd20_dacr_ref_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), +}; + +static const struct mtk_parent hd20_hdcp_c_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), +}; + +static const struct mtk_parent hdmi_xtal_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_CLK26M_D2), +}; + +static const struct mtk_parent hdmi_apb_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), +}; + +static const struct mtk_parent snps_eth_250m_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D2), +}; + +static const struct mtk_parent snps_eth_62p4m_ptp_parents[] = { + TOP_PARENT(CLK_TOP_APLL2_D3), + TOP_PARENT(CLK_TOP_APLL1_D3), + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D8), +}; + +static const struct mtk_parent snps_eth_50m_rmii_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D10), +}; + +static const struct mtk_parent dgi_out_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_DGIPLL), + TOP_PARENT(CLK_TOP_DGIPLL_D2), + TOP_PARENT(CLK_TOP_IN_DGI), + TOP_PARENT(CLK_TOP_IN_DGI_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D4), +}; + +static const struct mtk_parent nna_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_NNAPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), +}; + +static const struct mtk_parent adsp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_ULPOSC1), + APMIXED_PARENT(CLK_APMIXED_ADSPPLL), + TOP_PARENT(CLK_TOP_ADSPPLL_D2), + TOP_PARENT(CLK_TOP_ADSPPLL_D4), + TOP_PARENT(CLK_TOP_ADSPPLL_D8), +}; + +static const struct mtk_parent asm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), +}; + +static const struct mtk_parent apll1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_D4), +}; + +static const struct mtk_parent apll2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_D4), +}; + +static const struct mtk_parent apll3_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL3_D4), +}; + +static const struct mtk_parent apll4_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL4_D4), +}; + +static const struct mtk_parent apll5_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL5_D4), +}; + +static const struct mtk_parent i2s_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL3), + TOP_PARENT(CLK_TOP_APLL4), + TOP_PARENT(CLK_TOP_APLL5), + APMIXED_PARENT(CLK_APMIXED_HDMIRX_APLL), +}; + +static const struct mtk_parent a1sys_hp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_D4), +}; + +static const struct mtk_parent a2sys_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_D4), +}; + +static const struct mtk_parent a3sys_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL3_D4), + TOP_PARENT(CLK_TOP_APLL4_D4), + TOP_PARENT(CLK_TOP_APLL5_D4), + TOP_PARENT(CLK_TOP_HDMIRX_APLL_D3), + TOP_PARENT(CLK_TOP_HDMIRX_APLL_D4), + TOP_PARENT(CLK_TOP_HDMIRX_APLL_D6), +}; + +static const struct mtk_parent spinfi_b_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), +}; + +static const struct mtk_parent nfi1x_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), +}; + +static const struct mtk_parent ecc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), +}; + +static const struct mtk_parent audio_local_bus_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_ULPOSC1), + TOP_PARENT(CLK_TOP_ULPOSC1_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D2), +}; + +static const struct mtk_parent spinor_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), +}; + +static const struct mtk_parent dvio_dgi_ref_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_IN_DGI), + TOP_PARENT(CLK_TOP_IN_DGI_D2), + TOP_PARENT(CLK_TOP_IN_DGI_D4), + TOP_PARENT(CLK_TOP_IN_DGI_D6), + TOP_PARENT(CLK_TOP_IN_DGI_D8), + TOP_PARENT(CLK_TOP_MMPLL_D4_D4), +}; + +static const struct mtk_parent ulposc_parents[] = { + TOP_PARENT(CLK_TOP_ULPOSC1), + TOP_PARENT(CLK_TOP_ETHPLL_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_ETHPLL_D10), +}; + +static const struct mtk_parent ulposc_core_parents[] = { + TOP_PARENT(CLK_TOP_ULPOSC2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_ETHPLL_D10), +}; + +static const struct mtk_parent srck_parents[] = { + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + EXT_PARENT(CLK_PAD_CLK26M), +}; + +static const struct mtk_composite top_muxes[] = { + /* CLK_CFG_0 */ + MUX_GATE(CLK_TOP_AXI, axi_parents, 0x020, 0, 3, 7), + MUX_GATE(CLK_TOP_SPM, spm_parents, 0x020, 8, 2, 15), + MUX_GATE(CLK_TOP_SCP, scp_parents, 0x020, 16, 3, 23), + MUX_GATE(CLK_TOP_BUS_AXIMEM, bus_aximem_parents, 0x020, 24, 3, 31), + /* CLK_CFG_1 */ + MUX_GATE(CLK_TOP_VPP, vpp_parents, 0x02C, 0, 4, 7), + MUX_GATE(CLK_TOP_ETHDR, ethdr_parents, 0x02C, 8, 4, 15), + MUX_GATE(CLK_TOP_IPE, ipe_parents, 0x02C, 16, 4, 23), + MUX_GATE(CLK_TOP_CAM, cam_parents, 0x02C, 24, 4, 31), + /* CLK_CFG_2 */ + MUX_GATE(CLK_TOP_CCU, ccu_parents, 0x038, 0, 4, 7), + MUX_GATE(CLK_TOP_IMG, img_parents, 0x038, 8, 4, 15), + MUX_GATE(CLK_TOP_CAMTM, camtm_parents, 0x038, 16, 2, 23), + MUX_GATE(CLK_TOP_DSP, dsp_parents, 0x038, 24, 3, 31), + /* CLK_CFG_3 */ + MUX_GATE(CLK_TOP_DSP1, dsp1_parents, 0x044, 0, 3, 7), + MUX_GATE(CLK_TOP_DSP2, dsp1_parents, 0x044, 8, 3, 15), + MUX_GATE(CLK_TOP_DSP3, dsp1_parents, 0x044, 16, 3, 23), + MUX_GATE(CLK_TOP_DSP4, dsp2_parents, 0x044, 24, 3, 31), + /* CLK_CFG_4 */ + MUX_GATE(CLK_TOP_DSP5, dsp2_parents, 0x050, 0, 3, 7), + MUX_GATE(CLK_TOP_DSP6, dsp2_parents, 0x050, 8, 3, 15), + MUX_GATE(CLK_TOP_DSP7, dsp_parents, 0x050, 16, 3, 23), + MUX_GATE(CLK_TOP_IPU_IF, ipu_if_parents, 0x050, 24, 3, 31), + /* CLK_CFG_5 */ + MUX_GATE(CLK_TOP_MFG_CORE_TMP, mfg_parents, 0x05C, 0, 2, 7), + MUX_GATE(CLK_TOP_CAMTG, camtg_parents, 0x05C, 8, 3, 15), + MUX_GATE(CLK_TOP_CAMTG2, camtg_parents, 0x05C, 16, 3, 23), + MUX_GATE(CLK_TOP_CAMTG3, camtg_parents, 0x05C, 24, 3, 31), + /* CLK_CFG_6 */ + MUX_GATE(CLK_TOP_CAMTG4, camtg_parents, 0x068, 0, 3, 7), + MUX_GATE(CLK_TOP_CAMTG5, camtg_parents, 0x068, 8, 3, 15), + MUX_GATE(CLK_TOP_UART, uart_parents, 0x068, 16, 1, 23), + MUX_GATE(CLK_TOP_SPI, spi_parents, 0x068, 24, 3, 31), + /* CLK_CFG_7 */ + MUX_GATE(CLK_TOP_SPIS, spis_parents, 0x074, 0, 3, 7), + MUX_GATE(CLK_TOP_MSDC50_0_HCLK, msdc50_0_h_parents, 0x074, 8, 2, 15), + MUX_GATE(CLK_TOP_MSDC50_0, msdc50_0_parents, 0x074, 16, 3, 23), + MUX_GATE(CLK_TOP_MSDC30_1, msdc30_parents, 0x074, 24, 3, 31), + /* CLK_CFG_8 */ + MUX_GATE(CLK_TOP_MSDC30_2, msdc30_parents, 0x080, 0, 3, 7), + MUX_GATE(CLK_TOP_INTDIR, intdir_parents, 0x080, 8, 2, 15), + MUX_GATE(CLK_TOP_AUD_INTBUS, aud_intbus_parents, 0x080, 16, 2, 23), + MUX_GATE(CLK_TOP_AUDIO_H, audio_h_parents, 0x080, 24, 2, 31), + /* CLK_CFG_9 */ + MUX_GATE(CLK_TOP_PWRAP_ULPOSC, pwrap_ulposc_parents, 0x08C, 0, 3, 7), + MUX_GATE(CLK_TOP_ATB, atb_parents, 0x08C, 8, 2, 15), + MUX_GATE(CLK_TOP_PWRMCU, pwrmcu_parents, 0x08C, 16, 3, 23), + MUX_GATE(CLK_TOP_DP, dp_parents, 0x08C, 24, 4, 31), + /* CLK_CFG_10 */ + MUX_GATE(CLK_TOP_EDP, dp_parents, 0x098, 0, 4, 7), + MUX_GATE(CLK_TOP_DPI, dp_parents, 0x098, 8, 4, 15), + MUX_GATE(CLK_TOP_DISP_PWM0, disp_pwm_parents, 0x098, 16, 3, 23), + MUX_GATE(CLK_TOP_DISP_PWM1, disp_pwm_parents, 0x098, 24, 3, 31), + /* CLK_CFG_11 */ + MUX_GATE(CLK_TOP_USB_TOP, usb_parents, 0x0A4, 0, 2, 7), + MUX_GATE(CLK_TOP_SSUSB_XHCI, usb_parents, 0x0A4, 8, 2, 15), + MUX_GATE(CLK_TOP_USB_TOP_1P, usb_parents, 0x0A4, 16, 2, 23), + MUX_GATE(CLK_TOP_SSUSB_XHCI_1P, usb_parents, 0x0A4, 24, 2, 31), + /* CLK_CFG_12 */ + MUX_GATE(CLK_TOP_USB_TOP_2P, usb_parents, 0x0B0, 0, 2, 7), + MUX_GATE(CLK_TOP_SSUSB_XHCI_2P, usb_parents, 0x0B0, 8, 2, 15), + MUX_GATE(CLK_TOP_USB_TOP_3P, usb_parents, 0x0B0, 16, 2, 23), + MUX_GATE(CLK_TOP_SSUSB_XHCI_3P, usb_parents, 0x0B0, 24, 2, 31), + /* CLK_CFG_13 */ + MUX_GATE(CLK_TOP_I2C, i2c_parents, 0x0BC, 0, 2, 7), + MUX_GATE(CLK_TOP_SENINF, seninf_parents, 0x0BC, 8, 3, 15), + MUX_GATE(CLK_TOP_SENINF1, seninf_parents, 0x0BC, 16, 3, 23), + MUX_GATE(CLK_TOP_SENINF2, seninf_parents, 0x0BC, 24, 3, 31), + /* CLK_CFG_14 */ + MUX_GATE(CLK_TOP_SENINF3, seninf_parents, 0x0C8, 0, 3, 7), + MUX_GATE(CLK_TOP_GCPU, gcpu_parents, 0x0C8, 8, 3, 15), + MUX_GATE(CLK_TOP_DXCC, dxcc_parents, 0x0C8, 16, 2, 23), + MUX_GATE(CLK_TOP_DPMAIF_MAIN, dpmaif_parents, 0x0C8, 24, 3, 31), + /* CLK_CFG_15 */ + MUX_GATE(CLK_TOP_AES_UFSFDE, aes_fde_parents, 0x0D4, 0, 3, 7), + MUX_GATE(CLK_TOP_UFS, ufs_parents, 0x0D4, 8, 3, 15), + MUX_GATE(CLK_TOP_UFS_TICK1US, ufs_tick1us_parents, 0x0D4, 16, 1, 23), + MUX_GATE(CLK_TOP_UFS_MP_SAP_CFG, ufs_mp_sap_parents, 0x0D4, 24, 1, 31), + /* CLK_CFG_16 */ + MUX_GATE(CLK_TOP_VENC, venc_parents, 0x0E0, 0, 4, 7), + MUX_GATE(CLK_TOP_VDEC, vdec_parents, 0x0E0, 8, 4, 15), + MUX_GATE(CLK_TOP_PWM, pwm_parents, 0x0E0, 16, 1, 23), + MUX_GATE(CLK_TOP_MCUPM, mcupm_parents, 0x0E0, 24, 2, 31), + /* CLK_CFG_17 */ + MUX_GATE(CLK_TOP_SPMI_P_MST, spmi_parents, 0x0EC, 0, 4, 7), + MUX_GATE(CLK_TOP_SPMI_M_MST, spmi_parents, 0x0EC, 8, 4, 15), + MUX_GATE(CLK_TOP_DVFSRC, dvfsrc_parents, 0x0EC, 16, 2, 23), + MUX_GATE(CLK_TOP_TL, tl_parents, 0x0EC, 24, 2, 31), + /* CLK_CFG_18 */ + MUX_GATE(CLK_TOP_TL_P1, tl_parents, 0x0F8, 0, 2, 7), + MUX_GATE(CLK_TOP_AES_MSDCFDE, aes_fde_parents, 0x0F8, 8, 3, 15), + MUX_GATE(CLK_TOP_DSI_OCC, dsi_occ_parents, 0x0F8, 16, 2, 23), + MUX_GATE(CLK_TOP_WPE_VPP, wpe_vpp_parents, 0x0F8, 24, 4, 31), + /* CLK_CFG_19 */ + MUX_GATE(CLK_TOP_HDCP, hdcp_parents, 0x0104, 0, 2, 7), + MUX_GATE(CLK_TOP_HDCP_24M, hdcp_24m_parents, 0x0104, 8, 2, 15), + MUX_GATE(CLK_TOP_HD20_DACR_REF_CLK, hd20_dacr_ref_parents, 0x0104, 16, 2, 23), + MUX_GATE(CLK_TOP_HD20_HDCP_CCLK, hd20_hdcp_c_parents, 0x0104, 24, 2, 31), + /* CLK_CFG_20 */ + MUX_GATE(CLK_TOP_HDMI_XTAL, hdmi_xtal_parents, 0x0110, 0, 1, 7), + MUX_GATE(CLK_TOP_HDMI_APB, hdmi_apb_parents, 0x0110, 8, 2, 15), + MUX_GATE(CLK_TOP_SNPS_ETH_250M, snps_eth_250m_parents, 0x0110, 16, 1, 23), + MUX_GATE(CLK_TOP_SNPS_ETH_62P4M_PTP, snps_eth_62p4m_ptp_parents, 0x0110, 24, 2, 31), + /* CLK_CFG_21 */ + MUX_GATE(CLK_TOP_SNPS_ETH_50M_RMII, snps_eth_50m_rmii_parents, 0x011C, 0, 1, 7), + MUX_GATE(CLK_TOP_DGI_OUT, dgi_out_parents, 0x011C, 8, 3, 15), + MUX_GATE(CLK_TOP_NNA0, nna_parents, 0x011C, 16, 4, 23), + MUX_GATE(CLK_TOP_NNA1, nna_parents, 0x011C, 24, 4, 31), + /* CLK_CFG_22 */ + MUX_GATE(CLK_TOP_ADSP, adsp_parents, 0x0128, 0, 4, 7), + MUX_GATE(CLK_TOP_ASM_H, asm_parents, 0x0128, 8, 2, 15), + MUX_GATE(CLK_TOP_ASM_M, asm_parents, 0x0128, 16, 2, 23), + MUX_GATE(CLK_TOP_ASM_L, asm_parents, 0x0128, 24, 2, 31), + /* CLK_CFG_23 */ + MUX_GATE(CLK_TOP_APLL1, apll1_parents, 0x0134, 0, 1, 7), + MUX_GATE(CLK_TOP_APLL2, apll2_parents, 0x0134, 8, 1, 15), + MUX_GATE(CLK_TOP_APLL3, apll3_parents, 0x0134, 16, 1, 23), + MUX_GATE(CLK_TOP_APLL4, apll4_parents, 0x0134, 24, 1, 31), + /* + * CLK_CFG_24 + * i2so4_mck is not used in MT8195. + */ + MUX_GATE(CLK_TOP_APLL5, apll5_parents, 0x0140, 0, 1, 7), + MUX_GATE(CLK_TOP_I2SO1_MCK, i2s_parents, 0x0140, 8, 3, 15), + MUX_GATE(CLK_TOP_I2SO2_MCK, i2s_parents, 0x0140, 16, 3, 23), + /* + * CLK_CFG_25 + * i2so5_mck and i2si4_mck are not used in MT8195. + */ + MUX_GATE(CLK_TOP_I2SI1_MCK, i2s_parents, 0x014C, 8, 3, 15), + MUX_GATE(CLK_TOP_I2SI2_MCK, i2s_parents, 0x014C, 16, 3, 23), + /* + * CLK_CFG_26 + * i2si5_mck is not used in MT8195. + */ + MUX_GATE(CLK_TOP_DPTX_MCK, i2s_parents, 0x0158, 8, 3, 15), + MUX_GATE(CLK_TOP_AUD_IEC_CLK, i2s_parents, 0x0158, 16, 3, 23), + MUX_GATE(CLK_TOP_A1SYS_HP, a1sys_hp_parents, 0x0158, 24, 1, 31), + /* CLK_CFG_27 */ + MUX_GATE(CLK_TOP_A2SYS_HF, a2sys_parents, 0x0164, 0, 1, 7), + MUX_GATE(CLK_TOP_A3SYS_HF, a3sys_parents, 0x0164, 8, 3, 15), + MUX_GATE(CLK_TOP_A4SYS_HF, a3sys_parents, 0x0164, 16, 3, 23), + MUX_GATE(CLK_TOP_SPINFI_BCLK, spinfi_b_parents, 0x0164, 24, 3, 31), + /* CLK_CFG_28 */ + MUX_GATE(CLK_TOP_NFI1X, nfi1x_parents, 0x0170, 0, 3, 7), + MUX_GATE(CLK_TOP_ECC, ecc_parents, 0x0170, 8, 3, 15), + MUX_GATE(CLK_TOP_AUDIO_LOCAL_BUS, audio_local_bus_parents, 0x0170, 16, 4, 23), + MUX_GATE(CLK_TOP_SPINOR, spinor_parents, 0x0170, 24, 2, 31), + /* CLK_CFG_29 */ + MUX_GATE(CLK_TOP_DVIO_DGI_REF, dvio_dgi_ref_parents, 0x017C, 0, 3, 7), + MUX_GATE(CLK_TOP_ULPOSC, ulposc_parents, 0x017C, 8, 2, 15), + MUX_GATE(CLK_TOP_ULPOSC_CORE, ulposc_core_parents, 0x017C, 16, 2, 23), + MUX_GATE(CLK_TOP_SRCK, srck_parents, 0x017C, 24, 1, 31), +}; + +static const struct mtk_gate_regs top0_cg_regs = { + .set_ofs = 0x238, + .clr_ofs = 0x238, + .sta_ofs = 0x238, +}; + +static const struct mtk_gate_regs top1_cg_regs = { + .set_ofs = 0x250, + .clr_ofs = 0x250, + .sta_ofs = 0x250, +}; + +#define GATE_TOP0(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &top0_cg_regs, _shift, \ + CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN) + +#define GATE_TOP0E(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &top0_cg_regs, _shift, \ + CLK_GATE_NO_SETCLR_INV | CLK_PARENT_EXT) + +#define GATE_TOP1(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &top1_cg_regs, _shift, \ + CLK_GATE_NO_SETCLR_INV | CLK_PARENT_EXT) + +static const struct mtk_gate top_cg_clks[] = { + /* TOP0 */ + GATE_TOP0(CLK_TOP_CFG_VPP0, CLK_TOP_VPP, 0), + GATE_TOP0(CLK_TOP_CFG_VPP1, CLK_TOP_VPP, 1), + GATE_TOP0(CLK_TOP_CFG_VDO0, CLK_TOP_VPP, 2), + GATE_TOP0(CLK_TOP_CFG_VDO1, CLK_TOP_VPP, 3), + GATE_TOP0(CLK_TOP_CFG_UNIPLL_SES, CLK_TOP_UNIVPLL_D2, 4), + GATE_TOP0E(CLK_TOP_CFG_26M_VPP0, CLK_PAD_CLK26M, 5), + GATE_TOP0E(CLK_TOP_CFG_26M_VPP1, CLK_PAD_CLK26M, 6), + GATE_TOP0E(CLK_TOP_CFG_26M_AUD, CLK_PAD_CLK26M, 9), + /* + * cfg_axi_east, cfg_axi_east_north, cfg_axi_north and cfg_axi_south + * are peripheral bus clock branches. + */ + GATE_TOP0(CLK_TOP_CFG_AXI_EAST, CLK_TOP_AXI, 10), + GATE_TOP0(CLK_TOP_CFG_AXI_EAST_NORTH, CLK_TOP_AXI, 11), + GATE_TOP0(CLK_TOP_CFG_AXI_NORTH, CLK_TOP_AXI, 12), + GATE_TOP0(CLK_TOP_CFG_AXI_SOUTH, CLK_TOP_AXI, 13), + GATE_TOP0(CLK_TOP_CFG_EXT_TEST, CLK_TOP_MSDCPLL_D2, 15), + /* TOP1 */ + GATE_TOP1(CLK_TOP_SSUSB_REF, CLK_PAD_CLK26M, 0), + GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, CLK_PAD_CLK26M, 1), + GATE_TOP1(CLK_TOP_SSUSB_P1_REF, CLK_PAD_CLK26M, 2), + GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, CLK_PAD_CLK26M, 3), + GATE_TOP1(CLK_TOP_SSUSB_P2_REF, CLK_PAD_CLK26M, 4), + GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, CLK_PAD_CLK26M, 5), + GATE_TOP1(CLK_TOP_SSUSB_P3_REF, CLK_PAD_CLK26M, 6), + GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, CLK_PAD_CLK26M, 7), +}; + +static const int mt8195_id_top_offs_map[] = { + [0 ... CLK_TOP_NR_CLK - 1] = -1, + /* FIXED */ + [CLK_TOP_IN_DGI] = 0, + [CLK_TOP_ULPOSC1] = 1, + [CLK_TOP_ULPOSC2] = 2, + [CLK_TOP_MEM_466M] = 3, + [CLK_TOP_MPHONE_SLAVE_B] = 4, + [CLK_TOP_PEXTP_PIPE] = 5, + [CLK_TOP_UFS_RX_SYMBOL] = 6, + [CLK_TOP_UFS_TX_SYMBOL] = 7, + [CLK_TOP_SSUSB_U3PHY_P1_P_P0] = 8, + [CLK_TOP_UFS_RX_SYMBOL1] = 9, + [CLK_TOP_FPC] = 10, + [CLK_TOP_HDMIRX_P] = 11, + /* FACTOR */ + [CLK_TOP_CLK26M_D2] = 12, + [CLK_TOP_CLK26M_D52] = 13, + [CLK_TOP_IN_DGI_D2] = 14, + [CLK_TOP_IN_DGI_D4] = 15, + [CLK_TOP_IN_DGI_D6] = 16, + [CLK_TOP_IN_DGI_D8] = 17, + [CLK_TOP_MAINPLL_D3] = 18, + [CLK_TOP_MAINPLL_D4] = 19, + [CLK_TOP_MAINPLL_D4_D2] = 20, + [CLK_TOP_MAINPLL_D4_D4] = 21, + [CLK_TOP_MAINPLL_D4_D8] = 22, + [CLK_TOP_MAINPLL_D5] = 23, + [CLK_TOP_MAINPLL_D5_D2] = 24, + [CLK_TOP_MAINPLL_D5_D4] = 25, + [CLK_TOP_MAINPLL_D5_D8] = 26, + [CLK_TOP_MAINPLL_D6] = 27, + [CLK_TOP_MAINPLL_D6_D2] = 28, + [CLK_TOP_MAINPLL_D6_D4] = 29, + [CLK_TOP_MAINPLL_D6_D8] = 30, + [CLK_TOP_MAINPLL_D7] = 31, + [CLK_TOP_MAINPLL_D7_D2] = 32, + [CLK_TOP_MAINPLL_D7_D4] = 33, + [CLK_TOP_MAINPLL_D7_D8] = 34, + [CLK_TOP_MAINPLL_D9] = 35, + [CLK_TOP_UNIVPLL_D2] = 36, + [CLK_TOP_UNIVPLL_D3] = 37, + [CLK_TOP_UNIVPLL_D4] = 38, + [CLK_TOP_UNIVPLL_D4_D2] = 39, + [CLK_TOP_UNIVPLL_D4_D4] = 40, + [CLK_TOP_UNIVPLL_D4_D8] = 41, + [CLK_TOP_UNIVPLL_D5] = 42, + [CLK_TOP_UNIVPLL_D5_D2] = 43, + [CLK_TOP_UNIVPLL_D5_D4] = 44, + [CLK_TOP_UNIVPLL_D5_D8] = 45, + [CLK_TOP_UNIVPLL_D6] = 46, + [CLK_TOP_UNIVPLL_D6_D2] = 47, + [CLK_TOP_UNIVPLL_D6_D4] = 48, + [CLK_TOP_UNIVPLL_D6_D8] = 49, + [CLK_TOP_UNIVPLL_D6_D16] = 50, + [CLK_TOP_UNIVPLL_D7] = 51, + [CLK_TOP_UNIVPLL_192M] = 52, + [CLK_TOP_UNIVPLL_192M_D4] = 53, + [CLK_TOP_UNIVPLL_192M_D8] = 54, + [CLK_TOP_UNIVPLL_192M_D16] = 55, + [CLK_TOP_UNIVPLL_192M_D32] = 56, + [CLK_TOP_APLL1_D3] = 57, + [CLK_TOP_APLL1_D4] = 58, + [CLK_TOP_APLL2_D3] = 59, + [CLK_TOP_APLL2_D4] = 60, + [CLK_TOP_APLL3_D4] = 61, + [CLK_TOP_APLL4_D4] = 62, + [CLK_TOP_APLL5_D4] = 63, + [CLK_TOP_HDMIRX_APLL_D3] = 64, + [CLK_TOP_HDMIRX_APLL_D4] = 65, + [CLK_TOP_HDMIRX_APLL_D6] = 66, + [CLK_TOP_MMPLL_D4] = 67, + [CLK_TOP_MMPLL_D4_D2] = 68, + [CLK_TOP_MMPLL_D4_D4] = 69, + [CLK_TOP_MMPLL_D5] = 70, + [CLK_TOP_MMPLL_D5_D2] = 71, + [CLK_TOP_MMPLL_D5_D4] = 72, + [CLK_TOP_MMPLL_D6] = 73, + [CLK_TOP_MMPLL_D6_D2] = 74, + [CLK_TOP_MMPLL_D7] = 75, + [CLK_TOP_MMPLL_D9] = 76, + [CLK_TOP_TVDPLL1_D2] = 77, + [CLK_TOP_TVDPLL1_D4] = 78, + [CLK_TOP_TVDPLL1_D8] = 79, + [CLK_TOP_TVDPLL1_D16] = 80, + [CLK_TOP_TVDPLL2_D2] = 81, + [CLK_TOP_TVDPLL2_D4] = 82, + [CLK_TOP_TVDPLL2_D8] = 83, + [CLK_TOP_TVDPLL2_D16] = 84, + [CLK_TOP_MSDCPLL_D2] = 85, + [CLK_TOP_MSDCPLL_D4] = 86, + [CLK_TOP_MSDCPLL_D16] = 87, + [CLK_TOP_ETHPLL_D2] = 88, + [CLK_TOP_ETHPLL_D8] = 89, + [CLK_TOP_ETHPLL_D10] = 90, + [CLK_TOP_DGIPLL_D2] = 91, + [CLK_TOP_ULPOSC1_D2] = 92, + [CLK_TOP_ULPOSC1_D4] = 93, + [CLK_TOP_ULPOSC1_D7] = 94, + [CLK_TOP_ULPOSC1_D8] = 95, + [CLK_TOP_ULPOSC1_D10] = 96, + [CLK_TOP_ULPOSC1_D16] = 97, + [CLK_TOP_ADSPPLL_D2] = 98, + [CLK_TOP_ADSPPLL_D4] = 99, + [CLK_TOP_ADSPPLL_D8] = 100, + /* MUX */ + [CLK_TOP_AXI] = 101, + [CLK_TOP_SPM] = 102, + [CLK_TOP_SCP] = 103, + [CLK_TOP_BUS_AXIMEM] = 104, + [CLK_TOP_VPP] = 105, + [CLK_TOP_ETHDR] = 106, + [CLK_TOP_IPE] = 107, + [CLK_TOP_CAM] = 108, + [CLK_TOP_CCU] = 109, + [CLK_TOP_IMG] = 110, + [CLK_TOP_CAMTM] = 111, + [CLK_TOP_DSP] = 112, + [CLK_TOP_DSP1] = 113, + [CLK_TOP_DSP2] = 114, + [CLK_TOP_DSP3] = 115, + [CLK_TOP_DSP4] = 116, + [CLK_TOP_DSP5] = 117, + [CLK_TOP_DSP6] = 118, + [CLK_TOP_DSP7] = 119, + [CLK_TOP_IPU_IF] = 120, + [CLK_TOP_MFG_CORE_TMP] = 121, + [CLK_TOP_CAMTG] = 122, + [CLK_TOP_CAMTG2] = 123, + [CLK_TOP_CAMTG3] = 124, + [CLK_TOP_CAMTG4] = 125, + [CLK_TOP_CAMTG5] = 126, + [CLK_TOP_UART] = 127, + [CLK_TOP_SPI] = 128, + [CLK_TOP_SPIS] = 129, + [CLK_TOP_MSDC50_0_HCLK] = 130, + [CLK_TOP_MSDC50_0] = 131, + [CLK_TOP_MSDC30_1] = 132, + [CLK_TOP_MSDC30_2] = 133, + [CLK_TOP_INTDIR] = 134, + [CLK_TOP_AUD_INTBUS] = 135, + [CLK_TOP_AUDIO_H] = 136, + [CLK_TOP_PWRAP_ULPOSC] = 137, + [CLK_TOP_ATB] = 138, + [CLK_TOP_PWRMCU] = 139, + [CLK_TOP_DP] = 140, + [CLK_TOP_EDP] = 141, + [CLK_TOP_DPI] = 142, + [CLK_TOP_DISP_PWM0] = 143, + [CLK_TOP_DISP_PWM1] = 144, + [CLK_TOP_USB_TOP] = 145, + [CLK_TOP_SSUSB_XHCI] = 146, + [CLK_TOP_USB_TOP_1P] = 147, + [CLK_TOP_SSUSB_XHCI_1P] = 148, + [CLK_TOP_USB_TOP_2P] = 149, + [CLK_TOP_SSUSB_XHCI_2P] = 150, + [CLK_TOP_USB_TOP_3P] = 151, + [CLK_TOP_SSUSB_XHCI_3P] = 152, + [CLK_TOP_I2C] = 153, + [CLK_TOP_SENINF] = 154, + [CLK_TOP_SENINF1] = 155, + [CLK_TOP_SENINF2] = 156, + [CLK_TOP_SENINF3] = 157, + [CLK_TOP_GCPU] = 158, + [CLK_TOP_DXCC] = 159, + [CLK_TOP_DPMAIF_MAIN] = 160, + [CLK_TOP_AES_UFSFDE] = 161, + [CLK_TOP_UFS] = 162, + [CLK_TOP_UFS_TICK1US] = 163, + [CLK_TOP_UFS_MP_SAP_CFG] = 164, + [CLK_TOP_VENC] = 165, + [CLK_TOP_VDEC] = 166, + [CLK_TOP_PWM] = 167, + [CLK_TOP_MCUPM] = 168, + [CLK_TOP_SPMI_P_MST] = 169, + [CLK_TOP_SPMI_M_MST] = 170, + [CLK_TOP_DVFSRC] = 171, + [CLK_TOP_TL] = 172, + [CLK_TOP_TL_P1] = 173, + [CLK_TOP_AES_MSDCFDE] = 174, + [CLK_TOP_DSI_OCC] = 175, + [CLK_TOP_WPE_VPP] = 176, + [CLK_TOP_HDCP] = 177, + [CLK_TOP_HDCP_24M] = 178, + [CLK_TOP_HD20_DACR_REF_CLK] = 179, + [CLK_TOP_HD20_HDCP_CCLK] = 180, + [CLK_TOP_HDMI_XTAL] = 181, + [CLK_TOP_HDMI_APB] = 182, + [CLK_TOP_SNPS_ETH_250M] = 183, + [CLK_TOP_SNPS_ETH_62P4M_PTP] = 184, + [CLK_TOP_SNPS_ETH_50M_RMII] = 185, + [CLK_TOP_DGI_OUT] = 186, + [CLK_TOP_NNA0] = 187, + [CLK_TOP_NNA1] = 188, + [CLK_TOP_ADSP] = 189, + [CLK_TOP_ASM_H] = 190, + [CLK_TOP_ASM_M] = 191, + [CLK_TOP_ASM_L] = 192, + [CLK_TOP_APLL1] = 193, + [CLK_TOP_APLL2] = 194, + [CLK_TOP_APLL3] = 195, + [CLK_TOP_APLL4] = 196, + [CLK_TOP_APLL5] = 197, + [CLK_TOP_I2SO1_MCK] = 198, + [CLK_TOP_I2SO2_MCK] = 199, + [CLK_TOP_I2SI1_MCK] = 200, + [CLK_TOP_I2SI2_MCK] = 201, + [CLK_TOP_DPTX_MCK] = 202, + [CLK_TOP_AUD_IEC_CLK] = 203, + [CLK_TOP_A1SYS_HP] = 204, + [CLK_TOP_A2SYS_HF] = 205, + [CLK_TOP_A3SYS_HF] = 206, + [CLK_TOP_A4SYS_HF] = 207, + [CLK_TOP_SPINFI_BCLK] = 208, + [CLK_TOP_NFI1X] = 209, + [CLK_TOP_ECC] = 210, + [CLK_TOP_AUDIO_LOCAL_BUS] = 211, + [CLK_TOP_SPINOR] = 212, + [CLK_TOP_DVIO_DGI_REF] = 213, + [CLK_TOP_ULPOSC] = 214, + [CLK_TOP_ULPOSC_CORE] = 215, + [CLK_TOP_SRCK] = 216, + /* GATE */ + [CLK_TOP_CFG_VPP0] = 217, + [CLK_TOP_CFG_VPP1] = 218, + [CLK_TOP_CFG_VDO0] = 219, + [CLK_TOP_CFG_VDO1] = 220, + [CLK_TOP_CFG_UNIPLL_SES] = 221, + [CLK_TOP_CFG_26M_VPP0] = 222, + [CLK_TOP_CFG_26M_VPP1] = 223, + [CLK_TOP_CFG_26M_AUD] = 224, + [CLK_TOP_CFG_AXI_EAST] = 225, + [CLK_TOP_CFG_AXI_EAST_NORTH] = 226, + [CLK_TOP_CFG_AXI_NORTH] = 227, + [CLK_TOP_CFG_AXI_SOUTH] = 228, + [CLK_TOP_CFG_EXT_TEST] = 229, + [CLK_TOP_SSUSB_REF] = 230, + [CLK_TOP_SSUSB_PHY_REF] = 231, + [CLK_TOP_SSUSB_P1_REF] = 232, + [CLK_TOP_SSUSB_PHY_P1_REF] = 233, + [CLK_TOP_SSUSB_P2_REF] = 234, + [CLK_TOP_SSUSB_PHY_P2_REF] = 235, + [CLK_TOP_SSUSB_P3_REF] = 236, + [CLK_TOP_SSUSB_PHY_P3_REF] = 237, +}; + +static const struct mtk_clk_tree mt8195_topckgen_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), + .id_offs_map = mt8195_id_top_offs_map, + .id_offs_map_size = ARRAY_SIZE(mt8195_id_top_offs_map), + .fdivs_offs = mt8195_id_top_offs_map[CLK_TOP_CLK26M_D2], + .muxes_offs = mt8195_id_top_offs_map[CLK_TOP_AXI], + .gates_offs = mt8195_id_top_offs_map[CLK_TOP_CFG_VPP0], + .fclks = top_fixed_clks, + .fdivs = top_fixed_divs, + .muxes = top_muxes, + .gates = top_cg_clks, + .num_fclks = ARRAY_SIZE(top_fixed_clks), + .num_fdivs = ARRAY_SIZE(top_fixed_divs), + .num_muxes = ARRAY_SIZE(top_muxes), + .num_gates = ARRAY_SIZE(top_cg_clks), +}; + +static const struct mtk_gate_regs infra_ao0_cg_regs = { + .set_ofs = 0x80, + .clr_ofs = 0x84, + .sta_ofs = 0x90, +}; + +static const struct mtk_gate_regs infra_ao1_cg_regs = { + .set_ofs = 0x88, + .clr_ofs = 0x8c, + .sta_ofs = 0x94, +}; + +static const struct mtk_gate_regs infra_ao2_cg_regs = { + .set_ofs = 0xa4, + .clr_ofs = 0xa8, + .sta_ofs = 0xac, +}; + +static const struct mtk_gate_regs infra_ao3_cg_regs = { + .set_ofs = 0xc0, + .clr_ofs = 0xc4, + .sta_ofs = 0xc8, +}; + +static const struct mtk_gate_regs infra_ao4_cg_regs = { + .set_ofs = 0xe0, + .clr_ofs = 0xe4, + .sta_ofs = 0xe8, +}; + +#define GATE_INFRA_AO0(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &infra_ao0_cg_regs, _shift,\ + CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) + +#define GATE_INFRA_AO0E(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &infra_ao0_cg_regs, _shift,\ + CLK_PARENT_EXT | CLK_GATE_SETCLR) + +#define GATE_INFRA_AO1(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &infra_ao1_cg_regs, _shift,\ + CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) + +#define GATE_INFRA_AO1E(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &infra_ao1_cg_regs, _shift,\ + CLK_PARENT_EXT | CLK_GATE_SETCLR) + +#define GATE_INFRA_AO2(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &infra_ao2_cg_regs, _shift,\ + CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) + +#define GATE_INFRA_AO2E(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &infra_ao2_cg_regs, _shift,\ + CLK_PARENT_EXT | CLK_GATE_SETCLR) + +#define GATE_INFRA_AO3(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &infra_ao3_cg_regs, _shift,\ + CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) + +#define GATE_INFRA_AO3E(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &infra_ao3_cg_regs, _shift,\ + CLK_PARENT_EXT | CLK_GATE_SETCLR) + +#define GATE_INFRA_AO4(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &infra_ao4_cg_regs, _shift,\ + CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) + +static const struct mtk_gate infra_ao_clks[] = { + /* INFRA_AO0 */ + GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_TMR, CLK_TOP_PWRAP_ULPOSC, 0), + GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_AP, CLK_TOP_PWRAP_ULPOSC, 1), + GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_MD, CLK_TOP_PWRAP_ULPOSC, 2), + GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_CONN, CLK_TOP_PWRAP_ULPOSC, 3), + GATE_INFRA_AO0(CLK_INFRA_AO_SEJ, CLK_TOP_AXI, 5), + GATE_INFRA_AO0(CLK_INFRA_AO_APXGPT, CLK_TOP_AXI, 6), + GATE_INFRA_AO0(CLK_INFRA_AO_GCE, CLK_TOP_AXI, 8), + GATE_INFRA_AO0(CLK_INFRA_AO_GCE2, CLK_TOP_AXI, 9), + GATE_INFRA_AO0(CLK_INFRA_AO_THERM, CLK_TOP_AXI, 10), + GATE_INFRA_AO0(CLK_INFRA_AO_PWM_H, CLK_TOP_AXI, 15), + GATE_INFRA_AO0(CLK_INFRA_AO_PWM1, CLK_TOP_PWM, 16), + GATE_INFRA_AO0(CLK_INFRA_AO_PWM2, CLK_TOP_PWM, 17), + GATE_INFRA_AO0(CLK_INFRA_AO_PWM3, CLK_TOP_PWM, 18), + GATE_INFRA_AO0(CLK_INFRA_AO_PWM4, CLK_TOP_PWM, 19), + GATE_INFRA_AO0(CLK_INFRA_AO_PWM, CLK_TOP_PWM, 21), + GATE_INFRA_AO0(CLK_INFRA_AO_UART0, CLK_TOP_UART, 22), + GATE_INFRA_AO0(CLK_INFRA_AO_UART1, CLK_TOP_UART, 23), + GATE_INFRA_AO0(CLK_INFRA_AO_UART2, CLK_TOP_UART, 24), + GATE_INFRA_AO0(CLK_INFRA_AO_UART3, CLK_TOP_UART, 25), + GATE_INFRA_AO0(CLK_INFRA_AO_UART4, CLK_TOP_UART, 26), + GATE_INFRA_AO0E(CLK_INFRA_AO_GCE_26M, CLK_PAD_CLK26M, 27), + GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, CLK_TOP_FPC, 28), + GATE_INFRA_AO0(CLK_INFRA_AO_UART5, CLK_TOP_UART, 29), + /* INFRA_AO1 */ + GATE_INFRA_AO1E(CLK_INFRA_AO_HDMI_26M, CLK_PAD_CLK26M, 0), + GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, CLK_TOP_SPI, 1), + GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, CLK_TOP_MSDC50_0_HCLK, 2), + GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, CLK_TOP_AXI, 4), + GATE_INFRA_AO1(CLK_INFRA_AO_CG1_MSDC2, CLK_TOP_AXI, 5), + GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0_SRC, CLK_TOP_MSDC50_0, 6), + GATE_INFRA_AO1(CLK_INFRA_AO_TRNG, CLK_TOP_AXI, 9), + GATE_INFRA_AO1E(CLK_INFRA_AO_AUXADC, CLK_PAD_CLK26M, 10), + GATE_INFRA_AO1(CLK_INFRA_AO_CPUM, CLK_TOP_AXI, 11), + GATE_INFRA_AO1E(CLK_INFRA_AO_HDMI_32K, CLK_PAD_CLK32K, 12), + GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_H, CLK_TOP_AXI, 13), + GATE_INFRA_AO1(CLK_INFRA_AO_IRRX, CLK_TOP_AXI, 14), + GATE_INFRA_AO1E(CLK_INFRA_AO_PCIE_TL_26M, CLK_PAD_CLK26M, 15), + GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1_SRC, CLK_TOP_MSDC30_1, 16), + GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_B, CLK_TOP_AXI, 17), + GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_96M, CLK_TOP_TL, 18), + GATE_INFRA_AO1(CLK_INFRA_AO_DEVICE_APC, CLK_TOP_AXI, 20), + GATE_INFRA_AO1(CLK_INFRA_AO_ECC_66M_H, CLK_TOP_AXI, 23), + GATE_INFRA_AO1(CLK_INFRA_AO_DEBUGSYS, CLK_TOP_AXI, 24), + GATE_INFRA_AO1(CLK_INFRA_AO_AUDIO, CLK_TOP_AXI, 25), + GATE_INFRA_AO1E(CLK_INFRA_AO_PCIE_TL_32K, CLK_PAD_CLK32K, 26), + GATE_INFRA_AO1(CLK_INFRA_AO_DBG_TRACE, CLK_TOP_AXI, 29), + GATE_INFRA_AO1E(CLK_INFRA_AO_DRAMC_F26M, CLK_PAD_CLK26M, 31), + /* INFRA_AO2 */ + GATE_INFRA_AO2(CLK_INFRA_AO_IRTX, CLK_TOP_AXI, 0), + GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB, CLK_TOP_USB_TOP, 1), + GATE_INFRA_AO2(CLK_INFRA_AO_DISP_PWM, CLK_TOP_DISP_PWM0, 2), + GATE_INFRA_AO2(CLK_INFRA_AO_CLDMA_B, CLK_TOP_AXI, 3), + GATE_INFRA_AO2E(CLK_INFRA_AO_AUDIO_26M_B, CLK_PAD_CLK26M, 4), + GATE_INFRA_AO2(CLK_INFRA_AO_SPI1, CLK_TOP_SPI, 6), + GATE_INFRA_AO2(CLK_INFRA_AO_SPI2, CLK_TOP_SPI, 9), + GATE_INFRA_AO2(CLK_INFRA_AO_SPI3, CLK_TOP_SPI, 10), + GATE_INFRA_AO2(CLK_INFRA_AO_UNIPRO_SYS, CLK_TOP_UFS, 11), + GATE_INFRA_AO2(CLK_INFRA_AO_UNIPRO_TICK, CLK_TOP_UFS_TICK1US, 12), + GATE_INFRA_AO2(CLK_INFRA_AO_UFS_MP_SAP_B, CLK_TOP_UFS_MP_SAP_CFG, 13), + GATE_INFRA_AO2(CLK_INFRA_AO_PWRMCU, CLK_TOP_PWRMCU, 15), + GATE_INFRA_AO2(CLK_INFRA_AO_PWRMCU_BUS_H, CLK_TOP_AXI, 17), + GATE_INFRA_AO2(CLK_INFRA_AO_APDMA_B, CLK_TOP_AXI, 18), + GATE_INFRA_AO2(CLK_INFRA_AO_SPI4, CLK_TOP_SPI, 25), + GATE_INFRA_AO2(CLK_INFRA_AO_SPI5, CLK_TOP_SPI, 26), + GATE_INFRA_AO2(CLK_INFRA_AO_CQ_DMA, CLK_TOP_AXI, 27), + GATE_INFRA_AO2(CLK_INFRA_AO_AES_UFSFDE, CLK_TOP_UFS, 28), + GATE_INFRA_AO2(CLK_INFRA_AO_AES, CLK_TOP_AES_UFSFDE, 29), + GATE_INFRA_AO2(CLK_INFRA_AO_UFS_TICK, CLK_TOP_UFS_TICK1US, 30), + GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_XHCI, CLK_TOP_SSUSB_XHCI, 31), + /* INFRA_AO3 */ + GATE_INFRA_AO3(CLK_INFRA_AO_MSDC0_SELF, CLK_TOP_MSDC50_0, 0), + GATE_INFRA_AO3(CLK_INFRA_AO_MSDC1_SELF, CLK_TOP_MSDC50_0, 1), + GATE_INFRA_AO3(CLK_INFRA_AO_MSDC2_SELF, CLK_TOP_MSDC50_0, 2), + GATE_INFRA_AO3(CLK_INFRA_AO_I2S_DMA, CLK_TOP_AXI, 5), + GATE_INFRA_AO3(CLK_INFRA_AO_AP_MSDC0, CLK_TOP_MSDC50_0, 7), + GATE_INFRA_AO3(CLK_INFRA_AO_MD_MSDC0, CLK_TOP_MSDC50_0, 8), + GATE_INFRA_AO3(CLK_INFRA_AO_CG3_MSDC2, CLK_TOP_MSDC30_2, 9), + GATE_INFRA_AO3(CLK_INFRA_AO_GCPU, CLK_TOP_GCPU, 10), + GATE_INFRA_AO3E(CLK_INFRA_AO_PCIE_PERI_26M, CLK_PAD_CLK26M, 15), + GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_66M_B, CLK_TOP_AXI, 16), + GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_133M_B, CLK_TOP_AXI, 17), + GATE_INFRA_AO3(CLK_INFRA_AO_DISP_PWM1, CLK_TOP_DISP_PWM1, 20), + GATE_INFRA_AO3(CLK_INFRA_AO_FBIST2FPC, CLK_TOP_MSDC50_0, 24), + GATE_INFRA_AO3(CLK_INFRA_AO_DEVICE_APC_SYNC, CLK_TOP_AXI, 25), + GATE_INFRA_AO3E(CLK_INFRA_AO_PCIE_P1_PERI_26M, CLK_PAD_CLK26M, 26), + GATE_INFRA_AO3(CLK_INFRA_AO_SPIS0, CLK_TOP_SPIS, 28), + GATE_INFRA_AO3(CLK_INFRA_AO_SPIS1, CLK_TOP_SPIS, 29), + /* INFRA_AO4 */ + GATE_INFRA_AO4(CLK_INFRA_AO_133M_M_PERI, CLK_TOP_AXI, 0), + GATE_INFRA_AO4(CLK_INFRA_AO_66M_M_PERI, CLK_TOP_AXI, 1), + GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_PL_P_250M_P0, CLK_TOP_PEXTP_PIPE, 7), + GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_PL_P_250M_P1, + CLK_TOP_SSUSB_U3PHY_P1_P_P0, 8), + GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_P1_TL_96M, CLK_TOP_TL_P1, 17), + GATE_INFRA_AO4(CLK_INFRA_AO_AES_MSDCFDE_0P, CLK_TOP_AES_MSDCFDE, 18), + GATE_INFRA_AO4(CLK_INFRA_AO_UFS_TX_SYMBOL, CLK_TOP_UFS_TX_SYMBOL, 22), + GATE_INFRA_AO4(CLK_INFRA_AO_UFS_RX_SYMBOL, CLK_TOP_UFS_RX_SYMBOL, 23), + GATE_INFRA_AO4(CLK_INFRA_AO_UFS_RX_SYMBOL1, CLK_TOP_UFS_RX_SYMBOL1, 24), + GATE_INFRA_AO4(CLK_INFRA_AO_PERI_UFS_MEM_SUB, CLK_TOP_MEM_466M, 31), +}; + +static const struct mtk_clk_tree mt8195_infracfg_ao_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), +}; + +static int mt8195_apmixedsys_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt8195_apmixedsys_clk_tree); +} + +static int mt8195_topckgen_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt8195_topckgen_clk_tree); +} + +static int mt8195_infra_ao_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt8195_infracfg_ao_clk_tree, + infra_ao_clks, + ARRAY_SIZE(infra_ao_clks), 0); +} + +static const struct udevice_id mt8195_apmixed[] = { + { .compatible = "mediatek,mt8195-apmixedsys", }, + { } +}; + +static const struct udevice_id mt8195_topckgen_compat[] = { + { .compatible = "mediatek,mt8195-topckgen", }, + { } +}; + +static const struct udevice_id of_match_clk_mt8195_infra_ao[] = { + { .compatible = "mediatek,mt8195-infracfg_ao", }, + { } +}; + +U_BOOT_DRIVER(mtk_clk_apmixedsys) = { + .name = "mt8195-apmixedsys", + .id = UCLASS_CLK, + .of_match = mt8195_apmixed, + .probe = mt8195_apmixedsys_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_apmixedsys_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_topckgen) = { + .name = "mt8195-topckgen", + .id = UCLASS_CLK, + .of_match = mt8195_topckgen_compat, + .probe = mt8195_topckgen_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_topckgen_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_infra_ao) = { + .name = "mt8195-infra_ao", + .id = UCLASS_CLK, + .of_match = of_match_clk_mt8195_infra_ao, + .probe = mt8195_infra_ao_probe, + .priv_auto = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index 6ba464097ae..eb94b86622c 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -13,9 +13,15 @@ #include <dt-bindings/clock/mediatek,mt8365-clk.h> #include "clk-mtk.h" -/* Missing topckgen clocks definition in dt-bindings */ -#define CLK_TOP_CLK26M 141 -#define CLK_TOP_CLK32K 142 +enum { + CLK_PAD_CLK32K, + CLK_PAD_CLK26M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK32K] = 32000, + [CLK_PAD_CLK26M] = 26000000, +}; /* apmixedsys */ #define MT8365_PLL_FMAX (3800UL * MHZ) @@ -45,9 +51,9 @@ static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001, PLL_AO, 22, 0x0310, 24, 0x0310, 0, 0, 0), - PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0xFF000001, HAVE_RST_BAR, 22, + PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0xFF000001, CLK_PLL_HAVE_RST_BAR, 22, 0x022C, 24, 0x022C, 0, CON0_MT8365_RST_BAR, 0), - PLL(CLK_APMIXED_UNIVPLL, 0x0208, 0x0214, 0xFF000001, HAVE_RST_BAR, 22, + PLL(CLK_APMIXED_UNIVPLL, 0x0208, 0x0214, 0xFF000001, CLK_PLL_HAVE_RST_BAR, 22, 0x020C, 24, 0x020C, 0, CON0_MT8365_RST_BAR, 0), PLL(CLK_APMIXED_MFGPLL, 0x0218, 0x0224, 0x00000001, 0, 22, 0x021C, 24, 0x021C, 0, 0, 0), @@ -68,161 +74,22 @@ static const struct mtk_pll_data apmixed_plls[] = { }; static const struct mtk_clk_tree mt8365_apmixed_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .plls = apmixed_plls, .num_plls = ARRAY_SIZE(apmixed_plls), }; /* topckgen */ -/* - * The devicetree bindings missed a few clocks and can't be changed, so we need - * to provide a mapping to fix the omissions. - */ -static const int mt8365_topckgen_id_map[] = { - [0 ... CLK_TOP_NR_CLK - 1] = -1, - /* FIXED */ - /* Fixed 32K oscillator is not available in devicetree definitions */ - [CLK_TOP_CLK32K] = 0, - [CLK_TOP_CLK_NULL] = 1, - [CLK_TOP_I2S0_BCK] = 2, - [CLK_TOP_DSI0_LNTC_DSICK] = 3, - [CLK_TOP_VPLL_DPIX] = 4, - [CLK_TOP_LVDSTX_CLKDIG_CTS] = 5, - /* FACTOR */ - [CLK_TOP_MFGPLL] = 6, - [CLK_TOP_SYSPLL_D2] = 7, - [CLK_TOP_SYSPLL1_D2] = 8, - [CLK_TOP_SYSPLL1_D4] = 9, - [CLK_TOP_SYSPLL1_D8] = 10, - [CLK_TOP_SYSPLL1_D16] = 11, - [CLK_TOP_SYSPLL_D3] = 12, - [CLK_TOP_SYSPLL2_D2] = 13, - [CLK_TOP_SYSPLL2_D4] = 14, - [CLK_TOP_SYSPLL2_D8] = 15, - [CLK_TOP_SYSPLL_D5] = 16, - [CLK_TOP_SYSPLL3_D2] = 17, - [CLK_TOP_SYSPLL3_D4] = 18, - [CLK_TOP_SYSPLL_D7] = 19, - [CLK_TOP_SYSPLL4_D2] = 20, - [CLK_TOP_SYSPLL4_D4] = 21, - /* Skipping CLK_TOP_UNIVPLL since isn't a real clock. */ - [CLK_TOP_UNIVPLL_D2] = 22, - [CLK_TOP_UNIVPLL1_D2] = 23, - [CLK_TOP_UNIVPLL1_D4] = 24, - [CLK_TOP_UNIVPLL_D3] = 25, - [CLK_TOP_UNIVPLL2_D2] = 26, - [CLK_TOP_UNIVPLL2_D4] = 27, - [CLK_TOP_UNIVPLL2_D8] = 28, - [CLK_TOP_UNIVPLL2_D32] = 29, - [CLK_TOP_UNIVPLL_D5] = 30, - [CLK_TOP_UNIVPLL3_D2] = 31, - [CLK_TOP_UNIVPLL3_D4] = 32, - [CLK_TOP_MMPLL] = 33, - [CLK_TOP_MMPLL_D2] = 34, - [CLK_TOP_LVDSPLL_D2] = 35, - [CLK_TOP_LVDSPLL_D4] = 36, - [CLK_TOP_LVDSPLL_D8] = 37, - [CLK_TOP_LVDSPLL_D16] = 38, - [CLK_TOP_USB20_192M] = 39, - [CLK_TOP_USB20_192M_D4] = 40, - [CLK_TOP_USB20_192M_D8] = 41, - [CLK_TOP_USB20_192M_D16] = 42, - [CLK_TOP_USB20_192M_D32] = 43, - [CLK_TOP_APLL1] = 44, - [CLK_TOP_APLL1_D2] = 45, - [CLK_TOP_APLL1_D4] = 46, - [CLK_TOP_APLL1_D8] = 47, - [CLK_TOP_APLL2] = 48, - [CLK_TOP_APLL2_D2] = 49, - [CLK_TOP_APLL2_D4] = 50, - [CLK_TOP_APLL2_D8] = 51, - /* Fixed 26M oscillator is not available in devicetree definitions */ - [CLK_TOP_CLK26M] = 52, - [CLK_TOP_SYS_26M_D2] = 53, - [CLK_TOP_MSDCPLL] = 54, - [CLK_TOP_MSDCPLL_D2] = 55, - [CLK_TOP_DSPPLL] = 56, - [CLK_TOP_DSPPLL_D2] = 57, - [CLK_TOP_DSPPLL_D4] = 58, - [CLK_TOP_DSPPLL_D8] = 59, - [CLK_TOP_APUPLL] = 60, - [CLK_TOP_CLK26M_D52] = 61, - /* MUX */ - [CLK_TOP_AXI_SEL] = 62, - [CLK_TOP_MEM_SEL] = 63, - [CLK_TOP_MM_SEL] = 64, - [CLK_TOP_SCP_SEL] = 65, - [CLK_TOP_MFG_SEL] = 66, - [CLK_TOP_ATB_SEL] = 67, - [CLK_TOP_CAMTG_SEL] = 68, - [CLK_TOP_CAMTG1_SEL] = 69, - [CLK_TOP_UART_SEL] = 70, - [CLK_TOP_SPI_SEL] = 71, - [CLK_TOP_MSDC50_0_HC_SEL] = 72, - [CLK_TOP_MSDC2_2_HC_SEL] = 73, - [CLK_TOP_MSDC50_0_SEL] = 74, - [CLK_TOP_MSDC50_2_SEL] = 75, - [CLK_TOP_MSDC30_1_SEL] = 76, - [CLK_TOP_AUDIO_SEL] = 77, - [CLK_TOP_AUD_INTBUS_SEL] = 78, - [CLK_TOP_AUD_1_SEL] = 79, - [CLK_TOP_AUD_2_SEL] = 80, - [CLK_TOP_AUD_ENGEN1_SEL] = 81, - [CLK_TOP_AUD_ENGEN2_SEL] = 82, - [CLK_TOP_AUD_SPDIF_SEL] = 83, - [CLK_TOP_DISP_PWM_SEL] = 84, - [CLK_TOP_DXCC_SEL] = 85, - [CLK_TOP_SSUSB_SYS_SEL] = 86, - [CLK_TOP_SSUSB_XHCI_SEL] = 87, - [CLK_TOP_SPM_SEL] = 88, - [CLK_TOP_I2C_SEL] = 89, - [CLK_TOP_PWM_SEL] = 90, - [CLK_TOP_SENIF_SEL] = 91, - [CLK_TOP_AES_FDE_SEL] = 92, - [CLK_TOP_CAMTM_SEL] = 93, - [CLK_TOP_DPI0_SEL] = 94, - [CLK_TOP_DPI1_SEL] = 95, - [CLK_TOP_DSP_SEL] = 96, - [CLK_TOP_NFI2X_SEL] = 97, - [CLK_TOP_NFIECC_SEL] = 98, - [CLK_TOP_ECC_SEL] = 99, - [CLK_TOP_ETH_SEL] = 100, - [CLK_TOP_GCPU_SEL] = 101, - [CLK_TOP_GCPU_CPM_SEL] = 102, - [CLK_TOP_APU_SEL] = 103, - [CLK_TOP_APU_IF_SEL] = 104, - /* GATE */ - [CLK_TOP_AUD_I2S0_M] = 105, - [CLK_TOP_AUD_I2S1_M] = 106, - [CLK_TOP_AUD_I2S2_M] = 107, - [CLK_TOP_AUD_I2S3_M] = 108, - [CLK_TOP_AUD_TDMOUT_M] = 109, - [CLK_TOP_AUD_TDMOUT_B] = 110, - [CLK_TOP_AUD_TDMIN_M] = 111, - [CLK_TOP_AUD_TDMIN_B] = 112, - [CLK_TOP_AUD_SPDIF_M] = 113, - [CLK_TOP_USB20_48M_EN] = 114, - [CLK_TOP_UNIVPLL_48M_EN] = 115, - [CLK_TOP_LVDSTX_CLKDIG_EN] = 116, - [CLK_TOP_VPLL_DPIX_EN] = 117, - [CLK_TOP_SSUSB_TOP_CK_EN] = 118, - [CLK_TOP_SSUSB_PHY_CK_EN] = 119, - [CLK_TOP_CONN_32K] = 120, - [CLK_TOP_CONN_26M] = 121, - [CLK_TOP_DSP_32K] = 122, - [CLK_TOP_DSP_26M] = 123, -}; - #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) #define FIXED_CLK1(_id, _rate) \ FIXED_CLK(_id, CLK_TOP_CLK_NULL, CLK_PARENT_TOPCKGEN, _rate) static const struct mtk_fixed_clk top_fixed_clks[] = { - FIXED_CLK0(CLK_TOP_CLK32K, 32000), FIXED_CLK0(CLK_TOP_CLK_NULL, 0), FIXED_CLK1(CLK_TOP_I2S0_BCK, 26000000), FIXED_CLK0(CLK_TOP_DSI0_LNTC_DSICK, 75000000), @@ -237,7 +104,7 @@ static const struct mtk_fixed_clk top_fixed_clks[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define PLL_FACTOR2(_id, _name, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) static const struct mtk_fixed_factor top_divs[] = { PLL_FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", CLK_APMIXED_MFGPLL, 1, 1), @@ -256,6 +123,7 @@ static const struct mtk_fixed_factor top_divs[] = { PLL_FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", CLK_APMIXED_MAINPLL, 1, 7), PLL_FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", CLK_APMIXED_MAINPLL, 1, 14), PLL_FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", CLK_APMIXED_MAINPLL, 1, 28), + PLL_FACTOR(CLK_TOP_UNIVPLL, "univpll", CLK_APMIXED_UNIVPLL, 1, 1), PLL_FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", CLK_APMIXED_UNIVPLL, 1, 2), PLL_FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", CLK_APMIXED_UNIVPLL, 1, 4), PLL_FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", CLK_APMIXED_UNIVPLL, 1, 8), @@ -286,8 +154,7 @@ static const struct mtk_fixed_factor top_divs[] = { PLL_FACTOR1(CLK_TOP_APLL2_D2, "apll2_d2", CLK_TOP_APLL2, 1, 2), PLL_FACTOR1(CLK_TOP_APLL2_D4, "apll2_d4", CLK_TOP_APLL2, 1, 4), PLL_FACTOR1(CLK_TOP_APLL2_D8, "apll2_d8", CLK_TOP_APLL2, 1, 8), - PLL_FACTOR2(CLK_TOP_CLK26M, "clk26m_ck", CLK_XTAL, 1, 1), - PLL_FACTOR2(CLK_TOP_SYS_26M_D2, "sys_26m_d2", CLK_XTAL, 1, 2), + PLL_FACTOR2(CLK_TOP_SYS_26M_D2, "sys_26m_d2", CLK_PAD_CLK26M, 1, 2), PLL_FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", CLK_APMIXED_MSDCPLL, 1, 1), PLL_FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", CLK_APMIXED_MSDCPLL, 1, 2), PLL_FACTOR(CLK_TOP_DSPPLL, "dsppll_ck", CLK_APMIXED_DSPPLL, 1, 1), @@ -295,293 +162,293 @@ static const struct mtk_fixed_factor top_divs[] = { PLL_FACTOR(CLK_TOP_DSPPLL_D4, "dsppll_d4", CLK_APMIXED_DSPPLL, 1, 4), PLL_FACTOR(CLK_TOP_DSPPLL_D8, "dsppll_d8", CLK_APMIXED_DSPPLL, 1, 8), PLL_FACTOR(CLK_TOP_APUPLL, "apupll_ck", CLK_APMIXED_APUPLL, 1, 1), - PLL_FACTOR2(CLK_TOP_CLK26M_D52, "clk26m_d52", CLK_XTAL, 1, 52), + PLL_FACTOR2(CLK_TOP_CLK26M_D52, "clk26m_d52", CLK_PAD_CLK26M, 1, 52), }; -static const int axi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D7, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL3_D2 -}; - -static const int mem_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL, - CLK_TOP_SYSPLL_D3, - CLK_TOP_SYSPLL1_D2 -}; - -static const int mm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_MMPLL_D2, +static const struct mtk_parent axi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), +}; + +static const struct mtk_parent mem_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), +}; + +static const struct mtk_parent mm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_MMPLL_D2), }; -static const int scp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent scp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int mfg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MFGPLL, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent mfg_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MFGPLL), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int atb_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL1_D2 +static const struct mtk_parent atb_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), }; -static const int camtg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_USB20_192M_D8, - CLK_TOP_UNIVPLL2_D8, - CLK_TOP_USB20_192M_D4, - CLK_TOP_UNIVPLL2_D32, - CLK_TOP_USB20_192M_D16, - CLK_TOP_USB20_192M_D32, +static const struct mtk_parent camtg_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_USB20_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), + TOP_PARENT(CLK_TOP_USB20_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D32), + TOP_PARENT(CLK_TOP_USB20_192M_D16), + TOP_PARENT(CLK_TOP_USB20_192M_D32), }; -static const int uart_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent uart_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; -static const int spi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent spi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; -static const int msdc50_0_hc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_SYSPLL2_D2 +static const struct mtk_parent msdc50_0_hc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), }; -static const int msdc50_0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_SYSPLL4_D2 +static const struct mtk_parent msdc50_0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), }; -static const int msdc50_2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4 +static const struct mtk_parent msdc50_2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), }; -static const int msdc30_1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent msdc30_1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; -static const int audio_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_SYSPLL4_D4, - CLK_TOP_SYSPLL1_D16 +static const struct mtk_parent audio_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D16), }; -static const int aud_intbus_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL4_D2 +static const struct mtk_parent aud_intbus_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), }; -static const int aud_1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1 +static const struct mtk_parent aud_1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), }; -static const int aud_2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2 +static const struct mtk_parent aud_2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL2), }; -static const int aud_engen1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_D2, - CLK_TOP_APLL1_D4, - CLK_TOP_APLL1_D8 +static const struct mtk_parent aud_engen1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_D2), + TOP_PARENT(CLK_TOP_APLL1_D4), + TOP_PARENT(CLK_TOP_APLL1_D8), }; -static const int aud_engen2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_D2, - CLK_TOP_APLL2_D4, - CLK_TOP_APLL2_D8, +static const struct mtk_parent aud_engen2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_D2), + TOP_PARENT(CLK_TOP_APLL2_D4), + TOP_PARENT(CLK_TOP_APLL2_D8), }; -static const int aud_spdif_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2 +static const struct mtk_parent aud_spdif_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), }; -static const int disp_pwm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D4 +static const struct mtk_parent disp_pwm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int dxcc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL1_D8 +static const struct mtk_parent dxcc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; -static const int ssusb_sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL3_D2 +static const struct mtk_parent ssusb_sys_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), }; -static const int spm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D8 +static const struct mtk_parent spm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; -static const int i2c_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYSPLL2_D8 +static const struct mtk_parent i2c_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL2_D8), }; -static const int pwm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL1_D8 +static const struct mtk_parent pwm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; -static const int senif_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL2_D2 +static const struct mtk_parent senif_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), }; -static const int aes_fde_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2 +static const struct mtk_parent aes_fde_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), }; -static const int dpi0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_LVDSPLL_D2, - CLK_TOP_LVDSPLL_D4, - CLK_TOP_LVDSPLL_D8, - CLK_TOP_LVDSPLL_D16 +static const struct mtk_parent dpi0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_LVDSPLL_D2), + TOP_PARENT(CLK_TOP_LVDSPLL_D4), + TOP_PARENT(CLK_TOP_LVDSPLL_D8), + TOP_PARENT(CLK_TOP_LVDSPLL_D16), }; -static const int dsp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYS_26M_D2, - CLK_TOP_DSPPLL, - CLK_TOP_DSPPLL_D2, - CLK_TOP_DSPPLL_D4, - CLK_TOP_DSPPLL_D8 +static const struct mtk_parent dsp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYS_26M_D2), + TOP_PARENT(CLK_TOP_DSPPLL), + TOP_PARENT(CLK_TOP_DSPPLL_D2), + TOP_PARENT(CLK_TOP_DSPPLL_D4), + TOP_PARENT(CLK_TOP_DSPPLL_D8), }; -static const int nfi2x_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_SYSPLL_D7, - CLK_TOP_SYSPLL_D3, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL_D5 +static const struct mtk_parent nfi2x_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), }; -static const int nfiecc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_SYSPLL_D7, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL_D5 +static const struct mtk_parent nfiecc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), }; -static const int ecc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D2 +static const struct mtk_parent ecc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D2), }; -static const int eth_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D8, - CLK_TOP_SYSPLL4_D4, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYSPLL4_D2 +static const struct mtk_parent eth_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), }; -static const int gcpu_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL_D3, - CLK_TOP_SYSPLL2_D2 +static const struct mtk_parent gcpu_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), }; -static const int gcpu_cpm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL2_D2 +static const struct mtk_parent gcpu_cpm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), }; -static const int apu_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2, - CLK_TOP_APUPLL, - CLK_TOP_MMPLL, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL1_D4 +static const struct mtk_parent apu_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), + TOP_PARENT(CLK_TOP_APUPLL), + TOP_PARENT(CLK_TOP_MMPLL), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), }; static const struct mtk_composite top_muxes[] = { @@ -684,6 +551,14 @@ static const struct mtk_gate_regs top2_cg_regs = { .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ } +#define GATE_EXT(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &top0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_EXT, \ + } + static const struct mtk_gate top_clk_gates[] = { GATE_TOP2(CLK_TOP_AUD_I2S0_M, CLK_TOP_APLL12_CK_DIV0, 0), GATE_TOP2(CLK_TOP_AUD_I2S1_M, CLK_TOP_APLL12_CK_DIV1, 1), @@ -700,19 +575,18 @@ static const struct mtk_gate top_clk_gates[] = { GATE_TOP1(CLK_TOP_VPLL_DPIX_EN, CLK_TOP_VPLL_DPIX, 21), GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, CLK_TOP_CLK_NULL, 22), GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, CLK_TOP_CLK_NULL, 23), - GATE_TOP0(CLK_TOP_CONN_32K, CLK_TOP_CLK32K, 10), - GATE_TOP0(CLK_TOP_CONN_26M, CLK_TOP_CLK26M, 11), - GATE_TOP0(CLK_TOP_DSP_32K, CLK_TOP_CLK32K, 16), - GATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17), + GATE_EXT(CLK_TOP_CONN_32K, CLK_PAD_CLK32K, 10), + GATE_EXT(CLK_TOP_CONN_26M, CLK_PAD_CLK26M, 11), + GATE_EXT(CLK_TOP_DSP_32K, CLK_PAD_CLK32K, 16), + GATE_EXT(CLK_TOP_DSP_26M, CLK_PAD_CLK26M, 17), }; static const struct mtk_clk_tree mt8365_topckgen_tree = { - .xtal_rate = 26 * MHZ, - .id_offs_map = mt8365_topckgen_id_map, - .id_offs_map_size = ARRAY_SIZE(mt8365_topckgen_id_map), - .fdivs_offs = mt8365_topckgen_id_map[CLK_TOP_MFGPLL], - .muxes_offs = mt8365_topckgen_id_map[CLK_TOP_AXI_SEL], - .gates_offs = mt8365_topckgen_id_map[CLK_TOP_AUD_I2S0_M], + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), + .fdivs_offs = CLK_TOP_MFGPLL, + .muxes_offs = CLK_TOP_AXI_SEL, + .gates_offs = CLK_TOP_AUD_I2S0_M, .fclks = top_fixed_clks, .fdivs = top_divs, .muxes = top_muxes, @@ -778,12 +652,33 @@ static const struct mtk_gate_regs ifr6_cg_regs = { #define GATE_IFR6(_id, _parent, _shift) \ GATE_IFRX(_id, _parent, _shift, &ifr6_cg_regs) +#define GATE_IFRX_EXT(_id, _parent, _shift, _regs) \ + { \ + .id = _id, \ + .parent = _parent, \ + .regs = _regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_EXT, \ + } + +#define GATE_IFR2_EXT(_id, _parent, _shift) \ + GATE_IFRX_EXT(_id, _parent, _shift, &ifr2_cg_regs) + +#define GATE_IFR3_EXT(_id, _parent, _shift) \ + GATE_IFRX_EXT(_id, _parent, _shift, &ifr3_cg_regs) + +#define GATE_IFR4_EXT(_id, _parent, _shift) \ + GATE_IFRX_EXT(_id, _parent, _shift, &ifr4_cg_regs) + +#define GATE_IFR5_EXT(_id, _parent, _shift) \ + GATE_IFRX_EXT(_id, _parent, _shift, &ifr5_cg_regs) + static const struct mtk_gate ifr_clks[] = { /* IFR2 */ - GATE_IFR2(CLK_IFR_PMIC_TMR, CLK_TOP_CLK26M, 0), - GATE_IFR2(CLK_IFR_PMIC_AP, CLK_TOP_CLK26M, 1), - GATE_IFR2(CLK_IFR_PMIC_MD, CLK_TOP_CLK26M, 2), - GATE_IFR2(CLK_IFR_PMIC_CONN, CLK_TOP_CLK26M, 3), + GATE_IFR2_EXT(CLK_IFR_PMIC_TMR, CLK_PAD_CLK26M, 0), + GATE_IFR2_EXT(CLK_IFR_PMIC_AP, CLK_PAD_CLK26M, 1), + GATE_IFR2_EXT(CLK_IFR_PMIC_MD, CLK_PAD_CLK26M, 2), + GATE_IFR2_EXT(CLK_IFR_PMIC_CONN, CLK_PAD_CLK26M, 3), GATE_IFR2(CLK_IFR_ICUSB, CLK_TOP_AXI_SEL, 8), GATE_IFR2(CLK_IFR_GCE, CLK_TOP_AXI_SEL, 9), GATE_IFR2(CLK_IFR_THERM, CLK_TOP_AXI_SEL, 10), @@ -798,7 +693,7 @@ static const struct mtk_gate ifr_clks[] = { GATE_IFR2(CLK_IFR_UART1, CLK_TOP_UART_SEL, 23), GATE_IFR2(CLK_IFR_UART2, CLK_TOP_UART_SEL, 24), GATE_IFR2(CLK_IFR_DSP_UART, CLK_TOP_UART_SEL, 26), - GATE_IFR2(CLK_IFR_GCE_26M, CLK_TOP_CLK26M, 27), + GATE_IFR2_EXT(CLK_IFR_GCE_26M, CLK_PAD_CLK26M, 27), GATE_IFR2(CLK_IFR_CQ_DMA_FPC, CLK_TOP_AXI_SEL, 28), GATE_IFR2(CLK_IFR_BTIF, CLK_TOP_AXI_SEL, 31), /* IFR3 */ @@ -806,19 +701,19 @@ static const struct mtk_gate ifr_clks[] = { GATE_IFR3(CLK_IFR_MSDC0_HCLK, CLK_TOP_AXI_SEL, 2), GATE_IFR3(CLK_IFR_MSDC2_HCLK, CLK_TOP_AXI_SEL, 3), GATE_IFR3(CLK_IFR_MSDC1_HCLK, CLK_TOP_AXI_SEL, 4), - GATE_IFR3(CLK_IFR_DVFSRC, CLK_TOP_CLK26M, 7), + GATE_IFR3_EXT(CLK_IFR_DVFSRC, CLK_PAD_CLK26M, 7), GATE_IFR3(CLK_IFR_GCPU, CLK_TOP_AXI_SEL, 8), GATE_IFR3(CLK_IFR_TRNG, CLK_TOP_AXI_SEL, 9), - GATE_IFR3(CLK_IFR_AUXADC, CLK_TOP_CLK26M, 10), + GATE_IFR3_EXT(CLK_IFR_AUXADC, CLK_PAD_CLK26M, 10), GATE_IFR3(CLK_IFR_CPUM, CLK_TOP_AXI_SEL, 11), - GATE_IFR3(CLK_IFR_AUXADC_MD, CLK_TOP_CLK26M, 14), + GATE_IFR3_EXT(CLK_IFR_AUXADC_MD, CLK_PAD_CLK26M, 14), GATE_IFR3(CLK_IFR_AP_DMA, CLK_TOP_AXI_SEL, 18), GATE_IFR3(CLK_IFR_DEBUGSYS, CLK_TOP_AXI_SEL, 24), GATE_IFR3(CLK_IFR_AUDIO, CLK_TOP_AXI_SEL, 25), /* IFR4 */ GATE_IFR4(CLK_IFR_PWM_FBCLK6, CLK_TOP_PWM_SEL, 0), GATE_IFR4(CLK_IFR_DISP_PWM, CLK_TOP_DISP_PWM_SEL, 2), - GATE_IFR4(CLK_IFR_AUD_26M_BK, CLK_TOP_CLK26M, 4), + GATE_IFR4_EXT(CLK_IFR_AUD_26M_BK, CLK_PAD_CLK26M, 4), GATE_IFR4(CLK_IFR_CQ_DMA, CLK_TOP_AXI_SEL, 27), /* IFR5 */ GATE_IFR5(CLK_IFR_MSDC0_SF, CLK_TOP_MSDC50_0_SEL, 0), @@ -829,12 +724,12 @@ static const struct mtk_gate ifr_clks[] = { GATE_IFR5(CLK_IFR_MSDC0_SRC, CLK_TOP_MSDC50_0_SEL, 9), GATE_IFR5(CLK_IFR_MSDC1_SRC, CLK_TOP_MSDC30_1_SEL, 10), GATE_IFR5(CLK_IFR_MSDC2_SRC, CLK_TOP_MSDC50_2_SEL, 11), - GATE_IFR5(CLK_IFR_PWRAP_TMR, CLK_TOP_CLK26M, 12), - GATE_IFR5(CLK_IFR_PWRAP_SPI, CLK_TOP_CLK26M, 13), - GATE_IFR5(CLK_IFR_PWRAP_SYS, CLK_TOP_CLK26M, 14), + GATE_IFR5_EXT(CLK_IFR_PWRAP_TMR, CLK_PAD_CLK26M, 12), + GATE_IFR5_EXT(CLK_IFR_PWRAP_SPI, CLK_PAD_CLK26M, 13), + GATE_IFR5_EXT(CLK_IFR_PWRAP_SYS, CLK_PAD_CLK26M, 14), GATE_IFR5(CLK_IFR_MCU_PM_BK, CLK_TOP_AXI_SEL, 16), - GATE_IFR5(CLK_IFR_IRRX_26M, CLK_TOP_CLK26M, 22), - GATE_IFR5(CLK_IFR_IRRX_32K, CLK_TOP_CLK32K, 23), + GATE_IFR5_EXT(CLK_IFR_IRRX_26M, CLK_PAD_CLK26M, 22), + GATE_IFR5_EXT(CLK_IFR_IRRX_32K, CLK_PAD_CLK32K, 23), GATE_IFR5(CLK_IFR_I2C0_AXI, CLK_TOP_I2C_SEL, 24), GATE_IFR5(CLK_IFR_I2C1_AXI, CLK_TOP_I2C_SEL, 25), GATE_IFR5(CLK_IFR_I2C2_AXI, CLK_TOP_I2C_SEL, 26), @@ -858,7 +753,8 @@ static const struct mtk_gate ifr_clks[] = { }; static const struct mtk_clk_tree mt8365_infracfg_tree = { - .xtal_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; static int mt8365_apmixedsys_probe(struct udevice *dev) diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c index e6ced91fd06..d6e58be8e22 100644 --- a/drivers/clk/mediatek/clk-mt8512.c +++ b/drivers/clk/mediatek/clk-mt8512.c @@ -17,6 +17,14 @@ #define MT8512_PLL_FMIN (1500UL * MHZ) #define MT8512_CON0_RST_BAR BIT(23) +enum { + CLK_PAD_CLK26M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK26M] = 26 * MHZ, +}; + /* apmixedsys */ #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ _pd_shift, _pcw_reg, _pcw_shift, _pcw_chg_reg) { \ @@ -41,9 +49,9 @@ static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001, 0, 22, 0x0310, 24, 0x0310, 0, 0), PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0x00000001, - HAVE_RST_BAR, 22, 0x022C, 24, 0x022C, 0, 0), + CLK_PLL_HAVE_RST_BAR, 22, 0x022C, 24, 0x022C, 0, 0), PLL(CLK_APMIXED_UNIVPLL2, 0x0208, 0x0214, 0x00000001, - HAVE_RST_BAR, 22, 0x020C, 24, 0x020C, 0, 0), + CLK_PLL_HAVE_RST_BAR, 22, 0x020C, 24, 0x020C, 0, 0), PLL(CLK_APMIXED_MSDCPLL, 0x0350, 0x035C, 0x00000001, 0, 22, 0x0354, 24, 0x0354, 0, 0), PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x00000001, @@ -60,7 +68,7 @@ static const struct mtk_pll_data apmixed_plls[] = { /* topckgen */ #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -69,7 +77,7 @@ static const struct mtk_pll_data apmixed_plls[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, 0) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_CLK_NULL, 26000000), @@ -122,8 +130,8 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR0(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4), FACTOR0(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8), FACTOR0(CLK_TOP_APLL2_D16, CLK_APMIXED_APLL2, 1, 16), - FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1), - FACTOR2(CLK_TOP_SYS_26M_D2, CLK_XTAL, 1, 2), + FACTOR2(CLK_TOP_CLK26M, CLK_PAD_CLK26M, 1, 1), + FACTOR2(CLK_TOP_SYS_26M_D2, CLK_PAD_CLK26M, 1, 2), FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1), FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2), FACTOR0(CLK_TOP_DSPPLL, CLK_APMIXED_DSPPLL, 1, 1), @@ -135,317 +143,317 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_NFI2X_CK_D2, CLK_TOP_NFI2X_SEL, 1, 2), }; -static const int axi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYS_26M_D2, - CLK_TOP_CLK32K -}; - -static const int mem_parents[] = { - CLK_TOP_DSPPLL, - CLK_TOP_IPPLL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3 -}; - -static const int uart_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D8 -}; - -static const int spi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_SYSPLL4_D2 -}; - -static const int spis_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_SYSPLL4_D2 +static const struct mtk_parent axi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYS_26M_D2), + TOP_PARENT(CLK_TOP_CLK32K), +}; + +static const struct mtk_parent mem_parents[] = { + TOP_PARENT(CLK_TOP_DSPPLL), + TOP_PARENT(CLK_TOP_IPPLL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent uart_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), +}; + +static const struct mtk_parent spi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), +}; + +static const struct mtk_parent spis_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), }; -static const int msdc50_0_hc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_SYSPLL2_D2 +static const struct mtk_parent msdc50_0_hc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), }; -static const int msdc50_0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent msdc50_0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; -static const int msdc50_2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4 -}; - -static const int audio_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D8, - CLK_TOP_APLL1_D4, - CLK_TOP_APLL2_D4 -}; - -static const int aud_intbus_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_APLL2_D8, - CLK_TOP_SYS_26M_D2, - CLK_TOP_APLL1_D8, - CLK_TOP_UNIVPLL3_D4 -}; - -static const int hapll1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1, - CLK_TOP_APLL1_D2, - CLK_TOP_APLL1_D3, - CLK_TOP_APLL1_D4, - CLK_TOP_APLL1_D8, - CLK_TOP_APLL1_D16, - CLK_TOP_SYS_26M_D2 -}; - -static const int hapll2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2, - CLK_TOP_APLL2_D2, - CLK_TOP_APLL2_D3, - CLK_TOP_APLL2_D4, - CLK_TOP_APLL2_D8, - CLK_TOP_APLL2_D16, - CLK_TOP_SYS_26M_D2 -}; - -static const int asm_l_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL_D5 -}; - -static const int aud_spdif_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2, - CLK_TOP_DSPPLL -}; - -static const int aud_1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1 -}; - -static const int aud_2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2 -}; - -static const int ssusb_sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL3_D2 -}; - -static const int spm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D8 -}; - -static const int i2c_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYS_26M_D2, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYSPLL2_D8, - CLK_TOP_CLK32K -}; - -static const int pwm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_SYS_26M_D2, - CLK_TOP_CLK32K -}; - -static const int dsp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_DSPPLL, - CLK_TOP_DSPPLL_D2, - CLK_TOP_DSPPLL_D4, - CLK_TOP_DSPPLL_D8, - CLK_TOP_APLL2_D4, - CLK_TOP_SYS_26M_D2, - CLK_TOP_CLK32K -}; - -static const int nfi2x_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_SYSPLL_D7, - CLK_TOP_SYSPLL_D3, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL_D5 -}; - -static const int spinfi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D8, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL3_D2 -}; - -static const int ecc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D3 -}; - -static const int gcpu_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL2_D2 +static const struct mtk_parent msdc50_2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), +}; + +static const struct mtk_parent audio_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), + TOP_PARENT(CLK_TOP_APLL1_D4), + TOP_PARENT(CLK_TOP_APLL2_D4), +}; + +static const struct mtk_parent aud_intbus_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_APLL2_D8), + TOP_PARENT(CLK_TOP_SYS_26M_D2), + TOP_PARENT(CLK_TOP_APLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), +}; + +static const struct mtk_parent hapll1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL1_D2), + TOP_PARENT(CLK_TOP_APLL1_D3), + TOP_PARENT(CLK_TOP_APLL1_D4), + TOP_PARENT(CLK_TOP_APLL1_D8), + TOP_PARENT(CLK_TOP_APLL1_D16), + TOP_PARENT(CLK_TOP_SYS_26M_D2), +}; + +static const struct mtk_parent hapll2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL2_D2), + TOP_PARENT(CLK_TOP_APLL2_D3), + TOP_PARENT(CLK_TOP_APLL2_D4), + TOP_PARENT(CLK_TOP_APLL2_D8), + TOP_PARENT(CLK_TOP_APLL2_D16), + TOP_PARENT(CLK_TOP_SYS_26M_D2), +}; + +static const struct mtk_parent asm_l_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), +}; + +static const struct mtk_parent aud_spdif_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), + TOP_PARENT(CLK_TOP_DSPPLL), +}; + +static const struct mtk_parent aud_1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), +}; + +static const struct mtk_parent aud_2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2), +}; + +static const struct mtk_parent ssusb_sys_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), +}; + +static const struct mtk_parent spm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), +}; + +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYS_26M_D2), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL2_D8), + TOP_PARENT(CLK_TOP_CLK32K), +}; + +static const struct mtk_parent pwm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_SYS_26M_D2), + TOP_PARENT(CLK_TOP_CLK32K), +}; + +static const struct mtk_parent dsp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_DSPPLL), + TOP_PARENT(CLK_TOP_DSPPLL_D2), + TOP_PARENT(CLK_TOP_DSPPLL_D4), + TOP_PARENT(CLK_TOP_DSPPLL_D8), + TOP_PARENT(CLK_TOP_APLL2_D4), + TOP_PARENT(CLK_TOP_SYS_26M_D2), + TOP_PARENT(CLK_TOP_CLK32K), +}; + +static const struct mtk_parent nfi2x_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), +}; + +static const struct mtk_parent spinfi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), +}; + +static const struct mtk_parent ecc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent gcpu_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), }; -static const int gcpu_cpm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4 +static const struct mtk_parent gcpu_cpm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), }; -static const int mbist_diag_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYS_26M_D2 -}; - -static const int ip0_nna_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_DSPPLL, - CLK_TOP_DSPPLL_D2, - CLK_TOP_DSPPLL_D4, - CLK_TOP_IPPLL, - CLK_TOP_SYS_26M_D2, - CLK_TOP_IPPLL_D2, - CLK_TOP_MSDCPLL_D2 -}; - -static const int ip2_wfst_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_IPPLL, - CLK_TOP_IPPLL_D2, - CLK_TOP_SYS_26M_D2, - CLK_TOP_MSDCPLL -}; - -static const int sflash_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D16, - CLK_TOP_SYSPLL2_D8, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL1_D8, - CLK_TOP_USB20_192M_D2, - CLK_TOP_UNIVPLL2_D4 -}; - -static const int sram_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_DSPPLL, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_APLL1, - CLK_TOP_APLL2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYS_26M_D2 -}; - -static const int mm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D3, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL_D3 -}; - -static const int dpi0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_TCONPLL_D2, - CLK_TOP_TCONPLL_D4, - CLK_TOP_TCONPLL_D8, - CLK_TOP_TCONPLL_D16, - CLK_TOP_TCONPLL_D32, - CLK_TOP_TCONPLL_D64 -}; +static const struct mtk_parent mbist_diag_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYS_26M_D2), +}; + +static const struct mtk_parent ip0_nna_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_DSPPLL), + TOP_PARENT(CLK_TOP_DSPPLL_D2), + TOP_PARENT(CLK_TOP_DSPPLL_D4), + TOP_PARENT(CLK_TOP_IPPLL), + TOP_PARENT(CLK_TOP_SYS_26M_D2), + TOP_PARENT(CLK_TOP_IPPLL_D2), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), +}; + +static const struct mtk_parent ip2_wfst_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_IPPLL), + TOP_PARENT(CLK_TOP_IPPLL_D2), + TOP_PARENT(CLK_TOP_SYS_26M_D2), + TOP_PARENT(CLK_TOP_MSDCPLL), +}; + +static const struct mtk_parent sflash_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D16), + TOP_PARENT(CLK_TOP_SYSPLL2_D8), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + TOP_PARENT(CLK_TOP_USB20_192M_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), +}; + +static const struct mtk_parent sram_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_DSPPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYS_26M_D2), +}; + +static const struct mtk_parent mm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent dpi0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_TCONPLL_D2), + TOP_PARENT(CLK_TOP_TCONPLL_D4), + TOP_PARENT(CLK_TOP_TCONPLL_D8), + TOP_PARENT(CLK_TOP_TCONPLL_D16), + TOP_PARENT(CLK_TOP_TCONPLL_D32), + TOP_PARENT(CLK_TOP_TCONPLL_D64), +}; -static const int dbg_atclk_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL_D5 +static const struct mtk_parent dbg_atclk_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), }; -static const int occ_104m_parents[] = { - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent occ_104m_parents[] = { + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; -static const int occ_68m_parents[] = { - CLK_TOP_SYSPLL1_D8, - CLK_TOP_UNIVPLL2_D8 -}; +static const struct mtk_parent occ_68m_parents[] = { + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), +}; -static const int occ_182m_parents[] = { - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent occ_182m_parents[] = { + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; static const struct mtk_composite top_muxes[] = { @@ -785,8 +793,9 @@ static const struct mtk_gate infra_clks[] = { }; static const struct mtk_clk_tree mt8512_clk_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_SYSPLL1_D2, .muxes_offs = CLK_TOP_AXI_SEL, .plls = apmixed_plls, diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c index 4985ba3e5ce..1070dd1551b 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -16,6 +16,14 @@ #define MT8516_PLL_FMAX (1502UL * MHZ) #define MT8516_CON0_RST_BAR BIT(27) +enum { + CLK_PAD_CLK26M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK26M] = 26 * MHZ, +}; + /* apmixedsys */ #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ _pd_shift, _pcw_reg, _pcw_shift) { \ @@ -37,9 +45,9 @@ static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001, 0, 21, 0x0104, 24, 0x0104, 0), PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001, - HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0), + CLK_PLL_HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0), PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001, - HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0), + CLK_PLL_HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0), PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001, 0, 21, 0x0164, 24, 0x0164, 0), PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001, 0, @@ -50,7 +58,7 @@ static const struct mtk_pll_data apmixed_plls[] = { /* topckgen */ #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) #define FIXED_CLK1(_id, _parent, _rate) \ FIXED_CLK(_id, _parent, CLK_PARENT_TOPCKGEN, _rate) @@ -62,7 +70,7 @@ static const struct mtk_pll_data apmixed_plls[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, 0) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_CLK_NULL, 26000000), @@ -109,388 +117,388 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2), FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_RG_APLL2_D2_EN, 1, 2), FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_RG_APLL2_D4_EN, 1, 2), - FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1), - FACTOR2(CLK_TOP_CLK26M_D2, CLK_XTAL, 1, 2), + FACTOR2(CLK_TOP_CLK26M, CLK_PAD_CLK26M, 1, 1), + FACTOR2(CLK_TOP_CLK26M_D2, CLK_PAD_CLK26M, 1, 2), FACTOR1(CLK_TOP_AHB_INFRA_D2, CLK_TOP_AHB_INFRA_SEL, 1, 2), FACTOR1(CLK_TOP_NFI1X, CLK_TOP_NFI2X_PAD_SEL, 1, 2), FACTOR1(CLK_TOP_ETH_D2, CLK_TOP_ETH_SEL, 1, 2), }; -static const int uart0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D24, +static const struct mtk_parent uart0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), }; -static const int gfmux_emi1x_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_DMPLL, +static const struct mtk_parent gfmux_emi1x_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_DMPLL), }; -static const int emi_ddrphy_parents[] = { - CLK_TOP_GFMUX_EMI1X_SEL, - CLK_TOP_GFMUX_EMI1X_SEL, -}; - -static const int ahb_infra_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D11, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D12, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D10, -}; - -static const int csw_mux_mfg_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL_D2, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_MMPLL380M, -}; - -static const int msdc0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D8, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_MAINPLL_D16, - CLK_TOP_MMPLL_200M, - CLK_TOP_MAINPLL_D12, - CLK_TOP_MMPLL_D2, -}; - -static const int pwm_mm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D12, -}; - -static const int uart1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D24, -}; - -static const int msdc1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D8, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_MAINPLL_D16, - CLK_TOP_MMPLL_200M, - CLK_TOP_MAINPLL_D12, - CLK_TOP_MMPLL_D2, -}; - -static const int spm_52m_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D24, -}; - -static const int pmicspi_parents[] = { - CLK_TOP_UNIVPLL_D20, - CLK_TOP_USB_PHY48M, - CLK_TOP_UNIVPLL_D16, - CLK_TOP_CLK26M, -}; - -static const int qaxi_aud26m_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_AHB_INFRA_SEL, -}; - -static const int aud_intbus_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D22, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D11, -}; - -static const int nfi2x_pad_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D12, - CLK_TOP_MAINPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D6, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D4, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D10, - CLK_TOP_MAINPLL_D7, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D5 -}; - -static const int nfi1x_pad_parents[] = { - CLK_TOP_AHB_INFRA_SEL, - CLK_TOP_NFI1X, -}; - -static const int mfg_mm_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CSW_MUX_MFG_SEL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D3, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D5, - CLK_TOP_MAINPLL_D7, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D14 -}; - -static const int ddrphycfg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D16 -}; - -static const int usb_78m_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D16, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D20, -}; - -static const int spinor_parents[] = { - CLK_TOP_CLK26M_D2, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D40, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_UNIVPLL_D20, - CLK_TOP_MAINPLL_D20, - CLK_TOP_MAINPLL_D16, - CLK_TOP_UNIVPLL_D12 -}; - -static const int msdc2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D8, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_MAINPLL_D16, - CLK_TOP_MMPLL_200M, - CLK_TOP_MAINPLL_D12, - CLK_TOP_MMPLL_D2 -}; - -static const int eth_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D40, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_UNIVPLL_D20, - CLK_TOP_MAINPLL_D20 -}; - -static const int axi_mfg_in_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D11, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_MMPLL380M, -}; - -static const int slow_mfg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D12, - CLK_TOP_UNIVPLL_D24 +static const struct mtk_parent emi_ddrphy_parents[] = { + TOP_PARENT(CLK_TOP_GFMUX_EMI1X_SEL), + TOP_PARENT(CLK_TOP_GFMUX_EMI1X_SEL), +}; + +static const struct mtk_parent ahb_infra_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D11), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D10), +}; + +static const struct mtk_parent csw_mux_mfg_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_MMPLL380M), +}; + +static const struct mtk_parent msdc0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_MMPLL_200M), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_MMPLL_D2), +}; + +static const struct mtk_parent pwm_mm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), +}; + +static const struct mtk_parent uart1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), +}; + +static const struct mtk_parent msdc1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_MMPLL_200M), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_MMPLL_D2), +}; + +static const struct mtk_parent spm_52m_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), +}; + +static const struct mtk_parent pmicspi_parents[] = { + TOP_PARENT(CLK_TOP_UNIVPLL_D20), + TOP_PARENT(CLK_TOP_USB_PHY48M), + TOP_PARENT(CLK_TOP_UNIVPLL_D16), + TOP_PARENT(CLK_TOP_CLK26M), +}; + +static const struct mtk_parent qaxi_aud26m_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_AHB_INFRA_SEL), +}; + +static const struct mtk_parent aud_intbus_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D22), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D11), +}; + +static const struct mtk_parent nfi2x_pad_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D10), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D5), +}; + +static const struct mtk_parent nfi1x_pad_parents[] = { + TOP_PARENT(CLK_TOP_AHB_INFRA_SEL), + TOP_PARENT(CLK_TOP_NFI1X), +}; + +static const struct mtk_parent mfg_mm_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CSW_MUX_MFG_SEL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D14), +}; + +static const struct mtk_parent ddrphycfg_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D16), +}; + +static const struct mtk_parent usb_78m_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D16), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D20), +}; + +static const struct mtk_parent spinor_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D40), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_UNIVPLL_D20), + TOP_PARENT(CLK_TOP_MAINPLL_D20), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), +}; + +static const struct mtk_parent msdc2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_MMPLL_200M), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_MMPLL_D2), +}; + +static const struct mtk_parent eth_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D40), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_UNIVPLL_D20), + TOP_PARENT(CLK_TOP_MAINPLL_D20), +}; + +static const struct mtk_parent axi_mfg_in_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D11), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_MMPLL380M), +}; + +static const struct mtk_parent slow_mfg_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), }; - -static const int aud1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1 -}; - -static const int aud2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2 -}; - -static const int aud_engen1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_RG_APLL1_D2_EN, - CLK_TOP_RG_APLL1_D4_EN, - CLK_TOP_RG_APLL1_D8_EN + +static const struct mtk_parent aud1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), +}; + +static const struct mtk_parent aud2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2), +}; + +static const struct mtk_parent aud_engen1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_RG_APLL1_D2_EN), + TOP_PARENT(CLK_TOP_RG_APLL1_D4_EN), + TOP_PARENT(CLK_TOP_RG_APLL1_D8_EN), }; -static const int aud_engen2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_RG_APLL2_D2_EN, - CLK_TOP_RG_APLL2_D4_EN, - CLK_TOP_RG_APLL2_D8_EN +static const struct mtk_parent aud_engen2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_RG_APLL2_D2_EN), + TOP_PARENT(CLK_TOP_RG_APLL2_D4_EN), + TOP_PARENT(CLK_TOP_RG_APLL2_D8_EN), }; -static const int i2c_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D20, - CLK_TOP_UNIVPLL_D16, - CLK_TOP_UNIVPLL_D12 +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D20), + TOP_PARENT(CLK_TOP_UNIVPLL_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), }; -static const int aud_i2s0_m_parents[] = { - CLK_TOP_RG_AUD1, - CLK_TOP_RG_AUD2 +static const struct mtk_parent aud_i2s0_m_parents[] = { + TOP_PARENT(CLK_TOP_RG_AUD1), + TOP_PARENT(CLK_TOP_RG_AUD2), }; -static const int pwm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D12 +static const struct mtk_parent pwm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), }; -static const int spi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D12, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_UNIVPLL_D6 +static const struct mtk_parent spi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), }; -static const int aud_spdifin_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2 +static const struct mtk_parent aud_spdifin_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), }; -static const int uart2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D24 +static const struct mtk_parent uart2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), }; -static const int bsi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D10, - CLK_TOP_MAINPLL_D12, - CLK_TOP_MAINPLL_D20 +static const struct mtk_parent bsi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D10), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_MAINPLL_D20), }; -static const int dbg_atclk_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D5, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D5 +static const struct mtk_parent dbg_atclk_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), }; -static const int csw_nfiecc_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D7, - CLK_TOP_MAINPLL_D6, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D5 +static const struct mtk_parent csw_nfiecc_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D5), }; -static const int nfiecc_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_NFI2X_PAD_SEL, - CLK_TOP_MAINPLL_D4, - CLK_TOP_CLK_NULL, - CLK_TOP_CSW_NFIECC_SEL, +static const struct mtk_parent nfiecc_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_NFI2X_PAD_SEL), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CSW_NFIECC_SEL), }; static const struct mtk_composite top_muxes[] = { @@ -737,8 +745,9 @@ static const struct mtk_gate top_clks[] = { }; static const struct mtk_clk_tree mt8516_clk_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_DMPLL, .muxes_offs = CLK_TOP_UART0_SEL, .plls = apmixed_plls, diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c index 2fc492e7170..2b213e720a0 100644 --- a/drivers/clk/mediatek/clk-mt8518.c +++ b/drivers/clk/mediatek/clk-mt8518.c @@ -16,6 +16,14 @@ #define MT8518_PLL_FMAX (3000UL * MHZ) #define MT8518_CON0_RST_BAR BIT(27) +enum { + CLK_PAD_CLK26M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK26M] = 26 * MHZ, +}; + /* apmixedsys */ #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ _pd_shift, _pcw_reg, _pcw_shift) { \ @@ -37,9 +45,9 @@ static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001, 0, 21, 0x0104, 24, 0x0104, 0), PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001, - HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0), + CLK_PLL_HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0), PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001, - HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0), + CLK_PLL_HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0), PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001, 0, 21, 0x0164, 24, 0x0164, 0), PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001, @@ -52,7 +60,7 @@ static const struct mtk_pll_data apmixed_plls[] = { /* topckgen */ #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) #define FIXED_CLK1(_id, _rate) \ FIXED_CLK(_id, CLK_TOP_CLK_NULL, CLK_PARENT_TOPCKGEN, _rate) @@ -64,7 +72,7 @@ static const struct mtk_pll_data apmixed_plls[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, 0) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_CLK_NULL, 26000000), @@ -74,7 +82,7 @@ static const struct mtk_fixed_clk top_fixed_clks[] = { }; static const struct mtk_fixed_factor top_fixed_divs[] = { - FACTOR2(CLK_TOP_DMPLL, CLK_XTAL, 1, 1), + FACTOR2(CLK_TOP_DMPLL, CLK_PAD_CLK26M, 1, 1), FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4), FACTOR0(CLK_TOP_MAINPLL_D8, CLK_APMIXED_MAINPLL, 1, 8), FACTOR0(CLK_TOP_MAINPLL_D16, CLK_APMIXED_MAINPLL, 1, 16), @@ -109,11 +117,11 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_APLL2_D3, CLK_TOP_APLL2, 1, 3), FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_APLL2, 1, 4), FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_APLL2, 1, 8), - FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1), - FACTOR2(CLK_TOP_CLK26M_D2, CLK_XTAL, 1, 2), - FACTOR2(CLK_TOP_CLK26M_D4, CLK_XTAL, 1, 4), - FACTOR2(CLK_TOP_CLK26M_D8, CLK_XTAL, 1, 8), - FACTOR2(CLK_TOP_CLK26M_D793, CLK_XTAL, 1, 793), + FACTOR2(CLK_TOP_CLK26M, CLK_PAD_CLK26M, 1, 1), + FACTOR2(CLK_TOP_CLK26M_D2, CLK_PAD_CLK26M, 1, 2), + FACTOR2(CLK_TOP_CLK26M_D4, CLK_PAD_CLK26M, 1, 4), + FACTOR2(CLK_TOP_CLK26M_D8, CLK_PAD_CLK26M, 1, 8), + FACTOR2(CLK_TOP_CLK26M_D793, CLK_PAD_CLK26M, 1, 793), FACTOR0(CLK_TOP_TVDPLL, CLK_APMIXED_TVDPLL, 1, 1), FACTOR1(CLK_TOP_TVDPLL_D2, CLK_TOP_TVDPLL, 1, 2), FACTOR1(CLK_TOP_TVDPLL_D4, CLK_TOP_TVDPLL, 1, 4), @@ -134,1050 +142,1050 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_AHB_INFRA_D2, CLK_TOP_AXIBUS_SEL, 1, 2), }; -static const int uart0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D24 -}; - -static const int emi1x_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_DMPLL -}; - -static const int emi_ddrphy_parents[] = { - CLK_TOP_EMI1X_SEL, - CLK_TOP_EMI1X_SEL -}; - -static const int msdc1_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D16, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MMPLL_D2, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D12 -}; - -static const int pwm_mm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D12 -}; - -static const int pmicspi_parents[] = { - CLK_TOP_UNIVPLL_D20, - CLK_TOP_USB20_48M, - CLK_TOP_UNIVPLL_D16, - CLK_TOP_CLK26M, - CLK_TOP_CLK26M_D2 -}; - -static const int nfi2x_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4, - CLK_TOP_MAINPLL_D5, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MAINPLL_D7, - CLK_TOP_MAINPLL_D8, - CLK_TOP_MAINPLL_D10, - CLK_TOP_MAINPLL_D12 -}; - -static const int ddrphycfg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D16 -}; - -static const int smi_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MAINPLL_D7, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D14 -}; - -static const int usb_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D16, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D20 -}; - -static const int spinor_parents[] = { - CLK_TOP_CLK26M_D2, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D40, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_UNIVPLL_D20, - CLK_TOP_MAINPLL_D20, - CLK_TOP_MAINPLL_D16, - CLK_TOP_UNIVPLL_D12 -}; - -static const int eth_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D40, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_UNIVPLL_D20, - CLK_TOP_MAINPLL_D20 -}; - -static const int aud1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_SRC_SEL -}; - -static const int aud2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_SRC_SEL -}; - -static const int i2c_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_USB20_48M, - CLK_TOP_UNIVPLL_D12, - CLK_TOP_UNIVPLL_D10, - CLK_TOP_UNIVPLL_D8 -}; - -static const int aud_i2s0_m_parents[] = { - CLK_TOP_AUD1, - CLK_TOP_AUD2 -}; - -static const int aud_spdifin_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2, - CLK_TOP_TVDPLL -}; - -static const int dbg_atclk_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D5, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D5 -}; - -static const int png_sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_MAINPLL_D7, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MAINPLL_D5, - CLK_TOP_UNIVPLL_D3 -}; - -static const int sej_13m_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_CLK26M_D2 -}; - -static const int imgrz_sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MAINPLL_D7, - CLK_TOP_MAINPLL_D5, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_UNIVPLL_D10, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL_D6 -}; - -static const int graph_eclk_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D6, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_UNIVPLL_D16, - CLK_TOP_MAINPLL_D7, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_UNIVPLL_D10, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_MAINPLL_D8 -}; - -static const int fdbi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D12, - CLK_TOP_MAINPLL_D14, - CLK_TOP_MAINPLL_D16, - CLK_TOP_UNIVPLL_D10, - CLK_TOP_UNIVPLL_D12, - CLK_TOP_UNIVPLL_D16, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_TVDPLL_D2, - CLK_TOP_TVDPLL_D4, - CLK_TOP_TVDPLL_D8, - CLK_TOP_TVDPLL_D16 -}; - -static const int faudio_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_APLL1_D4, - CLK_TOP_APLL2_D4 -}; - -static const int fa2sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_SRC_SEL, - CLK_TOP_RG_APLL1_D2, - CLK_TOP_RG_APLL1_D4, - CLK_TOP_RG_APLL1_D8, - CLK_TOP_RG_APLL1_D16, - CLK_TOP_CLK26M_D2, - CLK_TOP_RG_APLL1_D3 -}; - -static const int fa1sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_SRC_SEL, - CLK_TOP_RG_APLL2_D2, - CLK_TOP_RG_APLL2_D4, - CLK_TOP_RG_APLL2_D8, - CLK_TOP_RG_APLL2_D16, - CLK_TOP_CLK26M_D2, - CLK_TOP_RG_APLL2_D3 -}; - -static const int fasm_m_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D12, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D7 -}; - -static const int fecc_ck_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D3 -}; - -static const int pe2_mac_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D11, - CLK_TOP_MAINPLL_D16, - CLK_TOP_UNIVPLL_D12, - CLK_TOP_UNIVPLL_D10 -}; - -static const int cmsys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D5, - CLK_TOP_APLL2, - CLK_TOP_APLL2_D2, - CLK_TOP_APLL2_D4, - CLK_TOP_APLL2_D3 -}; - -static const int gcpu_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4, - CLK_TOP_MAINPLL_D5, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MAINPLL_D7, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_UNIVPLL_D10, - CLK_TOP_UNIVPLL_D3 -}; - -static const int spis_ck_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D12, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D4, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D3 -}; - -static const int apll1_ref_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL -}; - -static const int int_32k_parents[] = { - CLK_TOP_CLK32K, - CLK_TOP_CLK26M_D793 -}; - -static const int apll1_src_parents[] = { - CLK_TOP_APLL1, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL -}; - -static const int apll2_src_parents[] = { - CLK_TOP_APLL2, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL -}; - -static const int faud_intbus_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D11, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D10, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_RG_APLL2_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M_D2, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_RG_APLL1_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D20 -}; - -static const int axibus_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D11, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D12, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D10, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M_D2, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_APLL2_D8 -}; - -static const int hapll1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_SRC_SEL, - CLK_TOP_RG_APLL1_D2, - CLK_TOP_RG_APLL1_D4, - CLK_TOP_RG_APLL1_D8, - CLK_TOP_RG_APLL1_D16, - CLK_TOP_CLK26M_D2, - CLK_TOP_CLK26M_D8, - CLK_TOP_RG_APLL1_D3 -}; - -static const int hapll2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_SRC_SEL, - CLK_TOP_RG_APLL2_D2, - CLK_TOP_RG_APLL2_D4, - CLK_TOP_RG_APLL2_D8, - CLK_TOP_RG_APLL2_D16, - CLK_TOP_CLK26M_D2, - CLK_TOP_CLK26M_D4, - CLK_TOP_RG_APLL2_D3 -}; - -static const int spinfi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_UNIVPLL_D20, - CLK_TOP_MAINPLL_D22, - CLK_TOP_UNIVPLL_D16, - CLK_TOP_MAINPLL_D16, - CLK_TOP_UNIVPLL_D12, - CLK_TOP_UNIVPLL_D10, - CLK_TOP_MAINPLL_D11 -}; - -static const int msdc0_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D16, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D12, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_APMIXED_MMPLL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MMPLL_D2 -}; - -static const int msdc0_clk50_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D6 -}; - -static const int msdc2_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D16, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MMPLL_D2, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D12, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_APMIXED_MMPLL -}; - -static const int disp_dpi_ck_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_TVDPLL_D2, - CLK_TOP_CLK_NULL, - CLK_TOP_TVDPLL_D4, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_TVDPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_TVDPLL_D16 +static const struct mtk_parent uart0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), +}; + +static const struct mtk_parent emi1x_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_DMPLL), +}; + +static const struct mtk_parent emi_ddrphy_parents[] = { + TOP_PARENT(CLK_TOP_EMI1X_SEL), + TOP_PARENT(CLK_TOP_EMI1X_SEL), +}; + +static const struct mtk_parent msdc1_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MMPLL_D2), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D12), +}; + +static const struct mtk_parent pwm_mm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), +}; + +static const struct mtk_parent pmicspi_parents[] = { + TOP_PARENT(CLK_TOP_UNIVPLL_D20), + TOP_PARENT(CLK_TOP_USB20_48M), + TOP_PARENT(CLK_TOP_UNIVPLL_D16), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_CLK26M_D2), +}; + +static const struct mtk_parent nfi2x_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D10), + TOP_PARENT(CLK_TOP_MAINPLL_D12), +}; + +static const struct mtk_parent ddrphycfg_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D16), +}; + +static const struct mtk_parent smi_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D14), +}; + +static const struct mtk_parent usb_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D16), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D20), +}; + +static const struct mtk_parent spinor_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D40), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_UNIVPLL_D20), + TOP_PARENT(CLK_TOP_MAINPLL_D20), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), +}; + +static const struct mtk_parent eth_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D40), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_UNIVPLL_D20), + TOP_PARENT(CLK_TOP_MAINPLL_D20), +}; + +static const struct mtk_parent aud1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_SRC_SEL), +}; + +static const struct mtk_parent aud2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_SRC_SEL), +}; + +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_USB20_48M), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), +}; + +static const struct mtk_parent aud_i2s0_m_parents[] = { + TOP_PARENT(CLK_TOP_AUD1), + TOP_PARENT(CLK_TOP_AUD2), +}; + +static const struct mtk_parent aud_spdifin_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), + TOP_PARENT(CLK_TOP_TVDPLL), +}; + +static const struct mtk_parent dbg_atclk_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), +}; + +static const struct mtk_parent png_sys_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent sej_13m_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_CLK26M_D2), +}; + +static const struct mtk_parent imgrz_sys_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), +}; + +static const struct mtk_parent graph_eclk_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D16), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_MAINPLL_D8), +}; + +static const struct mtk_parent fdbi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_MAINPLL_D14), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), + TOP_PARENT(CLK_TOP_UNIVPLL_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_TVDPLL_D2), + TOP_PARENT(CLK_TOP_TVDPLL_D4), + TOP_PARENT(CLK_TOP_TVDPLL_D8), + TOP_PARENT(CLK_TOP_TVDPLL_D16), +}; + +static const struct mtk_parent faudio_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_APLL1_D4), + TOP_PARENT(CLK_TOP_APLL2_D4), +}; + +static const struct mtk_parent fa2sys_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_SRC_SEL), + TOP_PARENT(CLK_TOP_RG_APLL1_D2), + TOP_PARENT(CLK_TOP_RG_APLL1_D4), + TOP_PARENT(CLK_TOP_RG_APLL1_D8), + TOP_PARENT(CLK_TOP_RG_APLL1_D16), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_RG_APLL1_D3), +}; + +static const struct mtk_parent fa1sys_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_SRC_SEL), + TOP_PARENT(CLK_TOP_RG_APLL2_D2), + TOP_PARENT(CLK_TOP_RG_APLL2_D4), + TOP_PARENT(CLK_TOP_RG_APLL2_D8), + TOP_PARENT(CLK_TOP_RG_APLL2_D16), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_RG_APLL2_D3), +}; + +static const struct mtk_parent fasm_m_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D7), +}; + +static const struct mtk_parent fecc_ck_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D3), +}; + +static const struct mtk_parent pe2_mac_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D11), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), +}; + +static const struct mtk_parent cmsys_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL2_D2), + TOP_PARENT(CLK_TOP_APLL2_D4), + TOP_PARENT(CLK_TOP_APLL2_D3), +}; + +static const struct mtk_parent gcpu_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent spis_ck_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent apll1_ref_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), +}; + +static const struct mtk_parent int_32k_parents[] = { + TOP_PARENT(CLK_TOP_CLK32K), + TOP_PARENT(CLK_TOP_CLK26M_D793), +}; + +static const struct mtk_parent apll1_src_parents[] = { + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), +}; + +static const struct mtk_parent apll2_src_parents[] = { + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), +}; + +static const struct mtk_parent faud_intbus_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D11), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_RG_APLL2_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_RG_APLL1_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D20), +}; + +static const struct mtk_parent axibus_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D11), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_APLL2_D8), +}; + +static const struct mtk_parent hapll1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_SRC_SEL), + TOP_PARENT(CLK_TOP_RG_APLL1_D2), + TOP_PARENT(CLK_TOP_RG_APLL1_D4), + TOP_PARENT(CLK_TOP_RG_APLL1_D8), + TOP_PARENT(CLK_TOP_RG_APLL1_D16), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_CLK26M_D8), + TOP_PARENT(CLK_TOP_RG_APLL1_D3), +}; + +static const struct mtk_parent hapll2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_SRC_SEL), + TOP_PARENT(CLK_TOP_RG_APLL2_D2), + TOP_PARENT(CLK_TOP_RG_APLL2_D4), + TOP_PARENT(CLK_TOP_RG_APLL2_D8), + TOP_PARENT(CLK_TOP_RG_APLL2_D16), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_CLK26M_D4), + TOP_PARENT(CLK_TOP_RG_APLL2_D3), +}; + +static const struct mtk_parent spinfi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_UNIVPLL_D20), + TOP_PARENT(CLK_TOP_MAINPLL_D22), + TOP_PARENT(CLK_TOP_UNIVPLL_D16), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), + TOP_PARENT(CLK_TOP_MAINPLL_D11), +}; + +static const struct mtk_parent msdc0_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_APMIXED_MMPLL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MMPLL_D2), +}; + +static const struct mtk_parent msdc0_clk50_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D6), +}; + +static const struct mtk_parent msdc2_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MMPLL_D2), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_APMIXED_MMPLL), +}; + +static const struct mtk_parent disp_dpi_ck_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL_D2), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_TVDPLL_D4), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_TVDPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_TVDPLL_D16), }; static const struct mtk_composite top_muxes[] = { @@ -1493,8 +1501,9 @@ static const struct mtk_gate top_clks[] = { }; static const struct mtk_clk_tree mt8518_clk_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_DMPLL, .muxes_offs = CLK_TOP_UART0_SEL, .plls = apmixed_plls, diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index b4de38719e1..3557aeac3d5 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -85,6 +85,34 @@ static int mtk_common_clk_get_unmapped_id(struct clk *clk) return -ENOENT; } +static bool mtk_clk_id_is_pll(const struct mtk_clk_tree *tree, int mapped_id) +{ + return tree->plls && mapped_id < tree->num_plls; +} + +static bool mtk_clk_id_is_fclk(const struct mtk_clk_tree *tree, int mapped_id) +{ + return tree->fclks && mapped_id < tree->num_fclks; +} + +static bool mtk_clk_id_is_fdiv(const struct mtk_clk_tree *tree, int mapped_id) +{ + return tree->fdivs && mapped_id >= tree->fdivs_offs && + mapped_id < tree->fdivs_offs + tree->num_fdivs; +} + +static bool mtk_clk_id_is_mux(const struct mtk_clk_tree *tree, int mapped_id) +{ + return tree->muxes && mapped_id >= tree->muxes_offs && + mapped_id < tree->muxes_offs + tree->num_muxes; +} + +static bool mtk_clk_id_is_gate(const struct mtk_clk_tree *tree, int mapped_id) +{ + return tree->gates && mapped_id >= tree->gates_offs && + mapped_id < tree->gates_offs + tree->num_gates; +} + static int mtk_dummy_enable(struct clk *clk) { return 0; @@ -140,6 +168,14 @@ static int mtk_gate_disable(void __iomem *base, const struct mtk_gate *gate) return 0; } +static ulong mtk_ext_clock_get_rate(const struct mtk_clk_tree *tree, int id) +{ + if (!tree->ext_clk_rates || id >= tree->num_ext_clks) + return -ENOENT; + + return tree->ext_clk_rates[id]; +} + /* * In case the rate change propagation to parent clocks is undesirable, * this function is recursively called to find the parent to calculate @@ -168,28 +204,83 @@ static ulong mtk_clk_find_parent_rate(struct clk *clk, int id, return clk_get_rate(&parent); } +const struct clk_ops mtk_clk_apmixedsys_ops; +const struct clk_ops mtk_clk_topckgen_ops; +const struct clk_ops mtk_clk_infrasys_ops; + +static ulong mtk_find_parent_rate(struct mtk_clk_priv *priv, struct clk *clk, + const int parent, u16 flags) +{ + struct udevice *parent_dev; + + switch (flags & CLK_PARENT_MASK) { + case CLK_PARENT_APMIXED: + /* APMIXEDSYS can be parent or grandparent. */ + if (dev_get_driver_ops(clk->dev) == &mtk_clk_apmixedsys_ops) + parent_dev = clk->dev; + else if (dev_get_driver_ops(priv->parent) == &mtk_clk_apmixedsys_ops) + parent_dev = priv->parent; + else if (dev_get_driver_ops(dev_get_parent(priv->parent)) == &mtk_clk_apmixedsys_ops) + parent_dev = dev_get_parent(priv->parent); + else + return -EINVAL; + + break; + case CLK_PARENT_TOPCKGEN: + if (dev_get_driver_ops(clk->dev) == &mtk_clk_topckgen_ops) + parent_dev = clk->dev; + else if (dev_get_driver_ops(priv->parent) == &mtk_clk_topckgen_ops) + parent_dev = priv->parent; + else + return -EINVAL; + + break; + case CLK_PARENT_INFRASYS: + if (dev_get_driver_ops(clk->dev) != &mtk_clk_infrasys_ops) + return -EINVAL; + + parent_dev = clk->dev; + break; + case CLK_PARENT_EXT: + return mtk_ext_clock_get_rate(priv->tree, parent); + default: + parent_dev = NULL; + break; + } + + return mtk_clk_find_parent_rate(clk, parent, parent_dev); +} + +static ulong mtk_clk_mux_get_rate(struct clk *clk, u32 off) +{ + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + const struct mtk_composite *mux = &priv->tree->muxes[off]; + const struct mtk_parent *parent; + u32 index; + + index = readl(priv->base + mux->mux_reg); + index &= mux->mux_mask << mux->mux_shift; + index = index >> mux->mux_shift; + parent = &mux->parent[index]; + + return mtk_find_parent_rate(priv, clk, parent->id, parent->flags); +} + static int mtk_clk_mux_set_parent(void __iomem *base, u32 parent, u32 parent_type, const struct mtk_composite *mux) { u32 val, index = 0; - if (mux->flags & CLK_PARENT_MIXED) { - /* - * Assume parent_type in clk_tree to be always set with - * CLK_PARENT_MIXED implementation. If it's not, assume - * not parent clk ID clash is possible. - */ - while (mux->parent_flags[index].id != parent || - (parent_type && (mux->parent_flags[index].flags & CLK_PARENT_MASK) != - parent_type)) - if (++index == mux->num_parents) - return -EINVAL; - } else { - while (mux->parent[index] != parent) - if (++index == mux->num_parents) - return -EINVAL; - } + /* + * Assume parent_type in clk_tree to be always set. If it's not, assume + * parent clk ID clash is not possible. + */ + while (mux->parent[index].id != parent || + (parent_type && (mux->parent[index].flags & CLK_PARENT_MASK) != + parent_type)) + if (++index == mux->num_parents) + return -EINVAL; if (mux->flags & CLK_MUX_SETCLR_UPD) { val = (mux->mux_mask << mux->mux_shift); @@ -259,11 +350,8 @@ static void mtk_clk_print_parent(const char *prefix, int parent, u32 flags) case CLK_PARENT_INFRASYS: parent_type_str = "infrasys"; break; - case CLK_PARENT_XTAL: - parent_type_str = "xtal"; - break; - case CLK_PARENT_MIXED: - parent_type_str = "mixed"; + case CLK_PARENT_EXT: + parent_type_str = "ext"; break; default: parent_type_str = "default"; @@ -293,18 +381,14 @@ static void mtk_clk_print_mux_parents(struct mtk_clk_priv *priv, /* Print parents separated by "/" and selected parent enclosed in "*"s */ for (i = 0; i < mux->num_parents; i++) { + const struct mtk_parent *parent = &mux->parent[i]; + if (i == selected) { printf("%s", prefix); prefix = "*"; } - if (mux->flags & CLK_PARENT_MIXED) { - const struct mtk_parent *parent = &mux->parent_flags[i]; - - mtk_clk_print_parent(prefix, parent->id, parent->flags); - } else { - mtk_clk_print_parent(prefix, mux->parent[i], mux->flags); - } + mtk_clk_print_parent(prefix, parent->id, parent->flags); prefix = "/"; @@ -328,15 +412,10 @@ static const int mtk_apmixedsys_of_xlate(struct clk *clk, return ret; /* apmixedsys only uses plls and gates. */ + if (!mtk_clk_id_is_pll(tree, clk->id) && !mtk_clk_id_is_gate(tree, clk->id)) + return -ENOENT; - if (tree->plls && clk->id < tree->num_plls) - return 0; - - if (tree->gates && clk->id >= tree->gates_offs && - clk->id < tree->gates_offs + tree->num_gates) - return 0; - - return -ENOENT; + return 0; } static unsigned long __mtk_pll_recalc_rate(const struct mtk_pll_data *pll, @@ -415,16 +494,21 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_priv *priv, u32 id, * @postdiv: The post divider (output) * @freq: The desired target frequency */ -static void mtk_pll_calc_values(struct mtk_clk_priv *priv, u32 id, - u32 *pcw, u32 *postdiv, u32 freq) +static int mtk_pll_calc_values(struct mtk_clk_priv *priv, struct clk *clk, + u32 *pcw, u32 *postdiv, u32 freq) { const struct mtk_pll_data *pll; - unsigned long fmin; + const struct mtk_parent *parent = &priv->tree->pll_parent; + unsigned long xtal_rate, fmin; u64 _pcw; int ibits; u32 val; - pll = &priv->tree->plls[id]; + xtal_rate = mtk_find_parent_rate(priv, clk, parent->id, parent->flags); + if (IS_ERR_VALUE(xtal_rate)) + return xtal_rate; + + pll = &priv->tree->plls[clk->id]; fmin = pll->fmin ? pll->fmin : 1000 * MHZ; if (freq > pll->fmax) @@ -439,9 +523,11 @@ static void mtk_pll_calc_values(struct mtk_clk_priv *priv, u32 id, /* _pcw = freq * postdiv / xtal_rate * 2^pcwfbits */ ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS; _pcw = ((u64)freq << val) << (pll->pcwbits - ibits); - do_div(_pcw, priv->tree->xtal2_rate); + do_div(_pcw, xtal_rate); *pcw = (u32)_pcw; + + return 0; } static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate) @@ -449,11 +535,15 @@ static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate) struct mtk_clk_priv *priv = dev_get_priv(clk->dev); u32 pcw = 0; u32 postdiv; + int ret; - if (priv->tree->gates && clk->id >= priv->tree->gates_offs) + if (!mtk_clk_id_is_pll(priv->tree, clk->id)) return -EINVAL; - mtk_pll_calc_values(priv, clk->id, &pcw, &postdiv, rate); + ret = mtk_pll_calc_values(priv, clk, &pcw, &postdiv, rate); + if (ret) + return ret; + mtk_pll_set_rate_regs(priv, clk->id, pcw, postdiv); return 0; @@ -462,17 +552,24 @@ static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate) static ulong mtk_apmixedsys_get_rate(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + const struct mtk_parent *parent; const struct mtk_pll_data *pll; const struct mtk_gate *gate; + unsigned long xtal_rate; u32 postdiv; u32 pcw; /* GATE handling */ - if (priv->tree->gates && clk->id >= priv->tree->gates_offs) { + if (mtk_clk_id_is_gate(priv->tree, clk->id)) { gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; - return mtk_clk_find_parent_rate(clk, gate->parent, NULL); + return mtk_find_parent_rate(priv, clk, gate->parent, gate->flags); } + parent = &priv->tree->pll_parent; + xtal_rate = mtk_find_parent_rate(priv, clk, parent->id, parent->flags); + if (IS_ERR_VALUE(xtal_rate)) + return xtal_rate; + pll = &priv->tree->plls[clk->id]; postdiv = (readl(priv->base + pll->pd_reg) >> pll->pd_shift) & @@ -482,8 +579,7 @@ static ulong mtk_apmixedsys_get_rate(struct clk *clk) pcw = readl(priv->base + pll->pcw_reg) >> pll->pcw_shift; pcw &= GENMASK(pll->pcwbits - 1, 0); - return __mtk_pll_recalc_rate(pll, priv->tree->xtal2_rate, - pcw, postdiv); + return __mtk_pll_recalc_rate(pll, xtal_rate, pcw, postdiv); } static int mtk_apmixedsys_enable(struct clk *clk) @@ -494,7 +590,7 @@ static int mtk_apmixedsys_enable(struct clk *clk) u32 r; /* GATE handling */ - if (priv->tree->gates && clk->id >= priv->tree->gates_offs) { + if (mtk_clk_id_is_gate(priv->tree, clk->id)) { gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; return mtk_gate_enable(priv->base, gate); } @@ -515,7 +611,7 @@ static int mtk_apmixedsys_enable(struct clk *clk) udelay(20); - if (pll->flags & HAVE_RST_BAR) { + if (pll->flags & CLK_PLL_HAVE_RST_BAR) { r = readl(priv->base + pll->reg + REG_CON0); r |= pll->rst_bar_mask; writel(r, priv->base + pll->reg + REG_CON0); @@ -532,14 +628,14 @@ static int mtk_apmixedsys_disable(struct clk *clk) u32 r; /* GATE handling */ - if (priv->tree->gates && clk->id >= priv->tree->gates_offs) { + if (mtk_clk_id_is_gate(priv->tree, clk->id)) { gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; return mtk_gate_disable(priv->base, gate); } pll = &priv->tree->plls[clk->id]; - if (pll->flags & HAVE_RST_BAR) { + if (pll->flags & CLK_PLL_HAVE_RST_BAR) { r = readl(priv->base + pll->reg + REG_CON0); r &= ~pll->rst_bar_mask; writel(r, priv->base + pll->reg + REG_CON0); @@ -602,23 +698,11 @@ static const int mtk_topckgen_of_xlate(struct clk *clk, return ret; /* topckgen only uses fclks, fdivs, muxes and gates. */ + if (!mtk_clk_id_is_fclk(tree, clk->id) && !mtk_clk_id_is_fdiv(tree, clk->id) && + !mtk_clk_id_is_mux(tree, clk->id) && !mtk_clk_id_is_gate(tree, clk->id)) + return -ENOENT; - if (tree->fclks && clk->id < tree->num_fclks) - return 0; - - if (tree->fdivs && clk->id >= tree->fdivs_offs && - clk->id < tree->fdivs_offs + tree->num_fdivs) - return 0; - - if (tree->muxes && clk->id >= tree->muxes_offs && - clk->id < tree->muxes_offs + tree->num_muxes) - return 0; - - if (tree->gates && clk->id >= tree->gates_offs && - clk->id < tree->gates_offs + tree->num_gates) - return 0; - - return -ENOENT; + return 0; } static ulong mtk_factor_recalc_rate(const struct mtk_fixed_factor *fdiv, @@ -637,105 +721,34 @@ static ulong mtk_topckgen_get_factor_rate(struct clk *clk, u32 off) const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off]; ulong rate; - switch (fdiv->flags & CLK_PARENT_MASK) { - case CLK_PARENT_APMIXED: - rate = mtk_clk_find_parent_rate(clk, fdiv->parent, - priv->parent); - break; - case CLK_PARENT_TOPCKGEN: - rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL); - break; - - case CLK_PARENT_XTAL: - default: - rate = priv->tree->xtal_rate; - } - + rate = mtk_find_parent_rate(priv, clk, fdiv->parent, fdiv->flags); if (IS_ERR_VALUE(rate)) return rate; return mtk_factor_recalc_rate(fdiv, rate); } -static ulong mtk_topckgen_find_parent_rate(struct mtk_clk_priv *priv, struct clk *clk, - const int parent, u16 flags) -{ - switch (flags & CLK_PARENT_MASK) { - case CLK_PARENT_XTAL: - return priv->tree->xtal_rate; - case CLK_PARENT_APMIXED: - return mtk_clk_find_parent_rate(clk, parent, priv->parent); - default: - return mtk_clk_find_parent_rate(clk, parent, NULL); - } -} - -static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off) +static ulong mtk_topckgen_get_rate(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); - const struct mtk_composite *mux = &priv->tree->muxes[off]; - u32 index; - - index = readl(priv->base + mux->mux_reg); - index &= mux->mux_mask << mux->mux_shift; - index = index >> mux->mux_shift; - - /* - * Parents can be either from APMIXED or TOPCKGEN, - * inspect the mtk_parent struct to check the source - */ - if (mux->flags & CLK_PARENT_MIXED) { - const struct mtk_parent *parent = &mux->parent_flags[index]; - - return mtk_topckgen_find_parent_rate(priv, clk, parent->id, - parent->flags); - } + const struct mtk_clk_tree *tree = priv->tree; - if (mux->parent[index] == CLK_XTAL && - !(priv->tree->flags & CLK_BYPASS_XTAL)) - return priv->tree->xtal_rate; + if (mtk_clk_id_is_fclk(tree, clk->id)) + return tree->fclks[clk->id].rate; - return mtk_topckgen_find_parent_rate(priv, clk, mux->parent[index], - mux->flags); -} + if (mtk_clk_id_is_fdiv(tree, clk->id)) + return mtk_topckgen_get_factor_rate(clk, clk->id - tree->fdivs_offs); -static ulong mtk_find_parent_rate(struct mtk_clk_priv *priv, struct clk *clk, - const int parent, u16 flags) -{ - switch (flags & CLK_PARENT_MASK) { - case CLK_PARENT_XTAL: - return priv->tree->xtal_rate; - /* Assume the second level parent is always APMIXED */ - case CLK_PARENT_APMIXED: - priv = dev_get_priv(priv->parent); - fallthrough; - case CLK_PARENT_TOPCKGEN: - return mtk_clk_find_parent_rate(clk, parent, priv->parent); - default: - return mtk_clk_find_parent_rate(clk, parent, NULL); - } -} - -static ulong mtk_topckgen_get_rate(struct clk *clk) -{ - struct mtk_clk_priv *priv = dev_get_priv(clk->dev); - const struct mtk_clk_tree *tree = priv->tree; + if (mtk_clk_id_is_mux(tree, clk->id)) + return mtk_clk_mux_get_rate(clk, clk->id - tree->muxes_offs); - if (tree->gates && clk->id >= tree->gates_offs && - clk->id < tree->gates_offs + tree->num_gates) { + if (mtk_clk_id_is_gate(tree, clk->id)) { const struct mtk_gate *gate = &tree->gates[clk->id - tree->gates_offs]; - return mtk_clk_find_parent_rate(clk, gate->parent, NULL); + return mtk_find_parent_rate(priv, clk, gate->parent, gate->flags); } - if (clk->id < priv->tree->fdivs_offs) - return priv->tree->fclks[clk->id].rate; - else if (clk->id < priv->tree->muxes_offs) - return mtk_topckgen_get_factor_rate(clk, clk->id - - priv->tree->fdivs_offs); - else - return mtk_topckgen_get_mux_rate(clk, clk->id - - priv->tree->muxes_offs); + return -ENOENT; } static int mtk_clk_mux_enable(struct clk *clk) @@ -744,7 +757,7 @@ static int mtk_clk_mux_enable(struct clk *clk) const struct mtk_composite *mux; u32 val; - if (clk->id < priv->tree->muxes_offs) + if (!mtk_clk_id_is_mux(priv->tree, clk->id)) return 0; mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs]; @@ -761,7 +774,7 @@ static int mtk_clk_mux_enable(struct clk *clk) writel(val, priv->base + mux->gate_reg); } - if (mux->flags & CLK_DOMAIN_SCPSYS) { + if (mux->flags & CLK_MUX_DOMAIN_SCPSYS) { /* enable scpsys clock off control */ writel(SCP_ARMCK_OFF_EN, priv->base + CLK_SCP_CFG0); writel(SCP_AXICK_DCM_DIS_EN | SCP_AXICK_26M_SEL_EN, @@ -776,8 +789,7 @@ static int mtk_topckgen_enable(struct clk *clk) struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_clk_tree *tree = priv->tree; - if (tree->gates && clk->id >= tree->gates_offs && - clk->id < tree->gates_offs + tree->num_gates) { + if (mtk_clk_id_is_gate(tree, clk->id)) { const struct mtk_gate *gate = &tree->gates[clk->id - tree->gates_offs]; return mtk_gate_enable(priv->base, gate); @@ -792,7 +804,7 @@ static int mtk_clk_mux_disable(struct clk *clk) const struct mtk_composite *mux; u32 val; - if (clk->id < priv->tree->muxes_offs) + if (!mtk_clk_id_is_mux(priv->tree, clk->id)) return 0; mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs]; @@ -817,8 +829,7 @@ static int mtk_topckgen_disable(struct clk *clk) struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_clk_tree *tree = priv->tree; - if (tree->gates && clk->id >= tree->gates_offs && - clk->id < tree->gates_offs + tree->num_gates) { + if (mtk_clk_id_is_gate(tree, clk->id)) { const struct mtk_gate *gate = &tree->gates[clk->id - tree->gates_offs]; return mtk_gate_disable(priv->base, gate); @@ -834,8 +845,7 @@ static int mtk_common_clk_set_parent(struct clk *clk, struct clk *parent) int parent_unmapped_id; u32 parent_type; - if (!priv->tree->muxes || clk->id < priv->tree->muxes_offs || - clk->id >= priv->tree->muxes_offs + priv->tree->num_muxes) + if (!mtk_clk_id_is_mux(priv->tree, clk->id)) return 0; if (!parent_priv) @@ -915,29 +925,20 @@ static const int mtk_infrasys_of_xlate(struct clk *clk, return ret; /* ifrasys only uses fdivs, muxes and gates. */ + if (!mtk_clk_id_is_fdiv(tree, clk->id) && !mtk_clk_id_is_mux(tree, clk->id) && + !mtk_clk_id_is_gate(tree, clk->id)) + return -ENOENT; - if (tree->fdivs && clk->id >= tree->fdivs_offs && - clk->id < tree->fdivs_offs + tree->num_fdivs) - return 0; - - if (tree->muxes && clk->id >= tree->muxes_offs && - clk->id < tree->muxes_offs + tree->num_muxes) - return 0; - - if (tree->gates && clk->id >= tree->gates_offs && - clk->id < tree->gates_offs + tree->num_gates) - return 0; - - return -ENOENT; + return 0; } static int mtk_clk_infrasys_enable(struct clk *clk) { - struct mtk_cg_priv *priv = dev_get_priv(clk->dev); + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_gate *gate; /* MUX handling */ - if (!priv->tree->gates || clk->id < priv->tree->gates_offs) + if (!mtk_clk_id_is_gate(priv->tree, clk->id)) return mtk_clk_mux_enable(clk); gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; @@ -946,11 +947,11 @@ static int mtk_clk_infrasys_enable(struct clk *clk) static int mtk_clk_infrasys_disable(struct clk *clk) { - struct mtk_cg_priv *priv = dev_get_priv(clk->dev); + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_gate *gate; /* MUX handling */ - if (!priv->tree->gates || clk->id < priv->tree->gates_offs) + if (!mtk_clk_id_is_gate(priv->tree, clk->id)) return mtk_clk_mux_disable(clk); gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; @@ -963,81 +964,33 @@ static ulong mtk_infrasys_get_factor_rate(struct clk *clk, u32 off) const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off]; ulong rate; - switch (fdiv->flags & CLK_PARENT_MASK) { - case CLK_PARENT_TOPCKGEN: - rate = mtk_clk_find_parent_rate(clk, fdiv->parent, - priv->parent); - break; - case CLK_PARENT_XTAL: - rate = priv->tree->xtal_rate; - break; - default: - rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL); - } - + rate = mtk_find_parent_rate(priv, clk, fdiv->parent, fdiv->flags); if (IS_ERR_VALUE(rate)) return rate; return mtk_factor_recalc_rate(fdiv, rate); } -static ulong mtk_infrasys_get_mux_rate(struct clk *clk, u32 off) -{ - struct mtk_clk_priv *priv = dev_get_priv(clk->dev); - const struct mtk_composite *mux = &priv->tree->muxes[off]; - u32 index; - - index = readl(priv->base + mux->mux_reg); - index &= mux->mux_mask << mux->mux_shift; - index = index >> mux->mux_shift; - - /* - * Parents can be either from TOPCKGEN or INFRACFG, - * inspect the mtk_parent struct to check the source - */ - if (mux->flags & CLK_PARENT_MIXED) { - const struct mtk_parent *parent = &mux->parent_flags[index]; - - return mtk_find_parent_rate(priv, clk, parent->id, parent->flags); - } - - if (mux->parent[index] == CLK_XTAL && - !(priv->tree->flags & CLK_BYPASS_XTAL)) - return priv->tree->xtal_rate; - - return mtk_find_parent_rate(priv, clk, mux->parent[index], mux->flags); -} - static ulong mtk_infrasys_get_rate(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); ulong rate; - if (clk->id < priv->tree->fdivs_offs) { + if (mtk_clk_id_is_fclk(priv->tree, clk->id)) { rate = priv->tree->fclks[clk->id].rate; - } else if (clk->id < priv->tree->muxes_offs) { + } else if (mtk_clk_id_is_fdiv(priv->tree, clk->id)) { rate = mtk_infrasys_get_factor_rate(clk, clk->id - priv->tree->fdivs_offs); /* No gates defined or ID is a MUX */ - } else if (!priv->tree->gates || clk->id < priv->tree->gates_offs) { - rate = mtk_infrasys_get_mux_rate(clk, clk->id - - priv->tree->muxes_offs); + } else if (!mtk_clk_id_is_gate(priv->tree, clk->id)) { + rate = mtk_clk_mux_get_rate(clk, clk->id - priv->tree->muxes_offs); /* Only valid with muxes + gates implementation */ } else { - struct udevice *parent = NULL; const struct mtk_gate *gate; gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; - if (gate->flags & CLK_PARENT_TOPCKGEN) - parent = priv->parent; - /* - * Assume xtal_rate to be declared if some gates have - * XTAL as parent - */ - else if (gate->flags & CLK_PARENT_XTAL) - return priv->tree->xtal_rate; - - rate = mtk_clk_find_parent_rate(clk, gate->parent, parent); + + rate = mtk_find_parent_rate(priv, clk, gate->parent, gate->flags); } return rate; @@ -1146,12 +1099,8 @@ static ulong mtk_clk_gate_get_rate(struct clk *clk) parent->driver != DM_DRIVER_GET(mtk_clk_topckgen)) { priv = dev_get_priv(parent); parent = priv->parent; - /* - * Assume xtal_rate to be declared if some gates have - * XTAL as parent - */ - } else if (gate->flags & CLK_PARENT_XTAL) { - return priv->tree->xtal_rate; + } else if (gate->flags & CLK_PARENT_EXT) { + return mtk_ext_clock_get_rate(priv->tree, gate->parent); } return mtk_clk_find_parent_rate(clk, gate->parent, parent); diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index e618e982e8b..b39a62edc43 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -8,20 +8,14 @@ #define __DRV_CLK_MTK_H #include <linux/bitops.h> -#define CLK_XTAL 0 + #define MHZ (1000 * 1000) /* flags in struct mtk_clk_tree */ -/* clk id == 0 doesn't mean it's xtal clk - * This doesn't apply when CLK_PARENT_MIXED is defined. - * With CLK_PARENT_MIXED declare CLK_PARENT_XTAL for the - * relevant parent. - */ -#define CLK_BYPASS_XTAL BIT(0) +#define CLK_PLL_HAVE_RST_BAR BIT(0) -#define HAVE_RST_BAR BIT(0) -#define CLK_DOMAIN_SCPSYS BIT(0) +#define CLK_MUX_DOMAIN_SCPSYS BIT(0) #define CLK_MUX_SETCLR_UPD BIT(1) #define CLK_GATE_SETCLR BIT(0) @@ -33,13 +27,8 @@ #define CLK_PARENT_APMIXED BIT(4) #define CLK_PARENT_TOPCKGEN BIT(5) #define CLK_PARENT_INFRASYS BIT(6) -#define CLK_PARENT_XTAL BIT(7) -/* - * For CLK_PARENT_MIXED to correctly work, is required to - * define in clk_tree flags the clk type using the alias. - */ -#define CLK_PARENT_MIXED BIT(8) -#define CLK_PARENT_MASK GENMASK(8, 4) +#define CLK_PARENT_EXT BIT(7) +#define CLK_PARENT_MASK GENMASK(7, 4) #define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34 @@ -127,12 +116,17 @@ struct mtk_parent { .flags = _flags, \ } +#define APMIXED_PARENT(id) PARENT(id, CLK_PARENT_APMIXED) +#define TOP_PARENT(id) PARENT(id, CLK_PARENT_TOPCKGEN) +#define INFRA_PARENT(id) PARENT(id, CLK_PARENT_INFRASYS) +#define EXT_PARENT(id) PARENT(id, CLK_PARENT_EXT) +#define VOID_PARENT PARENT(-1, 0) + /** * struct mtk_composite - aggregate clock of mux, divider and gate clocks * * @id: unmapped ID of clocks - * @parent: unmapped ID of parent clocks - * @parent_flags: table of parent clocks with flags + * @parent: array of parent clocks * @mux_reg: hardware-specific mux register * @gate_reg: hardware-specific gate register * @mux_mask: mask to the mux bit field @@ -143,10 +137,7 @@ struct mtk_parent { */ struct mtk_composite { const int id; - union { - const int *parent; - const struct mtk_parent *parent_flags; - }; + const struct mtk_parent *parent; u32 mux_reg; u32 mux_set_reg; u32 mux_clr_reg; @@ -176,19 +167,6 @@ struct mtk_composite { #define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate) \ MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0) -#define MUX_MIXED_FLAGS(_id, _parents, _reg, _shift, _width, _flags) { \ - .id = _id, \ - .mux_reg = _reg, \ - .mux_shift = _shift, \ - .mux_mask = BIT(_width) - 1, \ - .gate_shift = -1, \ - .parent_flags = _parents, \ - .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_PARENT_MIXED | (_flags), \ - } -#define MUX_MIXED(_id, _parents, _reg, _shift, _width) \ - MUX_MIXED_FLAGS(_id, _parents, _reg, _shift, _width, 0) - #define MUX_FLAGS(_id, _parents, _reg, _shift, _width, _flags) { \ .id = _id, \ .mux_reg = _reg, \ @@ -243,10 +221,20 @@ struct mtk_gate { u32 flags; }; +#define GATE_FLAGS(_id, _parent, _regs, _shift, _flags) { \ + .id = _id, \ + .parent = _parent, \ + .regs = _regs, \ + .shift = _shift, \ + .flags = _flags, \ + } + /* struct mtk_clk_tree - clock tree */ struct mtk_clk_tree { - unsigned long xtal_rate; - unsigned long xtal2_rate; + const struct mtk_parent pll_parent; + /* External fixed clocks - excluded from mapping. */ + const ulong *ext_clk_rates; + const int num_ext_clks; /* * Clock IDs may be remapped with an auxiliary table. Enable this by * defining .id_offs_map and .id_offs_map_size. This is needed e.g. when diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig index 62072e100b1..6ac7c9c5654 100644 --- a/drivers/clk/microchip/Kconfig +++ b/drivers/clk/microchip/Kconfig @@ -2,6 +2,5 @@ config CLK_MPFS bool "Clock support for Microchip PolarFire SoC" depends on CLK && CLK_CCF depends on SYSCON - depends on REGMAP help This enables support clock driver for Microchip PolarFire SoC platform. diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 34b63d4df34..07525c36432 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += clk_rk3308.o obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o +obj-$(CONFIG_ROCKCHIP_RK3506) += clk_rk3506.o obj-$(CONFIG_ROCKCHIP_RK3528) += clk_rk3528.o obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o obj-$(CONFIG_ROCKCHIP_RK3576) += clk_rk3576.o diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c index b5054e84c32..d143a6b85ee 100644 --- a/drivers/clk/rockchip/clk_px30.c +++ b/drivers/clk/rockchip/clk_px30.c @@ -13,15 +13,12 @@ #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/cru_px30.h> #include <asm/arch-rockchip/hardware.h> -#include <asm/global_data.h> #include <dm/device-internal.h> #include <dm/lists.h> #include <dt-bindings/clock/px30-cru.h> #include <linux/bitops.h> #include <linux/delay.h> -DECLARE_GLOBAL_DATA_PTR; - enum { VCO_MAX_HZ = 3200U * 1000000, VCO_MIN_HZ = 800 * 1000000, diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c index e73bb6790af..97043b8693c 100644 --- a/drivers/clk/rockchip/clk_rk3308.c +++ b/drivers/clk/rockchip/clk_rk3308.c @@ -10,7 +10,6 @@ #include <log.h> #include <malloc.h> #include <syscon.h> -#include <asm/global_data.h> #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/cru_rk3308.h> #include <asm/arch-rockchip/hardware.h> @@ -19,8 +18,6 @@ #include <dt-bindings/clock/rk3308-cru.h> #include <linux/bitops.h> -DECLARE_GLOBAL_DATA_PTR; - enum { VCO_MAX_HZ = 3200U * 1000000, VCO_MIN_HZ = 800 * 1000000, diff --git a/drivers/clk/rockchip/clk_rk3506.c b/drivers/clk/rockchip/clk_rk3506.c new file mode 100644 index 00000000000..38066c5c3e3 --- /dev/null +++ b/drivers/clk/rockchip/clk_rk3506.c @@ -0,0 +1,1166 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * Author: Finley Xiao <[email protected]> + */ + +#define LOG_CATEGORY UCLASS_CLK + +#include <clk-uclass.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3506.h> +#include <asm/arch-rockchip/hardware.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <dt-bindings/clock/rockchip,rk3506-cru.h> + +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +/* + * [FRAC PLL]: GPLL, V0PLL, V1PLL + * - VCO Frequency: 950MHz to 3800MHZ + * - Output Frequency: 19MHz to 3800MHZ + * - refdiv: 1 to 63 (Int Mode), 1 to 2 (Frac Mode) + * - fbdiv: 16 to 3800 (Int Mode), 20 to 380 (Frac Mode) + * - post1div: 1 to 7 + * - post2div: 1 to 7 + */ +static struct rockchip_pll_rate_table rk3506_pll_rates[] = { + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ + RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), + RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), + RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), + RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), + RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), + RK3036_PLL_RATE(1500000000, 1, 125, 2, 1, 1, 0), + RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), + RK3036_PLL_RATE(1350000000, 4, 225, 1, 1, 1, 0), + RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), + RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), + RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), + RK3036_PLL_RATE(1179648000, 1, 49, 1, 1, 0, 2550137), + RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), + RK3036_PLL_RATE(1000000000, 3, 125, 1, 1, 1, 0), + RK3036_PLL_RATE(993484800, 1, 41, 1, 1, 0, 6630355), + RK3036_PLL_RATE(983040000, 1, 40, 1, 1, 0, 16106127), + RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0), + RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), + RK3036_PLL_RATE(903168000, 1, 75, 2, 1, 0, 4429185), + RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), + RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0), + RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0), + RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0), + RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), + RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), + RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), + RK3036_PLL_RATE(96000000, 1, 48, 6, 2, 1, 0), + { /* sentinel */ }, +}; + +static struct rockchip_pll_clock rk3506_pll_clks[] = { + [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3506_PLL_CON(0), + RK3506_MODE_CON, 0, 10, 0, rk3506_pll_rates), + [V0PLL] = PLL(pll_rk3328, PLL_V0PLL, RK3506_PLL_CON(8), + RK3506_MODE_CON, 2, 10, 0, rk3506_pll_rates), + [V1PLL] = PLL(pll_rk3328, PLL_V1PLL, RK3506_PLL_CON(16), + RK3506_MODE_CON, 4, 10, 0, rk3506_pll_rates), +}; + +#define RK3506_CPUCLK_RATE(_rate, _aclk_m_core, _pclk_dbg) \ +{ \ + .rate = _rate##U, \ + .aclk_div = (_aclk_m_core), \ + .pclk_div = (_pclk_dbg), \ +} + +/* SIGN-OFF: aclk_core: 500M, pclk_core: 125M, */ +static struct rockchip_cpu_rate_table rk3506_cpu_rates[] = { + RK3506_CPUCLK_RATE(1179648000, 1, 6), + RK3506_CPUCLK_RATE(903168000, 1, 5), + RK3506_CPUCLK_RATE(800000000, 1, 4), + RK3506_CPUCLK_RATE(589824000, 1, 3), + RK3506_CPUCLK_RATE(400000000, 1, 2), + RK3506_CPUCLK_RATE(200000000, 1, 1), + { /* sentinel */ }, +}; + +static int rk3506_armclk_get_rate(struct rk3506_clk_priv *priv) +{ + u32 con, div, sel; + ulong prate; + + con = readl(RK3506_CLKSEL_CON(15)); + sel = FIELD_GET(CLK_CORE_SRC_SEL_MASK, con); + div = FIELD_GET(CLK_CORE_SRC_DIV_MASK, con); + + if (sel == CLK_CORE_SEL_GPLL) + prate = priv->gpll_hz; + else if (sel == CLK_CORE_SEL_V0PLL) + prate = priv->v0pll_hz; + else if (sel == CLK_CORE_SEL_V1PLL) + prate = priv->v1pll_hz; + else + return -EINVAL; + + return DIV_TO_RATE(prate, div); +} + +static int rk3506_armclk_set_rate(struct rk3506_clk_priv *priv, ulong new_rate) +{ + const struct rockchip_cpu_rate_table *rate; + u32 con, div, old_div, sel; + ulong old_rate, prate; + + rate = rockchip_get_cpu_settings(rk3506_cpu_rates, new_rate); + if (!rate) { + log_debug("unsupported cpu rate %lu\n", new_rate); + return -EINVAL; + } + + /* + * set up dependent divisors for PCLK and ACLK clocks. + */ + old_rate = rk3506_armclk_get_rate(priv); + if (new_rate >= old_rate) { + rk_clrsetreg(RK3506_CLKSEL_CON(15), ACLK_CORE_DIV_MASK, + FIELD_PREP(ACLK_CORE_DIV_MASK, rate->aclk_div)); + rk_clrsetreg(RK3506_CLKSEL_CON(16), PCLK_CORE_DIV_MASK, + FIELD_PREP(PCLK_CORE_DIV_MASK, rate->pclk_div)); + } + + if (new_rate == 589824000 || new_rate == 1179648000) { + sel = CLK_CORE_SEL_V0PLL; + div = DIV_ROUND_UP(priv->v0pll_hz, new_rate); + prate = priv->v0pll_hz; + } else if (new_rate == 903168000) { + sel = CLK_CORE_SEL_V1PLL; + div = DIV_ROUND_UP(priv->v1pll_hz, new_rate); + prate = priv->v1pll_hz; + } else { + sel = CLK_CORE_SEL_GPLL; + div = DIV_ROUND_UP(priv->gpll_hz, new_rate); + prate = priv->gpll_hz; + } + assert(div - 1 <= 31); + + con = readl(RK3506_CLKSEL_CON(15)); + old_div = FIELD_GET(CLK_CORE_SRC_DIV_MASK, con); + if (DIV_TO_RATE(prate, old_div) > new_rate) { + rk_clrsetreg(RK3506_CLKSEL_CON(15), CLK_CORE_SRC_DIV_MASK, + FIELD_PREP(CLK_CORE_SRC_DIV_MASK, div - 1)); + rk_clrsetreg(RK3506_CLKSEL_CON(15), CLK_CORE_SRC_SEL_MASK, + FIELD_PREP(CLK_CORE_SRC_SEL_MASK, sel)); + } else { + rk_clrsetreg(RK3506_CLKSEL_CON(15), CLK_CORE_SRC_SEL_MASK, + FIELD_PREP(CLK_CORE_SRC_SEL_MASK, sel)); + rk_clrsetreg(RK3506_CLKSEL_CON(15), CLK_CORE_SRC_DIV_MASK, + FIELD_PREP(CLK_CORE_SRC_DIV_MASK, div - 1)); + } + + if (new_rate < old_rate) { + rk_clrsetreg(RK3506_CLKSEL_CON(15), ACLK_CORE_DIV_MASK, + FIELD_PREP(ACLK_CORE_DIV_MASK, rate->aclk_div)); + rk_clrsetreg(RK3506_CLKSEL_CON(16), PCLK_CORE_DIV_MASK, + FIELD_PREP(PCLK_CORE_DIV_MASK, rate->pclk_div)); + } + + return rk3506_armclk_get_rate(priv); +} + +static ulong rk3506_pll_div_get_rate(struct rk3506_clk_priv *priv, ulong clk_id) +{ + u32 con, div; + ulong prate; + + switch (clk_id) { + case CLK_GPLL_DIV: + con = readl(RK3506_CLKSEL_CON(0)); + div = FIELD_GET(CLK_GPLL_DIV_MASK, con); + prate = priv->gpll_hz; + break; + case CLK_GPLL_DIV_100M: + con = readl(RK3506_CLKSEL_CON(0)); + div = FIELD_GET(CLK_GPLL_DIV_100M_MASK, con); + prate = priv->gpll_div_hz; + break; + case CLK_V0PLL_DIV: + con = readl(RK3506_CLKSEL_CON(1)); + div = FIELD_GET(CLK_V0PLL_DIV_MASK, con); + prate = priv->v0pll_hz; + break; + case CLK_V1PLL_DIV: + con = readl(RK3506_CLKSEL_CON(1)); + div = FIELD_GET(CLK_V1PLL_DIV_MASK, con); + prate = priv->v1pll_hz; + break; + default: + return -ENOENT; + } + + return DIV_TO_RATE(prate, div); +} + +static ulong rk3506_pll_div_set_rate(struct rk3506_clk_priv *priv, ulong clk_id, + ulong rate) +{ + u32 div; + + switch (clk_id) { + case CLK_GPLL_DIV: + div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(div - 1 <= 15); + rk_clrsetreg(RK3506_CLKSEL_CON(0), CLK_GPLL_DIV_MASK, + FIELD_PREP(CLK_GPLL_DIV_MASK, div - 1)); + break; + case CLK_GPLL_DIV_100M: + div = DIV_ROUND_UP(priv->gpll_div_hz, rate); + assert(div - 1 <= 15); + rk_clrsetreg(RK3506_CLKSEL_CON(0), CLK_GPLL_DIV_100M_MASK, + FIELD_PREP(CLK_GPLL_DIV_100M_MASK, div - 1)); + break; + case CLK_V0PLL_DIV: + div = DIV_ROUND_UP(priv->v0pll_hz, rate); + assert(div - 1 <= 15); + rk_clrsetreg(RK3506_CLKSEL_CON(1), CLK_V0PLL_DIV_MASK, + FIELD_PREP(CLK_V0PLL_DIV_MASK, div - 1)); + break; + case CLK_V1PLL_DIV: + div = DIV_ROUND_UP(priv->v1pll_hz, rate); + assert(div - 1 <= 15); + rk_clrsetreg(RK3506_CLKSEL_CON(1), CLK_V1PLL_DIV_MASK, + FIELD_PREP(CLK_V1PLL_DIV_MASK, div - 1)); + break; + default: + return -ENOENT; + } + + return rk3506_pll_div_get_rate(priv, clk_id); +} + +static ulong rk3506_bus_get_rate(struct rk3506_clk_priv *priv, ulong clk_id) +{ + u32 con, div, sel; + ulong prate; + + switch (clk_id) { + case ACLK_BUS_ROOT: + con = readl(RK3506_CLKSEL_CON(21)); + sel = FIELD_GET(ACLK_BUS_SEL_MASK, con); + div = FIELD_GET(ACLK_BUS_DIV_MASK, con); + break; + case HCLK_BUS_ROOT: + con = readl(RK3506_CLKSEL_CON(21)); + sel = FIELD_GET(HCLK_BUS_SEL_MASK, con); + div = FIELD_GET(HCLK_BUS_DIV_MASK, con); + break; + case PCLK_BUS_ROOT: + con = readl(RK3506_CLKSEL_CON(22)); + sel = FIELD_GET(PCLK_BUS_SEL_MASK, con); + div = FIELD_GET(PCLK_BUS_DIV_MASK, con); + break; + default: + return -ENOENT; + } + + if (sel == ACLK_BUS_SEL_GPLL_DIV) + prate = priv->gpll_div_hz; + else if (sel == ACLK_BUS_SEL_V0PLL_DIV) + prate = priv->v0pll_div_hz; + else if (sel == ACLK_BUS_SEL_V1PLL_DIV) + prate = priv->v1pll_div_hz; + else + return -EINVAL; + + return DIV_TO_RATE(prate, div); +} + +static ulong rk3506_bus_set_rate(struct rk3506_clk_priv *priv, ulong clk_id, + ulong rate) +{ + u32 div, sel; + + if (priv->v0pll_div_hz % rate == 0) { + sel = ACLK_BUS_SEL_V0PLL_DIV; + div = DIV_ROUND_UP(priv->v0pll_div_hz, rate); + } else if (priv->v1pll_div_hz % rate == 0) { + sel = ACLK_BUS_SEL_V1PLL_DIV; + div = DIV_ROUND_UP(priv->v1pll_div_hz, rate); + } else { + sel = ACLK_BUS_SEL_GPLL_DIV; + div = DIV_ROUND_UP(priv->gpll_div_hz, rate); + } + assert(div - 1 <= 31); + + switch (clk_id) { + case ACLK_BUS_ROOT: + rk_clrsetreg(RK3506_CLKSEL_CON(21), + ACLK_BUS_SEL_MASK | ACLK_BUS_DIV_MASK, + FIELD_PREP(ACLK_BUS_SEL_MASK, sel) | + FIELD_PREP(ACLK_BUS_DIV_MASK, div - 1)); + break; + case HCLK_BUS_ROOT: + rk_clrsetreg(RK3506_CLKSEL_CON(21), + HCLK_BUS_SEL_MASK | HCLK_BUS_DIV_MASK, + FIELD_PREP(HCLK_BUS_SEL_MASK, sel) | + FIELD_PREP(HCLK_BUS_DIV_MASK, div - 1)); + break; + case PCLK_BUS_ROOT: + rk_clrsetreg(RK3506_CLKSEL_CON(22), + PCLK_BUS_SEL_MASK | PCLK_BUS_DIV_MASK, + FIELD_PREP(PCLK_BUS_SEL_MASK, sel) | + FIELD_PREP(PCLK_BUS_DIV_MASK, div - 1)); + break; + default: + return -ENOENT; + } + + return rk3506_bus_get_rate(priv, clk_id); +} + +static ulong rk3506_peri_get_rate(struct rk3506_clk_priv *priv, ulong clk_id) +{ + u32 con, div, sel; + ulong prate; + + switch (clk_id) { + case ACLK_HSPERI_ROOT: + con = readl(RK3506_CLKSEL_CON(49)); + sel = FIELD_GET(ACLK_HSPERI_SEL_MASK, con); + div = FIELD_GET(ACLK_HSPERI_DIV_MASK, con); + break; + case HCLK_LSPERI_ROOT: + con = readl(RK3506_CLKSEL_CON(29)); + sel = FIELD_GET(HCLK_LSPERI_SEL_MASK, con); + div = FIELD_GET(HCLK_LSPERI_DIV_MASK, con); + break; + default: + return -ENOENT; + } + + if (sel == ACLK_HSPERI_SEL_GPLL_DIV) + prate = priv->gpll_div_hz; + else if (sel == ACLK_HSPERI_SEL_V0PLL_DIV) + prate = priv->v0pll_div_hz; + else if (sel == ACLK_HSPERI_SEL_V1PLL_DIV) + prate = priv->v1pll_div_hz; + else + return -EINVAL; + + return DIV_TO_RATE(prate, div); +} + +static ulong rk3506_peri_set_rate(struct rk3506_clk_priv *priv, ulong clk_id, + ulong rate) +{ + u32 div, sel; + + if (priv->v0pll_div_hz % rate == 0) { + sel = ACLK_BUS_SEL_V0PLL_DIV; + div = DIV_ROUND_UP(priv->v0pll_div_hz, rate); + } else if (priv->v1pll_div_hz % rate == 0) { + sel = ACLK_BUS_SEL_V1PLL_DIV; + div = DIV_ROUND_UP(priv->v1pll_div_hz, rate); + } else { + sel = ACLK_BUS_SEL_GPLL_DIV; + div = DIV_ROUND_UP(priv->gpll_div_hz, rate); + } + assert(div - 1 <= 31); + + switch (clk_id) { + case ACLK_HSPERI_ROOT: + rk_clrsetreg(RK3506_CLKSEL_CON(49), + ACLK_HSPERI_SEL_MASK | ACLK_HSPERI_DIV_MASK, + FIELD_PREP(ACLK_HSPERI_SEL_MASK, sel) | + FIELD_PREP(ACLK_HSPERI_DIV_MASK, div - 1)); + break; + case HCLK_LSPERI_ROOT: + rk_clrsetreg(RK3506_CLKSEL_CON(29), + HCLK_LSPERI_SEL_MASK | HCLK_LSPERI_DIV_MASK, + FIELD_PREP(HCLK_LSPERI_SEL_MASK, sel) | + FIELD_PREP(HCLK_LSPERI_DIV_MASK, div - 1)); + break; + default: + return -ENOENT; + } + + return rk3506_peri_get_rate(priv, clk_id); +} + +static ulong rk3506_sdmmc_get_rate(struct rk3506_clk_priv *priv, ulong clk_id) +{ + u32 con, div, sel; + ulong prate; + + con = readl(RK3506_CLKSEL_CON(49)); + sel = FIELD_GET(CCLK_SDMMC_SEL_MASK, con); + div = FIELD_GET(CCLK_SDMMC_DIV_MASK, con); + + if (sel == CCLK_SDMMC_SEL_24M) + prate = OSC_HZ; + else if (sel == CCLK_SDMMC_SEL_GPLL) + prate = priv->gpll_hz; + else if (sel == CCLK_SDMMC_SEL_V0PLL) + prate = priv->v0pll_hz; + else if (sel == CCLK_SDMMC_SEL_V1PLL) + prate = priv->v1pll_hz; + else + return -EINVAL; + + return DIV_TO_RATE(prate, div); +} + +static ulong rk3506_sdmmc_set_rate(struct rk3506_clk_priv *priv, ulong clk_id, + ulong rate) +{ + u32 div, sel; + + if (OSC_HZ % rate == 0) { + sel = CCLK_SDMMC_SEL_24M; + div = DIV_ROUND_UP(OSC_HZ, rate); + } else if (priv->v0pll_hz % rate == 0) { + sel = CCLK_SDMMC_SEL_V0PLL; + div = DIV_ROUND_UP(priv->v0pll_hz, rate); + } else if (priv->v1pll_hz % rate == 0) { + sel = CCLK_SDMMC_SEL_V1PLL; + div = DIV_ROUND_UP(priv->v1pll_hz, rate); + } else { + sel = CCLK_SDMMC_SEL_GPLL; + div = DIV_ROUND_UP(priv->gpll_hz, rate); + } + assert(div - 1 <= 63); + + rk_clrsetreg(RK3506_CLKSEL_CON(49), + CCLK_SDMMC_SEL_MASK | CCLK_SDMMC_DIV_MASK, + FIELD_PREP(CCLK_SDMMC_SEL_MASK, sel) | + FIELD_PREP(CCLK_SDMMC_DIV_MASK, div - 1)); + + return rk3506_sdmmc_get_rate(priv, clk_id); +} + +static ulong rk3506_saradc_get_rate(struct rk3506_clk_priv *priv, ulong clk_id) +{ + u32 con, div, sel; + ulong prate; + + con = readl(RK3506_CLKSEL_CON(54)); + sel = FIELD_GET(CLK_SARADC_SEL_MASK, con); + div = FIELD_GET(CLK_SARADC_DIV_MASK, con); + + if (sel == CLK_SARADC_SEL_24M) + prate = OSC_HZ; + else if (sel == CLK_SARADC_SEL_400K) + prate = 400000; + else if (sel == CLK_SARADC_SEL_32K) + prate = 32000; + else + return -EINVAL; + + return DIV_TO_RATE(prate, div); +} + +static ulong rk3506_saradc_set_rate(struct rk3506_clk_priv *priv, ulong clk_id, + ulong rate) +{ + u32 div, sel; + + if (32000 % rate == 0) { + sel = CLK_SARADC_SEL_32K; + div = 1; + } else if (400000 % rate == 0) { + sel = CLK_SARADC_SEL_400K; + div = 1; + } else { + sel = CLK_SARADC_SEL_24M; + div = DIV_ROUND_UP(OSC_HZ, rate); + } + assert(div - 1 <= 15); + + rk_clrsetreg(RK3506_CLKSEL_CON(54), + CLK_SARADC_SEL_MASK | CLK_SARADC_DIV_MASK, + FIELD_PREP(CLK_SARADC_SEL_MASK, sel) | + FIELD_PREP(CLK_SARADC_DIV_MASK, div - 1)); + + return rk3506_saradc_get_rate(priv, clk_id); +} + +static ulong rk3506_tsadc_get_rate(struct rk3506_clk_priv *priv, ulong clk_id) +{ + u32 con, div; + + con = readl(RK3506_CLKSEL_CON(61)); + switch (clk_id) { + case CLK_TSADC_TSEN: + div = FIELD_GET(CLK_TSADC_TSEN_DIV_MASK, con); + break; + case CLK_TSADC: + div = FIELD_GET(CLK_TSADC_DIV_MASK, con); + break; + default: + return -ENOENT; + } + + return DIV_TO_RATE(OSC_HZ, div); +} + +static ulong rk3506_tsadc_set_rate(struct rk3506_clk_priv *priv, ulong clk_id, + ulong rate) +{ + u32 div; + + switch (clk_id) { + case CLK_TSADC_TSEN: + div = DIV_ROUND_UP(OSC_HZ, rate); + assert(div - 1 <= 7); + rk_clrsetreg(RK3506_CLKSEL_CON(61), CLK_TSADC_TSEN_DIV_MASK, + FIELD_PREP(CLK_TSADC_TSEN_DIV_MASK, div - 1)); + break; + case CLK_TSADC: + div = DIV_ROUND_UP(OSC_HZ, rate); + assert(div - 1 <= 255); + rk_clrsetreg(RK3506_CLKSEL_CON(61), CLK_TSADC_DIV_MASK, + FIELD_PREP(CLK_TSADC_DIV_MASK, div - 1)); + break; + default: + return -ENOENT; + } + + return rk3506_tsadc_get_rate(priv, clk_id); +} + +static ulong rk3506_i2c_get_rate(struct rk3506_clk_priv *priv, ulong clk_id) +{ + u32 con, div, sel; + ulong prate; + + switch (clk_id) { + case CLK_I2C0: + con = readl(RK3506_CLKSEL_CON(32)); + sel = FIELD_GET(CLK_I2C0_SEL_MASK, con); + div = FIELD_GET(CLK_I2C0_DIV_MASK, con); + case CLK_I2C1: + con = readl(RK3506_CLKSEL_CON(32)); + sel = FIELD_GET(CLK_I2C1_SEL_MASK, con); + div = FIELD_GET(CLK_I2C1_DIV_MASK, con); + case CLK_I2C2: + con = readl(RK3506_CLKSEL_CON(33)); + sel = FIELD_GET(CLK_I2C2_SEL_MASK, con); + div = FIELD_GET(CLK_I2C2_DIV_MASK, con); + break; + default: + return -ENOENT; + } + + if (sel == CLK_I2C_SEL_GPLL) + prate = priv->gpll_hz; + else if (sel == CLK_I2C_SEL_V0PLL) + prate = priv->v0pll_hz; + else if (sel == CLK_I2C_SEL_V1PLL) + prate = priv->v1pll_hz; + else + return -EINVAL; + + return DIV_TO_RATE(prate, div); +} + +static ulong rk3506_i2c_set_rate(struct rk3506_clk_priv *priv, ulong clk_id, + ulong rate) +{ + u32 div, sel; + + if (priv->v0pll_hz % rate == 0) { + sel = CLK_I2C_SEL_V0PLL; + div = DIV_ROUND_UP(priv->v0pll_hz, rate); + } else if (priv->v1pll_hz % rate == 0) { + sel = CLK_I2C_SEL_V1PLL; + div = DIV_ROUND_UP(priv->v1pll_hz, rate); + } else { + sel = CLK_I2C_SEL_GPLL; + div = DIV_ROUND_UP(priv->gpll_hz, rate); + } + assert(div - 1 <= 15); + + switch (clk_id) { + case CLK_I2C0: + rk_clrsetreg(RK3506_CLKSEL_CON(32), + CLK_I2C0_SEL_MASK | CLK_I2C0_DIV_MASK, + FIELD_PREP(CLK_I2C0_SEL_MASK, sel) | + FIELD_PREP(CLK_I2C0_DIV_MASK, div - 1)); + break; + case CLK_I2C1: + rk_clrsetreg(RK3506_CLKSEL_CON(32), + CLK_I2C1_SEL_MASK | CLK_I2C1_DIV_MASK, + FIELD_PREP(CLK_I2C1_SEL_MASK, sel) | + FIELD_PREP(CLK_I2C1_DIV_MASK, div - 1)); + break; + case CLK_I2C2: + rk_clrsetreg(RK3506_CLKSEL_CON(33), + CLK_I2C2_SEL_MASK | CLK_I2C2_DIV_MASK, + FIELD_PREP(CLK_I2C2_SEL_MASK, sel) | + FIELD_PREP(CLK_I2C2_DIV_MASK, div - 1)); + break; + default: + return -ENOENT; + } + + return rk3506_i2c_get_rate(priv, clk_id); +} + +static ulong rk3506_pwm_get_rate(struct rk3506_clk_priv *priv, ulong clk_id) +{ + u32 con, div, sel; + ulong prate; + + switch (clk_id) { + case CLK_PWM0: + con = readl(RK3506_PMU_CLKSEL_CON(0)); + div = FIELD_GET(CLK_PWM0_DIV_MASK, con); + prate = priv->gpll_div_100mhz; + break; + case CLK_PWM1: + con = readl(RK3506_CLKSEL_CON(33)); + sel = FIELD_GET(CLK_PWM1_SEL_MASK, con); + div = FIELD_GET(CLK_PWM1_DIV_MASK, con); + if (sel == CLK_PWM1_SEL_GPLL_DIV) + prate = priv->gpll_div_hz; + else if (sel == CLK_PWM1_SEL_V0PLL_DIV) + prate = priv->v0pll_div_hz; + else if (sel == CLK_PWM1_SEL_V1PLL_DIV) + prate = priv->v1pll_div_hz; + else + return -EINVAL; + break; + default: + return -ENOENT; + } + + return DIV_TO_RATE(prate, div); +} + +static ulong rk3506_pwm_set_rate(struct rk3506_clk_priv *priv, ulong clk_id, + ulong rate) +{ + u32 div, sel; + + switch (clk_id) { + case CLK_PWM0: + div = DIV_ROUND_UP(priv->gpll_div_100mhz, rate); + assert(div - 1 <= 15); + rk_clrsetreg(RK3506_PMU_CLKSEL_CON(0), CLK_PWM0_DIV_MASK, + FIELD_PREP(CLK_PWM0_DIV_MASK, div - 1)); + break; + case CLK_PWM1: + if (priv->v0pll_hz % rate == 0) { + sel = CLK_PWM1_SEL_V0PLL_DIV; + div = DIV_ROUND_UP(priv->v0pll_div_hz, rate); + } else if (priv->v1pll_hz % rate == 0) { + sel = CLK_PWM1_SEL_V1PLL_DIV; + div = DIV_ROUND_UP(priv->v1pll_div_hz, rate); + } else { + sel = CLK_PWM1_SEL_GPLL_DIV; + div = DIV_ROUND_UP(priv->gpll_div_hz, rate); + } + assert(div - 1 <= 15); + rk_clrsetreg(RK3506_CLKSEL_CON(33), + CLK_PWM1_SEL_MASK | CLK_PWM1_DIV_MASK, + FIELD_PREP(CLK_PWM1_SEL_MASK, sel) | + FIELD_PREP(CLK_PWM1_DIV_MASK, div - 1)); + break; + default: + return -ENOENT; + } + + return rk3506_pwm_get_rate(priv, clk_id); +} + +static ulong rk3506_spi_get_rate(struct rk3506_clk_priv *priv, ulong clk_id) +{ + u32 con, div, sel; + ulong prate; + + switch (clk_id) { + case CLK_SPI0: + con = readl(RK3506_CLKSEL_CON(34)); + sel = FIELD_GET(CLK_SPI0_SEL_MASK, con); + div = FIELD_GET(CLK_SPI0_DIV_MASK, con); + break; + case CLK_SPI1: + con = readl(RK3506_CLKSEL_CON(34)); + sel = FIELD_GET(CLK_SPI1_SEL_MASK, con); + div = FIELD_GET(CLK_SPI1_DIV_MASK, con); + break; + default: + return -ENOENT; + } + + if (sel == CLK_SPI_SEL_24M) + prate = OSC_HZ; + else if (sel == CLK_SPI_SEL_GPLL_DIV) + prate = priv->gpll_div_hz; + else if (sel == CLK_SPI_SEL_V0PLL_DIV) + prate = priv->v0pll_div_hz; + else if (sel == CLK_SPI_SEL_V1PLL_DIV) + prate = priv->v1pll_div_hz; + else + return -EINVAL; + + return DIV_TO_RATE(prate, div); +} + +static ulong rk3506_spi_set_rate(struct rk3506_clk_priv *priv, ulong clk_id, + ulong rate) +{ + u32 div, sel; + + if (OSC_HZ % rate == 0) { + sel = CLK_SPI_SEL_24M; + div = DIV_ROUND_UP(OSC_HZ, rate); + } else if (priv->v0pll_div_hz % rate == 0) { + sel = CLK_SPI_SEL_V0PLL_DIV; + div = DIV_ROUND_UP(priv->v0pll_div_hz, rate); + } else if (priv->v1pll_div_hz % rate == 0) { + sel = CLK_SPI_SEL_V1PLL_DIV; + div = DIV_ROUND_UP(priv->v1pll_div_hz, rate); + } else { + sel = CLK_SPI_SEL_GPLL_DIV; + div = DIV_ROUND_UP(priv->gpll_div_hz, rate); + } + assert(div - 1 <= 15); + + switch (clk_id) { + case CLK_SPI0: + rk_clrsetreg(RK3506_CLKSEL_CON(34), + CLK_SPI0_SEL_MASK | CLK_SPI0_DIV_MASK, + FIELD_PREP(CLK_SPI0_SEL_MASK, sel) | + FIELD_PREP(CLK_SPI0_DIV_MASK, div - 1)); + break; + case CLK_SPI1: + rk_clrsetreg(RK3506_CLKSEL_CON(34), + CLK_SPI1_SEL_MASK | CLK_SPI1_DIV_MASK, + FIELD_PREP(CLK_SPI1_SEL_MASK, sel) | + FIELD_PREP(CLK_SPI1_DIV_MASK, div - 1)); + break; + default: + return -ENOENT; + } + + return rk3506_spi_get_rate(priv, clk_id); +} + +static ulong rk3506_fspi_get_rate(struct rk3506_clk_priv *priv) +{ + u32 con, div, sel; + ulong prate; + + con = readl(RK3506_CLKSEL_CON(50)); + sel = FIELD_GET(SCLK_FSPI_SEL_MASK, con); + div = FIELD_GET(SCLK_FSPI_DIV_MASK, con); + + if (sel == SCLK_FSPI_SEL_24M) + prate = OSC_HZ; + else if (sel == SCLK_FSPI_SEL_GPLL) + prate = priv->gpll_hz; + else if (sel == SCLK_FSPI_SEL_V0PLL) + prate = priv->v0pll_hz; + else if (sel == SCLK_FSPI_SEL_V1PLL) + prate = priv->v1pll_hz; + else + return -EINVAL; + + return DIV_TO_RATE(prate, div); +} + +static ulong rk3506_fspi_set_rate(struct rk3506_clk_priv *priv, ulong rate) +{ + int div, sel; + + if (OSC_HZ % rate == 0) { + sel = SCLK_FSPI_SEL_24M; + div = DIV_ROUND_UP(OSC_HZ, rate); + } else if (priv->v0pll_hz % rate == 0) { + sel = SCLK_FSPI_SEL_V0PLL; + div = DIV_ROUND_UP(priv->v0pll_hz, rate); + } else if (priv->v1pll_hz % rate == 0) { + sel = SCLK_FSPI_SEL_V1PLL; + div = DIV_ROUND_UP(priv->v1pll_hz, rate); + } else { + sel = SCLK_FSPI_SEL_GPLL; + div = DIV_ROUND_UP(priv->gpll_hz, rate); + } + assert(div - 1 <= 31); + + rk_clrsetreg(RK3506_CLKSEL_CON(50), + SCLK_FSPI_SEL_MASK | SCLK_FSPI_DIV_MASK, + FIELD_PREP(SCLK_FSPI_SEL_MASK, sel) | + FIELD_PREP(SCLK_FSPI_DIV_MASK, div - 1)); + + return rk3506_fspi_get_rate(priv); +} + +static ulong rk3506_vop_dclk_get_rate(struct rk3506_clk_priv *priv) +{ + u32 con, div, sel; + ulong prate; + + con = readl(RK3506_CLKSEL_CON(60)); + sel = FIELD_GET(DCLK_VOP_SEL_MASK, con); + div = FIELD_GET(DCLK_VOP_DIV_MASK, con); + + if (sel == DCLK_VOP_SEL_24M) + prate = OSC_HZ; + else if (sel == DCLK_VOP_SEL_GPLL) + prate = priv->gpll_hz; + else if (sel == DCLK_VOP_SEL_V0PLL) + prate = priv->v0pll_hz; + else if (sel == DCLK_VOP_SEL_V1PLL) + prate = priv->v1pll_hz; + else + return -EINVAL; + + return DIV_TO_RATE(prate, div); +} + +static ulong rk3506_vop_dclk_set_rate(struct rk3506_clk_priv *priv, ulong rate) +{ + int div, sel; + + if (OSC_HZ % rate == 0) { + sel = DCLK_VOP_SEL_24M; + div = DIV_ROUND_UP(OSC_HZ, rate); + } else if (priv->v0pll_hz % rate == 0) { + sel = DCLK_VOP_SEL_V0PLL; + div = DIV_ROUND_UP(priv->v0pll_hz, rate); + } else if (priv->v1pll_hz % rate == 0) { + sel = DCLK_VOP_SEL_V1PLL; + div = DIV_ROUND_UP(priv->v1pll_hz, rate); + } else { + sel = DCLK_VOP_SEL_GPLL; + div = DIV_ROUND_UP(priv->gpll_hz, rate); + } + assert(div - 1 <= 255); + + rk_clrsetreg(RK3506_CLKSEL_CON(60), + DCLK_VOP_SEL_MASK | DCLK_VOP_DIV_MASK, + FIELD_PREP(DCLK_VOP_SEL_MASK, sel) | + FIELD_PREP(DCLK_VOP_DIV_MASK, div - 1)); + + return rk3506_vop_dclk_get_rate(priv); +} + +static ulong rk3506_mac_get_rate(struct rk3506_clk_priv *priv, ulong clk_id) +{ + u32 con, div; + + switch (clk_id) { + case CLK_MAC0: + case CLK_MAC1: + con = readl(RK3506_CLKSEL_CON(50)); + div = FIELD_GET(CLK_MAC_DIV_MASK, con); + break; + case CLK_MAC_OUT: + con = readl(RK3506_PMU_CLKSEL_CON(0)); + div = FIELD_GET(CLK_MAC_OUT_DIV_MASK, con); + break; + default: + return -ENOENT; + } + + return DIV_TO_RATE(priv->gpll_hz, div); +} + +static ulong rk3506_mac_set_rate(struct rk3506_clk_priv *priv, ulong clk_id, + ulong rate) +{ + u32 div; + + switch (clk_id) { + case CLK_MAC0: + case CLK_MAC1: + div = DIV_ROUND_UP(priv->gpll_hz, rate); + rk_clrsetreg(RK3506_CLKSEL_CON(50), CLK_MAC_DIV_MASK, + FIELD_PREP(CLK_MAC_DIV_MASK, div - 1)); + break; + case CLK_MAC_OUT: + div = DIV_ROUND_UP(priv->gpll_hz, rate); + rk_clrsetreg(RK3506_PMU_CLKSEL_CON(0), CLK_MAC_OUT_DIV_MASK, + FIELD_PREP(CLK_MAC_OUT_DIV_MASK, div - 1)); + break; + default: + return -ENOENT; + } + + return rk3506_mac_get_rate(priv, clk_id); +} + +static ulong rk3506_clk_get_rate(struct clk *clk) +{ + struct rk3506_clk_priv *priv = dev_get_priv(clk->dev); + ulong rate = 0; + + if (!priv->gpll_hz || !priv->v0pll_hz || !priv->v1pll_hz) { + log_debug("gpll=%lu, v0pll=%lu, v1pll=%lu\n", + priv->gpll_hz, priv->v0pll_hz, priv->v1pll_hz); + return -ENOENT; + } + + switch (clk->id) { + case PLL_GPLL: + rate = priv->gpll_hz; + break; + case PLL_V0PLL: + rate = priv->v0pll_hz; + break; + case PLL_V1PLL: + rate = priv->v1pll_hz; + break; + case ARMCLK: + rate = rk3506_armclk_get_rate(priv); + break; + case CLK_GPLL_DIV: + case CLK_GPLL_DIV_100M: + case CLK_V0PLL_DIV: + case CLK_V1PLL_DIV: + rate = rk3506_pll_div_get_rate(priv, clk->id); + break; + case ACLK_BUS_ROOT: + case HCLK_BUS_ROOT: + case PCLK_BUS_ROOT: + rate = rk3506_bus_get_rate(priv, clk->id); + break; + case ACLK_HSPERI_ROOT: + case HCLK_LSPERI_ROOT: + rate = rk3506_peri_get_rate(priv, clk->id); + break; + case HCLK_SDMMC: + case CCLK_SRC_SDMMC: + rate = rk3506_sdmmc_get_rate(priv, clk->id); + break; + case CLK_SARADC: + rate = rk3506_saradc_get_rate(priv, clk->id); + break; + case CLK_TSADC: + case CLK_TSADC_TSEN: + rate = rk3506_tsadc_get_rate(priv, clk->id); + break; + case CLK_I2C0: + case CLK_I2C1: + case CLK_I2C2: + rate = rk3506_i2c_get_rate(priv, clk->id); + break; + case CLK_PWM0: + case CLK_PWM1: + rate = rk3506_pwm_get_rate(priv, clk->id); + break; + case CLK_SPI0: + case CLK_SPI1: + rate = rk3506_spi_get_rate(priv, clk->id); + break; + case SCLK_FSPI: + rate = rk3506_fspi_get_rate(priv); + break; + case DCLK_VOP: + rate = rk3506_vop_dclk_get_rate(priv); + break; + case CLK_MAC0: + case CLK_MAC1: + case CLK_MAC_OUT: + rate = rk3506_mac_get_rate(priv, clk->id); + break; + default: + log_debug("unsupported clk id=%ld\n", clk->id); + return -ENOENT; + } + + return rate; +}; + +static ulong rk3506_clk_set_rate(struct clk *clk, ulong rate) +{ + struct rk3506_clk_priv *priv = dev_get_priv(clk->dev); + ulong ret = 0; + + if (!priv->gpll_hz || !priv->v0pll_hz || !priv->v1pll_hz) { + log_debug("gpll=%lu, v0pll=%lu, v1pll=%lu\n", + priv->gpll_hz, priv->v0pll_hz, priv->v1pll_hz); + return -ENOENT; + } + + switch (clk->id) { + case ARMCLK: + ret = rk3506_armclk_set_rate(priv, rate); + break; + case CLK_GPLL_DIV: + case CLK_GPLL_DIV_100M: + case CLK_V0PLL_DIV: + case CLK_V1PLL_DIV: + ret = rk3506_pll_div_set_rate(priv, clk->id, rate); + break; + case ACLK_BUS_ROOT: + case HCLK_BUS_ROOT: + case PCLK_BUS_ROOT: + ret = rk3506_bus_set_rate(priv, clk->id, rate); + break; + case ACLK_HSPERI_ROOT: + case HCLK_LSPERI_ROOT: + ret = rk3506_peri_set_rate(priv, clk->id, rate); + break; + case HCLK_SDMMC: + case CCLK_SRC_SDMMC: + ret = rk3506_sdmmc_set_rate(priv, clk->id, rate); + break; + case CLK_SARADC: + ret = rk3506_saradc_set_rate(priv, clk->id, rate); + break; + case CLK_TSADC: + case CLK_TSADC_TSEN: + ret = rk3506_tsadc_set_rate(priv, clk->id, rate); + break; + case CLK_I2C0: + case CLK_I2C1: + case CLK_I2C2: + ret = rk3506_i2c_set_rate(priv, clk->id, rate); + break; + case CLK_PWM0: + case CLK_PWM1: + ret = rk3506_pwm_set_rate(priv, clk->id, rate); + break; + case CLK_SPI0: + case CLK_SPI1: + ret = rk3506_spi_set_rate(priv, clk->id, rate); + break; + case SCLK_FSPI: + ret = rk3506_fspi_set_rate(priv, rate); + break; + case DCLK_VOP: + ret = rk3506_vop_dclk_set_rate(priv, rate); + break; + case CLK_MAC0: + case CLK_MAC1: + case CLK_MAC_OUT: + ret = rk3506_mac_set_rate(priv, clk->id, rate); + break; + default: + log_debug("unsupported clk id=%ld rate=%ld\n", clk->id, rate); + return -ENOENT; + } + + return ret; +}; + +static struct clk_ops rk3506_clk_ops = { + .get_rate = rk3506_clk_get_rate, + .set_rate = rk3506_clk_set_rate, +}; + +static void rk3506_clk_init(struct rk3506_clk_priv *priv) +{ + static void * const cru_base = (void *)RK3506_CRU_BASE; + + if (!priv->gpll_hz) { + priv->gpll_hz = rockchip_pll_get_rate(&rk3506_pll_clks[GPLL], + cru_base, GPLL); + priv->gpll_hz = roundup(priv->gpll_hz, 1000); + } + if (!priv->v0pll_hz) { + priv->v0pll_hz = rockchip_pll_get_rate(&rk3506_pll_clks[V0PLL], + cru_base, V0PLL); + priv->v0pll_hz = roundup(priv->v0pll_hz, 1000); + } + if (!priv->v1pll_hz) { + priv->v1pll_hz = rockchip_pll_get_rate(&rk3506_pll_clks[V1PLL], + cru_base, V1PLL); + priv->v1pll_hz = roundup(priv->v1pll_hz, 1000); + } + if (!priv->gpll_div_hz) { + priv->gpll_div_hz = rk3506_pll_div_get_rate(priv, CLK_GPLL_DIV); + priv->gpll_div_hz = roundup(priv->gpll_div_hz, 1000); + } + if (!priv->gpll_div_100mhz) { + priv->gpll_div_100mhz = rk3506_pll_div_get_rate(priv, + CLK_GPLL_DIV_100M); + priv->gpll_div_100mhz = roundup(priv->gpll_div_100mhz, 1000); + } + if (!priv->v0pll_div_hz) { + priv->v0pll_div_hz = rk3506_pll_div_get_rate(priv, CLK_V0PLL_DIV); + priv->v0pll_div_hz = roundup(priv->v0pll_div_hz, 1000); + } + if (!priv->v1pll_div_hz) { + priv->v1pll_div_hz = rk3506_pll_div_get_rate(priv, CLK_V1PLL_DIV); + priv->v1pll_div_hz = roundup(priv->v1pll_div_hz, 1000); + } +} + +static void rk3506_clk_init_xpl(void) +{ + /* Init pka crypto rate, sel=v0pll, div=3 */ + rk_clrsetreg(RK3506_SCRU_BASE + 0x0010, + CLK_PKA_CRYPTO_SEL_MASK | CLK_PKA_CRYPTO_DIV_MASK, + FIELD_PREP(CLK_PKA_CRYPTO_SEL_MASK, CLK_PKA_CRYPTO_SEL_V0PLL) | + FIELD_PREP(CLK_PKA_CRYPTO_DIV_MASK, 3)); + + /* Change clk core src rate, sel=gpll, div=3 */ + rk_clrsetreg(RK3506_CLKSEL_CON(15), + CLK_CORE_SRC_SEL_MASK | CLK_CORE_SRC_DIV_MASK, + FIELD_PREP(CLK_CORE_SRC_SEL_MASK, CLK_CORE_SEL_GPLL) | + FIELD_PREP(CLK_CORE_SRC_DIV_MASK, 3)); +} + +static int rk3506_clk_probe(struct udevice *dev) +{ + struct rk3506_clk_priv *priv = dev_get_priv(dev); + int ret; + + rk3506_clk_init(priv); + + /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ + ret = clk_set_defaults(dev, 1); + if (ret) + log_debug("clk_set_defaults failed: ret=%d\n", ret); + + return 0; +} + +static int rk3506_clk_bind(struct udevice *dev) +{ + struct udevice *sys_child; + struct sysreset_reg *priv; + int ret; + + if (IS_ENABLED(CONFIG_XPL_BUILD)) + rk3506_clk_init_xpl(); + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", + &sys_child); + if (ret) { + log_debug("Warning: No sysreset driver: ret=%d\n", ret); + } else { + priv = malloc(sizeof(struct sysreset_reg)); + priv->glb_srst_fst_value = RK3506_GLB_SRST_FST; + priv->glb_srst_snd_value = RK3506_GLB_SRST_SND; + dev_set_priv(sys_child, priv); + } + + if (!CONFIG_IS_ENABLED(RESET_ROCKCHIP)) + return 0; + + ret = rk3506_reset_bind_lut(dev, RK3506_SOFTRST_CON0, 23); + if (ret) + log_debug("Warning: software reset driver bind failed\n"); + + return 0; +} + +static const struct udevice_id rk3506_clk_ids[] = { + { .compatible = "rockchip,rk3506-cru" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3506_cru) = { + .name = "rockchip_rk3506_cru", + .id = UCLASS_CLK, + .of_match = rk3506_clk_ids, + .priv_auto = sizeof(struct rk3506_clk_priv), + .ops = &rk3506_clk_ops, + .bind = rk3506_clk_bind, + .probe = rk3506_clk_probe, +}; diff --git a/drivers/clk/rockchip/clk_rk3528.c b/drivers/clk/rockchip/clk_rk3528.c index d58557ff56d..bcdc0f930d2 100644 --- a/drivers/clk/rockchip/clk_rk3528.c +++ b/drivers/clk/rockchip/clk_rk3528.c @@ -17,8 +17,6 @@ #include <dt-bindings/clock/rockchip,rk3528-cru.h> #include <linux/delay.h> -DECLARE_GLOBAL_DATA_PTR; - #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) /* diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 533031caead..bb49af358e6 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -16,8 +16,6 @@ #include <dm/lists.h> #include <dt-bindings/clock/rk3568-cru.h> -DECLARE_GLOBAL_DATA_PTR; - #if CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3568_clk_plat { struct dtd_rockchip_rk3568_cru dtd; diff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c index 125b08ee832..1026af27ca1 100644 --- a/drivers/clk/rockchip/clk_rk3576.c +++ b/drivers/clk/rockchip/clk_rk3576.c @@ -17,8 +17,6 @@ #include <dt-bindings/clock/rockchip,rk3576-cru.h> #include <linux/delay.h> -DECLARE_GLOBAL_DATA_PTR; - #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) static struct rockchip_pll_rate_table rk3576_24m_pll_rates[] = { diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index 8c3a113526f..be401a9faee 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -17,8 +17,6 @@ #include <dm/lists.h> #include <dt-bindings/clock/rockchip,rk3588-cru.h> -DECLARE_GLOBAL_DATA_PTR; - #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) static struct rockchip_pll_rate_table rk3588_pll_rates[] = { diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c index 75202a66aa6..e1b9ccf1236 100644 --- a/drivers/clk/rockchip/clk_rv1108.c +++ b/drivers/clk/rockchip/clk_rv1108.c @@ -11,7 +11,6 @@ #include <log.h> #include <malloc.h> #include <syscon.h> -#include <asm/global_data.h> #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/cru_rv1108.h> #include <asm/arch-rockchip/hardware.h> @@ -21,8 +20,6 @@ #include <linux/delay.h> #include <linux/stringify.h> -DECLARE_GLOBAL_DATA_PTR; - enum { VCO_MAX_HZ = 2400U * 1000000, VCO_MIN_HZ = 600 * 1000000, diff --git a/drivers/clk/rockchip/clk_rv1126.c b/drivers/clk/rockchip/clk_rv1126.c index aeeea956914..39920d34b75 100644 --- a/drivers/clk/rockchip/clk_rv1126.c +++ b/drivers/clk/rockchip/clk_rv1126.c @@ -18,8 +18,6 @@ #include <dm/lists.h> #include <dt-bindings/clock/rockchip,rv1126-cru.h> -DECLARE_GLOBAL_DATA_PTR; - #define RV1126_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \ { \ .rate = _rate##U, \ diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index e55a26ab8fd..5d0b08d3755 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -59,25 +59,25 @@ static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = { /* List of clock controls provided by the PRCI */ static struct __prci_clock __prci_init_clocks_fu540[] = { - [PRCI_CLK_COREPLL] = { + [FU540_PRCI_CLK_COREPLL] = { .name = "corepll", .parent_name = "hfclk", .ops = &sifive_fu540_prci_wrpll_clk_ops, .pwd = &__prci_corepll_data, }, - [PRCI_CLK_DDRPLL] = { + [FU540_PRCI_CLK_DDRPLL] = { .name = "ddrpll", .parent_name = "hfclk", .ops = &sifive_fu540_prci_wrpll_clk_ops, .pwd = &__prci_ddrpll_data, }, - [PRCI_CLK_GEMGXLPLL] = { + [FU540_PRCI_CLK_GEMGXLPLL] = { .name = "gemgxlpll", .parent_name = "hfclk", .ops = &sifive_fu540_prci_wrpll_clk_ops, .pwd = &__prci_gemgxlpll_data, }, - [PRCI_CLK_TLCLK] = { + [FU540_PRCI_CLK_TLCLK] = { .name = "tlclk", .parent_name = "corepll", .ops = &sifive_fu540_prci_tlclksel_clk_ops, diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index c9253099e6e..5419bf65b5d 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -195,7 +195,7 @@ config DM_DMA the physical address space. config REGMAP - bool "Support register maps" + bool depends on DM select DEVRES help @@ -206,7 +206,7 @@ config REGMAP direct memory access. config SPL_REGMAP - bool "Support register maps in SPL" + bool depends on SPL_DM help Hardware peripherals tend to have one or more sets of registers @@ -216,7 +216,7 @@ config SPL_REGMAP direct memory access. config TPL_REGMAP - bool "Support register maps in TPL" + bool depends on TPL_DM help Hardware peripherals tend to have one or more sets of registers @@ -226,7 +226,7 @@ config TPL_REGMAP direct memory access. config VPL_REGMAP - bool "Support register maps in VPL" + bool depends on VPL_DM help Hardware peripherals tend to have one or more sets of registers @@ -237,7 +237,7 @@ config VPL_REGMAP config SYSCON bool "Support system controllers" - depends on REGMAP + select REGMAP help Many SoCs have a number of system controllers which are dealt with as a group by a single driver. Some common functionality is provided @@ -246,7 +246,8 @@ config SYSCON config SPL_SYSCON bool "Support system controllers in SPL" - depends on SPL_REGMAP + depends on SPL_DM + select SPL_REGMAP help Many SoCs have a number of system controllers which are dealt with as a group by a single driver. Some common functionality is provided @@ -255,7 +256,8 @@ config SPL_SYSCON config TPL_SYSCON bool "Support system controllers in TPL" - depends on TPL_REGMAP + depends on TPL_DM + select TPL_REGMAP help Many SoCs have a number of system controllers which are dealt with as a group by a single driver. Some common functionality is provided @@ -264,7 +266,8 @@ config TPL_SYSCON config VPL_SYSCON bool "Support system controllers in VPL" - depends on VPL_REGMAP + depends on VPL_DM + select VPL_REGMAP help Many SoCs have a number of system controllers which are dealt with as a group by a single driver. Some common functionality is provided diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c index 437080ed778..557afb8d817 100644 --- a/drivers/core/device-remove.c +++ b/drivers/core/device-remove.c @@ -198,7 +198,7 @@ static int flags_remove(uint flags, uint drv_flags) int device_remove(struct udevice *dev, uint flags) { const struct driver *drv; - int ret; + int ret, cret; if (!dev) return -EINVAL; @@ -211,24 +211,34 @@ int device_remove(struct udevice *dev, uint flags) return ret; /* + * Remove the device if called with the "normal" remove flag set, + * or if the remove flag matches any of the drivers remove flags + */ + drv = dev->driver; + assert(drv); + cret = flags_remove(flags, drv->flags); + + /* + * Remove all children. If this device is being removed due to + * active-DMA or OS-prepare flags, drop the active-flag requirement + * for children so they are removed even without matching active + * flags, since a deactivated device must not have activated + * children. Preserve other flags (e.g. DM_REMOVE_NON_VITAL) so + * that vital children are still protected. + * * If the child returns EKEYREJECTED, continue. It just means that it * didn't match the flags. */ - ret = device_chld_remove(dev, NULL, flags); + ret = device_chld_remove(dev, NULL, + cret ? flags : + (flags & ~DM_REMOVE_ACTIVE_ALL)); if (ret && ret != -EKEYREJECTED) return ret; - /* - * Remove the device if called with the "normal" remove flag set, - * or if the remove flag matches any of the drivers remove flags - */ - drv = dev->driver; - assert(drv); - ret = flags_remove(flags, drv->flags); - if (ret) { + if (cret) { log_debug("%s: When removing: flags=%x, drv->flags=%x, err=%d\n", - dev->name, flags, drv->flags, ret); - return ret; + dev->name, flags, drv->flags, cret); + return cret; } ret = uclass_pre_remove_device(dev); diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig index 6a96be94de4..c805c0bbfa1 100644 --- a/drivers/cpu/Kconfig +++ b/drivers/cpu/Kconfig @@ -35,9 +35,8 @@ config CPU_ARMV8 config CPU_MICROBLAZE bool "Enable Microblaze CPU driver" - depends on CPU && MICROBLAZE + depends on CPU && MICROBLAZE && XILINX_MICROBLAZE0_PVR select DM_EVENT - select XILINX_MICROBLAZE0_PVR help Support CPU cores for Microblaze architecture. diff --git a/drivers/cpu/bcm283x_cpu.c b/drivers/cpu/bcm283x_cpu.c index 59a7b142c95..ad638cd8fff 100644 --- a/drivers/cpu/bcm283x_cpu.c +++ b/drivers/cpu/bcm283x_cpu.c @@ -11,7 +11,6 @@ #include <asm/armv8/cpu.h> #include <asm/cache.h> #include <asm/io.h> -#include <asm/global_data.h> #include <asm/system.h> #include <asm-generic/sections.h> #include <linux/bitops.h> @@ -19,8 +18,6 @@ #include <linux/delay.h> #include "armv8_cpu.h" -DECLARE_GLOBAL_DATA_PTR; - struct bcm_plat { u64 release_addr; }; diff --git a/drivers/cpu/cpu-uclass.c b/drivers/cpu/cpu-uclass.c index 2c8e46c05e3..b73768de918 100644 --- a/drivers/cpu/cpu-uclass.c +++ b/drivers/cpu/cpu-uclass.c @@ -15,8 +15,6 @@ #include <linux/err.h> #include <relocate.h> -DECLARE_GLOBAL_DATA_PTR; - int cpu_probe_all(void) { int ret = uclass_probe_all(UCLASS_CPU); diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 5f17122c36c..785c299eca5 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -6,7 +6,6 @@ #include <cpu.h> #include <dm.h> #include <thermal.h> -#include <asm/global_data.h> #include <asm/ptrace.h> #include <asm/system.h> #include <firmware/imx/sci/sci.h> @@ -18,8 +17,6 @@ #include <linux/clk-provider.h> #include <linux/psci.h> -DECLARE_GLOBAL_DATA_PTR; - #define IMX_REV_LEN 4 struct cpu_imx_plat { const char *name; @@ -115,6 +112,8 @@ static const char *get_imx_type_str(u32 imxtype) return "95"; case MXC_CPU_IMX94: return "94"; + case MXC_CPU_IMX952: + return "952"; default: return "??"; } diff --git a/drivers/cpu/mtk_cpu.c b/drivers/cpu/mtk_cpu.c index 2a08be9b6d1..4f4e5480eac 100644 --- a/drivers/cpu/mtk_cpu.c +++ b/drivers/cpu/mtk_cpu.c @@ -10,12 +10,9 @@ #include <dm.h> #include <regmap.h> #include <syscon.h> -#include <asm/global_data.h> #include <linux/err.h> #include <linux/io.h> -DECLARE_GLOBAL_DATA_PTR; - struct mtk_cpu_plat { struct regmap *hwver; }; diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index fe694f6022c..eb01c6cf700 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -3,6 +3,7 @@ if ARM || PPC config FSL_CAAM bool "Freescale Crypto Driver Support" select SHA_HW_ACCEL + select ARCH_MISC_INIT # hw_sha1() under drivers/crypto, and needed with SHA_HW_ACCEL select MISC if DM imply SPL_CRYPTO if (ARM && SPL) diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig index 4660d20deff..615e0421abf 100644 --- a/drivers/ddr/altera/Kconfig +++ b/drivers/ddr/altera/Kconfig @@ -1,8 +1,8 @@ config SPL_ALTERA_SDRAM bool "SoCFPGA DDR SDRAM driver in SPL" depends on SPL - depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_SOC64 - select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_SOC64 - select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_SOC64 + depends on ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10 || ARCH_SOCFPGA_SOC64 + select RAM if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_SOC64 + select SPL_RAM if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_SOC64 help Enable DDR SDRAM controller for the SoCFPGA devices. diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index 7ed43965be5..8259ab04a7e 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -7,11 +7,11 @@ # Copyright (C) 2014-2025 Altera Corporation <www.altera.com> ifdef CONFIG_$(PHASE_)ALTERA_SDRAM -obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o -obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o -obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o -obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o -obj-$(CONFIG_TARGET_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o -obj-$(CONFIG_TARGET_SOCFPGA_AGILEX5) += sdram_soc64.o sdram_agilex5.o iossm_mailbox.o -obj-$(CONFIG_TARGET_SOCFPGA_AGILEX7M) += sdram_soc64.o sdram_agilex7m.o iossm_mailbox.o uibssm_mailbox.o +obj-$(CONFIG_ARCH_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o +obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += sdram_arria10.o +obj-$(CONFIG_ARCH_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o +obj-$(CONFIG_ARCH_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o +obj-$(CONFIG_ARCH_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o +obj-$(CONFIG_ARCH_SOCFPGA_AGILEX5) += sdram_soc64.o sdram_agilex5.o iossm_mailbox.o +obj-$(CONFIG_ARCH_SOCFPGA_AGILEX7M) += sdram_soc64.o sdram_agilex7m.o iossm_mailbox.o uibssm_mailbox.o endif diff --git a/drivers/ddr/altera/iossm_mailbox.c b/drivers/ddr/altera/iossm_mailbox.c index 2a2f86a650e..3156cb9d4b6 100644 --- a/drivers/ddr/altera/iossm_mailbox.c +++ b/drivers/ddr/altera/iossm_mailbox.c @@ -86,7 +86,7 @@ #define INTF_DDR_TYPE_MASK GENMASK(2, 0) /* offset info of MEM_TOTAL_CAPACITY_INTF */ -#define INTF_CAPACITY_GBITS_MASK GENMASK(7, 0) +#define INTF_CAPACITY_GBITS_MASK GENMASK(31, 0) /* offset info of ECC_ENABLE_INTF */ #define INTF_ECC_ENABLE_TYPE_MASK GENMASK(1, 0) diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index d3305a6c82d..c281f711fdf 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -8,6 +8,7 @@ #include <fdtdec.h> #include <init.h> #include <log.h> +#include <hang.h> #include <malloc.h> #include <wait_bit.h> #include <watchdog.h> @@ -667,6 +668,22 @@ static int of_sdram_firewall_setup(const void *blob) return 0; } +static void sdram_size_check(void) +{ + phys_size_t ram_check = 0; + + debug("DDR: Running SDRAM size sanity check\n"); + + ram_check = get_ram_size((long *)gd->bd->bi_dram[0].start, + gd->bd->bi_dram[0].size); + if (ram_check != gd->bd->bi_dram[0].size) { + puts("DDR: SDRAM size check failed!\n"); + hang(); + } + + debug("DDR: SDRAM size check passed!\n"); +} + int ddr_calibration_sequence(void) { schedule(); @@ -702,11 +719,26 @@ int ddr_calibration_sequence(void) /* setup the dram info within bd */ dram_init_banksize(); + if (gd->ram_size != gd->bd->bi_dram[0].size) { + printf("DDR: Warning: DRAM size from device tree (%ld MiB)\n", + gd->bd->bi_dram[0].size >> 20); + printf(" mismatch with hardware (%ld MiB).\n", + gd->ram_size >> 20); + } + + if (gd->bd->bi_dram[0].size > gd->ram_size) { + printf("DDR: Error: DRAM size from device tree is greater\n"); + printf(" than hardware size.\n"); + hang(); + } + if (of_sdram_firewall_setup(gd->fdt_blob)) puts("FW: Error Configuring Firewall\n"); if (sdram_is_ecc_enabled()) sdram_init_ecc_bits(gd->ram_size); + sdram_size_check(); + return 0; } diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index 2d0093c591c..8ee7049b164 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -32,7 +32,7 @@ #define SINGLE_RANK_CLAMSHELL 0xc3c3 #define DUAL_RANK_CLAMSHELL 0xa5a5 -#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) && !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#if !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) && !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg) { return readl(plat->iomhc + reg); @@ -106,7 +106,7 @@ int emif_reset(struct altera_sdram_plat *plat) } #endif -#if !(IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) +#if !(IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) || IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)) int poll_hmc_clock_status(void) { return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() + @@ -347,7 +347,7 @@ static void sdram_set_firewall_non_f2sdram(struct bd_info *bd) } } -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) static void sdram_set_firewall_f2sdram(struct bd_info *bd) { u32 i, lower, upper; @@ -397,22 +397,22 @@ void sdram_set_firewall(struct bd_info *bd) { sdram_set_firewall_non_f2sdram(bd); -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) sdram_set_firewall_f2sdram(bd); #endif } static int altera_sdram_of_to_plat(struct udevice *dev) { -#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#if !IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) struct altera_sdram_plat *plat = dev_get_plat(dev); fdt_addr_t addr; #endif /* These regs info are part of DDR handoff in bitstream */ -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) return 0; -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) || IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) addr = dev_read_addr_index(dev, 0); if (addr == FDT_ADDR_T_NONE) return -EINVAL; diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 6fe0653922c..e8090f91002 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -15,13 +15,13 @@ struct altera_sdram_priv { struct reset_ctl_bulk resets; }; -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) struct altera_sdram_plat { fdt_addr_t mpfe_base_addr; bool dualport; bool dualemif; }; -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) enum memory_type { DDR_MEMORY = 0, HBM_MEMORY diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig index 2cf4289b448..962bda40ad2 100644 --- a/drivers/dfu/Kconfig +++ b/drivers/dfu/Kconfig @@ -13,10 +13,10 @@ config DFU_OVER_TFTP bool depends on NET -if DFU config DFU_WRITE_ALT bool +if DFU config DFU_TFTP bool "DFU via TFTP" depends on NETDEVICES diff --git a/drivers/dma/ti/Kconfig b/drivers/dma/ti/Kconfig index 5cec6ddd3e3..d904982c800 100644 --- a/drivers/dma/ti/Kconfig +++ b/drivers/dma/ti/Kconfig @@ -8,7 +8,6 @@ config TI_K3_NAVSS_UDMA select DEVRES select DMA select TI_K3_NAVSS_RINGACC - select TI_K3_NAVSS_PSILCFG select TI_K3_PSIL help Support for UDMA used in K3 devices. diff --git a/drivers/fastboot/fb_block.c b/drivers/fastboot/fb_block.c index 2a7e47992f8..51d1abb18c7 100644 --- a/drivers/fastboot/fb_block.c +++ b/drivers/fastboot/fb_block.c @@ -28,6 +28,11 @@ */ #define FASTBOOT_MAX_BLOCKS_WRITE 65536 +__weak lbaint_t fb_mmc_get_boot_offset(void) +{ + return 0; +} + struct fb_block_sparse { struct blk_desc *dev_desc; }; @@ -160,7 +165,8 @@ void fastboot_block_raw_erase_disk(struct blk_desc *dev_desc, const char *disk_n debug("Start Erasing %s...\n", disk_name); - written = fb_block_write(dev_desc, 0, dev_desc->lba, NULL); + written = fb_block_write(dev_desc, fb_mmc_get_boot_offset(), + dev_desc->lba, NULL); if (written != dev_desc->lba) { pr_err("Failed to erase %s\n", disk_name); fastboot_response("FAIL", response, "Failed to erase %s", disk_name); @@ -211,7 +217,8 @@ void fastboot_block_erase(const char *part_name, char *response) if (fastboot_block_get_part_info(part_name, &dev_desc, &part_info, response) < 0) return; - fastboot_block_raw_erase(dev_desc, &part_info, part_name, 0, response); + fastboot_block_raw_erase(dev_desc, &part_info, part_name, + fb_mmc_get_boot_offset(), response); } void fastboot_block_write_raw_disk(struct blk_desc *dev_desc, const char *disk_name, @@ -224,7 +231,7 @@ void fastboot_block_write_raw_disk(struct blk_desc *dev_desc, const char *disk_n blkcnt = ((download_bytes + (dev_desc->blksz - 1)) & ~(dev_desc->blksz - 1)); blkcnt = lldiv(blkcnt, dev_desc->blksz); - if (blkcnt > dev_desc->lba) { + if ((blkcnt + fb_mmc_get_boot_offset()) > dev_desc->lba) { pr_err("too large for disk: '%s'\n", disk_name); fastboot_fail("too large for disk", response); return; @@ -232,7 +239,7 @@ void fastboot_block_write_raw_disk(struct blk_desc *dev_desc, const char *disk_n printf("Flashing Raw Image\n"); - blks = fb_block_write(dev_desc, 0, blkcnt, buffer); + blks = fb_block_write(dev_desc, fb_mmc_get_boot_offset(), blkcnt, buffer); if (blks != blkcnt) { pr_err("failed writing to %s\n", disk_name); diff --git a/drivers/firmware/arm-ffa/arm-ffa-uclass.c b/drivers/firmware/arm-ffa/arm-ffa-uclass.c index 96c64964bb7..76a8775e911 100644 --- a/drivers/firmware/arm-ffa/arm-ffa-uclass.c +++ b/drivers/firmware/arm-ffa/arm-ffa-uclass.c @@ -12,15 +12,12 @@ #include <malloc.h> #include <string.h> #include <u-boot/uuid.h> -#include <asm/global_data.h> #include <dm/device-internal.h> #include <dm/devres.h> #include <dm/root.h> #include <linux/errno.h> #include <linux/sizes.h> -DECLARE_GLOBAL_DATA_PTR; - /* Error mapping declarations */ int ffa_to_std_errmap[MAX_NUMBER_FFA_ERR] = { diff --git a/drivers/firmware/arm-ffa/arm-ffa.c b/drivers/firmware/arm-ffa/arm-ffa.c index 94e6105cb38..9e6b5dcc542 100644 --- a/drivers/firmware/arm-ffa/arm-ffa.c +++ b/drivers/firmware/arm-ffa/arm-ffa.c @@ -10,12 +10,9 @@ #include <arm_ffa_priv.h> #include <dm.h> #include <log.h> -#include <asm/global_data.h> #include <dm/device-internal.h> #include <linux/errno.h> -DECLARE_GLOBAL_DATA_PTR; - /** * invoke_ffa_fn() - SMC wrapper * @args: FF-A ABI arguments to be copied to Xn registers diff --git a/drivers/firmware/arm-ffa/ffa-emul-uclass.c b/drivers/firmware/arm-ffa/ffa-emul-uclass.c index 1521d9b66ac..6198d687354 100644 --- a/drivers/firmware/arm-ffa/ffa-emul-uclass.c +++ b/drivers/firmware/arm-ffa/ffa-emul-uclass.c @@ -8,7 +8,6 @@ #include <dm.h> #include <mapmem.h> #include <string.h> -#include <asm/global_data.h> #include <asm/sandbox_arm_ffa.h> #include <asm/sandbox_arm_ffa_priv.h> #include <dm/device-internal.h> @@ -17,8 +16,6 @@ #include <linux/errno.h> #include <linux/sizes.h> -DECLARE_GLOBAL_DATA_PTR; - /* The partitions (SPs) table */ static struct ffa_partition_desc sandbox_partitions[SANDBOX_PARTITIONS_CNT] = { { diff --git a/drivers/firmware/arm-ffa/sandbox_ffa.c b/drivers/firmware/arm-ffa/sandbox_ffa.c index 44b32a829dd..f1e8de4bf0d 100644 --- a/drivers/firmware/arm-ffa/sandbox_ffa.c +++ b/drivers/firmware/arm-ffa/sandbox_ffa.c @@ -8,13 +8,10 @@ #include <arm_ffa.h> #include <dm.h> #include <log.h> -#include <asm/global_data.h> #include <asm/sandbox_arm_ffa_priv.h> #include <dm/device-internal.h> #include <linux/errno.h> -DECLARE_GLOBAL_DATA_PTR; - /** * sandbox_ffa_discover() - perform sandbox FF-A discovery * @dev: The sandbox FF-A bus device diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index f8a9945c1da..fb583580ebe 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -427,6 +427,104 @@ U_BOOT_DRIVER(zynqmp_power) = { }; #endif +static const char *const pinctrl_functions[] = { + "can0", + "can1", + "ethernet0", + "ethernet1", + "ethernet2", + "ethernet3", + "gemtsu0", + "gpio0", + "i2c0", + "i2c1", + "mdio0", + "mdio1", + "mdio2", + "mdio3", + "qspi0", + "qspi_fbclk", + "qspi_ss", + "spi0", + "spi1", + "spi0_ss", + "spi1_ss", + "sdio0", + "sdio0_pc", + "sdio0_cd", + "sdio0_wp", + "sdio1", + "sdio1_pc", + "sdio1_cd", + "sdio1_wp", + "nand0", + "nand0_ce", + "nand0_rb", + "nand0_dqs", + "ttc0_clk", + "ttc0_wav", + "ttc1_clk", + "ttc1_wav", + "ttc2_clk", + "ttc2_wav", + "ttc3_clk", + "ttc3_wav", + "uart0", + "uart1", + "usb0", + "usb1", + "swdt0_clk", + "swdt0_rst", + "swdt1_clk", + "swdt1_rst", + "pmu0", + "pcie0", + "csu0", + "dpaux0", + "pjtag0", + "trace0", + "trace0_clk", + "testscan0", +}; + +/* + * PM_QUERY_DATA is implemented by ATF and not the PMU firmware, so we have to + * emulate it in SPL. Just implement functions/pins since the groups take up a + * lot of rodata and are mostly superfluous. + */ +static int zynqmp_pm_query_data(enum pm_query_id qid, u32 arg1, u32 arg2, + u32 *ret_payload) +{ + switch (qid) { + case PM_QID_PINCTRL_GET_NUM_PINS: + ret_payload[1] = 78; /* NUM_PINS */ + ret_payload[0] = 0; + return 0; + case PM_QID_PINCTRL_GET_NUM_FUNCTIONS: + ret_payload[1] = ARRAY_SIZE(pinctrl_functions); + ret_payload[0] = 0; + return 0; + case PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS: + ret_payload[1] = 0; + ret_payload[0] = 0; + return 0; + case PM_QID_PINCTRL_GET_FUNCTION_NAME: + assert(arg1 < ARRAY_SIZE(pinctrl_functions)); + memset(ret_payload, 0, MAX_FUNC_NAME_LEN); + strcpy((char *)ret_payload, pinctrl_functions[arg1]); + return 0; + case PM_QID_PINCTRL_GET_FUNCTION_GROUPS: + case PM_QID_PINCTRL_GET_PIN_GROUPS: + memset(ret_payload + 1, 0xff, + sizeof(s16) * NUM_GROUPS_PER_RESP); + ret_payload[0] = 0; + return 0; + default: + ret_payload[0] = 1; + return 1; + } +} + smc_call_handler_t __data smc_call_handler; static int smc_call_legacy(u32 api_id, u32 arg0, u32 arg1, u32 arg2, @@ -493,6 +591,9 @@ int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2, __func__, current_el(), api_id, arg0, arg1, arg2, arg3, arg4, arg5); if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) { + if (CONFIG_IS_ENABLED(PINCTRL_ZYNQMP) && + api_id == PM_QUERY_DATA) + return zynqmp_pm_query_data(arg0, arg1, arg2, ret_payload); #if defined(CONFIG_ZYNQMP_IPI) /* * Use fixed payload and arg size as the EL2 call. The firmware diff --git a/drivers/firmware/scmi/Kconfig b/drivers/firmware/scmi/Kconfig index 33e089c460b..cd912ebe409 100644 --- a/drivers/firmware/scmi/Kconfig +++ b/drivers/firmware/scmi/Kconfig @@ -3,6 +3,7 @@ config SCMI_FIRMWARE select FIRMWARE select OF_TRANSLATE depends on SANDBOX || DM_MAILBOX || ARM_SMCCC || OPTEE + depends on OF_CONTROL help System Control and Management Interface (SCMI) is a communication protocol that defines standard interfaces for power, performance diff --git a/drivers/firmware/scmi/Makefile b/drivers/firmware/scmi/Makefile index 6129726f817..761d89a1161 100644 --- a/drivers/firmware/scmi/Makefile +++ b/drivers/firmware/scmi/Makefile @@ -5,5 +5,6 @@ obj-$(CONFIG_SCMI_AGENT_SMCCC) += smccc_agent.o obj-$(CONFIG_SCMI_AGENT_MAILBOX) += mailbox_agent.o obj-$(CONFIG_SCMI_AGENT_OPTEE) += optee_agent.o obj-$(CONFIG_SCMI_POWER_DOMAIN) += pwdom.o +obj-$(CONFIG_PINCTRL_SCMI) += pinctrl.o obj-$(CONFIG_SANDBOX) += sandbox-scmi_agent.o sandbox-scmi_devices.o obj-y += vendors/imx/ diff --git a/drivers/firmware/scmi/pinctrl.c b/drivers/firmware/scmi/pinctrl.c new file mode 100644 index 00000000000..47f7a8ad9b8 --- /dev/null +++ b/drivers/firmware/scmi/pinctrl.c @@ -0,0 +1,365 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 Linaro Ltd. + */ + +#define LOG_CATEGORY UCLASS_PINCTRL + +#include <dm.h> +#include <dm/device_compat.h> +#include <dm/devres.h> +#include <dm/pinctrl.h> +#include <linux/bitfield.h> +#include <linux/compat.h> +#include <scmi_agent.h> +#include <scmi_agent-uclass.h> +#include <scmi_protocols.h> + +static int map_config_param_to_scmi(u32 config_param) +{ + switch (config_param) { + case PIN_CONFIG_BIAS_BUS_HOLD: + return SCMI_PIN_BIAS_BUS_HOLD; + case PIN_CONFIG_BIAS_DISABLE: + return SCMI_PIN_BIAS_DISABLE; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + return SCMI_PIN_BIAS_HIGH_IMPEDANCE; + case PIN_CONFIG_BIAS_PULL_DOWN: + return SCMI_PIN_BIAS_PULL_DOWN; + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + return SCMI_PIN_BIAS_PULL_DEFAULT; + case PIN_CONFIG_BIAS_PULL_UP: + return SCMI_PIN_BIAS_PULL_UP; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + return SCMI_PIN_DRIVE_OPEN_DRAIN; + case PIN_CONFIG_DRIVE_OPEN_SOURCE: + return SCMI_PIN_DRIVE_OPEN_SOURCE; + case PIN_CONFIG_DRIVE_PUSH_PULL: + return SCMI_PIN_DRIVE_PUSH_PULL; + case PIN_CONFIG_DRIVE_STRENGTH: + return SCMI_PIN_DRIVE_STRENGTH; + case PIN_CONFIG_INPUT_DEBOUNCE: + return SCMI_PIN_INPUT_DEBOUNCE; + case PIN_CONFIG_INPUT_ENABLE: + return SCMI_PIN_INPUT_MODE; + case PIN_CONFIG_INPUT_SCHMITT: + return SCMI_PIN_INPUT_SCHMITT; + case PIN_CONFIG_LOW_POWER_MODE: + return SCMI_PIN_LOW_POWER_MODE; + case PIN_CONFIG_OUTPUT_ENABLE: + return SCMI_PIN_OUTPUT_MODE; + case PIN_CONFIG_OUTPUT: + return SCMI_PIN_OUTPUT_VALUE; + case PIN_CONFIG_POWER_SOURCE: + return SCMI_PIN_POWER_SOURCE; + case PIN_CONFIG_SLEW_RATE: + return SCMI_PIN_SLEW_RATE; + } + + return -EINVAL; +} + +int scmi_pinctrl_protocol_attrs(struct udevice *dev, int *num_pins, + int *num_groups, int *num_functions) +{ + struct scmi_pinctrl_protocol_attrs_out out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_PINCTRL, + .message_id = SCMI_PROTOCOL_ATTRIBUTES, + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + return ret; + if (out.status) + return scmi_to_linux_errno(out.status); + + if (num_groups) + *num_groups = FIELD_GET(GENMASK(31, 16), out.attr_low); + if (num_pins) + *num_pins = FIELD_GET(GENMASK(15, 0), out.attr_low); + if (num_functions) + *num_functions = FIELD_GET(GENMASK(15, 0), out.attr_high); + + return 0; +} + +int scmi_pinctrl_attrs(struct udevice *dev, enum select_type select_type, + unsigned int selector, bool *gpio, unsigned int *count, + char *name) +{ + struct scmi_pinctrl_attrs_in in; + struct scmi_pinctrl_attrs_out out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_PINCTRL, + .message_id = SCMI_PINCTRL_ATTRIBUTES, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + + in.select_type = select_type; + in.id = selector; + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + return ret; + if (out.status) + return scmi_to_linux_errno(out.status); + + if (gpio) + *gpio = FIELD_GET(BIT(17), out.attr); + if (count) + *count = FIELD_GET(GENMASK(15, 0), out.attr); + if (name) + strncpy(name, out.name, sizeof(out.name)); + + return 0; +} + +int scmi_pinctrl_list_associations(struct udevice *dev, + enum select_type select_type, + unsigned int selector, + unsigned short *output, + unsigned short num_out) +{ + struct scmi_pinctrl_list_associations_in in; + struct scmi_pinctrl_list_associations_out *out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_PINCTRL, + .message_id = SCMI_PINCTRL_LIST_ASSOCIATIONS, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + }; + size_t out_sz = sizeof(*out) + num_out * sizeof(out->array[0]); + unsigned int count; + int ret = -EINVAL; + + out = kzalloc(out_sz, GFP_KERNEL); + if (!out) + return -ENOMEM; + + msg.out_msg = (u8 *)out; + msg.out_msg_sz = out_sz; + in.select_type = select_type; + in.id = selector; + in.index = 0; + + while (num_out > 0) { + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + goto free; + if (out->status) { + ret = scmi_to_linux_errno(out->status); + goto free; + } + + count = FIELD_GET(GENMASK(11, 0), out->flags); + if (count > num_out) + return -EINVAL; + memcpy(&output[in.index], out->array, count * sizeof(u16)); + num_out -= count; + in.index += count; + } +free: + kfree(out); + return ret; +} + +#define SCMI_PINCTRL_CONFIG_SETTINGS_FUNCTION -2u + +int scmi_pinctrl_settings_get_one(struct udevice *dev, enum select_type select_type, + unsigned int selector, + u32 config_type, u32 *value) +{ + struct scmi_pinctrl_settings_get_in in; + struct scmi_pinctrl_settings_get_out *out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_PINCTRL, + .message_id = SCMI_PINCTRL_SETTINGS_GET, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + }; + size_t out_sz = sizeof(*out) + (sizeof(u32) * 2); + u32 num_configs; + int ret; + + if (config_type == SCMI_PINCTRL_CONFIG_SETTINGS_ALL) { + /* FIXME: implement */ + return -EIO; + } + + out = kzalloc(out_sz, GFP_KERNEL); + if (!out) + return -ENOMEM; + + msg.out_msg = (u8 *)out; + msg.out_msg_sz = out_sz; + in.id = selector; + in.attr = 0; + if (config_type == SCMI_PINCTRL_CONFIG_SETTINGS_FUNCTION) + in.attr = FIELD_PREP(GENMASK(19, 18), 2); + in.attr |= FIELD_PREP(GENMASK(17, 16), select_type); + if (config_type != SCMI_PINCTRL_CONFIG_SETTINGS_FUNCTION) + in.attr |= FIELD_PREP(GENMASK(7, 0), config_type); + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + goto free; + if (out->status) { + ret = scmi_to_linux_errno(out->status); + goto free; + } + num_configs = FIELD_GET(GENMASK(7, 0), out->num_configs); + if (out->num_configs == 0) { + *value = out->function_selected; + goto free; + } + if (num_configs != 1) { + ret = -EINVAL; + goto free; + } + + *value = out->configs[1]; +free: + kfree(out); + return ret; +} + +static int scmi_pinctrl_settings_configure_helper(struct udevice *dev, + enum select_type select_type, + unsigned int selector, + u32 function_id, + u16 num_configs, u32 *configs) +{ + struct scmi_pinctrl_settings_configure_in *in; + struct scmi_pinctrl_settings_configure_out out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_PINCTRL, + .message_id = SCMI_PINCTRL_SETTINGS_CONFIGURE, + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + size_t in_sz = sizeof(*in) + (num_configs * sizeof(u32) * 2); + int ret; + + in = kzalloc(in_sz, GFP_KERNEL); + if (!in) + return -ENOMEM; + + msg.in_msg = (u8 *)in; + msg.in_msg_sz = in_sz; + in->id = selector; + in->function_id = function_id; + in->attr = 0; + in->attr |= FIELD_PREP(GENMASK(9, 2), num_configs); + in->attr |= FIELD_PREP(GENMASK(1, 0), select_type); + memcpy(in->configs, configs, num_configs * sizeof(u32) * 2); + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + goto free; + if (out.status) { + ret = scmi_to_linux_errno(out.status); + goto free; + } +free: + kfree(in); + return ret; +} + +int scmi_pinctrl_settings_configure(struct udevice *dev, enum select_type select_type, + unsigned int selector, u16 num_configs, + u32 *configs) +{ + return scmi_pinctrl_settings_configure_helper(dev, select_type, + selector, + SCMI_PINCTRL_FUNCTION_NONE, + num_configs, configs); +} + +int scmi_pinctrl_settings_configure_one(struct udevice *dev, enum select_type select_type, + unsigned int selector, + u32 param, u32 argument) +{ + u32 config_value[2]; + int scmi_config; + + /* see stmfx_pinctrl_conf_set() */ + scmi_config = map_config_param_to_scmi(param); + if (scmi_config < 0) + return scmi_config; + + config_value[0] = scmi_config; + config_value[1] = argument; + + return scmi_pinctrl_settings_configure(dev, select_type, selector, 1, + &config_value[0]); +} + +int scmi_pinctrl_set_function(struct udevice *dev, enum select_type select_type, + unsigned int selector, u32 function_id) +{ + return scmi_pinctrl_settings_configure_helper(dev, select_type, selector, + function_id, 0, NULL); +} + +int scmi_pinctrl_request(struct udevice *dev, enum select_type select_type, + unsigned int selector) +{ + struct scmi_pinctrl_request_in in; + struct scmi_pinctrl_request_out out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_PINCTRL, + .message_id = SCMI_PINCTRL_REQUEST, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + + in.id = selector; + in.flags = FIELD_PREP(GENMASK(1, 0), select_type); + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + return ret; + if (out.status) + return scmi_to_linux_errno(out.status); + + return 0; +} + +int scmi_pinctrl_release(struct udevice *dev, enum select_type select_type, + unsigned int selector) +{ + struct scmi_pinctrl_release_in in; + struct scmi_pinctrl_release_out out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_PINCTRL, + .message_id = SCMI_PINCTRL_RELEASE, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + + in.id = selector; + in.flags = FIELD_PREP(GENMASK(1, 0), select_type); + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + return ret; + if (out.status) + return scmi_to_linux_errno(out.status); + + return 0; +} + diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c index ad825d66da2..cd458a7f458 100644 --- a/drivers/firmware/scmi/scmi_agent-uclass.c +++ b/drivers/firmware/scmi/scmi_agent-uclass.c @@ -106,7 +106,7 @@ struct udevice *scmi_get_protocol(struct udevice *dev, proto = priv->voltagedom_dev; break; #endif -#if IS_ENABLED(CONFIG_PINCTRL_IMX_SCMI) +#if IS_ENABLED(CONFIG_PINCTRL_SCMI) || IS_ENABLED(CONFIG_PINCTRL_IMX_SCMI) case SCMI_PROTOCOL_ID_PINCTRL: proto = priv->pinctrl_dev; break; @@ -179,7 +179,7 @@ static int scmi_add_protocol(struct udevice *dev, priv->voltagedom_dev = proto; break; #endif -#if IS_ENABLED(CONFIG_PINCTRL_IMX_SCMI) +#if IS_ENABLED(CONFIG_PINCTRL_SCMI) || IS_ENABLED(CONFIG_PINCTRL_IMX_SCMI) case SCMI_PROTOCOL_ID_PINCTRL: priv->pinctrl_dev = proto; break; diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index e2593057fac..1658c73bca4 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -46,7 +46,7 @@ config FPGA_CYCLON2 config FPGA_INTEL_SDM_MAILBOX bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver" - depends on TARGET_SOCFPGA_SOC64 + depends on ARCH_SOCFPGA_SOC64 select FPGA_ALTERA help Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index f22d3b3d86e..ccfed94717e 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -21,6 +21,6 @@ obj-$(CONFIG_FPGA_INTEL_SDM_MAILBOX) += intel_sdm_mb.o obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o -obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o -obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o +obj-$(CONFIG_ARCH_SOCFPGA_GEN5) += socfpga_gen5.o +obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += socfpga_arria10.o endif diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index 4a9aa74357e..822183c5785 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -12,8 +12,8 @@ /* * Altera FPGA support */ -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10) #include <asm/arch/misc.h> #endif #include <errno.h> @@ -48,8 +48,8 @@ static const struct altera_fpga { #endif }; -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10) int fpga_is_partial_data(int devnum, size_t img_len) { /* diff --git a/drivers/fwu-mdata/Kconfig b/drivers/fwu-mdata/Kconfig index 42736a5e43b..59571ac01ea 100644 --- a/drivers/fwu-mdata/Kconfig +++ b/drivers/fwu-mdata/Kconfig @@ -1,4 +1,4 @@ -config FWU_MDATA +menuconfig FWU_MDATA bool "Driver support for accessing FWU Metadata" depends on DM help @@ -6,16 +6,14 @@ config FWU_MDATA FWU Metadata partitions reside on the same storage device which contains the other FWU updatable firmware images. -choice - prompt "Storage Layout Scheme" - depends on FWU_MDATA - default FWU_MDATA_GPT_BLK +if FWU_MDATA config FWU_MDATA_GPT_BLK bool "FWU Metadata access for GPT partitioned Block devices" select PARTITION_TYPE_GUID select PARTITION_UUIDS - depends on FWU_MDATA && BLK && EFI_PARTITION + depends on BLK && EFI_PARTITION + default y help Enable support for accessing FWU Metadata on GPT partitioned block devices. @@ -28,4 +26,4 @@ config FWU_MDATA_MTD (or non-GPT partitioned, e.g. partition nodes in devicetree) MTD devices. -endchoice +endif diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 60c5c54688e..1484dd3504c 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -1,3 +1,11 @@ +config GPIO_DELAY + bool "GPIO delay driver" + depends on DM_GPIO + help + Enable the GPIO delay driver. + This driver allows wrapping another GPIO controller and inserting + ramp-up/ramp-down delays on output changes, as described in the + Linux gpio-delay binding. # # GPIO infrastructure and drivers # @@ -375,6 +383,7 @@ config OMAP_GPIO config CMD_PCA953X bool "Enable the pca953x command" + depends on PCA953X help Deprecated: This should be converted to driver model. diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 910478c0c7a..fec258f59f5 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o obj-$(CONFIG_BCM6345_GPIO) += bcm6345_gpio.o obj-$(CONFIG_CORTINA_GPIO) += cortina_gpio.o obj-$(CONFIG_FXL6408_GPIO) += gpio-fxl6408.o +obj-$(CONFIG_GPIO_DELAY) += gpio-delay.o obj-$(CONFIG_INTEL_GPIO) += intel_gpio.o obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o diff --git a/drivers/gpio/gpio-delay.c b/drivers/gpio/gpio-delay.c new file mode 100644 index 00000000000..9105deecc4f --- /dev/null +++ b/drivers/gpio/gpio-delay.c @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 - 2026, Advanced Micro Devices, Inc. + * + * Michal Simek <[email protected]> + */ + +#include <dm.h> +#include <dm/device_compat.h> +#include <dm/devres.h> +#include <asm/gpio.h> +#include <linux/delay.h> + +struct gpio_delay_desc { + struct gpio_desc real_gpio; + u32 ramp_up_us; + u32 ramp_down_us; +}; + +struct gpio_delay_priv { + struct gpio_delay_desc *descs; +}; + +static int gpio_delay_direction_input(struct udevice *dev, unsigned int offset) +{ + return -ENOSYS; +} + +static int gpio_delay_get_value(struct udevice *dev, unsigned int offset) +{ + return -ENOSYS; +} + +static int gpio_delay_set_value(struct udevice *dev, unsigned int offset, + int value) +{ + struct gpio_delay_priv *priv = dev_get_priv(dev); + struct gpio_delay_desc *desc = &priv->descs[offset]; + u32 wait; + int ret; + + dev_dbg(dev, "gpio %d set to %d\n", offset, value); + + ret = dm_gpio_set_value(&desc->real_gpio, value); + if (ret) { + dev_err(dev, "Failed to set gpio %d, value %d\n", offset, value); + return ret; + } + + if (value) + wait = desc->ramp_up_us; + else + wait = desc->ramp_down_us; + + udelay(wait); + + dev_dbg(dev, "waited for %d us\n", wait); + + return 0; +} + +static int gpio_delay_direction_output(struct udevice *dev, unsigned int offset, + int value) +{ + return gpio_delay_set_value(dev, offset, value); +} + +static int gpio_delay_xlate(struct udevice *dev, struct gpio_desc *desc, + struct ofnode_phandle_args *args) +{ + struct gpio_delay_priv *priv = dev_get_priv(dev); + + if (args->args_count < 3) + return -EINVAL; + + if (args->args[0] >= 32) + return -EINVAL; + + struct gpio_delay_desc *d = &priv->descs[args->args[0]]; + + d->ramp_up_us = args->args[1]; + d->ramp_down_us = args->args[2]; + + dev_dbg(dev, "pin: %d, ramp_up_us: %d, ramp_down_us: %d\n", + args->args[0], d->ramp_up_us, d->ramp_down_us); + + return 0; +} + +static const struct dm_gpio_ops gpio_delay_ops = { + .direction_output = gpio_delay_direction_output, + .direction_input = gpio_delay_direction_input, + .get_value = gpio_delay_get_value, + .set_value = gpio_delay_set_value, + .xlate = gpio_delay_xlate, +}; + +static int gpio_delay_probe(struct udevice *dev) +{ + struct gpio_delay_priv *priv = dev_get_priv(dev); + struct gpio_delay_desc *d; + ofnode node = dev_ofnode(dev); + int i = 0, ret, ngpio; + + ngpio = gpio_get_list_count(dev, "gpios"); + if (ngpio < 0) + return ngpio; + + dev_dbg(dev, "gpios: %d\n", ngpio); + + priv->descs = devm_kmalloc_array(dev, ngpio, sizeof(*d), GFP_KERNEL); + if (!priv->descs) + return -ENOMEM; + + /* Request all GPIOs described in the controller node */ + for (i = 0; i < ngpio; i++) { + d = &priv->descs[i]; + ret = gpio_request_by_name_nodev(node, "gpios", i, + &d->real_gpio, 0); + if (ret) + return ret; + } + + return 0; +} + +static const struct udevice_id gpio_delay_ids[] = { + { .compatible = "gpio-delay" }, + { } +}; + +U_BOOT_DRIVER(gpio_delay) = { + .name = "gpio-delay", + .id = UCLASS_GPIO, + .of_match = gpio_delay_ids, + .ops = &gpio_delay_ops, + .priv_auto = sizeof(struct gpio_delay_priv), + .probe = gpio_delay_probe, +}; diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 38151ef1bee..7651d5360d6 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -18,15 +18,12 @@ #include <fdtdec.h> #include <malloc.h> #include <acpi/acpi_device.h> -#include <asm/global_data.h> #include <asm/gpio.h> #include <dm/device_compat.h> #include <linux/bug.h> #include <linux/ctype.h> #include <linux/delay.h> -DECLARE_GLOBAL_DATA_PTR; - #define GPIO_ALLOC_BITS 32 /** diff --git a/drivers/gpio/nx_gpio.c b/drivers/gpio/nx_gpio.c index 741b2ff7f17..5abbb34daea 100644 --- a/drivers/gpio/nx_gpio.c +++ b/drivers/gpio/nx_gpio.c @@ -7,12 +7,9 @@ #include <dm.h> #include <errno.h> #include <malloc.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/gpio.h> -DECLARE_GLOBAL_DATA_PTR; - struct nx_gpio_regs { u32 data; /* Data register */ u32 outputenb; /* Output Enable register */ diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c index d13947a0d9c..3e933acb24b 100644 --- a/drivers/i2c/muxes/pca954x.c +++ b/drivers/i2c/muxes/pca954x.c @@ -28,6 +28,7 @@ enum pca_type { PCA9548, PCA9646, PCA9847, + PCA9848, }; struct chip_desc { @@ -106,6 +107,10 @@ static const struct chip_desc chips[] = { .muxtype = pca954x_ismux, .width = 8, }, + [PCA9848] = { + .muxtype = pca954x_isswi, + .width = 8, + }, }; static int pca954x_deselect(struct udevice *mux, struct udevice *bus, @@ -152,6 +157,7 @@ static const struct udevice_id pca954x_ids[] = { { .compatible = "nxp,pca9548", .data = PCA9548 }, { .compatible = "nxp,pca9646", .data = PCA9646 }, { .compatible = "nxp,pca9847", .data = PCA9847 }, + { .compatible = "nxp,pca9848", .data = PCA9848 }, { } }; diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 2dfc1c4eab5..268bb39f009 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -18,7 +18,6 @@ #include <log.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> -#include <asm/global_data.h> #include <dm/device_compat.h> #include <linux/delay.h> #include <linux/errno.h> @@ -30,8 +29,6 @@ #include <dm.h> #include <dm/pinctrl.h> -DECLARE_GLOBAL_DATA_PTR; - #define I2C_QUIRK_FLAG (1 << 0) #define IMX_I2C_REGSHIFT 2 diff --git a/drivers/i2c/nx_i2c.c b/drivers/i2c/nx_i2c.c index 8562dd82bd6..706b7adefe8 100644 --- a/drivers/i2c/nx_i2c.c +++ b/drivers/i2c/nx_i2c.c @@ -7,7 +7,6 @@ #include <asm/arch/reset.h> #include <asm/arch/clk.h> #include <asm/arch/nx_gpio.h> -#include <asm/global_data.h> #include <linux/delay.h> #define I2C_WRITE 0 @@ -45,8 +44,6 @@ #define DEFAULT_SPEED 100000 /* default I2C speed [Hz] */ -DECLARE_GLOBAL_DATA_PTR; - struct nx_i2c_regs { uint iiccon; uint iicstat; diff --git a/drivers/i2c/ocores_i2c.c b/drivers/i2c/ocores_i2c.c index cf714d22ee4..32704ee8854 100644 --- a/drivers/i2c/ocores_i2c.c +++ b/drivers/i2c/ocores_i2c.c @@ -12,7 +12,6 @@ * Andreas Larsson <[email protected]> */ -#include <asm/global_data.h> #include <asm/io.h> #include <clk.h> #include <dm.h> @@ -75,8 +74,6 @@ struct ocores_i2c_bus { u8 (*getreg)(struct ocores_i2c_bus *i2c, int reg); }; -DECLARE_GLOBAL_DATA_PTR; - /* Boolean attribute values */ enum { FALSE = 0, diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 79f7a320502..4102375e5b7 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -25,7 +25,6 @@ #endif #endif #include <i2c.h> -#include <asm/global_data.h> #include <linux/delay.h> #if defined(CONFIG_SOFT_I2C_GPIO_SCL) @@ -82,8 +81,6 @@ /* #define DEBUG_I2C */ -DECLARE_GLOBAL_DATA_PTR; - #ifndef I2C_SOFT_DECLARATIONS # define I2C_SOFT_DECLARATIONS #endif diff --git a/drivers/i2c/synquacer_i2c.c b/drivers/i2c/synquacer_i2c.c index 6672d9435e3..6e5722327c5 100644 --- a/drivers/i2c/synquacer_i2c.c +++ b/drivers/i2c/synquacer_i2c.c @@ -112,8 +112,6 @@ #define SPEED_FM 400 // Fast Mode #define SPEED_SM 100 // Standard Mode -DECLARE_GLOBAL_DATA_PTR; - struct synquacer_i2c { void __iomem *base; unsigned long pclkrate; diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index 47ce0ea690f..5bf122c5505 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -48,7 +48,8 @@ config APPLE_SPI_KEYB config BUTTON_KEYBOARD bool "Buttons as keyboard" - depends on DM_KEYBOARD + depends on DM_KEYBOARD && DM_GPIO + select BUTTON select BUTTON_GPIO help Enable support for mapping buttons to keycode events. Use linux,code button driver diff --git a/drivers/input/cpcap_pwrbutton.c b/drivers/input/cpcap_pwrbutton.c index c8ad39d33ca..ef6311bbfc5 100644 --- a/drivers/input/cpcap_pwrbutton.c +++ b/drivers/input/cpcap_pwrbutton.c @@ -76,7 +76,7 @@ static int cpcap_pwrbutton_of_to_plat(struct udevice *dev) /* Check interrupt parent, driver supports only CPCAP as parent */ irq_parent = ofnode_parse_phandle(dev_ofnode(dev), "interrupt-parent", 0); - if (!ofnode_device_is_compatible(irq_parent, "motorola,cpcap")) + if (!strstr(ofnode_get_name(irq_parent), "cpcap")) return -EINVAL; ret = dev_read_u32(dev, "interrupts", &irq_desc); @@ -87,9 +87,7 @@ static int cpcap_pwrbutton_of_to_plat(struct udevice *dev) priv->bank = irq_desc / 16; priv->id = irq_desc % 16; - ret = dev_read_u32(dev, "linux,code", &priv->keycode); - if (ret) - return ret; + priv->keycode = dev_read_u32_default(dev, "linux,code", KEY_POWER); priv->old_state = false; priv->skip = false; diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig index cc715ceb286..de95a1debdc 100644 --- a/drivers/led/Kconfig +++ b/drivers/led/Kconfig @@ -138,271 +138,4 @@ config SPL_LED_GPIO This option is an SPL-variant of the LED_GPIO option. See the help of LED_GPIO for details. -config LED_STATUS - bool "Enable legacy status LED API" - depends on !LED - help - Allows common u-boot commands to use a board's leds to - provide status for activities like booting and downloading files. - -if LED_STATUS - -# Hidden constants - -config LED_STATUS_OFF - int - default 0 - -config LED_STATUS_BLINKING - int - default 1 - -config LED_STATUS_ON - int - default 2 - -# Hidden constants end - -config LED_STATUS_GPIO - bool "GPIO status LED implementation" - help - The status LED can be connected to a GPIO pin. In such cases, the - gpio_led driver can be used as a status LED backend implementation. - -config LED_STATUS_BOARD_SPECIFIC - bool "Specific board" - default y - help - LED support is only for a specific board. - -comment "LEDs parameters" - -config LED_STATUS0 - bool "Enable status LED 0" - -if LED_STATUS0 - -config LED_STATUS_BIT - int "identification" - help - CONFIG_LED_STATUS_BIT is passed into the __led_* functions to identify - which LED is being acted on. As such, the chosen value must be unique - with respect to the other CONFIG_LED_STATUS_BIT's. Mapping the value - to a physical LED is the responsibility of the __led_* function. - -config LED_STATUS_STATE - int "initial state" - range LED_STATUS_OFF LED_STATUS_ON - default LED_STATUS_OFF - help - Should be set one of the following: - 0 - off - 1 - blinking - 2 - on - -config LED_STATUS_FREQ - int "blink frequency" - range 2 10 - default 2 - help - The LED blink period calculated from LED_STATUS_FREQ: - LED_STATUS_PERIOD = CONFIG_SYS_HZ/LED_STATUS_FREQ - Values range: 2 - 10 - -endif # LED_STATUS0 - -config LED_STATUS1 - bool "Enable status LED 1" - -if LED_STATUS1 - -config LED_STATUS_BIT1 - int "identification" - help - CONFIG_LED_STATUS_BIT1 is passed into the __led_* functions to - identify which LED is being acted on. As such, the chosen value must - be unique with respect to the other CONFIG_LED_STATUS_BIT's. Mapping - the value to a physical LED is the responsibility of the __led_* - function. - -config LED_STATUS_STATE1 - int "initial state" - range LED_STATUS_OFF LED_STATUS_ON - default LED_STATUS_OFF - help - Should be set one of the following: - 0 - off - 1 - blinking - 2 - on - -config LED_STATUS_FREQ1 - int "blink frequency" - range 2 10 - default 2 - help - The LED blink period calculated from LED_STATUS_FREQ1: - LED_STATUS_PERIOD1 = CONFIG_SYS_HZ/LED_STATUS_FREQ1 - Values range: 2 - 10 - -endif # LED_STATUS1 - -config LED_STATUS2 - bool "Enable status LED 2" - -if LED_STATUS2 - -config LED_STATUS_BIT2 - int "identification" - help - CONFIG_LED_STATUS_BIT2 is passed into the __led_* functions to - identify which LED is being acted on. As such, the chosen value must - be unique with respect to the other CONFIG_LED_STATUS_BIT's. Mapping - the value to a physical LED is the responsibility of the __led_* - function. - -config LED_STATUS_STATE2 - int "initial state" - range LED_STATUS_OFF LED_STATUS_ON - default LED_STATUS_OFF - help - Should be set one of the following: - 0 - off - 1 - blinking - 2 - on - -config LED_STATUS_FREQ2 - int "blink frequency" - range 2 10 - default 2 - help - The LED blink period calculated from LED_STATUS_FREQ2: - LED_STATUS_PERIOD2 = CONFIG_SYS_HZ/LED_STATUS_FREQ2 - Values range: 2 - 10 - -endif # LED_STATUS2 - -config LED_STATUS3 - bool "Enable status LED 3" - -if LED_STATUS3 - -config LED_STATUS_BIT3 - int "identification" - help - CONFIG_LED_STATUS_BIT3 is passed into the __led_* functions to - identify which LED is being acted on. As such, the chosen value must - be unique with respect to the other CONFIG_LED_STATUS_BIT's. Mapping - the value to a physical LED is the responsibility of the __led_* - function. - -config LED_STATUS_STATE3 - int "initial state" - range LED_STATUS_OFF LED_STATUS_ON - default LED_STATUS_OFF - help - Should be set one of the following: - 0 - off - 1 - blinking - 2 - on - -config LED_STATUS_FREQ3 - int "blink frequency" - range 2 10 - default 2 - help - The LED blink period calculated from LED_STATUS_FREQ3: - LED_STATUS_PERIOD3 = CONFIG_SYS_HZ/LED_STATUS_FREQ3 - Values range: 2 - 10 - -endif # LED_STATUS3 - -config LED_STATUS4 - bool "Enable status LED 4" - -if LED_STATUS4 - -config LED_STATUS_BIT4 - int "identification" - help - CONFIG_LED_STATUS_BIT4 is passed into the __led_* functions to - identify which LED is being acted on. As such, the chosen value must - be unique with respect to the other CONFIG_LED_STATUS_BIT's. Mapping - the value to a physical LED is the responsibility of the __led_* - function. - -config LED_STATUS_STATE4 - int "initial state" - range LED_STATUS_OFF LED_STATUS_ON - default LED_STATUS_OFF - help - Should be set one of the following: - 0 - off - 1 - blinking - 2 - on - -config LED_STATUS_FREQ4 - int "blink frequency" - range 2 10 - default 2 - help - The LED blink period calculated from LED_STATUS_FREQ4: - LED_STATUS_PERIOD4 = CONFIG_SYS_HZ/LED_STATUS_FREQ4 - Values range: 2 - 10 - -endif # LED_STATUS4 - -config LED_STATUS5 - bool "Enable status LED 5" - -if LED_STATUS5 - -config LED_STATUS_BIT5 - int "identification" - help - CONFIG_LED_STATUS_BIT5 is passed into the __led_* functions to - identify which LED is being acted on. As such, the chosen value must - be unique with respect to the other CONFIG_LED_STATUS_BIT's. Mapping - the value to a physical LED is the responsibility of the __led_* - function. - -config LED_STATUS_STATE5 - int "initial state" - range LED_STATUS_OFF LED_STATUS_ON - default LED_STATUS_OFF - help - Should be set one of the following: - 0 - off - 1 - blinking - 2 - on - -config LED_STATUS_FREQ5 - int "blink frequency" - range 2 10 - default 2 - help - The LED blink period calculated from LED_STATUS_FREQ5: - LED_STATUS_PERIOD5 = CONFIG_SYS_HZ/LED_STATUS_FREQ5 - Values range: 2 - 10 - -endif # LED_STATUS5 - -config LED_STATUS_BOOT_ENABLE - bool "Enable BOOT LED" - help - Enable to turn an LED on when the board is booting. - -if LED_STATUS_BOOT_ENABLE - -config LED_STATUS_BOOT - int "LED to light when the board is booting" - help - Valid enabled LED device number. - -endif # LED_STATUS_BOOT_ENABLE - -config LED_STATUS_CMD - bool "Enable status LED commands" - -endif # LED_STATUS - endmenu diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c index b1e0465e7a8..c7eaa3de96f 100644 --- a/drivers/mailbox/imx-mailbox.c +++ b/drivers/mailbox/imx-mailbox.c @@ -15,8 +15,6 @@ /* This driver only exposes the status bits to keep with the * polling methodology of u-boot. */ -DECLARE_GLOBAL_DATA_PTR; - #define IMX_MU_CHANS 24 #define IMX_MU_V2_PAR_OFF 0x4 diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index a0aa290480e..ea785793d18 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -86,6 +86,7 @@ config GATEWORKS_SC config QCOM_GENI bool "Qualcomm Generic Interface (GENI) driver" depends on MISC + select EFI_PARTITION select PARTITION_TYPE_GUID help Enable support for Qualcomm GENI and it's peripherals. GENI is responseible @@ -256,7 +257,7 @@ config VPL_CROS_EC_LPC config CROS_EC_SANDBOX bool "Enable Chrome OS EC sandbox driver" - depends on CROS_EC && SANDBOX + depends on CROS_EC && SANDBOX && HASH help Enable a sandbox emulation of the Chrome OS EC. This supports keyboard (use the -l flag to enable the LCD), verified boot context, @@ -350,7 +351,8 @@ config MXS_OCOTP config NPCM_HOST bool "Enable support espi or LPC for Host" - depends on REGMAP && SYSCON + depends on SYSCON + select REGMAP help Enable NPCM BMC espi or LPC support for Host reading and writing. diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 1d950f7a0ab..e2170212e5a 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -48,8 +48,6 @@ obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o obj-$(CONFIG_IMX8) += imx8/ obj-$(CONFIG_IMX_ELE) += imx_ele/ obj-$(CONFIG_K3_FUSE) += k3_fuse.o -obj-$(CONFIG_LED_STATUS) += status_led.o -obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o obj-$(CONFIG_$(PHASE_)LS2_SFP) += ls2_sfp.o obj-$(CONFIG_$(PHASE_)MXC_OCOTP) += mxc_ocotp.o diff --git a/drivers/misc/atsha204a-i2c.c b/drivers/misc/atsha204a-i2c.c index 3b9046da880..aa3094fcc01 100644 --- a/drivers/misc/atsha204a-i2c.c +++ b/drivers/misc/atsha204a-i2c.c @@ -15,7 +15,6 @@ #include <errno.h> #include <atsha204a-i2c.h> #include <log.h> -#include <asm/global_data.h> #include <linux/delay.h> #include <linux/bitrev.h> #include <u-boot/crc.h> @@ -25,8 +24,6 @@ #define ATSHA204A_TRANSACTION_RETRY 5 #define ATSHA204A_EXECTIME 5000 -DECLARE_GLOBAL_DATA_PTR; - static inline u16 atsha204a_crc16(const u8 *buffer, size_t len) { return bitrev16(crc16(0, buffer, len)); diff --git a/drivers/misc/fs_loader.c b/drivers/misc/fs_loader.c index 2928cf75f89..6af4c7f15e7 100644 --- a/drivers/misc/fs_loader.c +++ b/drivers/misc/fs_loader.c @@ -13,7 +13,6 @@ #include <fs.h> #include <fs_loader.h> #include <log.h> -#include <asm/global_data.h> #include <dm/device-internal.h> #include <dm/root.h> #include <linux/string.h> @@ -25,8 +24,6 @@ #include <ubi_uboot.h> #endif -DECLARE_GLOBAL_DATA_PTR; - /** * struct firmware - A place for storing firmware and its attribute data. * diff --git a/drivers/misc/gpio_led.c b/drivers/misc/gpio_led.c deleted file mode 100644 index 1e2f83cca93..00000000000 --- a/drivers/misc/gpio_led.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Status LED driver based on GPIO access conventions of Linux - * - * Copyright (C) 2010 Thomas Chou <[email protected]> - * Licensed under the GPL-2 or later. - */ - -#include <status_led.h> -#include <asm/gpio.h> - -#ifndef CFG_GPIO_LED_INVERTED_TABLE -#define CFG_GPIO_LED_INVERTED_TABLE {} -#endif - -static led_id_t gpio_led_inv[] = CFG_GPIO_LED_INVERTED_TABLE; - -static int gpio_led_gpio_value(led_id_t mask, int state) -{ - int i, gpio_value = (state == CONFIG_LED_STATUS_ON); - - for (i = 0; i < ARRAY_SIZE(gpio_led_inv); i++) { - if (gpio_led_inv[i] == mask) - gpio_value = !gpio_value; - } - - return gpio_value; -} - -void __led_init(led_id_t mask, int state) -{ - int gpio_value; - - if (gpio_request(mask, "gpio_led") != 0) { - printf("%s: failed requesting GPIO%lu!\n", __func__, mask); - return; - } - - gpio_value = gpio_led_gpio_value(mask, state); - gpio_direction_output(mask, gpio_value); -} - -void __led_set(led_id_t mask, int state) -{ - int gpio_value = gpio_led_gpio_value(mask, state); - - gpio_set_value(mask, gpio_value); -} - -void __led_toggle(led_id_t mask) -{ - gpio_set_value(mask, !gpio_get_value(mask)); -} diff --git a/drivers/misc/imx8/fuse.c b/drivers/misc/imx8/fuse.c index 90d251a4405..872713e30b6 100644 --- a/drivers/misc/imx8/fuse.c +++ b/drivers/misc/imx8/fuse.c @@ -8,11 +8,8 @@ #include <fuse.h> #include <firmware/imx/sci/sci.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <linux/arm-smccc.h> -DECLARE_GLOBAL_DATA_PTR; - #define FSL_ECC_WORD_START_1 0x10 #define FSL_ECC_WORD_END_1 0x10F diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index d9cc7acb970..c15a4a629ad 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -374,6 +374,31 @@ void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status) __func__, status, RPC_R8(&msg)); } +int sc_misc_get_boot_type(sc_ipc_t ipc, sc_misc_bt_t *type) +{ + struct udevice *dev = gd->arch.scu_dev; + int size = sizeof(struct sc_rpc_msg_s); + struct sc_rpc_msg_s msg; + int ret; + + if (!dev) + hang(); + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (u8)MISC_FUNC_GET_BOOT_TYPE; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret < 0) + return ret; + + if (type) + *type = (u8)RPC_U8(&msg, 0U); + + return 0; +} + int sc_misc_get_boot_container(sc_ipc_t ipc, u8 *idx) { struct udevice *dev = gd->arch.scu_dev; diff --git a/drivers/misc/imx_ele/Makefile b/drivers/misc/imx_ele/Makefile index f8d8c55f983..a5317454583 100644 --- a/drivers/misc/imx_ele/Makefile +++ b/drivers/misc/imx_ele/Makefile @@ -1,4 +1,3 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-y += ele_api.o ele_mu.o -obj-$(CONFIG_CMD_FUSE) += fuse.o +obj-y += ele_api.o ele_mu.o fuse.o diff --git a/drivers/misc/imx_ele/ele_api.c b/drivers/misc/imx_ele/ele_api.c index e7aee0fcef1..8ee0a7733ca 100644 --- a/drivers/misc/imx_ele/ele_api.c +++ b/drivers/misc/imx_ele/ele_api.c @@ -844,3 +844,31 @@ int ele_volt_change_finish_req(void) return ret; } + +int ele_set_gmid(u32 *response) +{ + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg = {}; + int ret; + + if (!dev) { + printf("ele dev is not initialized\n"); + return -ENODEV; + } + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 1; + msg.command = ELE_SET_GMID_REQ; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x\n", + __func__, ret, msg.data[0]); + + if (response) + *response = msg.data[0]; + + return ret; +} diff --git a/drivers/misc/k3_fuse.c b/drivers/misc/k3_fuse.c index 4a8ff1f2523..faafaffe07e 100644 --- a/drivers/misc/k3_fuse.c +++ b/drivers/misc/k3_fuse.c @@ -7,6 +7,7 @@ #include <stdio.h> #include <fuse.h> #include <linux/arm-smccc.h> +#include <linux/bitops.h> #include <string.h> #define K3_SIP_OTP_WRITEBUFF 0xC2000000 @@ -28,20 +29,19 @@ int fuse_read(u32 bank, u32 word, u32 *val) *val = res.a1; if (res.a0 != 0) - printf("SMC call failed: Error code %lu\n", res.a0); + printf("SMC call failed: Error code %ld\n", res.a0); return res.a0; } int fuse_sense(u32 bank, u32 word, u32 *val) { - return -EPERM; + return fuse_read(bank, word, val); } int fuse_prog(u32 bank, u32 word, u32 val) { struct arm_smccc_res res; - u32 mask = val; if (bank != 0U) { printf("Invalid bank argument, ONLY bank 0 is supported\n"); @@ -49,11 +49,18 @@ int fuse_prog(u32 bank, u32 word, u32 val) } /* Make SiP SMC call and send the word, val and mask in the parameter register */ - arm_smccc_smc(K3_SIP_OTP_WRITE, word, - val, mask, 0, 0, 0, 0, &res); + arm_smccc_smc(K3_SIP_OTP_WRITE, bank, word, + val, GENMASK(25, 0), 0, 0, 0, &res); - if (res.a0 != 0) - printf("SMC call failed: Error code %lu\n", res.a0); + if (res.a0 != 0) { + printf("SMC call failed: Error code %ld\n", res.a0); + return res.a0; + } + + if (res.a1 != val) { + printf("Readback failed, written 0x%x readback 0x%lx\n", val, res.a1); + return -EINVAL; + } return res.a0; } @@ -72,7 +79,7 @@ int fuse_writebuff(ulong addr) 0, 0, 0, 0, 0, 0, &res); if (res.a0 != 0) - printf("SMC call failed: Error code %lu\n", res.a0); + printf("SMC call failed: Error code %ld\n", res.a0); return res.a0; } diff --git a/drivers/misc/rockchip-otp.c b/drivers/misc/rockchip-otp.c index 46820425a84..64b6238981b 100644 --- a/drivers/misc/rockchip-otp.c +++ b/drivers/misc/rockchip-otp.c @@ -391,6 +391,10 @@ static const struct udevice_id rockchip_otp_ids[] = { .data = (ulong)&px30_data, }, { + .compatible = "rockchip,rk3506-otp", + .data = (ulong)&rk3568_data, + }, + { .compatible = "rockchip,rk3528-otp", .data = (ulong)&rk3568_data, }, diff --git a/drivers/misc/status_led.c b/drivers/misc/status_led.c deleted file mode 100644 index 3b1baa4f840..00000000000 --- a/drivers/misc/status_led.c +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, [email protected]. - */ - -#include <status_led.h> -#include <linux/types.h> - -/* - * The purpose of this code is to signal the operational status of a - * target which usually boots over the network; while running in - * U-Boot, a status LED is blinking. As soon as a valid BOOTP reply - * message has been received, the LED is turned off. The Linux - * kernel, once it is running, will start blinking the LED again, - * with another frequency. - */ - -/* ------------------------------------------------------------------------- */ - -typedef struct { - led_id_t mask; - int state; - int period; - int cnt; -} led_dev_t; - -led_dev_t led_dev[] = { - { CONFIG_LED_STATUS_BIT, - CONFIG_LED_STATUS_STATE, - LED_STATUS_PERIOD, - 0, - }, -#if defined(CONFIG_LED_STATUS1) - { CONFIG_LED_STATUS_BIT1, - CONFIG_LED_STATUS_STATE1, - LED_STATUS_PERIOD1, - 0, - }, -#endif -#if defined(CONFIG_LED_STATUS2) - { CONFIG_LED_STATUS_BIT2, - CONFIG_LED_STATUS_STATE2, - LED_STATUS_PERIOD2, - 0, - }, -#endif -#if defined(CONFIG_LED_STATUS3) - { CONFIG_LED_STATUS_BIT3, - CONFIG_LED_STATUS_STATE3, - LED_STATUS_PERIOD3, - 0, - }, -#endif -#if defined(CONFIG_LED_STATUS4) - { CONFIG_LED_STATUS_BIT4, - CONFIG_LED_STATUS_STATE4, - LED_STATUS_PERIOD4, - 0, - }, -#endif -#if defined(CONFIG_LED_STATUS5) - { CONFIG_LED_STATUS_BIT5, - CONFIG_LED_STATUS_STATE5, - LED_STATUS_PERIOD5, - 0, - }, -#endif -}; - -#define MAX_LED_DEV (sizeof(led_dev)/sizeof(led_dev_t)) - -static int status_led_init_done = 0; - -void status_led_init(void) -{ - led_dev_t *ld; - int i; - - for (i = 0, ld = led_dev; i < MAX_LED_DEV; i++, ld++) - __led_init (ld->mask, ld->state); - status_led_init_done = 1; -} - -void status_led_tick(ulong timestamp) -{ - led_dev_t *ld; - int i; - - if (!status_led_init_done) - status_led_init(); - - for (i = 0, ld = led_dev; i < MAX_LED_DEV; i++, ld++) { - - if (ld->state != CONFIG_LED_STATUS_BLINKING) - continue; - - if (++ld->cnt >= ld->period) { - __led_toggle (ld->mask); - ld->cnt -= ld->period; - } - - } -} - -void status_led_set(int led, int state) -{ - led_dev_t *ld; - - if (led < 0 || led >= MAX_LED_DEV) - return; - - if (!status_led_init_done) - status_led_init(); - - ld = &led_dev[led]; - - ld->state = state; - if (state == CONFIG_LED_STATUS_BLINKING) { - ld->cnt = 0; /* always start with full period */ - state = CONFIG_LED_STATUS_ON; /* always start with LED _ON_ */ - } - __led_set (ld->mask, state); -} diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 39caf2eff1b..22bd3a972bd 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -627,8 +627,9 @@ config MMC_SDHCI_AM654 depends on ARCH_K3 depends on MMC_SDHCI depends on OF_CONTROL - depends on REGMAP select MMC_SDHCI_IO_ACCESSORS + select REGMAP + select SPL_REGMAP if SPL_MMC help Support for Secure Digital Host Controller Interface (SDHCI) controllers present on TI's AM654 SOCs. diff --git a/drivers/mmc/ca_dw_mmc.c b/drivers/mmc/ca_dw_mmc.c index 1af5ec0532e..d5a4453a62e 100644 --- a/drivers/mmc/ca_dw_mmc.c +++ b/drivers/mmc/ca_dw_mmc.c @@ -6,7 +6,6 @@ #include <dwmmc.h> #include <fdtdec.h> -#include <asm/global_data.h> #include <linux/libfdt.h> #include <malloc.h> #include <errno.h> @@ -26,8 +25,6 @@ #define MIN_FREQ (400000) -DECLARE_GLOBAL_DATA_PTR; - struct ca_mmc_plat { struct mmc_config cfg; struct mmc mmc; diff --git a/drivers/mmc/f_sdh30.c b/drivers/mmc/f_sdh30.c index f47cf848521..f0356e1e960 100644 --- a/drivers/mmc/f_sdh30.c +++ b/drivers/mmc/f_sdh30.c @@ -29,8 +29,6 @@ struct f_sdh30_plat { const struct f_sdh30_data *data; }; -DECLARE_GLOBAL_DATA_PTR; - static void f_sdh30_e51_init(struct udevice *dev) { struct f_sdh30_plat *plat = dev_get_plat(dev); diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 7dc76563b7e..335b44a8a1a 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -752,10 +752,11 @@ static int esdhc_set_voltage(struct mmc *mmc) int ret; priv->signal_voltage = mmc->signal_voltage; + if (priv->vs18_enable) + return -ENOTSUPP; + switch (mmc->signal_voltage) { case MMC_SIGNAL_VOLTAGE_330: - if (priv->vs18_enable) - return -ENOTSUPP; if (CONFIG_IS_ENABLED(DM_REGULATOR) && !IS_ERR_OR_NULL(priv->vqmmc_dev)) { ret = regulator_set_value(priv->vqmmc_dev, diff --git a/drivers/mmc/jz_mmc.c b/drivers/mmc/jz_mmc.c index fc10bb256a4..651d9868305 100644 --- a/drivers/mmc/jz_mmc.c +++ b/drivers/mmc/jz_mmc.c @@ -8,7 +8,6 @@ #include <malloc.h> #include <mmc.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/unaligned.h> #include <errno.h> @@ -419,8 +418,6 @@ int jz_mmc_init(void __iomem *base) #else /* CONFIG_DM_MMC */ #include <dm.h> -DECLARE_GLOBAL_DATA_PTR; - static int jz_mmc_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data) { diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index c5705f4f215..f0e38efb262 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -2343,7 +2343,8 @@ static int mmc_startup_v4(struct mmc *mmc) MMC_VERSION_4_41, MMC_VERSION_4_5, MMC_VERSION_5_0, - MMC_VERSION_5_1 + MMC_VERSION_5_1, + MMC_VERSION_5_1B }; #if CONFIG_IS_ENABLED(MMC_TINY) diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index 38dc36a2194..66f3cf2de4f 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -13,7 +13,6 @@ #include <reset.h> #include <sdhci.h> #include <wait_bit.h> -#include <asm/global_data.h> #include <asm/io.h> #include <linux/bitops.h> #include <power/regulator.h> @@ -61,8 +60,6 @@ struct msm_sdhc_variant_info { u32 core_vendor_spec_capabilities0; }; -DECLARE_GLOBAL_DATA_PTR; - static int msm_sdc_clk_init(struct udevice *dev) { struct msm_sdhc *prv = dev_get_priv(dev); diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c index 4928a880038..7a4bdee7496 100644 --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c @@ -1979,6 +1979,16 @@ static const struct msdc_compatible mt8183_compat = { .use_dma_mode = true, }; +static const struct msdc_compatible mt8189_compat = { + .clk_div_bits = 12, + .pad_tune0 = true, + .async_fifo = true, + .data_tune = true, + .busy_check = true, + .stop_clk_fix = true, + .enhance_rx = true, +}; + static const struct udevice_id msdc_ids[] = { { .compatible = "mediatek,mt7620-mmc", .data = (ulong)&mt7620_compat }, { .compatible = "mediatek,mt7621-mmc", .data = (ulong)&mt7621_compat }, @@ -1990,6 +2000,7 @@ static const struct udevice_id msdc_ids[] = { { .compatible = "mediatek,mt8512-mmc", .data = (ulong)&mt8512_compat }, { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat }, { .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat }, + { .compatible = "mediatek,mt8189-mmc", .data = (ulong)&mt8189_compat }, {} }; diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c index 2da5334c21f..a8b63a20387 100644 --- a/drivers/mmc/mv_sdhci.c +++ b/drivers/mmc/mv_sdhci.c @@ -6,7 +6,6 @@ #include <dm.h> #include <malloc.h> #include <sdhci.h> -#include <asm/global_data.h> #include <linux/mbus.h> #define MVSDH_NAME "mv_sdh" @@ -14,8 +13,6 @@ #define SDHCI_WINDOW_CTRL(win) (0x4080 + ((win) << 4)) #define SDHCI_WINDOW_BASE(win) (0x4084 + ((win) << 4)) -DECLARE_GLOBAL_DATA_PTR; - struct mv_sdhci_plat { struct mmc_config cfg; struct mmc mmc; diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 6219284df3e..c8da6ead0ea 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -58,8 +58,8 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host) u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) | ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT); - if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) && - !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)) { + if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) && + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M)) { /* Disable SDMMC clock. */ clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN, CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); @@ -95,8 +95,8 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host) readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC)); #endif - if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) && - !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)) { + if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) && + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M)) { /* Enable SDMMC clock */ setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN, CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 306175873fa..2999e6b1710 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -217,7 +217,7 @@ config NAND_DENALI bool select DEVRES select SYS_NAND_SELF_INIT - select SYS_NAND_ONFI_DETECTION if TARGET_SOCFPGA_SOC64 + select SYS_NAND_ONFI_DETECTION if ARCH_SOCFPGA_SOC64 imply CMD_NAND config NAND_DENALI_DT diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c b/drivers/mtd/nand/raw/pxa3xx_nand.c index 7bf54fa4654..7324dc72e0a 100644 --- a/drivers/mtd/nand/raw/pxa3xx_nand.c +++ b/drivers/mtd/nand/raw/pxa3xx_nand.c @@ -9,7 +9,6 @@ #include <malloc.h> #include <fdtdec.h> #include <nand.h> -#include <asm/global_data.h> #include <dm/device_compat.h> #include <dm/devres.h> #include <linux/bitops.h> @@ -30,8 +29,6 @@ #include "pxa3xx_nand.h" -DECLARE_GLOBAL_DATA_PTR; - #define TIMEOUT_DRAIN_FIFO 5 /* in ms */ #define CHIP_DELAY_TIMEOUT 200 #define NAND_STOP_DELAY 40 diff --git a/drivers/mtd/nand/raw/tegra_nand.c b/drivers/mtd/nand/raw/tegra_nand.c index ef43dcad079..0bee7eace90 100644 --- a/drivers/mtd/nand/raw/tegra_nand.c +++ b/drivers/mtd/nand/raw/tegra_nand.c @@ -7,7 +7,6 @@ */ #include <log.h> -#include <asm/global_data.h> #include <asm/io.h> #include <memalign.h> #include <nand.h> @@ -26,8 +25,6 @@ #include <linux/printk.h> #include "tegra_nand.h" -DECLARE_GLOBAL_DATA_PTR; - #define NAND_CMD_TIMEOUT_MS 10 #define SKIPPED_SPARE_BYTES 4 diff --git a/drivers/mtd/nvmxip/nvmxip_qspi.c b/drivers/mtd/nvmxip/nvmxip_qspi.c index 1a109bee557..383971bea66 100644 --- a/drivers/mtd/nvmxip/nvmxip_qspi.c +++ b/drivers/mtd/nvmxip/nvmxip_qspi.c @@ -11,9 +11,6 @@ #include <nvmxip.h> #include <linux/errno.h> -#include <asm/global_data.h> -DECLARE_GLOBAL_DATA_PTR; - #define NVMXIP_QSPI_DRV_NAME "nvmxip_qspi" /** diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index a13c7fc60e6..56f6fb70acd 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -292,4 +292,10 @@ config SPL_SPI_FLASH_MTD If unsure, say N +config SPI_FRAM_FUJITSU + bool "Fujitsu SPI FRAM support" + help + Add support for the Fujitsu MB85RS256TY FRAM chip. It's treated the same + as SPI NOR flash at the moment. + endmenu # menu "SPI Flash Support" diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c index 102a9236826..a9db5296b2d 100644 --- a/drivers/mtd/spi/sf-uclass.c +++ b/drivers/mtd/spi/sf-uclass.c @@ -11,13 +11,10 @@ #include <malloc.h> #include <spi.h> #include <spi_flash.h> -#include <asm/global_data.h> #include <dm/device-internal.h> #include <test/test.h> #include "sf_internal.h" -DECLARE_GLOBAL_DATA_PTR; - int spi_flash_read_dm(struct udevice *dev, u32 offset, size_t len, void *buf) { return log_ret(sf_get_ops(dev)->read(dev, offset, len, buf)); diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 76c33b24368..937d79af64e 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -4250,6 +4250,90 @@ static struct spi_nor_fixups macronix_octal_fixups = { }; #endif /* CONFIG_SPI_FLASH_MACRONIX */ +#if CONFIG_IS_ENABLED(SPI_FLASH_WINBOND) + +#define WINBOND_NOR_OP_SELDIE 0xc2 /* Select active die */ + +struct winbond_nor_priv { + unsigned int n_dice; +}; + +/** + * winbond_nor_select_die() - Set active die. + * @nor: pointer to 'struct spi_nor'. + * @die: die to set active. + * + * Certain Winbond chips feature more than a single die. This is mostly hidden + * to the user, except that some chips may experience time deviation when + * modifying the status bits between dies, which in some corner cases may + * produce problematic races. Being able to explicitly select a die to check its + * state in this case may be useful. + * + * Return: 0 on success, -errno otherwise. + */ +static int winbond_nor_select_die(struct spi_nor *nor, u8 die) +{ + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(WINBOND_NOR_OP_SELDIE, 1), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, &die, 0)); + + int ret; + + spi_nor_setup_op(nor, &op, SNOR_PROTO_1_1_1); + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) + debug("Error %d selecting die %d\n", ret, die); + + return ret; +} + +static int winbond_nor_multi_die_ready(struct spi_nor *nor) +{ + struct winbond_nor_priv *winbond_priv = nor->priv; + unsigned int n_dice = winbond_priv ? winbond_priv->n_dice : 1; + int ret, i; + + for (i = 0; i < n_dice; i++) { + ret = winbond_nor_select_die(nor, i); + if (ret) + return ret; + + ret = spi_nor_sr_ready(nor); + if (ret <= 0) + return ret; + } + + return 1; +} + +static void winbond_nor_multi_die_post_sfdp_fixups(struct spi_nor *nor, + struct spi_nor_flash_parameter *param) +{ + struct winbond_nor_priv *winbond_priv; + + winbond_priv = kmalloc(sizeof(*winbond_priv), GFP_KERNEL); + if (!winbond_priv) + return; + + winbond_priv->n_dice = param->size / SZ_64M; + + /* + * SFDP supports dice numbers, but this information is only available in + * optional additional tables which are not provided by these chips. + * Dice number has an impact though, because these devices need extra + * care when reading the busy bit. + */ + nor->priv = winbond_priv; + nor->ready = winbond_nor_multi_die_ready; +} + +static struct spi_nor_fixups winbond_nor_multi_die_fixups = { + .post_sfdp = winbond_nor_multi_die_post_sfdp_fixups, +}; +#endif /* CONFIG_SPI_FLASH_WINBOND */ + /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed * @nor: pointer to a 'struct spi_nor' * @@ -4464,6 +4548,23 @@ void spi_nor_set_fixups(struct spi_nor *nor) nor->info->flags & SPI_NOR_OCTAL_DTR_READ) nor->fixups = ¯onix_octal_fixups; #endif /* SPI_FLASH_MACRONIX */ + +#if CONFIG_IS_ENABLED(SPI_FLASH_WINBOND) + if (JEDEC_MFR(nor->info) == SNOR_MFR_WINBOND) { + u8 multi_die_models[][2] = { + { 0x40, 0x21 }, /* W25Q01JV */ + { 0x70, 0x22 }, /* W25Q02JV */ + }; + int i; + + for (i = 0; i < sizeof(multi_die_models) / 2; i++) { + if (!memcmp(nor->info->id + 1, multi_die_models[i], 2)) { + nor->fixups = &winbond_nor_multi_die_fixups; + break; + } + } + } +#endif /* SPI_FLASH_WINBOND */ } int spi_nor_scan(struct spi_nor *nor) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index b6a07fa9063..e7fea375706 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -86,6 +86,19 @@ const struct flash_info spi_nor_ids[] = { { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) }, { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, #endif +#ifdef CONFIG_SPI_FRAM_FUJITSU + /* Fujitsu MB85RS256TY */ + { + INFO_NAME("mb85rs256ty") + .id = {0x04, 0x7f, 0x25, 0x00, 0x00}, + .id_len = 3, + .sector_size = 32 * 1024, + .n_sectors = 1, + .page_size = 32 * 1024, /* Whole chip can be written at once */ + .flags = SPI_NOR_NO_ERASE, + .addr_width = 2, + }, +#endif #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ /* GigaDevice */ { @@ -243,6 +256,8 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES | SPI_NOR_HAS_TB) }, { INFO("is25lp01gg", 0x9d6021, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) }, + { INFO("is25wp02gg", 0x9d7022, 0, 64 * 1024, 4096, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) }, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ /* Macronix */ @@ -473,7 +488,6 @@ const struct flash_info spi_nor_ids[] = { { INFO("w25q20cl", 0xef4012, 0, 64 * 1024, 4, SECT_4K) }, { INFO("w25q20bw", 0xef5012, 0, 64 * 1024, 4, SECT_4K) }, { INFO("w25q20ew", 0xef6012, 0, 64 * 1024, 4, SECT_4K) }, - { INFO("w25q32", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | @@ -540,11 +554,6 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, { - INFO("w25q512jv", 0xef7119, 0, 64 * 1024, 512, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) - }, - { INFO("w25q512nwq", 0xef6020, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) @@ -581,7 +590,7 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, - { INFO("w25q32bv", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("w25q32", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | diff --git a/drivers/mtd/spi/spi-nor-tiny.c b/drivers/mtd/spi/spi-nor-tiny.c index 23de64a1520..cf00473ee83 100644 --- a/drivers/mtd/spi/spi-nor-tiny.c +++ b/drivers/mtd/spi/spi-nor-tiny.c @@ -220,6 +220,7 @@ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info, /* Some Micron need WREN command; all will accept it */ need_wren = true; fallthrough; + case SNOR_MFR_ISSI: case SNOR_MFR_MACRONIX: case SNOR_MFR_WINBOND: if (need_wren) @@ -246,6 +247,9 @@ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info, } return status; + case SNOR_MFR_CYPRESS: + cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B_CYPRESS; + return spi_nor_write_reg(nor, cmd, NULL, 0); default: /* Spansion style */ nor->cmd_buf[0] = enable << 7; diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index fce8004e134..ed07e286676 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -1,7 +1,3 @@ -source "drivers/net/phy/Kconfig" -source "drivers/net/pfe_eth/Kconfig" -source "drivers/net/fsl-mc/Kconfig" - config ETH def_bool y @@ -94,9 +90,10 @@ config DSA_SANDBOX Ethernet device used as DSA master, to test DSA class code, including exported DSA API and datapath processing of Ethernet traffic. -menuconfig NETDEVICES - bool "Network device support" - depends on NET || NET_LWIP +menu "Network device support" + +config NETDEVICES + bool select DM_ETH help You must select Y to enable any network device support @@ -121,11 +118,15 @@ config AG7XXX This driver supports the Atheros AG7xxx Ethernet MAC. This MAC is present in the Atheros AR7xxx, AR9xxx and QCA9xxx MIPS chips. +source "drivers/net/airoha/Kconfig" + config AIROHA_ETH bool "Airoha Ethernet QDMA Driver" depends on ARCH_AIROHA + select MISC select PHYLIB select DEVRES + select DM_ETH_PHY select DM_RESET select MDIO_MT7531_MMIO help @@ -194,7 +195,7 @@ config DWC_ETH_XGMAC_SOCFPGA select SYSCON select DWC_ETH_XGMAC depends on ARCH_SOCFPGA - default y if TARGET_SOCFPGA_AGILEX5 + default y if ARCH_SOCFPGA_AGILEX5 help The Synopsys Designware Ethernet XGMAC IP block with specific configuration used in Intel SoC FPGA chip. @@ -979,7 +980,11 @@ source "drivers/net/mtk_eth/Kconfig" config HIFEMAC_ETH bool "HiSilicon Fast Ethernet Controller" + depends on DM && OF_CONTROL + select CLK select DM_CLK + select DM_ETH_PHY + select DM_MDIO select DM_RESET select PHYLIB help @@ -989,13 +994,14 @@ config HIFEMAC_ETH config HIFEMAC_MDIO bool "HiSilicon Fast Ethernet Controller MDIO interface" depends on DM_MDIO - select DM_CLK + select CLK help This driver supports the internal MDIO interface of HIFEMAC Ethernet controller. config HIGMACV300_ETH bool "HiSilicon Gigabit Ethernet Controller" + depends on DM && OF_CONTROL select DM_RESET select PHYLIB help @@ -1098,4 +1104,10 @@ config MDIO_MUX_MESON_GXL This driver is used for the MDIO mux found on the Amlogic GXL & compatible SoCs. +source "drivers/net/phy/Kconfig" +source "drivers/net/pfe_eth/Kconfig" +source "drivers/net/fsl-mc/Kconfig" + endif # NETDEVICES + +endmenu diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 5bb40480d88..5e90183d090 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_AG7XXX) += ag7xxx.o +obj-y += airoha/ obj-$(CONFIG_AIROHA_ETH) += airoha_eth.o obj-$(CONFIG_ALTERA_TSE) += altera_tse.o obj-$(CONFIG_ASPEED_MDIO) += aspeed_mdio.o diff --git a/drivers/net/airoha/Kconfig b/drivers/net/airoha/Kconfig new file mode 100644 index 00000000000..d0c007ced80 --- /dev/null +++ b/drivers/net/airoha/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config PCS_AIROHA + bool + select MISC + +config PCS_AIROHA_AN7581 + bool "Airoha AN7581 PCS driver" + depends on ARCH_AIROHA + select PCS_AIROHA + help + This module provides helper to phylink for managing the Airoha + AN7581 PCS for SoC Ethernet and PON SERDES. diff --git a/drivers/net/airoha/Makefile b/drivers/net/airoha/Makefile new file mode 100644 index 00000000000..81fd26cf813 --- /dev/null +++ b/drivers/net/airoha/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_PCS_AIROHA) += pcs-airoha-common.o +obj-$(CONFIG_PCS_AIROHA_AN7581) += pcs-an7581.o diff --git a/drivers/net/airoha/pcs-airoha-common.c b/drivers/net/airoha/pcs-airoha-common.c new file mode 100644 index 00000000000..1263092fcdd --- /dev/null +++ b/drivers/net/airoha/pcs-airoha-common.c @@ -0,0 +1,827 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 AIROHA Inc + * Author: Christian Marangi <[email protected]> + */ + +#include <dm.h> +#include <dm/devres.h> +#include <linux/ethtool.h> +#include <net.h> +#include <regmap.h> +#include <reset.h> +#include <asm/arch/scu-regmap.h> + +#include "pcs-airoha.h" + +static void airoha_pcs_setup_scu_eth(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + u32 xsi_sel; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + xsi_sel = AIROHA_SCU_ETH_XSI_HSGMII; + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + default: + xsi_sel = AIROHA_SCU_ETH_XSI_USXGMII; + } + + regmap_update_bits(priv->scu, AIROHA_SCU_SSR3, + AIROHA_SCU_ETH_XSI_SEL, + xsi_sel); +} + +static void airoha_pcs_setup_scu_pon(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + u32 xsi_sel, wan_sel; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + wan_sel = AIROHA_SCU_WAN_SEL_SGMII; + xsi_sel = AIROHA_SCU_PON_XSI_HSGMII; + break; + case PHY_INTERFACE_MODE_2500BASEX: + wan_sel = AIROHA_SCU_WAN_SEL_HSGMII; + xsi_sel = AIROHA_SCU_PON_XSI_HSGMII; + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + default: + wan_sel = AIROHA_SCU_WAN_SEL_USXGMII; + xsi_sel = AIROHA_SCU_PON_XSI_USXGMII; + } + + regmap_update_bits(priv->scu, AIROHA_SCU_SSTR, + AIROHA_SCU_PON_XSI_SEL, + xsi_sel); + + regmap_update_bits(priv->scu, AIROHA_SCU_WAN_CONF, + AIROHA_SCU_WAN_SEL, + wan_sel); +} + +static int airoha_pcs_setup_scu(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + const struct airoha_pcs_match_data *data = priv->data; + int ret; + + if (priv->xfi_rst) { + ret = reset_assert(priv->xfi_rst); + if (ret) + return ret; + } + + switch (data->port_type) { + case AIROHA_PCS_ETH: + airoha_pcs_setup_scu_eth(priv, interface); + break; + case AIROHA_PCS_PON: + airoha_pcs_setup_scu_pon(priv, interface); + break; + } + + if (priv->xfi_rst) { + ret = reset_deassert(priv->xfi_rst); + if (ret) + return ret; + } + + /* TODO better handle reset from MAC */ + ret = reset_assert_bulk(&priv->rsts); + if (ret) + return ret; + + ret = reset_deassert_bulk(&priv->rsts); + if (ret) + return ret; + + return 0; +} + +static void airoha_pcs_init_usxgmii(struct airoha_pcs_priv *priv) +{ + const struct airoha_pcs_match_data *data = priv->data; + + regmap_set_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0, + AIROHA_PCS_HSGMII_XFI_SEL); + + /* Disable Hibernation */ + if (data->hibernation_workaround) + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTROL_1, + AIROHA_PCS_USXGMII_SPEED_SEL_H); + + /* FIXME: wait Airoha */ + /* Avoid PCS sending garbage to MAC in some HW revision (E0) */ + if (data->usxgmii_ber_time_fixup) + regmap_write(priv->usxgmii_pcs, AIROHA_PCS_USGMII_VENDOR_DEFINE_116, 0); + + if (data->usxgmii_rx_gb_out_vld_tweak) + regmap_clear_bits(priv->usxgmii_pcs, AN7583_PCS_USXGMII_RTL_MODIFIED, + AIROHA_PCS_USXGMII_MODIFIED_RX_GB_OUT_VLD); +} + +static void airoha_pcs_init_hsgmii(struct airoha_pcs_priv *priv) +{ + regmap_clear_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0, + AIROHA_PCS_HSGMII_XFI_SEL); + + regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1, + AIROHA_PCS_TBI_10B_MODE); +} + +static void airoha_pcs_init_sgmii(struct airoha_pcs_priv *priv) +{ + regmap_clear_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0, + AIROHA_PCS_HSGMII_XFI_SEL); + + regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1, + AIROHA_PCS_TBI_10B_MODE); + + regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6, + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L, + FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L, 0x07070707)); + + regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8, + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C, + FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C, 0xff)); +} + +static void airoha_pcs_init(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + airoha_pcs_init_sgmii(priv); + break; + case PHY_INTERFACE_MODE_2500BASEX: + airoha_pcs_init_hsgmii(priv); + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + airoha_pcs_init_usxgmii(priv); + break; + default: + return; + } +} + +static void airoha_pcs_interrupt_init_sgmii(struct airoha_pcs_priv *priv) +{ + /* Disable every interrupt */ + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT, + AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT | + AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT | + AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT | + AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT | + AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT); + + /* Clear interrupt */ + regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT, + AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR | + AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR | + AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR | + AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR | + AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR); + + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT, + AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR | + AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR | + AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR | + AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR | + AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR); +} + +static void airoha_pcs_interrupt_init_usxgmii(struct airoha_pcs_priv *priv) +{ + /* Disable every Interrupt */ + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_0, + AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN | + AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN | + AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN | + AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN); + + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_1, + AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN | + AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN | + AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN | + AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN); + + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_2, + AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN | + AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN | + AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN | + AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN); + + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_3, + AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN | + AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN | + AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN | + AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN); + + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_4, + AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN); + + /* Clear any pending interrupt */ + regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_2, + AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT | + AIROHA_PCS_USXGMII_R_TYPE_E_INT | + AIROHA_PCS_USXGMII_R_TYPE_T_INT | + AIROHA_PCS_USXGMII_R_TYPE_D_INT); + + regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_3, + AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT | + AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT | + AIROHA_PCS_USXGMII_LINK_UP_ST_INT | + AIROHA_PCS_USXGMII_HI_BER_ST_INT); + + regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_4, + AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT); + + /* Interrupt saddly seems to be not weel supported for Link Down. + * PCS Poll is a must to correctly read and react on Cable Deatch + * as only cable attach interrupt are fired and Link Down interrupt + * are fired only in special case like AN restart. + */ +} + +static void airoha_pcs_interrupt_init(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + return airoha_pcs_interrupt_init_sgmii(priv); + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + return airoha_pcs_interrupt_init_usxgmii(priv); + default: + return; + } +} + +int airoha_pcs_config(struct udevice *dev, bool neg_mode, + phy_interface_t interface, + const unsigned long *advertising, + bool permit_pause_to_mac) +{ + struct airoha_pcs_priv *priv = dev_get_priv(dev); + const struct airoha_pcs_match_data *data; + u32 rate_adapt; + int ret; + + priv->interface = interface; + data = priv->data; + + /* Apply Analog and Digital configuration for PCS */ + if (data->bringup) { + ret = data->bringup(priv, interface); + if (ret) + return ret; + } + + /* Set final configuration for various modes */ + airoha_pcs_init(priv, interface); + + /* Configure Interrupt for various modes */ + airoha_pcs_interrupt_init(priv, interface); + + rate_adapt = AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN | + AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN; + + if (interface == PHY_INTERFACE_MODE_SGMII) + rate_adapt |= AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS | + AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS; + + /* AN Auto Settings (Rate Adaptation) */ + regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0, + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS | + AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS | + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN | + AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN, rate_adapt); + + /* FIXME: With an attached Aeonsemi PHY, AN is needed + * even with no inband. + */ + if (interface == PHY_INTERFACE_MODE_USXGMII || + interface == PHY_INTERFACE_MODE_10GBASER) { + if (interface == PHY_INTERFACE_MODE_USXGMII) + regmap_set_bits(priv->usxgmii_pcs, + AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0, + AIROHA_PCS_USXGMII_AN_ENABLE); + else + regmap_clear_bits(priv->usxgmii_pcs, + AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0, + AIROHA_PCS_USXGMII_AN_ENABLE); + + if (data->usxgmii_xfi_mode_sel && neg_mode) + regmap_set_bits(priv->usxgmii_pcs, + AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7, + AIROHA_PCS_USXGMII_XFI_MODE_TX_SEL | + AIROHA_PCS_USXGMII_XFI_MODE_RX_SEL); + } + + /* Clear any force bit that my be set by bootloader */ + if (interface == PHY_INTERFACE_MODE_SGMII || + interface == PHY_INTERFACE_MODE_1000BASEX || + interface == PHY_INTERFACE_MODE_2500BASEX) { + regmap_clear_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0, + AIROHA_PCS_LINK_MODE_P0 | + AIROHA_PCS_FORCE_SPD_MODE_P0 | + AIROHA_PCS_FORCE_LINKDOWN_P0 | + AIROHA_PCS_FORCE_LINKUP_P0); + } + + /* Toggle Rate Adaption for SGMII/HSGMII mode */ /* TODO */ + if (interface == PHY_INTERFACE_MODE_SGMII || + interface == PHY_INTERFACE_MODE_1000BASEX || + interface == PHY_INTERFACE_MODE_2500BASEX) { + if (neg_mode) + regmap_clear_bits(priv->hsgmii_rate_adp, + AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0, + AIROHA_PCS_HSGMII_P0_DIS_MII_MODE); + else + regmap_set_bits(priv->hsgmii_rate_adp, + AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0, + AIROHA_PCS_HSGMII_P0_DIS_MII_MODE); + } + + /* Setup SGMII AN and advertisement in DEV_ABILITY */ /* TODO */ + if (interface == PHY_INTERFACE_MODE_SGMII) { + if (neg_mode) { + int advertise = 0x1; + + regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4, + AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY, + FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY, + advertise)); + + regmap_set_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0, + AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE); + } else { + regmap_clear_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0, + AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE); + } + } + + if (interface == PHY_INTERFACE_MODE_2500BASEX) { + regmap_clear_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0, + AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE); + + regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6, + AIROHA_PCS_HSGMII_PCS_TX_ENABLE); + } + + if (interface == PHY_INTERFACE_MODE_SGMII || + interface == PHY_INTERFACE_MODE_1000BASEX) { + u32 if_mode = AIROHA_PCS_HSGMII_AN_SIDEBAND_EN; + + /* Toggle SGMII or 1000base-x mode */ + if (interface == PHY_INTERFACE_MODE_SGMII) + if_mode |= AIROHA_PCS_HSGMII_AN_SGMII_EN; + + if (neg_mode) + regmap_set_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13, + AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS); + else + regmap_clear_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13, + AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS); + + if (neg_mode) { + /* Clear force speed bits and MAC mode */ + regmap_clear_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6, + AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 | + AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 | + AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 | + AIROHA_PCS_HSGMII_PCS_MAC_MODE | + AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL | + AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT); + } else { + /* Enable compatibility with MAC PCS Layer */ + if_mode |= AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN; + + /* AN off force rate adaption, speed is set later in Link Up */ + regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6, + AIROHA_PCS_HSGMII_PCS_MAC_MODE | + AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT); + } + + regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13, + AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0, if_mode); + + regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6, + AIROHA_PCS_HSGMII_PCS_TX_ENABLE | + AIROHA_PCS_HSGMII_PCS_MODE2_EN); + } + + if (interface == PHY_INTERFACE_MODE_1000BASEX && + !neg_mode) { + regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1, + AIROHA_PCS_SGMII_SEND_AN_ERR_EN); + + regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37, + AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE); + } + + /* Configure Flow Control on XFI */ + regmap_update_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG, + AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN, + permit_pause_to_mac ? + AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN : + 0); + + return 0; +} + +void airoha_pcs_link_up(struct udevice *dev, unsigned int neg_mode, + phy_interface_t interface, int speed, int duplex) +{ + struct airoha_pcs_priv *priv = dev_get_priv(dev); + const struct airoha_pcs_match_data *data; + + data = priv->data; + + if (neg_mode) { + if (interface == PHY_INTERFACE_MODE_SGMII) { + regmap_update_bits(priv->hsgmii_rate_adp, + AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1, + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR | + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, + FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0x0) | + FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x0)); + udelay(1); + regmap_update_bits(priv->hsgmii_rate_adp, + AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1, + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR | + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, + FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0xf) | + FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x5)); + } + } else { + if (interface == PHY_INTERFACE_MODE_USXGMII || + interface == PHY_INTERFACE_MODE_10GBASER) { + u32 mode; + u32 rate_adapt; + + switch (speed) { + case SPEED_10000: + rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000; + mode = AIROHA_PCS_USXGMII_MODE_10000; + break; + /* case SPEED_5000: not supported in U-Boot + rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000; + mode = AIROHA_PCS_USXGMII_MODE_5000; + break; */ + case SPEED_2500: + rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500; + mode = AIROHA_PCS_USXGMII_MODE_2500; + break; + case SPEED_1000: + rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000; + mode = AIROHA_PCS_USXGMII_MODE_1000; + break; + case SPEED_100: + rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100; + mode = AIROHA_PCS_USXGMII_MODE_100; + break; + } + + /* Trigger USXGMII change mode and force selected speed */ + regmap_update_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7, + AIROHA_PCS_USXGMII_RATE_UPDATE_MODE | + AIROHA_PCS_USXGMII_MODE, + AIROHA_PCS_USXGMII_RATE_UPDATE_MODE | mode); + + regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11, + AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN | + AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, + AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN | + rate_adapt); + } + + if (interface == PHY_INTERFACE_MODE_SGMII || + interface == PHY_INTERFACE_MODE_1000BASEX) { + u32 force_speed; + u32 rate_adapt; + + switch (speed) { + case SPEED_1000: + force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000; + rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000; + break; + case SPEED_100: + force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100; + rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100; + break; + case SPEED_10: + force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10; + rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10; + break; + } + + regmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6, + AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 | + AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 | + AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 | + AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, + force_speed | rate_adapt); + } + + if (interface == PHY_INTERFACE_MODE_SGMII || + interface == PHY_INTERFACE_MODE_2500BASEX) { + u32 ck_gen_mode; + u32 speed_reg; + u32 if_mode; + + switch (speed) { + case SPEED_2500: + speed_reg = AIROHA_PCS_LINK_MODE_P0_2_5G; + break; + case SPEED_1000: + speed_reg = AIROHA_PCS_LINK_MODE_P0_1G; + if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000; + ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000; + break; + case SPEED_100: + speed_reg = AIROHA_PCS_LINK_MODE_P0_100M; + if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100; + ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100; + break; + case SPEED_10: + speed_reg = AIROHA_PCS_LINK_MODE_P0_100M; + if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10; + ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10; + break; + } + + if (interface == PHY_INTERFACE_MODE_SGMII) { + regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13, + AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, + if_mode); + + regmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE, + AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE | + AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL, + ck_gen_mode | + AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL); + } + + regmap_update_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0, + AIROHA_PCS_LINK_MODE_P0 | + AIROHA_PCS_FORCE_SPD_MODE_P0, + speed_reg | + AIROHA_PCS_FORCE_SPD_MODE_P0); + } + } + + if (data->link_up) + data->link_up(priv); + + /* BPI BMI enable */ + regmap_clear_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG, + AIROHA_PCS_XFI_RXMPI_STOP | + AIROHA_PCS_XFI_RXMBI_STOP | + AIROHA_PCS_XFI_TXMPI_STOP | + AIROHA_PCS_XFI_TXMBI_STOP); +} + +void airoha_pcs_link_down(struct udevice *dev) +{ + struct airoha_pcs_priv *priv = dev_get_priv(dev); + + /* MPI MBI disable */ + regmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG, + AIROHA_PCS_XFI_RXMPI_STOP | + AIROHA_PCS_XFI_RXMBI_STOP | + AIROHA_PCS_XFI_TXMPI_STOP | + AIROHA_PCS_XFI_TXMBI_STOP); +} + +void airoha_pcs_pre_config(struct udevice *dev, phy_interface_t interface) +{ + struct airoha_pcs_priv *priv = dev_get_priv(dev); + + /* Select HSGMII or USXGMII in SCU regs */ + airoha_pcs_setup_scu(priv, interface); + + /* MPI MBI disable */ + regmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG, + AIROHA_PCS_XFI_RXMPI_STOP | + AIROHA_PCS_XFI_RXMBI_STOP | + AIROHA_PCS_XFI_TXMPI_STOP | + AIROHA_PCS_XFI_TXMBI_STOP); + + /* Write 1 to trigger reset and clear */ + regmap_clear_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST, + AIROHA_PCS_XFI_MAC_LOGIC_RST); + regmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST, + AIROHA_PCS_XFI_MAC_LOGIC_RST); + + udelay(1000); + + /* Clear XFI MAC counter */ + regmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_CNT_CLR, + AIROHA_PCS_XFI_GLB_CNT_CLR); +} + +int airoha_pcs_post_config(struct udevice *dev, phy_interface_t interface) +{ + struct airoha_pcs_priv *priv = dev_get_priv(dev); + + /* Frag disable */ + regmap_update_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG, + AIROHA_PCS_XFI_RX_FRAG_LEN, + FIELD_PREP(AIROHA_PCS_XFI_RX_FRAG_LEN, 31)); + regmap_update_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG, + AIROHA_PCS_XFI_TX_FRAG_LEN, + FIELD_PREP(AIROHA_PCS_XFI_TX_FRAG_LEN, 31)); + + /* IPG NUM */ + regmap_update_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG, + AIROHA_PCS_XFI_IPG_NUM, + FIELD_PREP(AIROHA_PCS_XFI_IPG_NUM, 10)); + + /* Enable TX/RX flow control */ + regmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG, + AIROHA_PCS_XFI_TX_FC_EN); + regmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG, + AIROHA_PCS_XFI_RX_FC_EN); + + return 0; +} + +static const struct regmap_config airoha_pcs_regmap_config = { + .width = REGMAP_SIZE_32, +}; + +static int airoha_pcs_probe(struct udevice *dev) +{ + struct regmap_config syscon_config = airoha_pcs_regmap_config; + struct airoha_pcs_priv *priv = dev_get_priv(dev); + fdt_addr_t base; + fdt_size_t size; + int ret; + + priv->dev = dev; + priv->data = (void *)dev_get_driver_data(dev); + + base = dev_read_addr_size_name(dev, "xfi_mac", &size); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + syscon_config.r_start = base; + syscon_config.r_size = size; + priv->xfi_mac = devm_regmap_init(dev, NULL, NULL, &syscon_config); + if (IS_ERR(priv->xfi_mac)) + return PTR_ERR(priv->xfi_mac); + + base = dev_read_addr_size_name(dev, "hsgmii_an", &size); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + syscon_config.r_start = base; + syscon_config.r_size = size; + priv->hsgmii_an = devm_regmap_init(dev, NULL, NULL, &syscon_config); + if (IS_ERR(priv->hsgmii_an)) + return PTR_ERR(priv->hsgmii_an); + + base = dev_read_addr_size_name(dev, "hsgmii_pcs", &size); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + syscon_config.r_start = base; + syscon_config.r_size = size; + priv->hsgmii_pcs = devm_regmap_init(dev, NULL, NULL, &syscon_config); + if (IS_ERR(priv->hsgmii_pcs)) + return PTR_ERR(priv->hsgmii_pcs); + + base = dev_read_addr_size_name(dev, "hsgmii_rate_adp", &size); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + syscon_config.r_start = base; + syscon_config.r_size = size; + priv->hsgmii_rate_adp = devm_regmap_init(dev, NULL, NULL, &syscon_config); + if (IS_ERR(priv->hsgmii_rate_adp)) + return PTR_ERR(priv->hsgmii_rate_adp); + + base = dev_read_addr_size_name(dev, "multi_sgmii", &size); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + syscon_config.r_start = base; + syscon_config.r_size = size; + priv->multi_sgmii = devm_regmap_init(dev, NULL, NULL, &syscon_config); + if (IS_ERR(priv->multi_sgmii)) + return PTR_ERR(priv->multi_sgmii); + + base = dev_read_addr_size_name(dev, "usxgmii", &size); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + syscon_config.r_start = base; + syscon_config.r_size = size; + priv->usxgmii_pcs = devm_regmap_init(dev, NULL, NULL, &syscon_config); + if (IS_ERR(priv->usxgmii_pcs)) + return PTR_ERR(priv->usxgmii_pcs); + + base = dev_read_addr_size_name(dev, "xfi_pma", &size); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + syscon_config.r_start = base; + syscon_config.r_size = size; + priv->xfi_pma = devm_regmap_init(dev, NULL, NULL, &syscon_config); + if (IS_ERR(priv->xfi_pma)) + return PTR_ERR(priv->xfi_pma); + + base = dev_read_addr_size_name(dev, "xfi_ana", &size); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + syscon_config.r_start = base; + syscon_config.r_size = size; + priv->xfi_ana = devm_regmap_init(dev, NULL, NULL, &syscon_config); + if (IS_ERR(priv->xfi_ana)) + return PTR_ERR(priv->xfi_ana); + + /* SCU is used to toggle XFI or HSGMII in global SoC registers */ + priv->scu = airoha_get_scu_regmap(); + if (IS_ERR(priv->scu)) + return PTR_ERR(priv->scu); + + priv->rsts.resets = devm_kcalloc(dev, AIROHA_PCS_MAX_NUM_RSTS, + sizeof(struct reset_ctl), GFP_KERNEL); + if (!priv->rsts.resets) + return -ENOMEM; + priv->rsts.count = AIROHA_PCS_MAX_NUM_RSTS; + + ret = reset_get_by_name(dev, "mac", &priv->rsts.resets[0]); + if (ret) + return ret; + + ret = reset_get_by_name(dev, "phy", &priv->rsts.resets[1]); + if (ret) + return ret; + + priv->xfi_rst = devm_reset_control_get_optional(dev, "xfi"); + + /* For Ethernet PCS, read the AN7581 SoC revision to check if + * manual rx calibration is needed. This is only limited to + * any SoC revision before E2. + */ + if (device_is_compatible(dev, "airoha,an7581-pcs-eth") && + priv->data->port_type == AIROHA_PCS_ETH) { + u32 val; + + ret = regmap_read(priv->scu, AIROHA_SCU_PDIDR, &val); + if (ret) + return ret; + + if (FIELD_GET(AIROHA_SCU_PRODUCT_ID, val) < 0x2) + priv->manual_rx_calib = true; + } + + return 0; +} + +static const struct airoha_pcs_match_data an7581_pcs_eth = { + .port_type = AIROHA_PCS_ETH, + .hibernation_workaround = true, + .usxgmii_ber_time_fixup = true, + .bringup = an7581_pcs_bringup, + .link_up = an7581_pcs_phya_link_up, +}; + +static const struct airoha_pcs_match_data an7581_pcs_pon = { + .port_type = AIROHA_PCS_PON, + .hibernation_workaround = true, + .usxgmii_ber_time_fixup = true, + .bringup = an7581_pcs_bringup, + .link_up = an7581_pcs_phya_link_up, +}; + +static const struct udevice_id airoha_pcs_of_table[] = { + { .compatible = "airoha,an7581-pcs-eth", + .data = (ulong)&an7581_pcs_eth }, + { .compatible = "airoha,an7581-pcs-pon", + .data = (ulong)&an7581_pcs_pon }, + { }, +}; + +U_BOOT_DRIVER(airoha_pcs) = { + .name = "airoha-pcs", + .id = UCLASS_MISC, + .of_match = airoha_pcs_of_table, + .probe = airoha_pcs_probe, + .priv_auto = sizeof(struct airoha_pcs_priv), +}; diff --git a/drivers/net/airoha/pcs-airoha.h b/drivers/net/airoha/pcs-airoha.h new file mode 100644 index 00000000000..714d2ebe520 --- /dev/null +++ b/drivers/net/airoha/pcs-airoha.h @@ -0,0 +1,1220 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 AIROHA Inc + * Author: Christian Marangi <[email protected]> + */ + +#include <linux/bitfield.h> +#include <regmap.h> +#include <reset.h> + +/* SCU*/ +#define AIROHA_SCU_PDIDR 0x5c +#define AIROHA_SCU_PRODUCT_ID GENMASK(15, 0) +#define AIROHA_SCU_WAN_CONF 0x70 +#define AIROHA_SCU_ETH_MAC_SEL BIT(24) +#define AIROHA_SCU_ETH_MAC_SEL_XFI FIELD_PREP_CONST(AIROHA_SCU_ETH_MAC_SEL, 0x0) +#define AIROHA_SCU_ETH_MAC_SEL_PON FIELD_PREP_CONST(AIROHA_SCU_ETH_MAC_SEL, 0x1) +#define AIROHA_SCU_WAN_SEL GENMASK(7, 0) +#define AIROHA_SCU_WAN_SEL_SGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x10) +#define AIROHA_SCU_WAN_SEL_HSGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x11) +#define AIROHA_SCU_WAN_SEL_USXGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x12) +#define AIROHA_SCU_SSR3 0x94 +#define AIROHA_SCU_ETH_XSI_SEL GENMASK(14, 13) +#define AIROHA_SCU_ETH_XSI_USXGMII FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x1) +#define AIROHA_SCU_ETH_XSI_HSGMII FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x2) +#define AIROHA_SCU_SSTR 0x9c +#define AIROHA_SCU_PON_XSI_SEL GENMASK(10, 9) +#define AIROHA_SCU_PON_XSI_USXGMII FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x1) +#define AIROHA_SCU_PON_XSI_HSGMII FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x2) + +/* XFI_MAC */ +#define AIROHA_PCS_XFI_MAC_XFI_GIB_CFG 0x0 +#define AIROHA_PCS_XFI_RX_FRAG_LEN GENMASK(26, 22) +#define AIROHA_PCS_XFI_TX_FRAG_LEN GENMASK(21, 17) +#define AIROHA_PCS_XFI_IPG_NUM GENMASK(15, 10) +#define AIROHA_PCS_XFI_TX_FC_EN BIT(5) +#define AIROHA_PCS_XFI_RX_FC_EN BIT(4) +#define AIROHA_PCS_XFI_RXMPI_STOP BIT(3) +#define AIROHA_PCS_XFI_RXMBI_STOP BIT(2) +#define AIROHA_PCS_XFI_TXMPI_STOP BIT(1) +#define AIROHA_PCS_XFI_TXMBI_STOP BIT(0) +#define AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST 0x10 +#define AIROHA_PCS_XFI_MAC_LOGIC_RST BIT(0) +#define AIROHA_PCS_XFI_MAC_XFI_MACADDRH 0x60 +#define AIROHA_PCS_XFI_MAC_MACADDRH GENMASK(15, 0) +#define AIROHA_PCS_XFI_MAC_XFI_MACADDRL 0x64 +#define AIROHA_PCS_XFI_MAC_MACADDRL GENMASK(31, 0) +#define AIROHA_PCS_XFI_MAC_XFI_CNT_CLR 0x100 +#define AIROHA_PCS_XFI_GLB_CNT_CLR BIT(0) + +/* HSGMII_AN */ +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0 0x0 +#define AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE BIT(12) +#define AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART BIT(9) +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1 0x4 /* BMSR */ +#define AIROHA_PCS_HSGMII_AN_SGMII_UNIDIR_ABILITY BIT(6) +#define AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE BIT(5) +#define AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT BIT(4) +#define AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY BIT(3) +#define AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS BIT(2) +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4 0x10 +#define AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY GENMASK(15, 0) +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5 0x14 /* LPA */ +#define AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY GENMASK(15, 0) +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11 0x2c +#define AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER GENMASK(19, 0) +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13 0x34 +#define AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS BIT(8) +#define AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0 GENMASK(5, 0) +#define AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN BIT(5) +#define AIROHA_PCS_HSGMII_AN_DUPLEX_FORCE_MODE BIT(4) +#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE GENMASK(3, 2) +#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x2) +#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x1) +#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x0) +#define AIROHA_PCS_HSGMII_AN_SIDEBAND_EN BIT(1) +#define AIROHA_PCS_HSGMII_AN_SGMII_EN BIT(0) +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37 0x60 +#define AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE BIT(0) + +/* HSGMII_PCS */ +#define AIROHA_PCS_HSGMII_PCS_CTROL_1 0x0 +#define AIROHA_PCS_TBI_10B_MODE BIT(30) +#define AIROHA_PCS_SGMII_SEND_AN_ERR_EN BIT(24) +#define AIROHA_PCS_REMOTE_FAULT_DIS BIT(12) +#define AIROHA_PCS_HSGMII_PCS_CTROL_3 0x8 +#define AIROHA_PCS_HSGMII_PCS_LINK_STSTIME GENMASK(19, 0) +#define AIROHA_PCS_HSGMII_PCS_CTROL_6 0x14 +#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 BIT(14) +#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 BIT(13) +#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 BIT(12) +#define AIROHA_PCS_HSGMII_PCS_MAC_MODE BIT(8) +#define AIROHA_PCS_HSGMII_PCS_TX_ENABLE BIT(4) +#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL GENMASK(3, 2) +#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x0) +#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x1) +#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x2) +#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT BIT(1) +#define AIROHA_PCS_HSGMII_PCS_MODE2_EN BIT(0) +#define AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT 0x20 +#define AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR BIT(11) +#define AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT BIT(10) +#define AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR BIT(9) +#define AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT BIT(8) +#define AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR BIT(5) +#define AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT BIT(4) +#define AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR BIT(3) +#define AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR BIT(2) +#define AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT BIT(1) +#define AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT BIT(0) +#define AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE 0x24 +#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE GENMASK(5, 4) +#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x0) +#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x1) +#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x2) +#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL BIT(0) +#define ARIOHA_PCS_HSGMII_PCS_STATE_2 0x104 +#define AIROHA_PCS_HSGMII_PCS_RX_SYNC BIT(5) +#define AIROHA_PCS_HSGMII_PCS_AN_DONE BIT(0) +#define AIROHA_PCS_HSGMII_PCS_INT_STATE 0x15c +#define AIROHA_PCS_HSGMII_PCS_MODE2_REMOTE_FAULT_OCCUR_INT BIT(4) +#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_MLS BIT(3) +#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_CL37_TIMERDONE_INT BIT(2) +#define AIROHA_PCS_HSGMII_PCS_MODE2_RX_SYNC BIT(1) +#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_DONE BIT(0) + +/* MULTI_SGMII */ +#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_EN_0 0x14 +#define AIROHA_PCS_MULTI_SGMII_PCS_INT_EN_0 BIT(0) +#define AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0 0x18 +#define AIROHA_PCS_LINK_MODE_P0 GENMASK(5, 4) +#define AIROHA_PCS_LINK_MODE_P0_2_5G FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x3) +#define AIROHA_PCS_LINK_MODE_P0_1G FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x2) +#define AIROHA_PCS_LINK_MODE_P0_100M FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x1) +#define AIROHA_PCS_LINK_MODE_P0_10M FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x0) +#define AIROHA_PCS_FORCE_SPD_MODE_P0 BIT(2) +#define AIROHA_PCS_FORCE_LINKDOWN_P0 BIT(1) +#define AIROHA_PCS_FORCE_LINKUP_P0 BIT(0) +#define AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0 0x100 +#define AIROHA_PCS_HSGMII_XFI_SEL BIT(28) +#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_SEL 0x14c +#define AIROHA_PCS_HSGMII_PCS_INT BIT(0) +#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_15 0x43c +#define AIROHA_PCS_LINK_STS_P0 BIT(3) +#define AIROHA_PCS_SPEED_STS_P0 GENMASK(2, 0) +#define AIROHA_PCS_SPEED_STS_P0_1G FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x2) +#define AIROHA_PCS_SPEED_STS_P0_100M FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x1) +#define AIROHA_PCS_SPEED_STS_P0_10M FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x0) +#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_18 0x448 +#define AIROHA_PCS_P0_SGMII_IS_10 BIT(2) +#define AIROHA_PCS_P0_SGMII_IS_100 BIT(1) +#define AIROHA_PCS_P0_SGMII_IS_1000 BIT(0) + +/* HSGMII_RATE_ADP */ +#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0 0x0 +#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS BIT(27) +#define AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS BIT(26) +#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN BIT(4) +#define AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN BIT(0) +#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1 0x4 +#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR GENMASK(20, 16) +#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR GENMASK(28, 24) +#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6 0x18 +#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L GENMASK(31, 0) +#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8 0x20 +#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C GENMASK(7, 0) +#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11 0x2c +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN BIT(8) +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE GENMASK(15, 12) +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000 \ + FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x0) +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000 \ + FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x1) +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500 \ + FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x2) +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000 \ + FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x4) +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100 \ + FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x6) +#define AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0 0x100 +#define AIROHA_PCS_HSGMII_P0_DIS_MII_MODE BIT(31) + +/* USXGMII */ +#define AIROHA_PCS_USXGMII_PCS_CTROL_1 0x0 +#define AIROHA_PCS_USXGMII_SPEED_SEL_H BIT(13) +#define AIROHA_PCS_USXGMII_PCS_STUS_1 0x30 +#define AIROHA_PCS_USXGMII_RX_LINK_STUS BIT(12) +#define AIROHA_PCS_USXGMII_PRBS9_PATT_TST_ABILITY BIT(3) +#define AIROHA_PCS_USXGMII_PRBS31_PATT_TST_ABILITY BIT(2) +#define AIROHA_PCS_USXGMII_PCS_BLK_LK BIT(0) +#define AIROHA_PCS_USGMII_VENDOR_DEFINE_116 0x22c +#define AIROHA_PCS_USXGMII_PCS_CTRL_0 0x2c0 +#define AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN BIT(24) +#define AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN BIT(16) +#define AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN BIT(8) +#define AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN BIT(0) +#define AIROHA_PCS_USXGMII_PCS_CTRL_1 0x2c4 +#define AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN BIT(24) +#define AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN BIT(16) +#define AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN BIT(8) +#define AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN BIT(0) +#define AIROHA_PCS_USXGMII_PCS_CTRL_2 0x2c8 +#define AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN BIT(24) +#define AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN BIT(16) +#define AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN BIT(8) +#define AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN BIT(0) +#define AIROHA_PCS_USXGMII_PCS_CTRL_3 0x2cc +#define AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN BIT(24) +#define AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN BIT(16) +#define AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN BIT(8) +#define AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN BIT(0) +#define AIROHA_PCS_USXGMII_PCS_INT_STA_2 0x2d8 +#define AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT BIT(24) +#define AIROHA_PCS_USXGMII_R_TYPE_E_INT BIT(16) +#define AIROHA_PCS_USXGMII_R_TYPE_T_INT BIT(8) +#define AIROHA_PCS_USXGMII_R_TYPE_D_INT BIT(0) +#define AIROHA_PCS_USXGMII_PCS_INT_STA_3 0x2dc +#define AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT BIT(24) +#define AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT BIT(16) +#define AIROHA_PCS_USXGMII_LINK_UP_ST_INT BIT(8) +#define AIROHA_PCS_USXGMII_HI_BER_ST_INT BIT(0) +#define AIROHA_PCS_USXGMII_PCS_CTRL_4 0x2e0 +#define AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN BIT(0) +#define AIROHA_PCS_USXGMII_PCS_INT_STA_4 0x2e4 +#define AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT BIT(0) +#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0 0x2f8 +#define AIROHA_PCS_USXGMII_AN_RESTART BIT(8) +#define AIROHA_PCS_USXGMII_AN_ENABLE BIT(0) +#define AIROHA_PCS_USXGMII_PCS_AN_STATS_0 0x310 +#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE GENMASK(30, 28) +#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_10G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x0) +#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x1) +#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_2_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x2) +#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_1G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x3) +#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_100M FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x4) +#define AIROHA_PCS_USXGMII_PARTNER_ABILITY GENMASK(15, 0) +#define AIROHA_PCS_USXGMII_PCS_AN_STATS_2 0x318 +#define AIROHA_PCS_USXGMII_PCS_AN_COMPLETE BIT(24) +#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6 0x31c +#define AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS BIT(0) +#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7 0x320 +#define AIROHA_PCS_USXGMII_XFI_MODE_TX_SEL BIT(20) +#define AIROHA_PCS_USXGMII_XFI_MODE_RX_SEL BIT(16) +#define AIROHA_PCS_USXGMII_RATE_UPDATE_MODE BIT(12) +#define AIROHA_PCS_USXGMII_MODE GENMASK(10, 8) +#define AIROHA_PCS_USXGMII_MODE_10000 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x0) +#define AIROHA_PCS_USXGMII_MODE_5000 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x1) +#define AIROHA_PCS_USXGMII_MODE_2500 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x2) +#define AIROHA_PCS_USXGMII_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x3) +#define AIROHA_PCS_USXGMII_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x4) +#define AN7583_PCS_USXGMII_RTL_MODIFIED 0x334 +#define AIROHA_PCS_USXGMII_MODIFIED_RX_GB_OUT_VLD BIT(25) + +/* PMA_PHYA */ +#define AIROHA_PCS_ANA_PXP_CMN_EN 0x0 +#define AIROHA_PCS_ANA_CMN_VREFSEL GENMASK(18, 16) +#define AIROHA_PCS_ANA_CMN_VREFSEL_8V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x0) +#define AIROHA_PCS_ANA_CMN_VREFSEL_8_25V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x1) +#define AIROHA_PCS_ANA_CMN_VREFSEL_8_5V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x2) +#define AIROHA_PCS_ANA_CMN_VREFSEL_8_75V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x3) +#define AIROHA_PCS_ANA_CMN_VREFSEL_9V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x4) +#define AIROHA_PCS_ANA_CMN_VREFSEL_9_25V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x5) +#define AIROHA_PCS_ANA_CMN_VREFSEL_9_5V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x6) +#define AIROHA_PCS_ANA_CMN_VREFSEL_9_75V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x7) +#define AIROHA_PCS_ANA_CMN_VREFSEL GENMASK(18, 16) +/* GENMASK(2, 0) input selection from 0 to 7 + * BIT(3) OPAMP and path EN + * BIT(4) Current path measurement + * BIT(5) voltage/current path to PAD + */ +#define AIROHA_PCS_ANA_CMN_MPXSELTOP_DC GENMASK(13, 8) +#define AIROHA_PCS_ANA_CMN_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN 0x4 +#define AIROHA_PCS_ANA_JCPLL_CHP_IOFST GENMASK(29, 24) +#define AIROHA_PCS_ANA_JCPLL_CHP_IBIAS GENMASK(21, 16) +#define AIROHA_PCS_ANA_JCPLL_LPF_SHCK_EN BIT(8) +#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR 0x8 +#define AIROHA_PCS_ANA_JCPLL_LPF_BWR GENMASK(28, 24) +#define AIROHA_PCS_ANA_JCPLL_LPF_BP GENMASK(20, 16) +#define AIROHA_PCS_ANA_JCPLL_LPF_BC GENMASK(12, 8) +#define AIROHA_PCS_ANA_JCPLL_LPF_BR GENMASK(4, 0) +#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC 0xc +#define AIROHA_PCS_ANA_JCPLL_KBAND_DIV GENMASK(26, 24) +#define AIROHA_PCS_ANA_JCPLL_KBAND_CODE GENMASK(23, 16) +#define AIROHA_PCS_ANA_JCPLL_KBAND_OPTION BIT(8) +#define AIROHA_PCS_ANA_JCPLL_LPF_BWC GENMASK(4, 0) +#define AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC 0x10 +#define AIROHA_PCS_ANA_JCPLL_KBAND_KS GENMASK(17, 16) +#define AIROHA_PCS_ANA_JCPLL_KBAND_KF GENMASK(9, 8) +#define AIROHA_PCS_ANA_JCPLL_KBAND_KFC GENMASK(1, 0) +#define AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE 0x14 +#define AIROHA_PCS_ANA_JCPLL_POSTDIV_D5 BIT(24) +#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE GENMASK(1, 0) +#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x0) +#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x1) +#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x2) +#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x3) +#define AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY 0x1c +#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS GENMASK(25, 24) +#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x0) +#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_21 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x1) +#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_19 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x2) +#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_15 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x3) +#define AIROHA_PCS_ANA_JCPLL_SDM_DI_EN BIT(16) +#define AIROHA_PCS_ANA_JCPLL_PLL_RSTB BIT(8) +#define AIROHA_PCS_ANA_JCPLL_RST_DLY GENMASK(2, 0) +#define AIROHA_PCS_ANA_JCPLL_RST_DLY_20_25 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x1) +#define AIROHA_PCS_ANA_JCPLL_RST_DLY_40_50 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x2) +#define AIROHA_PCS_ANA_JCPLL_RST_DLY_80_100 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x3) +#define AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x4) +#define AIROHA_PCS_ANA_JCPLL_RST_DLY_300_400 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x5) +#define AIROHA_PCS_ANA_JCPLL_RST_DLY_600_800 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x6) +#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM 0x20 +#define AIROHA_PCS_ANA_JCPLL_SDM_OUT BIT(24) +#define AIROHA_PCS_ANA_JCPLL_SDM_ORD GENMASK(17, 16) +#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_INT FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x0) +#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_1SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x1) +#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_2SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x2) +#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x3) +#define AIROHA_PCS_ANA_JCPLL_SDM_MODE GENMASK(9, 8) +#define AIROHA_PCS_ANA_JCPLL_SDM_IFM BIT(0) +#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN 0x24 +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF GENMASK(28, 24) +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN GENMASK(18, 16) +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x0) +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x1) +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_6 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x2) +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_8 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x3) +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_10 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x4) +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN BIT(8) +#define AIROHA_PCS_ANA_JCPLL_SDM_HREN BIT(0) +#define AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN 0x28 +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW GENMASK(26, 24) +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_0_5 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x0) +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x1) +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x2) +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x3) +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_8 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x4) +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_16 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x6) +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN BIT(16) +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW GENMASK(26, 24) +#define AIROHA_PCS_ANA_PXP_JCPLL_VCODIV 0x2c +#define AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR GENMASK(26, 24) +#define AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN BIT(16) +#define AIROHA_PCS_ANA_JCPLL_VCO_CFIX GENMASK(9, 8) +#define AIROHA_PCS_ANA_JCPLL_VCODIV GENMASK(1, 0) +#define AIROHA_PCS_ANA_JCPLL_VCODIV_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_VCODIV, 0x0) +#define AIROHA_PCS_ANA_JCPLL_VCODIV_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_VCODIV, 0x1) +#define AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR 0x30 +#define AIROHA_PCS_ANA_JCPLL_SSC_PHASE_INI BIT(17) +#define AIROHA_PCS_ANA_JCPLL_SSC_EN BIT(16) +#define AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L GENMASK(10, 8) +#define AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H GENMASK(5, 3) +#define AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR GENMASK(2, 0) +#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN 0x34 +#define AIROHA_PCS_ANA_JCPLL_SSC_DELTA1 GENMASK(23, 8) +#define AIROHA_PCS_ANA_JCPLL_SSC_TRI_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA 0x38 +#define AIROHA_PCS_ANA_JCPLL_SSC_PERIOD GENMASK(31, 16) +#define AIROHA_PCS_ANA_JCPLL_SSC_DELTA GENMASK(15, 0) +#define AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H 0x48 +#define AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF GENMASK(20, 16) +#define AIROHA_PCS_ANA_JCPLL_SPARE_L GENMASK(15, 8) +#define AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SPARE_L, BIT(5)) +#define AIROHA_PCS_ANA_PXP_JCPLL_FREQ_MEAS_EN 0x4c +#define AIROHA_PCS_ANA_TXPLL_IB_EXT_EN BIT(24) +#define AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS 0x50 +#define AIROHA_PCS_ANA_TXPLL_LPF_BC GENMASK(28, 24) +#define AIROHA_PCS_ANA_TXPLL_LPF_BR GENMASK(20, 16) +#define AIROHA_PCS_ANA_TXPLL_CHP_IOFST GENMASK(13, 8) +#define AIROHA_PCS_ANA_TXPLL_CHP_IBIAS GENMASK(5, 0) +#define AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP 0x54 +#define AIROHA_PCS_ANA_TXPLL_KBAND_OPTION BIT(24) +#define AIROHA_PCS_ANA_TXPLL_LPF_BWC GENMASK(20, 16) +#define AIROHA_PCS_ANA_TXPLL_LPF_BWR GENMASK(12, 8) +#define AIROHA_PCS_ANA_TXPLL_LPF_BP GENMASK(4, 0) +#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE 0x58 +#define AIROHA_PCS_ANA_TXPLL_KBAND_KF GENMASK(25, 24) +#define AIROHA_PCS_ANA_TXPLL_KBAND_KFC GENMASK(17, 16) +#define AIROHA_PCS_ANA_TXPLL_KBAND_DIV GENMASK(10, 8) +#define AIROHA_PCS_ANA_TXPLL_KBAND_CODE GENMASK(7, 0) +#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS 0x5c +#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE GENMASK(17, 16) +#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x0) +#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x1) +#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x2) +#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x3) +#define AIROHA_PCS_ANA_TXPLL_POSTDIV_EN BIT(8) +#define AIROHA_PCS_ANA_TXPLL_KBAND_KS GENMASK(1, 0) +#define AIROHA_PCS_ANA_PXP_TXPLL_PHY_CK1_EN 0x60 +#define AIROHA_PCS_ANA_TXPLL_PHY_CK2_EN BIT(8) +#define AIROHA_PCS_ANA_TXPLL_PHY_CK1_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL 0x64 +#define AIROHA_PCS_ANA_TXPLL_PLL_RSTB BIT(24) +#define AIROHA_PCS_ANA_TXPLL_RST_DLY GENMASK(18, 16) +#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV GENMASK(9, 8) +#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x0) +#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x1) +#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x2) +#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x3) +#define AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL BIT(0) +#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN 0x68 +#define AIROHA_PCS_ANA_TXPLL_SDM_MODE GENMASK(25, 24) +#define AIROHA_PCS_ANA_TXPLL_SDM_IFM BIT(16) +#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS GENMASK(9, 8) +#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x0) +#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_21 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x1) +#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_19 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x2) +#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_15 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x3) +#define AIROHA_PCS_ANA_TXPLL_SDM_DI_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD 0x6c +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_EN BIT(24) +#define AIROHA_PCS_ANA_TXPLL_SDM_HREN BIT(16) +#define AIROHA_PCS_ANA_TXPLL_SDM_OUT BIT(8) +#define AIROHA_PCS_ANA_TXPLL_SDM_ORD GENMASK(1, 0) +#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_INT FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x0) +#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_1SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x1) +#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_2SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x2) +#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x3) +#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN 0x70 +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF GENMASK(12, 8) +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN GENMASK(2, 0) +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x0) +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2_5 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x1) +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x2) +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x3) +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_6 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x4) +#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN 0x74 +#define AIROHA_PCS_ANA_TXPLL_VCO_CFIX GENMASK(25, 24) +#define AIROHA_PCS_ANA_TXPLL_VCODIV GENMASK(17, 16) +#define AIROHA_PCS_ANA_TXPLL_VCODIV_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VCODIV, 0x0) +#define AIROHA_PCS_ANA_TXPLL_VCODIV_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VCODIV, 0x1) +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW GENMASK(10, 8) +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x0) +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x1) +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x2) +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x3) +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_8 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x4) +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_16 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x6) +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN 0x78 +#define AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L GENMASK(29, 27) +#define AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H GENMASK(26, 24) +#define AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR GENMASK(18, 16) +#define AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR GENMASK(10, 8) +#define AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN 0x7c +#define AIROHA_PCS_ANA_TXPLL_SSC_TRI_EN BIT(16) +#define AIROHA_PCS_ANA_TXPLL_SSC_PHASE_INI BIT(8) +#define AIROHA_PCS_ANA_TXPLL_SSC_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1 0x80 +#define AIROHA_PCS_ANA_TXPLL_SSC_DELTA GENMASK(31, 16) +#define AIROHA_PCS_ANA_TXPLL_SSC_DELTA1 GENMASK(15, 0) +#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD 0x84 +#define AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT GENMASK(25, 24) +#define AIROHA_PCS_ANA_TXPLL_LDO_OUT GENMASK(17, 16) +#define AIROHA_PCS_ANA_TXPLL_SSC_PERIOD GENMASK(15, 0) +#define AIROHA_PCS_ANA_PXP_TXPLL_VTP_EN 0x88 +#define AIROHA_PCS_ANA_TXPLL_VTP GENMASK(10, 8) +#define AIROHA_PCS_ANA_TXPLL_VTP_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF 0x94 +#define AIROHA_PCS_ANA_TXPLL_POSTDIV_D256_EN BIT(25) /* 0: 128 1: 256 */ +#define AIROHA_PCS_ANA_TXPLL_VCO_KBAND_MEAS_EN BIT(24) +#define AIROHA_PCS_ANA_TXPLL_FREQ_MEAS_EN BIT(16) +#define AIROHA_PCS_ANA_TXPLL_VREF_SEL BIT(8) +#define AIROHA_PCS_ANA_TXPLL_VREF_SEL_VBG FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VREF_SEL, 0x0) +#define AIROHA_PCS_ANA_TXPLL_VREF_SEL_AVDD FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VREF_SEL, 0x1) +#define AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF GENMASK(4, 0) +#define AN7583_PCS_ANA_PXP_TXPLL_CHP_DOUBLE_EN 0x98 +#define AIROHA_PCS_ANA_TXPLL_SPARE_L BIT(0) /* ICHP_DOUBLE */ +#define AIROHA_PCS_ANA_PXP_PLL_MONCLK_SEL 0xa0 +#define AIROHA_PCS_ANA_TDC_AUTOEN BIT(24) +#define AIROHA_PCS_ANA_PXP_TDC_SYNC_CK_SEL 0xa8 +#define AIROHA_PCS_ANA_PLL_LDO_CKDRV_VSEL GENMASK(17, 16) +#define AIROHA_PCS_ANA_PLL_LDO_CKDRV_EN BIT(8) +#define AIROHA_PCS_ANA_PXP_TX_TXLBRC_EN 0xc0 +#define AIROHA_PCS_ANA_TX_TERMCAL_VREF_L GENMASK(26, 24) +#define AIROHA_PCS_ANA_TX_TERMCAL_VREF_H GENMASK(18, 16) +#define AIROHA_PCS_ANA_PXP_TX_CKLDO_EN 0xc4 +#define AIROHA_PCS_ANA_TX_DMEDGEGEN_EN BIT(24) +#define AIROHA_PCS_ANA_TX_CKLDO_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_TX_TERMCAL_SELPN 0xc8 +#define AIROHA_PCS_ANA_TX_TDC_CK_SEL GENMASK(17, 16) +#define AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL 0xcc +#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE BIT(24) +#define AIROHA_PCS_ANA_RX_PHY_CK_SEL BIT(16) +#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FROM_PR FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_PHY_CK_SEL, 0x0) +#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FROM_DES FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_PHY_CK_SEL, 0x1) +#define AIROHA_PCS_ANA_RX_BUSBIT_SEL_FORCE BIT(8) +#define AIROHA_PCS_ANA_RX_BUSBIT_SEL BIT(0) +#define AIROHA_PCS_ANA_RX_BUSBIT_SEL_8BIT FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_BUSBIT_SEL, 0x0) +#define AIROHA_PCS_ANA_RX_BUSBIT_SEL_16BIT FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_BUSBIT_SEL, 0x1) +#define AIROHA_PCS_ANA_PXP_RX_REV_0 0xd4 +#define AIROHA_PCS_ANA_RX_REV_1 GENMASK(31, 16) +#define AIROHA_PCS_ANA_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28) +#define AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24) +#define AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20) +#define AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK GENMASK(19, 18) +#define AIROHA_PCS_ANA_REV_1_FECUR_PWDB BIT(16) +#define AIROHA_PCS_ANA_RX_REV_0 GENMASK(15, 0) +#define AIROHA_PCS_ANA_REV_0_FE_BUF2_BIAS_TYPE GENMASK(13, 12) +#define AIROHA_PCS_ANA_REV_0_OSCAL_FE_MODE_SET_SEL BIT(11) +#define AIROHA_PCS_ANA_REV_0_FE_EQ_GAIN_MODE_TRAINING BIT(10) +#define AIROHA_PCS_ANA_REV_0_FE_BUF_GAIN_MODE_TRAINING GENMASK(9, 8) +#define AIROHA_PCS_ANA_REV_0_FE_EQ_GAIN_MODE_NORMAL BIT(6) +#define AIROHA_PCS_ANA_REV_0_FE_BUF_GAIN_MODE_NORMAL GENMASK(5, 4) +#define AIROHA_PCS_ANA_REV_0_VOS_PNINV GENMASK(3, 2) +#define AIROHA_PCS_ANA_REV_0_PLEYEBD4 BIT(1) +#define AIROHA_PCS_ANA_REV_0_PLEYE_XOR_MON_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV 0xd8 +#define AIROHA_PCS_ANA_RX_TDC_CK_SEL BIT(24) +#define AIROHA_PCS_ANA_RX_PHYCK_RSTB BIT(16) +#define AIROHA_PCS_ANA_RX_PHYCK_SEL GENMASK(9, 8) +#define AIROHA_PCS_ANA_RX_PHYCK_DIV GENMASK(7, 0) +#define AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV 0xdc +#define AIROHA_PCS_ANA_CDR_PD_EDGE_DIS BIT(8) +#define AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV BIT(0) +#define AIROHA_PCS_ANA_PXP_CDR_LPF_BOT_LIM 0xe0 +#define AIROHA_PCS_ANA_CDR_LPF_BOT_LIM GENMASK(18, 0) +#define AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO 0xe8 +#define AIROHA_PCS_ANA_CDR_LPF_TOP_LIM GENMASK(26, 8) +#define AIROHA_PCS_ANA_CDR_LPF_RATIO GENMASK(1, 0) +#define AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE 0xf4 +#define AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF BIT(24) +#define AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC 0xf8 +#define AIROHA_PCS_ANA_CDR_PR_KBAND_DIV GENMASK(26, 24) +#define AIROHA_PCS_ANA_CDR_PR_BETA_SEL GENMASK(19, 16) +#define AIROHA_PCS_ANA_CDR_PR_VCOADC_OS GENMASK(11, 8) +#define AIROHA_PCS_ANA_CDR_PR_BETA_DAC GENMASK(6, 0) +#define AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL 0xfc +#define AIROHA_PCS_ANA_CDR_PR_FBKSEL GENMASK(25, 24) +#define AIROHA_PCS_ANA_CDR_PR_DAC_BAND GENMASK(20, 16) +#define AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL GENMASK(10, 8) +#define AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL GENMASK(2, 0) +#define AIROHA_PCS_ANA_PXP_CDR_PR_CKREF_DIV 0x100 +#define AIROHA_PCS_ANA_CDR_PR_RSTB_BYPASS BIT(16) +#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV GENMASK(1, 0) +#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV, 0x0) +#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV, 0x1) +#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV, 0x2) +#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV_X FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV, 0x3) +#define AIROHA_PCS_ANA_PXP_CDR_PR_TDC_REF_SEL 0x108 +#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1 GENMASK(25, 24) +#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1, 0x0) +#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1, 0x1) +#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1, 0x2) +#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1_X FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1, 0x3) +#define AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN 0x10c +#define AIROHA_PCS_ANA_RX_DAC_MON GENMASK(28, 24) +#define AIROHA_PCS_ANA_CDR_PR_CAP_EN BIT(19) +#define AIROHA_PCS_ANA_CDR_BUF_IN_SR GENMASK(18, 16) +#define AIROHA_PCS_ANA_CDR_PR_XFICK_EN BIT(2) +#define AIROHA_PCS_ANA_CDR_PR_MONDPI_EN BIT(1) +#define AIROHA_PCS_ANA_CDR_PR_MONDPR_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_RX_DAC_RANGE 0x110 +#define AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL GENMASK(25, 24) +#define AIROHA_PCS_ANA_RX_DAC_RANGE_EYE GENMASK(9, 8) +#define AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH 0x114 +#define AIROHA_PCS_ANA_RX_FE_50OHMS_SEL GENMASK(25, 24) +#define AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL GENMASK(20, 16) +#define AIROHA_PCS_ANA_RX_SIGDET_PEAK GENMASK(9, 8) +#define AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN 0x118 +#define AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN BIT(24) +#define AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN BIT(16) +#define AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN BIT(8) +#define AIROHA_PCS_ANA_RX_FE_EQ_HZEN BIT(0) +#define AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB 0x11c +#define AIROHA_PCS_ANA_FE_VCM_GEN_PWDB BIT(0) +#define AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW 0x120 +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE GENMASK(17, 8) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(0)) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(1)) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(2)) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(3)) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(4)) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(5)) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(6)) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(7)) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(8)) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(9)) +#define AIROHA_PCS_ANA_PXP_AEQ_CFORCE 0x13c +#define AIROHA_PCS_ANA_AEQ_OFORCE GENMASK(19, 8) +#define AIROHA_PCS_ANA_AEQ_OFORCE_SAOS FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(0)) +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP1 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(1)) +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP2 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(2)) +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP3 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(3)) +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP4 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(4)) +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP5 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(5)) +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP6 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(6)) +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP7 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(7)) +#define AIROHA_PCS_ANA_AEQ_OFORCE_VGA FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(8)) +#define AIROHA_PCS_ANA_AEQ_OFORCE_CTLE FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(9)) +#define AIROHA_PCS_ANA_AEQ_OFORCE_ATT FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(10)) +#define AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB 0x144 +#define AIROHA_PCS_ANA_RX_DAC_D0_BYPASS_AEQ BIT(24) +#define AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ 0x148 +#define AIROHA_PCS_ANA_RX_DAC_EYE_BYPASS_AEQ BIT(24) +#define AIROHA_PCS_ANA_RX_DAC_E1_BYPASS_AEQ BIT(16) +#define AIROHA_PCS_ANA_RX_DAC_E0_BYPASS_AEQ BIT(8) +#define AIROHA_PCS_ANA_RX_DAC_D1_BYPASS_AEQ BIT(0) + +/* PMA_PHYD */ +#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0 0x0 +#define AIROHA_PCS_PMA_SW_LCPLL_EN BIT(24) +#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1 0x4 +#define AIROHA_PCS_PMA_LCPLL_CK_STB_TIMER GENMASK(31, 24) +#define AIROHA_PCS_PMA_LCPLL_PCW_MAN_LOAD_TIMER GENMASK(23, 16) +#define AIROHA_PCS_PMA_LCPLL_EN_TIMER GENMASK(15, 8) +#define AIROHA_PCS_PMA_LCPLL_MAN_PWDB BIT(0) +#define AIROHA_PCS_PMA_LCPLL_TDC_PW_0 0x10 +#define AIROHA_PCS_PMA_LCPLL_TDC_DIG_PWDB BIT(0) +#define AIROHA_PCS_PMA_LCPLL_TDC_PW_5 0x24 +#define AIROHA_PCS_PMA_LCPLL_TDC_SYNC_IN_MODE BIT(24) +#define AIROHA_PCS_PMA_LCPLL_AUTOK_TDC BIT(16) +#define AIROHA_PCS_PMA_LCPLL_TDC_FLT_0 0x28 +#define AIROHA_PCS_PMA_LCPLL_KI GENMASK(10, 8) +#define AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC GENMASK(1, 0) +#define AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC_32 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC, 0x0) +#define AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC_16 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC, 0x1) +#define AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC, 0x2) +#define AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC, 0x3) +#define AIROHA_PCS_PMA_LCPLL_TDC_FLT_1 0x2c +#define AIROHA_PCS_PMA_LCPLL_A_TDC GENMASK(11, 8) +#define AIROHA_PCS_PMA_LCPLL_GPON_SEL BIT(0) +#define AIROHA_PCS_PMA_LCPLL_GPON_SEL_FROM_EPON FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_GPON_SEL, 0x0) +#define AIROHA_PCS_PMA_LCPLL_GPON_SEL_FROM_GPON FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_GPON_SEL, 0x1) +#define AIROHA_PCS_PMA_LCPLL_TDC_FLT_3 0x34 +#define AIROHA_PCS_PMA_LCPLL_NCPO_LOAD BIT(8) +#define AIROHA_PCS_PMA_LCPLL_NCPO_SHIFT GENMASK(1, 0) +#define AIROHA_PCS_PMA_LCPLL_TDC_FLT_5 0x3c +#define AIROHA_PCS_PMA_LCPLL_TDC_AUTOPW_NCPO BIT(16) +#define AIROHA_PCS_PMA_LCPLL_TDC_FLT_6 0x40 +#define AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY GENMASK(9, 8) +#define AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY_SEL FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY, 0x0) +#define AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY_SEL_D1 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY, 0x1) +#define AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY_SEL_D2 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY, 0x2) +#define AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY_SEL_D3 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY, 0x3) +#define AIROHA_PCS_PMA_LCPLL_TDC_PCW_1 0x48 +#define AIROHA_PCS_PMA_LCPLL_PON_HRDDS_PCW_NCPO_GPON GENMASK(30, 0) +#define AIROHA_PCS_PMA_LCPLL_TDC_PCW_2 0x4c +#define AIROHA_PCS_PMA_LCPLL_PON_HRDDS_PCW_NCPO_EPON GENMASK(30, 0) +#define AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_0 0x68 +#define AIROHA_PCS_PMA_X_MAX GENMASK(26, 16) +#define AIROHA_PCS_PMA_X_MIN GENMASK(10, 0) +#define AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_1 0x6c +#define AIROHA_PCS_PMA_INDEX_MODE BIT(16) +#define AIROHA_PCS_PMA_Y_MAX GENMASK(14, 8) +#define AIROHA_PCS_PMA_Y_MIN GENMASK(6, 0) +#define AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_2 0x70 +#define AIROHA_PCS_PMA_EYEDUR GENMASK(19, 0) +#define AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_3 0x74 +#define AIROHA_PCS_PMA_EYE_NEXTPTS BIT(16) +#define AIROHA_PCS_PMA_EYE_NEXTPTS_TOGGLE BIT(8) +#define AIROHA_PCS_PMA_EYE_NEXTPTS_SEL BIT(0) +#define AIROHA_PCS_PMA_RX_EYE_TOP_EYEOPENING_CTRL_0 0x78 +#define AIROHA_PCS_PMA_EYECNT_VTH GENMASK(15, 8) +#define AIROHA_PCS_PMA_EYECNT_HTH GENMASK(7, 0) +#define AIROHA_PCS_PMA_RX_EYE_TOP_EYEOPENING_CTRL_1 0x7c +#define AIROHA_PCS_PMA_EO_VTH GENMASK(23, 16) +#define AIROHA_PCS_PMA_EO_HTH GENMASK(10, 0) +#define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_0 0x80 +#define AIROHA_PCS_PMA_EYE_MASK GENMASK(31, 24) +#define AIROHA_PCS_PMA_CNTFOREVER BIT(16) +#define AIROHA_PCS_PMA_CNTLEN GENMASK(9, 0) +#define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_1 0x84 +#define AIROHA_PCS_PMA_FORCE_EYEDUR_INIT_B BIT(24) +#define AIROHA_PCS_PMA_FORCE_EYEDUR_EN BIT(16) +#define AIROHA_PCS_PMA_DISB_EYEDUR_INIT_B BIT(8) +#define AIROHA_PCS_PMA_DISB_EYEDUR_EN BIT(0) +#define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2 0x88 +#define AIROHA_PCS_PMA_DATA_SHIFT BIT(8) +#define AIROHA_PCS_PMA_EYECNT_FAST BIT(0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0 0x8c +#define AIROHA_PCS_PMA_RX_OS_START GENMASK(23, 8) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT GENMASK(2, 0) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_05 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x0) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x1) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_2 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x2) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x3) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x4) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_1_6 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x5) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_3_2 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x6) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_6_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x7) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1 0x90 +#define AIROHA_PCS_PMA_RX_PICAL_END GENMASK(31, 16) +#define AIROHA_PCS_PMA_RX_PICAL_START GENMASK(15, 0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2 0x94 +#define AIROHA_PCS_PMA_RX_PDOS_END GENMASK(31, 16) +#define AIROHA_PCS_PMA_RX_PDOS_START GENMASK(15, 0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3 0x98 +#define AIROHA_PCS_PMA_RX_FEOS_END GENMASK(31, 16) +#define AIROHA_PCS_PMA_RX_FEOS_START GENMASK(15, 0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4 0x9c +#define AIROHA_PCS_PMA_RX_SDCAL_END GENMASK(31, 16) +#define AIROHA_PCS_PMA_RX_SDCAL_START GENMASK(15, 0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5 0x100 +#define AIROHA_PCS_PMA_RX_RDY GENMASK(31, 16) +#define AIROHA_PCS_PMA_RX_BLWC_RDY_EN GENMASK(15, 0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6 0x104 +#define AIROHA_PCS_PMA_RX_OS_END GENMASK(15, 0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_0 0x108 +#define AIROHA_PCS_PMA_DISB_RX_FEOS_EN BIT(24) +#define AIROHA_PCS_PMA_DISB_RX_PDOS_EN BIT(16) +#define AIROHA_PCS_PMA_DISB_RX_PICAL_EN BIT(8) +#define AIROHA_PCS_PMA_DISB_RX_OS_EN BIT(0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1 0x10c +#define AIROHA_PCS_PMA_DISB_RX_RDY BIT(24) +#define AIROHA_PCS_PMA_DISB_RX_BLWC_EN BIT(16) +#define AIROHA_PCS_PMA_DISB_RX_OS_RDY BIT(8) +#define AIROHA_PCS_PMA_DISB_RX_SDCAL_EN BIT(0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_0 0x110 +#define AIROHA_PCS_PMA_FORCE_RX_FEOS_EN BIT(24) +#define AIROHA_PCS_PMA_FORCE_RX_PDOS_EN BIT(16) +#define AIROHA_PCS_PMA_FORCE_RX_PICAL_EN BIT(8) +#define AIROHA_PCS_PMA_FORCE_RX_OS_EN BIT(0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1 0x114 +#define AIROHA_PCS_PMA_FORCE_RX_RDY BIT(24) +#define AIROHA_PCS_PMA_FORCE_RX_BLWC_EN BIT(16) +#define AIROHA_PCS_PMA_FORCE_RX_OS_RDY BIT(8) +#define AIROHA_PCS_PMA_FORCE_RX_SDCAL_EN BIT(0) +#define AIROHA_PCS_PMA_PHY_EQ_CTRL_0 0x118 +#define AIROHA_PCS_PMA_VEO_MASK GENMASK(31, 24) +#define AIROHA_PCS_PMA_HEO_MASK GENMASK(18, 8) +#define AIROHA_PCS_PMA_EQ_EN_DELAY GENMASK(7, 0) +#define AIROHA_PCS_PMA_PHY_EQ_CTRL_1 0x11c +#define AIROHA_PCS_PMA_B_ZERO_SEL BIT(24) +#define AIROHA_PCS_PMA_HEO_EMPHASIS BIT(16) +#define AIROHA_PCS_PMA_A_MGAIN BIT(8) +#define AIROHA_PCS_PMA_A_LGAIN BIT(0) +#define AIROHA_PCS_PMA_PHY_EQ_CTRL_2 0x120 +#define AIROHA_PCS_PMA_EQ_DEBUG_SEL GENMASK(17, 16) +#define AIROHA_PCS_PMA_FOM_NUM_ORDER GENMASK(12, 8) +#define AIROHA_PCS_PMA_A_SEL GENMASK(1, 0) +#define AIROHA_PCS_PMA_SS_RX_FEOS 0x144 +#define AIROHA_PCS_PMA_EQ_FORCE_BLWC_FREEZE BIT(8) +#define AIROHA_PCS_PMA_LFSEL GENMASK(7, 0) +#define AIROHA_PCS_PMA_SS_RX_BLWC 0x148 +#define AIROHA_PCS_PMA_EQ_BLWC_CNT_BOT_LIM GENMASK(29, 23) +#define AIROHA_PCS_PMA_EQ_BLWC_CNT_TOP_LIM GENMASK(22, 16) +#define AIROHA_PCS_PMA_EQ_BLWC_GAIN GENMASK(11, 8) +#define AIROHA_PCS_PMA_EQ_BLWC_POL BIT(0) +#define AIROHA_PCS_PMA_EQ_BLWC_POL_NORMAL FIELD_PREP_CONST(AIROHA_PCS_PMA_EQ_BLWC_POL, 0x0) +#define AIROHA_PCS_PMA_EQ_BLWC_POL_INVERSION FIELD_PREP_CONST(AIROHA_PCS_PMA_EQ_BLWC_POL, 0x1) +#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_1 0x14c +#define AIROHA_PCS_PMA_UNLOCK_CYCLECNT GENMASK(31, 16) +#define AIROHA_PCS_PMA_LOCK_CYCLECNT GENMASK(15, 0) +#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_2 0x150 +#define AIROHA_PCS_PMA_LOCK_TARGET_END GENMASK(31, 16) +#define AIROHA_PCS_PMA_LOCK_TARGET_BEG GENMASK(15, 0) +#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_3 0x154 +#define AIROHA_PCS_PMA_UNLOCK_TARGET_END GENMASK(31, 16) +#define AIROHA_PCS_PMA_UNLOCK_TARGET_BEG GENMASK(15, 0) +#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_4 0x158 +#define AIROHA_PCS_PMA_LOCK_UNLOCKTH GENMASK(15, 12) +#define AIROHA_PCS_PMA_LOCK_LOCKTH GENMASK(11, 8) +#define AIROHA_PCS_PMA_FREQLOCK_DET_EN GENMASK(2, 0) +#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x0) +#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x1) +#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_WAIT FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x2) +#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x3) +#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_RX_STATE FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x7) +#define AIROHA_PCS_PMA_RX_PI_CAL 0x15c +#define AIROHA_PCS_PMA_KPGAIN GENMASK(10, 8) +#define AIROHA_PCS_PMA_RX_CAL1 0x160 +#define AIROHA_PCS_PMA_CAL_CYC GENMASK(25, 24) +#define AIROHA_PCS_PMA_CAL_CYC_63 FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_CYC, 0x0) +#define AIROHA_PCS_PMA_CAL_CYC_15 FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_CYC, 0x1) +#define AIROHA_PCS_PMA_CAL_CYC_31 FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_CYC, 0x2) +#define AIROHA_PCS_PMA_CAL_CYC_127 FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_CYC, 0x3) +#define AIROHA_PCS_PMA_CAL_STB GENMASK(17, 16) +#define AIROHA_PCS_PMA_CAL_STB_5US FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_STB, 0x0) +#define AIROHA_PCS_PMA_CAL_STB_8US FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_STB, 0x1) +#define AIROHA_PCS_PMA_CAL_STB_16US FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_STB, 0x2) +#define AIROHA_PCS_PMA_CAL_STB_32US FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_STB, 0x3) +#define AIROHA_PCS_PMA_CAL_1US_SET GENMASK(15, 8) +#define AIROHA_PCS_PMA_SIM_FAST_EN BIT(0) +#define AIROHA_PCS_PMA_RX_CAL2 0x164 +#define AIROHA_PCS_PMA_CAL_CYC_TIME GENMASK(17, 16) +#define AIROHA_PCS_PMA_CAL_OUT_OS GENMASK(11, 8) +#define AIROHA_PCS_PMA_CAL_OS_PULSE BIT(0) +#define AIROHA_PCS_PMA_SS_RX_SIGDET_1 0x16c +#define AIROHA_PCS_PMA_SIGDET_EN BIT(0) +#define AIROHA_PCS_PMA_RX_FLL_0 0x170 +#define AIROHA_PCS_PMA_KBAND_KFC GENMASK(25, 24) +#define AIROHA_PCS_PMA_KBAND_KFC_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_KFC, 0x0) +#define AIROHA_PCS_PMA_KBAND_KFC_16 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_KFC, 0x1) +#define AIROHA_PCS_PMA_KBAND_KFC_32 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_KFC, 0x2) +#define AIROHA_PCS_PMA_KBAND_KFC_64 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_KFC, 0x3) +#define AIROHA_PCS_PMA_FPKDIV GENMASK(18, 8) +#define AIROHA_PCS_PMA_KBAND_PREDIV GENMASK(2, 0) +#define AIROHA_PCS_PMA_KBAND_PREDIV_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_PREDIV, 0x0) +#define AIROHA_PCS_PMA_KBAND_PREDIV_2 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_PREDIV, 0x1) +#define AIROHA_PCS_PMA_KBAND_PREDIV_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_PREDIV, 0x2) +#define AIROHA_PCS_PMA_KBAND_PREDIV_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_PREDIV, 0x3) +#define AIROHA_PCS_PMA_RX_FLL_1 0x174 +#define AIROHA_PCS_PMA_SYMBOL_WD GENMASK(26, 24) +#define AIROHA_PCS_PMA_SETTLE_TIME_SEL GENMASK(18, 16) +#define AIROHA_PCS_PMA_LPATH_IDAC GENMASK(10, 0) +#define AIROHA_PCS_PMA_RX_FLL_2 0x178 +#define AIROHA_PCS_PMA_CK_RATE GENMASK(18, 16) +#define AIROHA_PCS_PMA_CK_RATE_20 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x0) +#define AIROHA_PCS_PMA_CK_RATE_10 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x1) +#define AIROHA_PCS_PMA_CK_RATE_5 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x2) +#define AIROHA_PCS_PMA_AMP GENMASK(10, 8) +#define AIROHA_PCS_PMA_PRBS_SEL GENMASK(2, 0) +#define AIROHA_PCS_PMA_RX_FLL_5 0x184 +#define AIROHA_PCS_PMA_FLL_IDAC_MIN GENMASK(26, 16) +#define AIROHA_PCS_PMA_FLL_IDAC_MAX GENMASK(10, 0) +#define AIROHA_PCS_PMA_RX_FLL_6 0x188 +#define AIROHA_PCS_PMA_LNX_SW_FLL_4_LATCH_EN BIT(24) +#define AIROHA_PCS_PMA_LNX_SW_FLL_3_LATCH_EN BIT(16) +#define AIROHA_PCS_PMA_LNX_SW_FLL_2_LATCH_EN BIT(8) +#define AIROHA_PCS_PMA_LNX_SW_FLL_1_LATCH_EN BIT(0) +#define AIROHA_PCS_PMA_RX_FLL_B 0x19c +#define AIROHA_PCS_PMA_LOAD_EN BIT(0) +#define AIROHA_PCS_PMA_RX_PDOS_CTRL_0 0x200 +#define AIROHA_PCS_PMA_SAP_SEL GENMASK(18, 16) +#define AIROHA_PCS_PMA_SAP_SEL_SHIFT_6 FIELD_PREP_CONST(AIROHA_PCS_PMA_SAP_SEL, 0x0) +#define AIROHA_PCS_PMA_SAP_SEL_SHIFT_7 FIELD_PREP_CONST(AIROHA_PCS_PMA_SAP_SEL, 0x1) +#define AIROHA_PCS_PMA_SAP_SEL_SHIFT_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_SAP_SEL, 0x2) +#define AIROHA_PCS_PMA_SAP_SEL_SHIFT_9 FIELD_PREP_CONST(AIROHA_PCS_PMA_SAP_SEL, 0x3) +#define AIROHA_PCS_PMA_SAP_SEL_SHIFT_10 FIELD_PREP_CONST(AIROHA_PCS_PMA_SAP_SEL, 0x4) +#define AIROHA_PCS_PMA_EYE_BLWC_ADD BIT(8) +#define AIROHA_PCS_PMA_DATA_BLWC_ADD BIT(0) +#define AIROHA_PCS_PMA_RX_RESET_0 0x204 +#define AIROHA_PCS_PMA_CAL_RST_B BIT(24) +#define AIROHA_PCS_PMA_EQ_PI_CAL_RST_B BIT(16) +#define AIROHA_PCS_PMA_FEOS_RST_B BIT(8) +#define AIROHA_PCS_PMA_RX_RESET_1 0x208 +#define AIROHA_PCS_PMA_SIGDET_RST_B BIT(8) +#define AIROHA_PCS_PMA_PDOS_RST_B BIT(0) +#define AIROHA_PCS_PMA_RX_DEBUG_0 0x20c +#define AIROHA_PCS_PMA_RO_TOGGLE BIT(24) +#define AIROHA_PCS_PMA_BISTCTL_CONTROL 0x210 +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL GENMASK(4, 0) +/* AIROHA_PCS_PMA_BISTCTL_PAT_SEL_ALL_0 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x0) */ +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS7 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x1) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS9 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x2) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS15 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x3) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS23 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x4) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS31 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x5) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_HFTP FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x6) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_MFTP FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x7) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x8) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_5_LFTP FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x9) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_6 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xa) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_7 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xb) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_8_LFTP FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xc) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_9 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xd) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_10 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xe) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_11 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xf) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PROG_80 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x10) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_ALL_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x11) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_ALL_0 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x12) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS11 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x13) +#define AIROHA_PCS_PMA_BISTCTL_ALIGN_PAT 0x214 +#define AIROHA_PCS_PMA_BISTCTL_POLLUTION 0x220 +#define AIROHA_PCS_PMA_BIST_TX_DATA_POLLUTION_LATCH BIT(16) +#define AIROHA_PCS_PMA_BISTCTL_PRBS_INITIAL_SEED 0x224 +#define AIROHA_PCS_PMA_BISTCTL_PRBS_FAIL_THRESHOLD 0x230 +#define AIROHA_PCS_PMA_BISTCTL_PRBS_FAIL_THRESHOLD_MASK GENMASK(15, 0) +#define AIROHA_PCS_PMA_RX_TORGS_DEBUG_2 0x23c +#define AIROHA_PCS_PMA_PI_CAL_DATA_OUT GENMASK(22, 16) +#define AIROHA_PCS_PMA_RX_TORGS_DEBUG_5 0x248 +#define AIROHA_PCS_PMA_VEO_RDY BIT(24) +#define AIROHA_PCS_PMA_HEO_RDY BIT(16) +#define AIROHA_PCS_PMA_RX_TORGS_DEBUG_9 0x258 +#define AIROHA_PCS_PMA_EO_Y_DONE BIT(24) +#define AIROHA_PCS_PMA_EO_X_DONE BIT(16) +#define AIROHA_PCS_PMA_RX_TORGS_DEBUG_10 0x25c +#define AIROHA_PCS_PMA_EYE_EL GENMASK(26, 16) +#define AIROHA_PCS_PMA_EYE_ER GENMASK(10, 0) +#define AIROHA_PCS_PMA_TX_RST_B 0x260 +#define AIROHA_PCS_PMA_TXCALIB_RST_B BIT(8) +#define AIROHA_PCS_PMA_TX_TOP_RST_B BIT(0) +#define AIROHA_PCS_PMA_TX_CALIB_0 0x264 +#define AIROHA_PCS_PMA_TXCALIB_FORCE_TERMP_SEL GENMASK(25, 24) +#define AIROHA_PCS_PMA_TXCALIB_FORCE_TERMP_SEL_EN BIT(16) +#define AIROHA_PCS_PMA_RX_TORGS_DEBUG_11 0x290 +#define AIROHA_PCS_PMA_EYE_EB GENMASK(14, 8) +#define AIROHA_PCS_PMA_EYE_EU GENMASK(6, 0) +#define AIROHA_PCS_PMA_RX_FORCE_MODE_0 0x294 +#define AIROHA_PCS_PMA_FORCE_DA_XPON_CDR_LPF_RSTB BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_XPON_RX_FE_GAIN_CTRL GENMASK(1, 0) +#define AIROHA_PCS_PMA_RX_DISB_MODE_0 0x300 +#define AIROHA_PCS_PMA_DISB_DA_XPON_CDR_LPF_RSTB BIT(24) +#define AIROHA_PCS_PMA_DISB_DA_XPON_RX_FE_GAIN_CTRL BIT(0) +#define AIROHA_PCS_PMA_RX_DISB_MODE_1 0x304 +#define AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_E0 BIT(24) +#define AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_D1 BIT(16) +#define AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_D0 BIT(8) +#define AIROHA_PCS_PMA_RX_DISB_MODE_2 0x308 +#define AIROHA_PCS_PMA_DISB_DA_XPON_CDR_PR_PIEYE BIT(24) +#define AIROHA_PCS_PMA_DISB_DA_XPON_RX_FE_VOS BIT(16) +#define AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_EYE BIT(8) +#define AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_E1 BIT(0) +#define AIROHA_PCS_PMA_RX_FORCE_MODE_3 0x30c +#define AIROHA_PCS_PMA_FORCE_EQ_PI_CAL_RDY BIT(0) +#define AIROHA_PCS_PMA_RX_FORCE_MODE_6 0x318 +#define AIROHA_PCS_PMA_FORCE_RX_OR_PICAL_EN BIT(8) +#define AIROHA_PCS_PMA_FORCE_EYECNT_RDY BIT(0) +#define AIROHA_PCS_PMA_RX_DISB_MODE_3 0x31c +#define AIROHA_PCS_PMA_DISB_RQ_PI_CAL_RDY BIT(0) +#define AIROHA_PCS_PMA_RX_DISB_MODE_4 0x320 +#define AIROHA_PCS_PMA_DISB_BLWC_OFFSET BIT(24) +#define AIROHA_PCS_PMA_RX_DISB_MODE_5 0x324 +#define AIROHA_PCS_PMA_DISB_RX_OR_PICAL_EN BIT(24) +#define AIROHA_PCS_PMA_DISB_EYECNT_RDY BIT(16) +#define AIROHA_PCS_PMA_RX_FORCE_MODE_7 0x328 +#define AIROHA_PCS_PMA_FORCE_PDOS_RX_RST_B BIT(16) +#define AIROHA_PCS_PMA_FORCE_RX_AND_PICAL_RSTB BIT(8) +#define AIROHA_PCS_PMA_FORCE_REF_AND_PICAL_RSTB BIT(0) +#define AIROHA_PCS_PMA_RX_FORCE_MODE_8 0x32c +#define AIROHA_PCS_PMA_FORCE_EYECNT_RX_RST_B BIT(24) +#define AIROHA_PCS_PMA_FORCE_FEOS_RX_RST_B BIT(16) +#define AIROHA_PCS_PMA_FORCE_SDCAL_REF_RST_B BIT(8) +#define AIROHA_PCS_PMA_FORCE_BLWC_RX_RST_B BIT(0) +#define AIROHA_PCS_PMA_RX_FORCE_MODE_9 0x330 +#define AIROHA_PCS_PMA_FORCE_EYE_TOP_EN BIT(16) +#define AIROHA_PCS_PMA_FORCE_EYE_RESET_PLU_O BIT(8) +#define AIROHA_PCS_PMA_FORCE_FBCK_LOCK BIT(0) +#define AIROHA_PCS_PMA_RX_DISB_MODE_6 0x334 +#define AIROHA_PCS_PMA_DISB_PDOS_RX_RST_B BIT(16) +#define AIROHA_PCS_PMA_DISB_RX_AND_PICAL_RSTB BIT(8) +#define AIROHA_PCS_PMA_DISB_REF_AND_PICAL_RSTB BIT(0) +#define AIROHA_PCS_PMA_RX_DISB_MODE_7 0x338 +#define AIROHA_PCS_PMA_DISB_EYECNT_RX_RST_B BIT(24) +#define AIROHA_PCS_PMA_DISB_FEOS_RX_RST_B BIT(16) +#define AIROHA_PCS_PMA_DISB_SDCAL_REF_RST_B BIT(8) +#define AIROHA_PCS_PMA_DISB_BLWC_RX_RST_B BIT(0) +#define AIROHA_PCS_PMA_RX_DISB_MODE_8 0x33c +#define AIROHA_PCS_PMA_DISB_EYE_TOP_EN BIT(16) +#define AIROHA_PCS_PMA_DISB_EYE_RESET_PLU_O BIT(8) +#define AIROHA_PCS_PMA_DISB_FBCK_LOCK BIT(0) +#define AIROHA_PCS_PMA_SS_BIST_1 0x344 +#define AIROHA_PCS_PMA_LNX_BISTCTL_BIT_ERROR_RST_SEL BIT(24) +#define AIROHA_PCS_PMA_ANLT_PX_LNX_LT_LOS BIT(0) +#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0 0x34c +#define AIROHA_PCS_PMA_XPON_CDR_PD_PWDB BIT(24) +#define AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB BIT(16) +#define AIROHA_PCS_PMA_XPON_CDR_PW_PWDB BIT(8) +#define AIROHA_PCS_PMA_XPON_RX_FE_PWDB BIT(0) +#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1 0x350 +#define AIROHA_PCS_PMA_RX_SIDGET_PWDB BIT(0) +#define AIROHA_PCS_PMA_DIG_RESERVE_0 0x360 +#define AIROHA_PCS_PMA_XPON_RX_RESERVED_1 0x374 +#define AIROHA_PCS_PMA_XPON_RX_RATE_CTRL GENMASK(1, 0) +#define AIROHA_PCS_PMA_RX_SYS_EN_SEL_0 0x38c +#define AIROHA_PCS_PMA_RX_SYS_EN_SEL GENMASK(1, 0) +#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_0 0x390 +#define AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT GENMASK(15, 0) +#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_1 0x394 +#define AIROHA_PCS_PMA_PLL_LOCK_TARGET_END GENMASK(31, 16) +#define AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG GENMASK(15, 0) +#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_3 0x39c +#define AIROHA_PCS_PMA_PLL_LOCK_LOCKTH GENMASK(11, 8) +#define AIROHA_PCS_PMA_ADD_CLKPATH_RST_0 0x410 +#define AIROHA_PCS_PMA_CLKPATH_RSTB_CK BIT(8) +#define AIROHA_PCS_PMA_CLKPATH_RST_EN BIT(0) +#define AIROHA_PCS_PMA_ADD_XPON_MODE_1 0x414 +#define AIROHA_PCS_PMA_TX_BIST_GEN_EN BIT(16) +#define AIROHA_PCS_PMA_R2T_MODE BIT(8) +#define AIROHA_PCS_PMA_ADD_RX2ANA_1 0x424 +#define AIROHA_PCS_PMA_RX_DAC_E0 GENMASK(30, 24) +#define AIROHA_PCS_PMA_RX_DAC_D1 GENMASK(22, 16) +#define AIROHA_PCS_PMA_RX_DAC_D0 GENMASK(14, 8) +#define AIROHA_PCS_PMA_RX_DAC_EYE GENMASK(6, 0) +#define AIROHA_PCS_PMA_ADD_RX2ANA_2 0x428 +#define AIROHA_PCS_PMA_RX_FEOS_OUT GENMASK(13, 8) +#define AIROHA_PCS_PMA_RX_DAC_E1 GENMASK(6, 0) +#define AIROHA_PCS_PMA_PON_TX_COUNTER_0 0x440 +#define AIROHA_PCS_PMA_TXCALIB_5US GENMASK(31, 16) +#define AIROHA_PCS_PMA_TXCALIB_50US GENMASK(15, 0) +#define AIROHA_PCS_PMA_PON_TX_COUNTER_1 0x444 +#define AIROHA_PCS_PMA_TX_HSDATA_EN_WAIT GENMASK(31, 16) +#define AIROHA_PCS_PMA_TX_CK_EN_WAIT GENMASK(15, 0) +#define AIROHA_PCS_PMA_PON_TX_COUNTER_2 0x448 +#define AIROHA_PCS_PMA_TX_SERDES_RDY_WAIT GENMASK(31, 16) +#define AIROHA_PCS_PMA_TX_POWER_ON_WAIT GENMASK(15, 0) +#define AIROHA_PCS_PMA_SW_RST_SET 0x460 +#define AIROHA_PCS_PMA_SW_XFI_RXMAC_RST_N BIT(17) +#define AIROHA_PCS_PMA_SW_XFI_TXMAC_RST_N BIT(16) +#define AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N BIT(11) +#define AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N BIT(10) +#define AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N BIT(9) +#define AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N BIT(8) +#define AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N BIT(7) +#define AIROHA_PCS_PMA_SW_TX_FIFO_RST_N BIT(6) +#define AIROHA_PCS_PMA_SW_REF_RST_N BIT(5) +#define AIROHA_PCS_PMA_SW_ALLPCS_RST_N BIT(4) +#define AIROHA_PCS_PMA_SW_PMA_RST_N BIT(3) +#define AIROHA_PCS_PMA_SW_TX_RST_N BIT(2) +#define AIROHA_PCS_PMA_SW_RX_RST_N BIT(1) +#define AIROHA_PCS_PMA_SW_RX_FIFO_RST_N BIT(0) +#define AIROHA_PCS_PMA_TX_DLY_CTRL 0x468 +#define AIROHA_PCS_PMA_OUTBEN_DATA_MODE GENMASK(30, 28) +#define AIROHA_PCS_PMA_TX_BEN_EXTEN_FTUNE GENMASK(23, 16) +#define AIROHA_PCS_PMA_TX_DLY_BEN_FTUNE GENMASK(14, 8) +#define AIROHA_PCS_PMA_TX_DLY_DATA_FTUNE GENMASK(6, 0) +#define AIROHA_PCS_PMA_XPON_INT_EN_3 0x474 +#define AIROHA_PCS_PMA_RX_SIGDET_INT_EN BIT(16) +#define AIROHA_PCS_PMA_XPON_INT_STA_3 0x47c +#define AIROHA_PCS_PMA_RX_SIGDET_INT BIT(16) +#define AIROHA_PCS_PMA_RX_EXTRAL_CTRL 0x48c +/* 4ref_ck step: + * - 0x1 4ref_ck + * - 0x2 8ref_ck + * - 0x3 12ref_ck + * ... + */ +#define AIROHA_PCS_PMA_L2D_TRIG_EQ_EN_TIME GENMASK(15, 8) +#define AIROHA_PCS_PMA_OS_RDY_LATCH BIT(1) +#define AIROHA_PCS_PMA_DISB_LEQ BIT(0) +#define AIROHA_PCS_PMA_RX_FREQDET 0x530 +#define AIROHA_PCS_PMA_FL_OUT GENMASK(31, 16) +#define AIROHA_PCS_PMA_FBCK_LOCK BIT(0) +#define AIROHA_PCS_PMA_XPON_TX_RATE_CTRL 0x580 +#define AIROHA_PCS_PMA_PON_TX_RATE_CTRL GENMASK(1, 0) +#define AIROHA_PCS_PMA_MD32_MEM_CLK_CTRL 0x60c +#define AIROHA_PCS_PMA_MD32PM_CK_SEL GENMASK(31, 0) +#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN 0x768 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL GENMASK(19, 16) +#define AIROHA_PCS_PMA_PXP_AEQ_SPEED 0x76c +#define AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_OSR_SEL GENMASK(17, 16) +#define AIROHA_PCS_PMA_PXP_TX_FIR_C0B 0x778 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 GENMASK(20, 16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B GENMASK(5, 0) +#define AIROHA_PCS_PMA_PXP_TX_TERM_SEL 0x77c +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR GENMASK(19, 16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL GENMASK(2, 0) +#define AIROHA_PCS_PMA_PXP_TX_FIR_C1 0x780 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 GENMASK(20, 16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1 GENMASK(5, 0) +#define AIROHA_PCS_PMA_PXP_TX_RATE_CTRL 0x784 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE GENMASK(22, 16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL GENMASK(1, 0) +#define AIROHA_PCS_PMA_PXP_CDR_PR_FLL_COR 0x790 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_DAC_EYE BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_RX_DAC_EYE GENMASK(22, 16) +#define AIROHA_PCS_PMA_PXP_CDR_PR_IDAC 0x794 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW BIT(24) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC BIT(16) +#define AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC GENMASK(10, 0) +#define AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR GENMASK(10, 8) +#define AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW 0x798 +#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW GENMASK(30, 0) +#define AIROHA_PCS_PMA_PXP_RX_FE_VOS 0x79c +#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_FE_VOS GENMASK(5, 0) +#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW 0x800 +#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW GENMASK(30, 0) +#define AIROHA_PCS_PMA_PXP_AEQ_BYPASS 0x80c +#define AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON BIT(16) +#define AIROHA_PCS_PMA_PXP_AEQ_RSTB 0x814 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL BIT(16) +#define AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA 0x818 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA BIT(0) +#define AIROHA_PCS_PMA_PXP_CDR_PD_PWDB 0x81c +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB BIT(0) +#define AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN 0x820 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN BIT(0) +#define AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB 0x824 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB BIT(0) +#define AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN 0x828 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN BIT(0) +#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN_RSTB 0x83c +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_OSCAL_CKON BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_RX_OSCAL_CKON BIT(16) +#define AIROHA_PCS_PMA_PXP_RX_OSCAL_EN 0x840 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_OSCAL_RSTB BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_RX_OSCAL_RSTB BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_OSCAL_EN BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_RX_OSCAL_EN BIT(0) +#define AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B 0x84c +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B BIT(0) +#define AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN 0x854 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN BIT(0) +#define AIROHA_PCS_PMA_PXP_TXPLL_KBAND_LOAD_EN 0x858 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_KBAND_LOAD_EN BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_KBAND_LOAD_EN BIT(0) +#define AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW_CHG 0x864 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW_CHG BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW_CHG BIT(0) +#define AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN 0x874 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL BIT(16) +#define AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL 0x88c +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL GENMASK(1, 0) +#define AIROHA_PCS_PMA_PXP_RX_FE_PWDB 0x894 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB BIT(0) +#define AIROHA_PCS_PMA_PXP_RX_SIGDET_CAL_EN 0x898 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_CAL_EN BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_CAL_EN BIT(0) +#define AIROHA_PCS_PMA_DIG_RESERVE_12 0x8b8 +#define AIROHA_PCS_PMA_RESERVE_12_FEOS_0 BIT(0) +#define AIROHA_PCS_PMA_DIG_RESERVE_24 0x8fc +#define AIROHA_PCS_PMA_FORCE_RX_GEARBOX BIT(12) +#define AIROHA_PCS_PMA_FORCE_SEL_RX_GEARBOX BIT(8) + +#define AIROHA_PCS_MAX_CALIBRATION_TRY 50 +#define AIROHA_PCS_MAX_NUM_RSTS 2 + +enum pon_eo_buf_vals { + EYE_EU, + EYE_EB, + DAC_D0, + DAC_D1, + DAC_E0, + DAC_E1, + DAC_EYE, + FEOS, + + EO_BUF_MAX, +}; + +enum xfi_port_type { + AIROHA_PCS_ETH, + AIROHA_PCS_PON, +}; + +struct airoha_pcs_priv { + struct udevice *dev; + const struct airoha_pcs_match_data *data; + phy_interface_t interface; + + struct regmap *scu; + + struct regmap *xfi_mac; + struct regmap *hsgmii_an; + struct regmap *hsgmii_pcs; + struct regmap *hsgmii_rate_adp; + struct regmap *multi_sgmii; + struct regmap *usxgmii_pcs; + + struct regmap *xfi_pma; + struct regmap *xfi_ana; + + struct reset_ctl *xfi_rst; + struct reset_ctl_bulk rsts; + + bool manual_rx_calib; +}; + +struct airoha_pcs_match_data { + enum xfi_port_type port_type; + + bool hibernation_workaround; + bool usxgmii_ber_time_fixup; + bool usxgmii_rx_gb_out_vld_tweak; + bool usxgmii_xfi_mode_sel; + + int (*bringup)(struct airoha_pcs_priv *priv, + phy_interface_t interface); + void (*link_up)(struct airoha_pcs_priv *priv); +}; + +void airoha_pcs_pre_config(struct udevice *dev, phy_interface_t interface); +int airoha_pcs_post_config(struct udevice *dev, phy_interface_t interface); +int airoha_pcs_config(struct udevice *dev, bool neg_mode, + phy_interface_t interface, + const unsigned long *advertising, + bool permit_pause_to_mac); +void airoha_pcs_link_up(struct udevice *dev, unsigned int neg_mode, + phy_interface_t interface, int speed, int duplex); +void airoha_pcs_link_down(struct udevice *dev); + +#ifdef CONFIG_PCS_AIROHA_AN7581 +int an7581_pcs_bringup(struct airoha_pcs_priv *priv, + phy_interface_t interface); + +void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv); +#else +static inline int an7581_pcs_bringup(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + return -EOPNOTSUPP; +} + +static inline void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv) +{ +} +#endif diff --git a/drivers/net/airoha/pcs-an7581.c b/drivers/net/airoha/pcs-an7581.c new file mode 100644 index 00000000000..746ff55d72f --- /dev/null +++ b/drivers/net/airoha/pcs-an7581.c @@ -0,0 +1,1375 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 AIROHA Inc + * Author: Christian Marangi <[email protected]> + */ +#include <dm.h> +#include <dm/device_compat.h> +#include <regmap.h> + +#include "pcs-airoha.h" + +static void an7581_pcs_jcpll_bringup(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + u32 kband_vref; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + kband_vref = 0x10; + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + kband_vref = 0xf; + break; + default: + return; + } + + /* Setup LDO */ + udelay(200); + + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H, + AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO); + + /* Setup RSTB */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, + AIROHA_PCS_ANA_JCPLL_RST_DLY, + AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200); + + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, + AIROHA_PCS_ANA_JCPLL_PLL_RSTB); + + /* Enable PLL force selection and Force Disable */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN | + AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN); + + /* Setup SDM */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, + AIROHA_PCS_ANA_JCPLL_SDM_DI_LS | + AIROHA_PCS_ANA_JCPLL_SDM_DI_EN, + AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, + AIROHA_PCS_ANA_JCPLL_SDM_OUT | + AIROHA_PCS_ANA_JCPLL_SDM_ORD | + AIROHA_PCS_ANA_JCPLL_SDM_MODE | + AIROHA_PCS_ANA_JCPLL_SDM_IFM, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x0) | + AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SDM_MODE, 0x0)); + + regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, + AIROHA_PCS_ANA_JCPLL_SDM_HREN); + + /* Setup SSC */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA, + AIROHA_PCS_ANA_JCPLL_SSC_PERIOD | + AIROHA_PCS_ANA_JCPLL_SSC_DELTA, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SSC_PERIOD, 0x0) | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SSC_DELTA, 0x0)); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN, + AIROHA_PCS_ANA_JCPLL_SSC_DELTA1 | + AIROHA_PCS_ANA_JCPLL_SSC_TRI_EN, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SSC_DELTA1, 0x0)); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, + AIROHA_PCS_ANA_JCPLL_SSC_PHASE_INI | + AIROHA_PCS_ANA_JCPLL_SSC_EN | + AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L | + AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L, 0x0) | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR, 0x0)); + + /* Setup LPF */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN, + AIROHA_PCS_ANA_JCPLL_CHP_IOFST | + AIROHA_PCS_ANA_JCPLL_CHP_IBIAS | + AIROHA_PCS_ANA_JCPLL_LPF_SHCK_EN, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_CHP_IOFST, 0x0) | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_CHP_IBIAS, 0x18)); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, + AIROHA_PCS_ANA_JCPLL_LPF_BWR | + AIROHA_PCS_ANA_JCPLL_LPF_BP | + AIROHA_PCS_ANA_JCPLL_LPF_BC | + AIROHA_PCS_ANA_JCPLL_LPF_BR, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BWR, 0x0) | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BP, 0x10) | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BC, 0x1f) | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BR, BIT(3) | BIT(1))); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, + AIROHA_PCS_ANA_JCPLL_LPF_BWC, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BWC, 0x0)); + + /* Setup VCO */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, + AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR | + AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN | + AIROHA_PCS_ANA_JCPLL_VCO_CFIX, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR, 0x4) | + AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_CFIX, 0x1)); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, + AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L | + AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H | + AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L, 0x0) | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H, 0x3) | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR, 0x3)); + + /* Setup PCW */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW, + AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW, + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW, 0x25800000)); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS, + AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW); + + /* Setup DIV */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE, + AIROHA_PCS_ANA_JCPLL_POSTDIV_D5 | + AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, + AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, + AIROHA_PCS_ANA_JCPLL_VCODIV, + AIROHA_PCS_ANA_JCPLL_VCODIV_1); + + /* Setup KBand */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC, + AIROHA_PCS_ANA_JCPLL_KBAND_KS | + AIROHA_PCS_ANA_JCPLL_KBAND_KF | + AIROHA_PCS_ANA_JCPLL_KBAND_KFC, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_KS, 0x0) | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_KF, 0x3) | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_KFC, 0x0)); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, + AIROHA_PCS_ANA_JCPLL_KBAND_DIV | + AIROHA_PCS_ANA_JCPLL_KBAND_CODE | + AIROHA_PCS_ANA_JCPLL_KBAND_OPTION, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_DIV, 0x2) | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_CODE, 0xe4)); + + /* Setup TCL */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H, + AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF, kband_vref)); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, + AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF | + AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN | + AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF, 0x5) | + AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4 | + AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN, + AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW | + AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN, + AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1 | + AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN); + + /* Enable PLL */ + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN, + AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN); + + /* Enale PLL Output */ + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN | + AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN); +} + +static void an7581_pcs_txpll_bringup(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + u32 lpf_chp_ibias, lpf_bp, lpf_bwr, lpf_bwc; + u32 vco_cfix; + u32 pcw; + u32 tcl_amp_vref; + bool sdm_hren; + bool vcodiv; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + lpf_chp_ibias = 0xf; + lpf_bp = BIT(1); + lpf_bwr = BIT(3) | BIT(1) | BIT(0); + lpf_bwc = BIT(4) | BIT(3); + vco_cfix = BIT(1) | BIT(0); + pcw = BIT(27); + tcl_amp_vref = BIT(3) | BIT(1) | BIT(0); + vcodiv = false; + sdm_hren = false; + break; + case PHY_INTERFACE_MODE_2500BASEX: + lpf_chp_ibias = 0xa; + lpf_bp = BIT(2) | BIT(0); + lpf_bwr = 0; + lpf_bwc = 0; + vco_cfix = 0; + pcw = BIT(27) | BIT(25); + tcl_amp_vref = BIT(3) | BIT(2) | BIT(0); + vcodiv = true; + sdm_hren = false; + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + lpf_chp_ibias = 0xf; + lpf_bp = BIT(1); + lpf_bwr = BIT(3) | BIT(1) | BIT(0); + lpf_bwc = BIT(4) | BIT(3); + vco_cfix = BIT(0); + pcw = BIT(27) | BIT(22); + tcl_amp_vref = BIT(3) | BIT(1) | BIT(0); + vcodiv = false; + sdm_hren = true; + break; + default: + return; + } + + /* Setup VCO LDO Output */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD, + AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT | + AIROHA_PCS_ANA_TXPLL_LDO_OUT, + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT, 0x1) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LDO_OUT, 0x1)); + + /* Setup RSTB */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, + AIROHA_PCS_ANA_TXPLL_PLL_RSTB | + AIROHA_PCS_ANA_TXPLL_RST_DLY | + AIROHA_PCS_ANA_TXPLL_REFIN_DIV | + AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL, + AIROHA_PCS_ANA_TXPLL_PLL_RSTB | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_RST_DLY, 0x4) | + AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1 | + AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL); + + /* Enable PLL force selection and Force Disable */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN | + AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN); + + /* Setup SDM */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, + AIROHA_PCS_ANA_TXPLL_SDM_MODE | + AIROHA_PCS_ANA_TXPLL_SDM_IFM | + AIROHA_PCS_ANA_TXPLL_SDM_DI_LS | + AIROHA_PCS_ANA_TXPLL_SDM_DI_EN, + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SDM_MODE, 0) | + AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, + AIROHA_PCS_ANA_TXPLL_SDM_HREN | + AIROHA_PCS_ANA_TXPLL_SDM_OUT | + AIROHA_PCS_ANA_TXPLL_SDM_ORD, + (sdm_hren ? AIROHA_PCS_ANA_TXPLL_SDM_HREN : 0) | + AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM); + + /* Setup SSC */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1, + AIROHA_PCS_ANA_TXPLL_SSC_DELTA | + AIROHA_PCS_ANA_TXPLL_SSC_DELTA1, + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_DELTA, 0x0) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_DELTA1, 0x0)); + + regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN, + AIROHA_PCS_ANA_TXPLL_SSC_TRI_EN | + AIROHA_PCS_ANA_TXPLL_SSC_PHASE_INI | + AIROHA_PCS_ANA_TXPLL_SSC_EN); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD, + AIROHA_PCS_ANA_TXPLL_SSC_PERIOD, + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_PERIOD, 0x0)); + + /* Setup LPF */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, + AIROHA_PCS_ANA_TXPLL_LPF_BC | + AIROHA_PCS_ANA_TXPLL_LPF_BR | + AIROHA_PCS_ANA_TXPLL_CHP_IOFST | + AIROHA_PCS_ANA_TXPLL_CHP_IBIAS, + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BC, 0x1f) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BR, 0x5) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_CHP_IOFST, 0x0) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_CHP_IBIAS, lpf_chp_ibias)); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, + AIROHA_PCS_ANA_TXPLL_LPF_BWC | + AIROHA_PCS_ANA_TXPLL_LPF_BWR | + AIROHA_PCS_ANA_TXPLL_LPF_BP, + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BWC, lpf_bwc) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BWR, lpf_bwr) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BP, lpf_bp)); + + /* Setup VCO */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, + AIROHA_PCS_ANA_TXPLL_VCO_CFIX, + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_CFIX, vco_cfix)); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, + AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L | + AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H | + AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR | + AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR | + AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN, + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L, 0x0) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H, 0x4) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR, 0x4) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR, 0x7) | + AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN); + + /* Setup PCW */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW, + AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW, pcw); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC, + AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW); + + /* Setup KBand */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, + AIROHA_PCS_ANA_TXPLL_KBAND_KF | + AIROHA_PCS_ANA_TXPLL_KBAND_KFC | + AIROHA_PCS_ANA_TXPLL_KBAND_DIV | + AIROHA_PCS_ANA_TXPLL_KBAND_CODE, + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KF, 0x3) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KFC, 0x0) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_DIV, 0x4) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_CODE, 0xe4)); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS, + AIROHA_PCS_ANA_TXPLL_KBAND_KS, + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KS, 0x1)); + + regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, + AIROHA_PCS_ANA_TXPLL_KBAND_OPTION); + + /* Setup DIV */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS, + AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE | + AIROHA_PCS_ANA_TXPLL_POSTDIV_EN, + AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, + AIROHA_PCS_ANA_TXPLL_VCODIV, + vcodiv ? AIROHA_PCS_ANA_TXPLL_VCODIV_2 : + AIROHA_PCS_ANA_TXPLL_VCODIV_1); + + /* Setup TCL */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF, + AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF, + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF, 0xf)); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN, + AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF | + AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF, tcl_amp_vref) | + AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, + AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW | + AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN, + AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5 | + AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN); + + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, + AIROHA_PCS_ANA_TXPLL_TCL_AMP_EN); + + /* Enable PLL */ + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN, + AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN); + + /* Enale PLL Output */ + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN | + AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN); +} + +static void an7581_pcs_tx_bringup(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + u32 tx_rate_ctrl; + u32 ckin_divisor; + u32 fir_cn1, fir_c0b, fir_c1; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + ckin_divisor = BIT(1); + tx_rate_ctrl = BIT(0); + fir_cn1 = 0; + fir_c0b = 12; + fir_c1 = 0; + break; + case PHY_INTERFACE_MODE_2500BASEX: + ckin_divisor = BIT(2); + tx_rate_ctrl = BIT(0); + fir_cn1 = 0; + fir_c0b = 11; + fir_c1 = 1; + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + ckin_divisor = BIT(2) | BIT(0); + tx_rate_ctrl = BIT(1); + fir_cn1 = 1; + fir_c0b = 1; + fir_c1 = 11; + break; + default: + return; + } + + /* Set TX rate ctrl */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_XPON_TX_RATE_CTRL, + AIROHA_PCS_PMA_PON_TX_RATE_CTRL, + FIELD_PREP(AIROHA_PCS_PMA_PON_TX_RATE_CTRL, + tx_rate_ctrl)); + + /* Setup TX Config */ + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TX_CKLDO_EN, + AIROHA_PCS_ANA_TX_DMEDGEGEN_EN | + AIROHA_PCS_ANA_TX_CKLDO_EN); + + udelay(1); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL | + AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL); + + /* FIXME: Ask Airoha TX term is OK to reset? */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_TERM_SEL, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR | + AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR | + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL | + AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR | + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR, + ckin_divisor) | + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL, 0x0)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_RATE_CTRL, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL | + AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL | + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL, + tx_rate_ctrl)); + + /* Setup TX FIR Load Parameters (Reference 660mV) */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C0B, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 | + AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 | + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B | + AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 | + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1, fir_cn1) | + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B | + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B, fir_c0b)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C1, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 | + AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 | + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 | + AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 | + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1, fir_c1)); + + /* Reset TX Bar */ + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_TX_RST_B, + AIROHA_PCS_PMA_TXCALIB_RST_B | AIROHA_PCS_PMA_TX_TOP_RST_B); +} + +static void an7581_pcs_rx_bringup(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + u32 rx_rate_ctrl; + u32 osr; + u32 pr_cdr_beta_dac; + u32 cdr_pr_buf_in_sr; + bool cdr_pr_cap_en; + u32 sigdet_vth_sel; + u32 phyck_div, phyck_sel; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + osr = BIT(1) | BIT(0); /* 1.25G */ + pr_cdr_beta_dac = BIT(3); + rx_rate_ctrl = 0; + cdr_pr_cap_en = false; + cdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0); + sigdet_vth_sel = BIT(2) | BIT(1); + phyck_div = BIT(5) | BIT(3) | BIT(0); + phyck_sel = BIT(0); + break; + case PHY_INTERFACE_MODE_2500BASEX: + osr = BIT(0); /* 2.5G */ + pr_cdr_beta_dac = BIT(2) | BIT(1); + rx_rate_ctrl = 0; + cdr_pr_cap_en = true; + cdr_pr_buf_in_sr = BIT(2) | BIT(1); + sigdet_vth_sel = BIT(2) | BIT(1); + phyck_div = BIT(3) | BIT(1) | BIT(0); + phyck_sel = BIT(0); + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + osr = 0; /* 10G */ + cdr_pr_cap_en = false; + pr_cdr_beta_dac = BIT(3); + rx_rate_ctrl = BIT(1); + cdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0); + sigdet_vth_sel = BIT(1); + phyck_div = BIT(6) | BIT(1); + phyck_sel = BIT(1); + break; + default: + return; + } + + /* Set RX rate ctrl */ + if (interface == PHY_INTERFACE_MODE_2500BASEX) + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_2, + AIROHA_PCS_PMA_CK_RATE, + AIROHA_PCS_PMA_CK_RATE_10); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_XPON_RX_RESERVED_1, + AIROHA_PCS_PMA_XPON_RX_RATE_CTRL, + FIELD_PREP(AIROHA_PCS_PMA_XPON_RX_RATE_CTRL, rx_rate_ctrl)); + + /* Setup RX Path */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_5, + AIROHA_PCS_PMA_FLL_IDAC_MIN | + AIROHA_PCS_PMA_FLL_IDAC_MAX, + FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MIN, 0x400) | + FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MAX, 0x3ff)); + + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, + AIROHA_PCS_ANA_RX_DAC_EYE_BYPASS_AEQ | + AIROHA_PCS_ANA_RX_DAC_E1_BYPASS_AEQ | + AIROHA_PCS_ANA_RX_DAC_E0_BYPASS_AEQ | + AIROHA_PCS_ANA_RX_DAC_D1_BYPASS_AEQ); + + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB, + AIROHA_PCS_ANA_RX_DAC_D0_BYPASS_AEQ); + + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB, + AIROHA_PCS_ANA_FE_VCM_GEN_PWDB); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1, + AIROHA_PCS_PMA_LCPLL_MAN_PWDB); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_AEQ_CFORCE, + AIROHA_PCS_ANA_AEQ_OFORCE, + AIROHA_PCS_ANA_AEQ_OFORCE_CTLE); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW, + AIROHA_PCS_ANA_RX_OSCAL_FORCE, + AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS); + + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_DISB_MODE_4, + AIROHA_PCS_PMA_DISB_BLWC_OFFSET); + + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_EXTRAL_CTRL, + AIROHA_PCS_PMA_DISB_LEQ); + + regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV, + AIROHA_PCS_ANA_CDR_PD_EDGE_DIS | + AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_AEQ_BYPASS, + AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON | + AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON, + AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_AEQ_RSTB, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL | + AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, + AIROHA_PCS_ANA_RX_DAC_MON | + AIROHA_PCS_ANA_CDR_PR_XFICK_EN | + AIROHA_PCS_ANA_CDR_PR_MONDPI_EN | + AIROHA_PCS_ANA_CDR_PR_MONDPR_EN, + FIELD_PREP(AIROHA_PCS_ANA_RX_DAC_MON, 0x0) | + AIROHA_PCS_ANA_CDR_PR_XFICK_EN); + + /* Setup FE Gain and FE Peacking */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL, + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL | + AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL, + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL, 0x0)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN, + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL | + AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL, + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL, 0x0)); + + /* Setup FE VOS */ + if (interface != PHY_INTERFACE_MODE_USXGMII && + interface != PHY_INTERFACE_MODE_10GBASER) + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS, + AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS | + AIROHA_PCS_PMA_FORCE_DA_FE_VOS, + AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS | + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_FE_VOS, 0x0)); + + /* Setup FLL PR FMeter (no bypass mode)*/ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_0, + AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT, + FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT, 0x1)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_1, + AIROHA_PCS_PMA_PLL_LOCK_TARGET_END | + AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG, + FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_END, 0xffff) | + FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG, 0x0)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_3, + AIROHA_PCS_PMA_PLL_LOCK_LOCKTH, + FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_LOCKTH, 0x1)); + + /* FIXME: Warn and Ask Airoha about typo in air_eth_xsgmii.c line 1391 */ + /* AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL is set 0x0 in SDK but seems a typo */ + /* Setup REV */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_REV_0, + AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL | + AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL | + AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK, + FIELD_PREP(AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL, BIT(2)) | + FIELD_PREP(AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL, BIT(2)) | + FIELD_PREP(AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK, 0x0)); + + /* Setup Rdy Timeout */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5, + AIROHA_PCS_PMA_RX_RDY | + AIROHA_PCS_PMA_RX_BLWC_RDY_EN, + FIELD_PREP(AIROHA_PCS_PMA_RX_RDY, 0xa) | + FIELD_PREP(AIROHA_PCS_PMA_RX_BLWC_RDY_EN, 0x5)); + + /* Setup CaBoundry Init */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0, + AIROHA_PCS_PMA_RX_OS_START | + AIROHA_PCS_PMA_OSC_SPEED_OPT, + FIELD_PREP(AIROHA_PCS_PMA_RX_OS_START, 0x1) | + AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6, + AIROHA_PCS_PMA_RX_OS_END, + FIELD_PREP(AIROHA_PCS_PMA_RX_OS_END, 0x2)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1, + AIROHA_PCS_PMA_RX_PICAL_END | + AIROHA_PCS_PMA_RX_PICAL_START, + FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_END, 0x32) | + FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_START, 0x2)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4, + AIROHA_PCS_PMA_RX_SDCAL_END | + AIROHA_PCS_PMA_RX_SDCAL_START, + FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_END, 0x32) | + FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_START, 0x2)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2, + AIROHA_PCS_PMA_RX_PDOS_END | + AIROHA_PCS_PMA_RX_PDOS_START, + FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_END, 0x32) | + FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_START, 0x2)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3, + AIROHA_PCS_PMA_RX_FEOS_END | + AIROHA_PCS_PMA_RX_FEOS_START, + FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_END, 0x32) | + FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_START, 0x2)); + + /* Setup By Serdes*/ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_AEQ_SPEED, + AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL | + AIROHA_PCS_PMA_FORCE_DA_OSR_SEL, + AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL | + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_OSR_SEL, osr)); + + /* Setup RX OSR */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV, + AIROHA_PCS_ANA_CDR_PD_EDGE_DIS, + osr ? AIROHA_PCS_ANA_CDR_PD_EDGE_DIS : 0); + + /* Setup CDR LPF Ratio */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO, + AIROHA_PCS_ANA_CDR_LPF_TOP_LIM | + AIROHA_PCS_ANA_CDR_LPF_RATIO, + FIELD_PREP(AIROHA_PCS_ANA_CDR_LPF_TOP_LIM, 0x20000) | + FIELD_PREP(AIROHA_PCS_ANA_CDR_LPF_RATIO, osr)); + + /* Setup CDR PR */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, + AIROHA_PCS_ANA_CDR_PR_KBAND_DIV | + AIROHA_PCS_ANA_CDR_PR_BETA_SEL | + AIROHA_PCS_ANA_CDR_PR_VCOADC_OS | + AIROHA_PCS_ANA_CDR_PR_BETA_DAC, + FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_KBAND_DIV, 0x4) | + FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_BETA_SEL, 0x1) | + FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VCOADC_OS, 0x8) | + FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_BETA_DAC, pr_cdr_beta_dac)); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, + AIROHA_PCS_ANA_CDR_PR_FBKSEL | + AIROHA_PCS_ANA_CDR_PR_DAC_BAND | + AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL | + AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL, + FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_FBKSEL, 0x0) | + FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_DAC_BAND, pr_cdr_beta_dac) | + FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL, 0x6) | + FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL, 0x6)); + + /* Setup Eye Mon */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PHY_EQ_CTRL_2, + AIROHA_PCS_PMA_EQ_DEBUG_SEL | + AIROHA_PCS_PMA_FOM_NUM_ORDER | + AIROHA_PCS_PMA_A_SEL, + FIELD_PREP(AIROHA_PCS_PMA_EQ_DEBUG_SEL, 0x0) | + FIELD_PREP(AIROHA_PCS_PMA_FOM_NUM_ORDER, 0x1) | + FIELD_PREP(AIROHA_PCS_PMA_A_SEL, 0x3)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2, + AIROHA_PCS_PMA_DATA_SHIFT | + AIROHA_PCS_PMA_EYECNT_FAST, + AIROHA_PCS_PMA_EYECNT_FAST); + + /* Calibration Start */ + + /* Enable SYS */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_SYS_EN_SEL_0, + AIROHA_PCS_PMA_RX_SYS_EN_SEL, + FIELD_PREP(AIROHA_PCS_PMA_RX_SYS_EN_SEL, 0x1)); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0, + AIROHA_PCS_PMA_SW_LCPLL_EN); + + udelay(500); + + /* Setup FLL PR FMeter (bypass mode)*/ + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_DISB_MODE_8, + AIROHA_PCS_PMA_DISB_FBCK_LOCK); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_9, + AIROHA_PCS_PMA_FORCE_FBCK_LOCK); + + /* Enable CMLEQ */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, + AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN | + AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN | + AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN | + AIROHA_PCS_ANA_RX_FE_EQ_HZEN, + AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN | + AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN | + AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN); + + /* Setup CDR PR */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, + AIROHA_PCS_ANA_CDR_PR_CAP_EN | + AIROHA_PCS_ANA_CDR_BUF_IN_SR, + (cdr_pr_cap_en ? AIROHA_PCS_ANA_CDR_PR_CAP_EN : 0) | + FIELD_PREP(AIROHA_PCS_ANA_CDR_BUF_IN_SR, cdr_pr_buf_in_sr)); + + /* Setup CDR xxx Pwdb, set force and disable */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB | + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB | + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB | + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB | + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB | + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB | + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB | + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB, + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN | + AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN | + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB | + AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB, + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B, + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB | + AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB | + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B | + AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B, + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB); + + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0, + AIROHA_PCS_PMA_XPON_CDR_PD_PWDB | + AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB | + AIROHA_PCS_PMA_XPON_CDR_PW_PWDB | + AIROHA_PCS_PMA_XPON_RX_FE_PWDB); + + /* FIXME: Ask Airoha WHY it's cleared? */ + /* regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH, + * AIROHA_PCS_ANA_RX_FE_50OHMS_SEL); + */ + + /* Setup SigDet */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH, + AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL | + AIROHA_PCS_ANA_RX_SIGDET_PEAK, + FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL, sigdet_vth_sel) | + FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_PEAK, BIT(1))); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_DAC_RANGE, + AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL, + FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL, BIT(1) | BIT(0))); + + /* Disable SigDet Pwdb */ + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1, + AIROHA_PCS_PMA_RX_SIDGET_PWDB); + + /* Setup PHYCK */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, + AIROHA_PCS_ANA_RX_TDC_CK_SEL | + AIROHA_PCS_ANA_RX_PHYCK_RSTB | + AIROHA_PCS_ANA_RX_PHYCK_SEL | + AIROHA_PCS_ANA_RX_PHYCK_DIV, + AIROHA_PCS_ANA_RX_PHYCK_RSTB | + FIELD_PREP(AIROHA_PCS_ANA_RX_PHYCK_SEL, phyck_sel) | + FIELD_PREP(AIROHA_PCS_ANA_RX_PHYCK_DIV, phyck_div)); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL, + AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE | + AIROHA_PCS_ANA_RX_PHY_CK_SEL, + AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE); + + udelay(100); + + /* Enable CDR xxx Pwdb */ + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB | + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB, + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB, + AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B, + AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0, + AIROHA_PCS_PMA_XPON_CDR_PD_PWDB | + AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB | + AIROHA_PCS_PMA_XPON_CDR_PW_PWDB | + AIROHA_PCS_PMA_XPON_RX_FE_PWDB); + + /* Enable SigDet Pwdb */ + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1, + AIROHA_PCS_PMA_RX_SIDGET_PWDB); +} + +static unsigned int an7581_pcs_apply_cdr_pr_idac(struct airoha_pcs_priv *priv, + u32 cdr_pr_idac) +{ + u32 val; + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC, + AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC, + FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC, + cdr_pr_idac)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4, + AIROHA_PCS_PMA_FREQLOCK_DET_EN, + AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4, + AIROHA_PCS_PMA_FREQLOCK_DET_EN, + AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL); + + udelay(5000); + + regmap_read(priv->xfi_pma, AIROHA_PCS_PMA_RX_FREQDET, &val); + + return FIELD_GET(AIROHA_PCS_PMA_FL_OUT, val); +} + +static u32 an7581_pcs_rx_prcal_idac_major(struct airoha_pcs_priv *priv, + u32 target_fl_out) +{ + unsigned int fl_out_diff = UINT_MAX; + unsigned int prcal_search; + u32 cdr_pr_idac = 0; + + for (prcal_search = 0; prcal_search < 8 ; prcal_search++) { + unsigned int fl_out_diff_new; + unsigned int fl_out; + u32 cdr_pr_idac_tmp; + + /* try to find the upper value by setting the last 3 bit */ + cdr_pr_idac_tmp = FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR, + prcal_search); + fl_out = an7581_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac_tmp); + + /* Use absolute values to find the closest one to target */ + fl_out_diff_new = abs(fl_out - target_fl_out); + dev_dbg(priv->dev, "Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\n", + cdr_pr_idac_tmp, fl_out, fl_out_diff_new); + if (fl_out_diff_new < fl_out_diff) { + cdr_pr_idac = cdr_pr_idac_tmp; + fl_out_diff = fl_out_diff_new; + } + } + + return cdr_pr_idac; +} + +static u32 an7581_pcs_rx_prcal_idac_minor(struct airoha_pcs_priv *priv, u32 target_fl_out, + u32 cdr_pr_idac_major) +{ + unsigned int remaining_prcal_search_bits = 0; + u32 cdr_pr_idac = cdr_pr_idac_major; + unsigned int fl_out, fl_out_diff; + int best_prcal_search_bit = -1; + int prcal_search_bit; + + fl_out = an7581_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac); + fl_out_diff = abs(fl_out - target_fl_out); + + /* Deadline search part. + * We start from top bits to bottom as we progressively decrease the + * signal. + */ + for (prcal_search_bit = 7; prcal_search_bit >= 0; prcal_search_bit--) { + unsigned int fl_out_diff_new; + u32 cdr_pr_idac_tmp; + + cdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit); + fl_out = an7581_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac_tmp); + + /* Use absolute values to find the closest one to target */ + fl_out_diff_new = abs(fl_out - target_fl_out); + dev_dbg(priv->dev, "Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\n", + cdr_pr_idac_tmp, fl_out, fl_out_diff_new); + if (fl_out_diff_new < fl_out_diff) { + best_prcal_search_bit = prcal_search_bit; + fl_out_diff = fl_out_diff_new; + } + } + + /* Set the idac with the best value we found and + * reset the search bit to start from bottom to top. + */ + if (best_prcal_search_bit >= 0) { + cdr_pr_idac |= BIT(best_prcal_search_bit); + remaining_prcal_search_bits = best_prcal_search_bit; + prcal_search_bit = 0; + } + + /* Fine tune part. + * Test remaining bits to find an even closer signal level to target + * by increasing the signal. + */ + while (remaining_prcal_search_bits) { + unsigned int fl_out_diff_new; + u32 cdr_pr_idac_tmp; + + cdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit); + fl_out = an7581_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac_tmp); + + /* Use absolute values to find the closest one to target */ + fl_out_diff_new = abs(fl_out - target_fl_out); + /* Assume we found the deadline when the new absolue signal difference + * from target is greater than the previous and the difference is at + * least 10% greater between the old and new value. + * This is to account for signal detection level tollerance making + * sure we are actually over a deadline (AKA we are getting farther + * from target) + */ + dev_dbg(priv->dev, "Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\n", + cdr_pr_idac_tmp, fl_out, fl_out_diff_new); + if (fl_out_diff_new > fl_out_diff && + (abs(fl_out_diff_new - fl_out_diff) * 100) / fl_out_diff > 10) { + /* Exit early if we are already at the deadline */ + if (prcal_search_bit == 0) + break; + + /* We found the deadline, set the value to the previous + * bit, and reset the loop to fine tune with the + * remaining values. + */ + cdr_pr_idac |= BIT(prcal_search_bit - 1); + remaining_prcal_search_bits = prcal_search_bit - 1; + prcal_search_bit = 0; + } else { + /* Update the signal level diff and try the next bit */ + fl_out_diff = fl_out_diff_new; + + /* If we didn't found the deadline, set the last bit + * and reset the loop to fine tune with the remainig + * values. + */ + if (prcal_search_bit == remaining_prcal_search_bits - 1) { + cdr_pr_idac |= BIT(prcal_search_bit); + remaining_prcal_search_bits = prcal_search_bit; + prcal_search_bit = 0; + } else { + prcal_search_bit++; + } + } + } + + return cdr_pr_idac; +} + +static void an7581_pcs_rx_prcal(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + u32 cdr_pr_idac_major, cdr_pr_idac; + unsigned int fl_out, fl_out_diff; + + u32 target_fl_out; + u32 cyclecnt; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: /* DS_1.25G / US_1.25G */ + case PHY_INTERFACE_MODE_1000BASEX: + target_fl_out = 0xa3d6; + cyclecnt = 32767; + break; + case PHY_INTERFACE_MODE_2500BASEX: /* DS_9.95328G / US_9.95328G */ + target_fl_out = 0xa000; + cyclecnt = 20000; + break; + case PHY_INTERFACE_MODE_USXGMII: /* DS_10.3125G / US_1.25G */ + case PHY_INTERFACE_MODE_10GBASER: + target_fl_out = 0x9edf; + cyclecnt = 32767; + break; + default: + return; + } + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET, + AIROHA_PCS_PMA_SW_REF_RST_N); + + udelay(100); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_2, + AIROHA_PCS_PMA_LOCK_TARGET_END | + AIROHA_PCS_PMA_LOCK_TARGET_BEG, + FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_END, target_fl_out + 100) | + FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_BEG, target_fl_out - 100)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_1, + AIROHA_PCS_PMA_UNLOCK_CYCLECNT | + AIROHA_PCS_PMA_LOCK_CYCLECNT, + FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_CYCLECNT, cyclecnt) | + FIELD_PREP(AIROHA_PCS_PMA_LOCK_CYCLECNT, cyclecnt)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4, + AIROHA_PCS_PMA_LOCK_UNLOCKTH | + AIROHA_PCS_PMA_LOCK_LOCKTH, + FIELD_PREP(AIROHA_PCS_PMA_LOCK_UNLOCKTH, 3) | + FIELD_PREP(AIROHA_PCS_PMA_LOCK_LOCKTH, 3)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_3, + AIROHA_PCS_PMA_UNLOCK_TARGET_END | + AIROHA_PCS_PMA_UNLOCK_TARGET_BEG, + FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_END, target_fl_out + 100) | + FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_BEG, target_fl_out - 100)); + + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE, + AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN | + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN | + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN | + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN | + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN | + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB); + + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB); + + /* Calibration logic: + * First check the major value by looping with every + * value in the last 3 bit of CDR_PR_IDAC. + * Get the signal level and save the value that is closer to + * the target. + * + * Then check each remaining 7 bits in search of the deadline + * where the signal gets farther than signal target. + * + * Finally fine tune for the remaining bits to find the one that + * produce the closest signal level. + */ + cdr_pr_idac_major = an7581_pcs_rx_prcal_idac_major(priv, target_fl_out); + + cdr_pr_idac = an7581_pcs_rx_prcal_idac_minor(priv, target_fl_out, cdr_pr_idac_major); + + fl_out = an7581_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac); + fl_out_diff = abs(fl_out - target_fl_out); + if (fl_out_diff > 100) { + u32 pr_idac_major = FIELD_GET(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR, + cdr_pr_idac_major); + unsigned int fl_out_tmp, fl_out_diff_tmp; + u32 cdr_pr_idac_tmp; + + if (pr_idac_major > 0) { + cdr_pr_idac_tmp = FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR, + pr_idac_major - 1); + + dev_dbg(priv->dev, "Fl Out is %d far from target %d with Pr Idac %x. Trying with Pr Idac %x.\n", + fl_out_diff, target_fl_out, cdr_pr_idac_major, cdr_pr_idac_tmp); + + cdr_pr_idac_tmp = an7581_pcs_rx_prcal_idac_minor(priv, target_fl_out, + cdr_pr_idac_tmp); + + fl_out_tmp = an7581_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac_tmp); + fl_out_diff_tmp = abs(fl_out_tmp - target_fl_out); + if (fl_out_diff_tmp < fl_out_diff) { + fl_out = fl_out_tmp; + fl_out_diff = fl_out_diff_tmp; + cdr_pr_idac = cdr_pr_idac_tmp; + } + } + } + dev_dbg(priv->dev, "Selected CDR Pr Idac: %x Fl Out: %x\n", cdr_pr_idac, fl_out); + if (fl_out_diff > 100) + dev_dbg(priv->dev, "Fl Out is %d far from target %d on intermediate calibration.\n", + fl_out_diff, target_fl_out); + + + /* Setup Load Band */ + regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE, + AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF); + + /* Disable force of LPF C previously enabled */ + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN); + + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_B, + AIROHA_PCS_PMA_LOAD_EN); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_1, + AIROHA_PCS_PMA_LPATH_IDAC, + FIELD_PREP(AIROHA_PCS_PMA_LPATH_IDAC, cdr_pr_idac)); + + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB); + + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB); + + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET, + AIROHA_PCS_PMA_SW_REF_RST_N); + + udelay(100); +} + +/* This is used to both calibrate and lock to signal (after a previous + * calibration) after a global reset. + */ +static void an7581_pcs_cdr_reset(struct airoha_pcs_priv *priv, + phy_interface_t interface, bool calibrate) +{ + /* Setup LPF L2D force and disable */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA | + AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA); + + /* Calibrate IDAC and setup Load Band */ + if (calibrate) + an7581_pcs_rx_prcal(priv, interface); + + /* Setup LPF RSTB force and disable */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB | + AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB); + + udelay(700); + + /* Force Enable LPF RSTB */ + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA, + AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB); + + udelay(100); + + /* Force Enable LPF L2D */ + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA, + AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA); + + /* Disable LPF RSTB force bit */ + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB); + + /* Disable LPF L2D force bit */ + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA); +} + +static int an7581_pcs_phya_bringup(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + int calibration_try = 0; + u32 val; + + an7581_pcs_tx_bringup(priv, interface); + an7581_pcs_rx_bringup(priv, interface); + + udelay(100); + +retry_calibration: + an7581_pcs_cdr_reset(priv, interface, priv->manual_rx_calib); + + /* Global reset clear */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET, + AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N | + AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N | + AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N | + AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N | + AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N | + AIROHA_PCS_PMA_SW_TX_FIFO_RST_N | + AIROHA_PCS_PMA_SW_REF_RST_N | + AIROHA_PCS_PMA_SW_ALLPCS_RST_N | + AIROHA_PCS_PMA_SW_PMA_RST_N | + AIROHA_PCS_PMA_SW_TX_RST_N | + AIROHA_PCS_PMA_SW_RX_RST_N | + AIROHA_PCS_PMA_SW_RX_FIFO_RST_N, + AIROHA_PCS_PMA_SW_REF_RST_N); + + udelay(100); + + /* Global reset */ + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET, + AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N | + AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N | + AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N | + AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N | + AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N | + AIROHA_PCS_PMA_SW_TX_FIFO_RST_N | + AIROHA_PCS_PMA_SW_REF_RST_N | + AIROHA_PCS_PMA_SW_ALLPCS_RST_N | + AIROHA_PCS_PMA_SW_PMA_RST_N | + AIROHA_PCS_PMA_SW_TX_RST_N | + AIROHA_PCS_PMA_SW_RX_RST_N | + AIROHA_PCS_PMA_SW_RX_FIFO_RST_N); + + udelay(5000); + + an7581_pcs_cdr_reset(priv, interface, false); + + /* Manual RX calibration is required only for SoC before E2 + * revision. E2+ SoC autocalibrate RX and only CDR reset is needed. + */ + if (!priv->manual_rx_calib) + return 0; + + /* It was discovered that after a global reset and auto mode gets + * actually enabled, the fl_out from calibration might change and + * might deviates a lot from the expected value it was calibrated for. + * To correctly work, the PCS FreqDet module needs to Lock to the fl_out + * (frequency level output) or no signal can correctly be transmitted. + * This is detected by checking the FreqDet module Lock bit. + * + * If it's detected that the FreqDet module is not locked, retry + * calibration. From observation on real hardware with a 10g SFP module, + * it required a maximum of an additional calibration to actually make + * the FreqDet module to lock. Try 10 times before failing to handle + * really strange case. + */ + regmap_read(priv->xfi_pma, AIROHA_PCS_PMA_RX_FREQDET, &val); + if (!(val & AIROHA_PCS_PMA_FBCK_LOCK)) { + if (calibration_try > AIROHA_PCS_MAX_CALIBRATION_TRY) { + dev_err(priv->dev, "No FBCK Lock from FreqDet module after %d calibration try. PCS won't work.\n", + AIROHA_PCS_MAX_CALIBRATION_TRY); + return -EIO; + } + + calibration_try++; + + dev_dbg(priv->dev, "No FBCK Lock from FreqDet module, retry calibration.\n"); + goto retry_calibration; + } + + return 0; +} + +static void an7581_pcs_pll_bringup(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + an7581_pcs_jcpll_bringup(priv, interface); + + udelay(200); + + an7581_pcs_txpll_bringup(priv, interface); + + udelay(200); +} + +int an7581_pcs_bringup(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + /* Enable Analog Common Lane */ + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CMN_EN, + AIROHA_PCS_ANA_CMN_EN); + + /* Setup PLL */ + an7581_pcs_pll_bringup(priv, interface); + + /* Setup PHYA */ + return an7581_pcs_phya_bringup(priv, interface); +} + +void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv) +{ + /* Reset TXPCS on link up */ + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET, + AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N); + + udelay(100); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET, + AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N); +} diff --git a/drivers/net/airoha_eth.c b/drivers/net/airoha_eth.c index 3a0ac7ce368..84ee9b2ad76 100644 --- a/drivers/net/airoha_eth.c +++ b/drivers/net/airoha_eth.c @@ -9,9 +9,11 @@ */ #include <dm.h> +#include <dm/device-internal.h> #include <dm/devres.h> #include <dm/lists.h> #include <mapmem.h> +#include <miiphy.h> #include <net.h> #include <regmap.h> #include <reset.h> @@ -19,12 +21,15 @@ #include <linux/bitfield.h> #include <linux/delay.h> #include <linux/dma-mapping.h> +#include <linux/ethtool.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/time.h> #include <asm/arch/scu-regmap.h> -#define AIROHA_MAX_NUM_GDM_PORTS 1 +#include "airoha/pcs-airoha.h" + +#define AIROHA_MAX_NUM_GDM_PORTS 4 #define AIROHA_MAX_NUM_QDMA 1 #define AIROHA_MAX_NUM_RSTS 3 #define AIROHA_MAX_NUM_XSI_RSTS 4 @@ -38,6 +43,8 @@ #define TX_DSCP_NUM 16 #define RX_DSCP_NUM PKTBUFSRX +#define AIROHA_GDM_PORT_STRING_LEN sizeof("airoha-gdmX") + /* SCU */ #define SCU_SHARE_FEMEM_SEL 0x958 @@ -246,6 +253,21 @@ #define QDMA_ETH_RXMSG_CRSN_MASK GENMASK(20, 16) #define QDMA_ETH_RXMSG_PPE_ENTRY_MASK GENMASK(15, 0) +enum { + FE_PSE_PORT_CDM1, + FE_PSE_PORT_GDM1, + FE_PSE_PORT_GDM2, + FE_PSE_PORT_GDM3, + FE_PSE_PORT_PPE1, + FE_PSE_PORT_CDM2, + FE_PSE_PORT_CDM3, + FE_PSE_PORT_CDM4, + FE_PSE_PORT_PPE2, + FE_PSE_PORT_GDM4, + FE_PSE_PORT_CDM5, + FE_PSE_PORT_DROP = 0xf, +}; + struct airoha_qdma_desc { __le32 rsv; __le32 ctrl; @@ -301,20 +323,30 @@ struct airoha_qdma { struct airoha_gdm_port { struct airoha_qdma *qdma; int id; + + struct udevice *pcs_dev; + phy_interface_t mode; + bool neg_mode; + + struct phy_device *phydev; }; struct airoha_eth { void __iomem *fe_regs; void __iomem *switch_regs; + struct udevice *switch_mdio_dev; struct reset_ctl_bulk rsts; struct reset_ctl_bulk xsi_rsts; + struct airoha_eth_soc_data *soc; + struct airoha_qdma qdma[AIROHA_MAX_NUM_QDMA]; - struct airoha_gdm_port *ports[AIROHA_MAX_NUM_GDM_PORTS]; + char gdm_port_str[AIROHA_MAX_NUM_GDM_PORTS + 1][AIROHA_GDM_PORT_STRING_LEN]; }; struct airoha_eth_soc_data { + u32 version; int num_xsi_rsts; const char * const *xsi_rsts_names; const char *switch_compatible; @@ -397,22 +429,33 @@ static inline void dma_unmap_unaligned(dma_addr_t addr, size_t len, dma_unmap_single(start, end - start, dir); } -static void airoha_fe_maccr_init(struct airoha_eth *eth) +static int airoha_get_fe_port(struct airoha_gdm_port *port) { - int p; - - for (p = 1; p <= ARRAY_SIZE(eth->ports); p++) { - /* - * Disable any kind of CRC drop or offload. - * Enable padding of short TX packets to 60 bytes. - */ - airoha_fe_wr(eth, REG_GDM_FWD_CFG(p), GDM_PAD_EN); + struct airoha_qdma *qdma = port->qdma; + struct airoha_eth *eth = qdma->eth; + + switch (eth->soc->version) { + case 0x7523: + /* FIXME: GDM1 is the only supported port */ + return FE_PSE_PORT_GDM1; + case 0x7581: + default: + return port->id == 4 ? FE_PSE_PORT_GDM4 : port->id; } } -static int airoha_fe_init(struct airoha_eth *eth) +static void airoha_fe_maccr_init(struct airoha_gdm_port *port) +{ + /* + * Disable any kind of CRC drop or offload. + * Enable padding of short TX packets to 60 bytes. + */ + airoha_fe_wr(port->qdma->eth, REG_GDM_FWD_CFG(port->id), GDM_PAD_EN); +} + +static int airoha_fe_init(struct airoha_gdm_port *port) { - airoha_fe_maccr_init(eth); + airoha_fe_maccr_init(port); return 0; } @@ -662,6 +705,36 @@ static int airoha_qdma_init(struct udevice *dev, return airoha_qdma_hw_init(qdma); } +#if defined(CONFIG_PCS_AIROHA) +static int airoha_pcs_init(struct udevice *dev) +{ + struct airoha_gdm_port *port = dev_get_priv(dev); + struct udevice *pcs_dev; + const char *managed; + int ret; + + ret = uclass_get_device_by_phandle(UCLASS_MISC, dev, "pcs", + &pcs_dev); + if (ret || !pcs_dev) + return ret; + + port->pcs_dev = pcs_dev; + port->mode = dev_read_phy_mode(dev); + managed = dev_read_string(dev, "managed"); + port->neg_mode = !strncmp(managed, "in-band-status", + sizeof("in-band-status")); + + airoha_pcs_pre_config(pcs_dev, port->mode); + + ret = airoha_pcs_post_config(pcs_dev, port->mode); + if (ret) + return ret; + + return airoha_pcs_config(pcs_dev, port->neg_mode, + port->mode, NULL, true); +} +#endif + static int airoha_hw_init(struct udevice *dev, struct airoha_eth *eth) { @@ -682,12 +755,12 @@ static int airoha_hw_init(struct udevice *dev, if (ret) return ret; - mdelay(20); - - ret = airoha_fe_init(eth); + ret = reset_deassert_bulk(ð->xsi_rsts); if (ret) return ret; + mdelay(20); + for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) { ret = airoha_qdma_init(dev, eth, ð->qdma[i]); if (ret) @@ -739,11 +812,45 @@ static int airoha_switch_init(struct udevice *dev, struct airoha_eth *eth) return 0; } +static int airoha_alloc_gdm_port(struct udevice *dev, ofnode node) +{ + struct airoha_eth *eth = dev_get_priv(dev); + struct udevice *gdm_dev; + struct driver *gdm_drv; + char *str; + int ret; + u32 id; + + gdm_drv = lists_driver_lookup_name("airoha-eth-port"); + if (!gdm_drv) + return -ENOENT; + + ret = ofnode_read_u32(node, "reg", &id); + if (ret) + return ret; + + if (id > AIROHA_MAX_NUM_GDM_PORTS) + return -EINVAL; + +#if !defined(CONFIG_PCS_AIROHA) + if (id != 1) + return -ENOTSUPP; +#endif + + str = eth->gdm_port_str[id]; + snprintf(str, AIROHA_GDM_PORT_STRING_LEN, + "airoha-gdm%d", id); + + return device_bind_with_driver_data(dev, gdm_drv, str, + (ulong)eth, node, &gdm_dev); +} + static int airoha_eth_probe(struct udevice *dev) { struct airoha_eth_soc_data *data = (void *)dev_get_driver_data(dev); struct airoha_eth *eth = dev_get_priv(dev); struct regmap *scu_regmap; + ofnode node; int i, ret; scu_regmap = airoha_get_scu_regmap(); @@ -756,6 +863,8 @@ static int airoha_eth_probe(struct udevice *dev) */ regmap_write(scu_regmap, SCU_SHARE_FEMEM_SEL, 0x0); + eth->soc = data; + eth->fe_regs = dev_remap_addr_name(dev, "fe"); if (!eth->fe_regs) return -ENOMEM; @@ -795,13 +904,68 @@ static int airoha_eth_probe(struct udevice *dev) if (ret) return ret; - return airoha_switch_init(dev, eth); + ret = airoha_switch_init(dev, eth); + if (ret) + return ret; + + if (eth->switch_mdio_dev) { + if (!device_probe(eth->switch_mdio_dev)) + debug("Warning: failed to probe airoha switch mdio\n"); + } + + ofnode_for_each_subnode(node, dev_ofnode(dev)) { + if (!ofnode_device_is_compatible(node, "airoha,eth-mac")) + continue; + + if (!ofnode_is_enabled(node)) + continue; + + ret = airoha_alloc_gdm_port(dev, node); + if (ret && ret != -ENOTSUPP) + return ret; + } + + return 0; +} + +static int airoha_eth_port_of_to_plat(struct udevice *dev) +{ + struct airoha_gdm_port *port = dev_get_priv(dev); + + return dev_read_u32(dev, "reg", &port->id); +} + +static int airoha_eth_port_probe(struct udevice *dev) +{ + struct airoha_eth *eth = (void *)dev_get_driver_data(dev); + struct airoha_gdm_port *port = dev_get_priv(dev); + int ret; + + port->qdma = ð->qdma[0]; + + ret = airoha_fe_init(port); + if (ret) + return ret; + + if (port->id > 1) { +#if defined(CONFIG_PCS_AIROHA) + ret = airoha_pcs_init(dev); + if (ret) + return ret; + + port->phydev = dm_eth_phy_connect(dev); +#else + return -EINVAL; +#endif + } + + return 0; } static int airoha_eth_init(struct udevice *dev) { - struct airoha_eth *eth = dev_get_priv(dev); - struct airoha_qdma *qdma = ð->qdma[0]; + struct airoha_gdm_port *port = dev_get_priv(dev); + struct airoha_qdma *qdma = port->qdma; struct airoha_queue *q; int qid; @@ -814,13 +978,65 @@ static int airoha_eth_init(struct udevice *dev) GLOBAL_CFG_TX_DMA_EN_MASK | GLOBAL_CFG_RX_DMA_EN_MASK); +#if defined(CONFIG_PCS_AIROHA) + if (port->id > 1) { + struct phy_device *phydev = port->phydev; + int speed, duplex; + int ret; + + if (phydev) { + ret = phy_config(phydev); + if (ret) + return ret; + + ret = phy_startup(phydev); + if (ret) + return ret; + + speed = phydev->speed; + duplex = phydev->duplex; + } else { + duplex = DUPLEX_FULL; + + /* Hardcode speed for linkup */ + switch (port->mode) { + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + speed = SPEED_10000; + break; + case PHY_INTERFACE_MODE_2500BASEX: + speed = SPEED_2500; + break; + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + speed = SPEED_1000; + break; + default: + return -EINVAL; + } + } + + airoha_pcs_link_up(port->pcs_dev, port->neg_mode, port->mode, + speed, duplex); + } +#endif + return 0; } static void airoha_eth_stop(struct udevice *dev) { - struct airoha_eth *eth = dev_get_priv(dev); - struct airoha_qdma *qdma = ð->qdma[0]; + struct airoha_gdm_port *port = dev_get_priv(dev); + struct airoha_qdma *qdma = port->qdma; + +#if defined(CONFIG_PCS_AIROHA) + if (port->id > 1) { + if (port->phydev) + phy_shutdown(port->phydev); + + airoha_pcs_link_down(port->pcs_dev); + } +#endif airoha_qdma_clear(qdma, REG_QDMA_GLOBAL_CFG, GLOBAL_CFG_TX_DMA_EN_MASK | @@ -829,8 +1045,8 @@ static void airoha_eth_stop(struct udevice *dev) static int airoha_eth_send(struct udevice *dev, void *packet, int length) { - struct airoha_eth *eth = dev_get_priv(dev); - struct airoha_qdma *qdma = ð->qdma[0]; + struct airoha_gdm_port *port = dev_get_priv(dev); + struct airoha_qdma *qdma = port->qdma; struct airoha_qdma_desc *desc; struct airoha_queue *q; dma_addr_t dma_addr; @@ -852,7 +1068,7 @@ static int airoha_eth_send(struct udevice *dev, void *packet, int length) desc = &q->desc[q->head]; index = (q->head + 1) % q->ndesc; - fport = 1; + fport = airoha_get_fe_port(port); msg0 = 0; msg1 = FIELD_PREP(QDMA_ETH_TXMSG_FPORT_MASK, fport) | @@ -894,8 +1110,8 @@ static int airoha_eth_send(struct udevice *dev, void *packet, int length) static int airoha_eth_recv(struct udevice *dev, int flags, uchar **packetp) { - struct airoha_eth *eth = dev_get_priv(dev); - struct airoha_qdma *qdma = ð->qdma[0]; + struct airoha_gdm_port *port = dev_get_priv(dev); + struct airoha_qdma *qdma = port->qdma; struct airoha_qdma_desc *desc; struct airoha_queue *q; u16 length; @@ -922,8 +1138,8 @@ static int airoha_eth_recv(struct udevice *dev, int flags, uchar **packetp) static int arht_eth_free_pkt(struct udevice *dev, uchar *packet, int length) { - struct airoha_eth *eth = dev_get_priv(dev); - struct airoha_qdma *qdma = ð->qdma[0]; + struct airoha_gdm_port *port = dev_get_priv(dev); + struct airoha_qdma *qdma = port->qdma; struct airoha_queue *q; int qid; @@ -964,8 +1180,9 @@ static int arht_eth_free_pkt(struct udevice *dev, uchar *packet, int length) static int arht_eth_write_hwaddr(struct udevice *dev) { + struct airoha_gdm_port *port = dev_get_priv(dev); struct eth_pdata *pdata = dev_get_plat(dev); - struct airoha_eth *eth = dev_get_priv(dev); + struct airoha_qdma *qdma = port->qdma; unsigned char *mac = pdata->enetaddr; u32 macaddr_lsb, macaddr_msb; @@ -977,8 +1194,8 @@ static int arht_eth_write_hwaddr(struct udevice *dev) FIELD_PREP(SMACCR1_MAC0, mac[0]); /* Set MAC for Switch */ - airoha_switch_wr(eth, SWITCH_SMACCR0, macaddr_lsb); - airoha_switch_wr(eth, SWITCH_SMACCR1, macaddr_msb); + airoha_switch_wr(qdma->eth, SWITCH_SMACCR0, macaddr_lsb); + airoha_switch_wr(qdma->eth, SWITCH_SMACCR1, macaddr_msb); return 0; } @@ -986,9 +1203,15 @@ static int arht_eth_write_hwaddr(struct udevice *dev) static int airoha_eth_bind(struct udevice *dev) { struct airoha_eth_soc_data *data = (void *)dev_get_driver_data(dev); + struct airoha_eth *eth = dev_get_priv(dev); ofnode switch_node, mdio_node; - struct udevice *mdio_dev; - int ret = 0; + int ret; + + /* + * Force Probe as we set the Main ETH driver as misc + * to register multiple eth port for each GDM + */ + dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND); if (!CONFIG_IS_ENABLED(MDIO_MT7531_MMIO)) return 0; @@ -1006,8 +1229,8 @@ static int airoha_eth_bind(struct udevice *dev) return 0; } - ret = device_bind_driver_to_node(dev, "mt7531-mdio-mmio", "mdio", - mdio_node, &mdio_dev); + ret = device_bind_driver_to_node(dev, "mt7531-mdio-mmio", "mt7531-mdio", + mdio_node, ð->switch_mdio_dev); if (ret) debug("Warning: failed to bind mdio controller\n"); @@ -1015,12 +1238,14 @@ static int airoha_eth_bind(struct udevice *dev) } static const struct airoha_eth_soc_data en7523_data = { + .version = 0x7523, .xsi_rsts_names = en7523_xsi_rsts_names, .num_xsi_rsts = ARRAY_SIZE(en7523_xsi_rsts_names), .switch_compatible = "airoha,en7523-switch", }; static const struct airoha_eth_soc_data en7581_data = { + .version = 0x7581, .xsi_rsts_names = en7581_xsi_rsts_names, .num_xsi_rsts = ARRAY_SIZE(en7581_xsi_rsts_names), .switch_compatible = "airoha,en7581-switch", @@ -1045,13 +1270,21 @@ static const struct eth_ops airoha_eth_ops = { .write_hwaddr = arht_eth_write_hwaddr, }; +U_BOOT_DRIVER(airoha_eth_port) = { + .name = "airoha-eth-port", + .id = UCLASS_ETH, + .of_to_plat = airoha_eth_port_of_to_plat, + .probe = airoha_eth_port_probe, + .ops = &airoha_eth_ops, + .priv_auto = sizeof(struct airoha_gdm_port), + .plat_auto = sizeof(struct eth_pdata), +}; + U_BOOT_DRIVER(airoha_eth) = { .name = "airoha-eth", - .id = UCLASS_ETH, + .id = UCLASS_MISC, .of_match = airoha_eth_ids, .probe = airoha_eth_probe, .bind = airoha_eth_bind, - .ops = &airoha_eth_ops, .priv_auto = sizeof(struct airoha_eth), - .plat_auto = sizeof(struct eth_pdata), }; diff --git a/drivers/net/bnxt/Kconfig b/drivers/net/bnxt/Kconfig index 6ff3ffa137b..e25ed479678 100644 --- a/drivers/net/bnxt/Kconfig +++ b/drivers/net/bnxt/Kconfig @@ -1,6 +1,6 @@ config BNXT_ETH bool "BNXT PCI support" - select PCI_INIT_R + depends on PCI help This driver implements support for bnxt pci controller driver of ethernet class. diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 8a396d0b29e..0f31d646845 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1621,6 +1621,10 @@ static const struct udevice_id eqos_ids[] = { #endif #if IS_ENABLED(CONFIG_DWC_ETH_QOS_ROCKCHIP) { + .compatible = "rockchip,rk3506-gmac", + .data = (ulong)&eqos_rockchip_config + }, + { .compatible = "rockchip,rk3528-gmac", .data = (ulong)&eqos_rockchip_config }, diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c index d646d3ebac8..4ccefda0ef5 100644 --- a/drivers/net/dwc_eth_qos_rockchip.c +++ b/drivers/net/dwc_eth_qos_rockchip.c @@ -50,6 +50,80 @@ struct rockchip_platform_data { (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) +#define RK3506_GRF_SOC_CON8 0x0020 +#define RK3506_GRF_SOC_CON11 0x002c + +#define RK3506_GMAC_RMII_MODE GRF_BIT(1) + +#define RK3506_GMAC_CLK_RMII_DIV2 GRF_BIT(3) +#define RK3506_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(3) + +#define RK3506_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(5) +#define RK3506_GMAC_CLK_SELECT_IO GRF_BIT(5) + +#define RK3506_GMAC_CLK_RMII_GATE GRF_BIT(2) +#define RK3506_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(2) + +static int rk3506_set_to_rgmii(struct udevice *dev, + int tx_delay, int rx_delay) +{ + return -EINVAL; +} + +static int rk3506_set_to_rmii(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct rockchip_platform_data *data = pdata->priv_pdata; + u32 reg; + + reg = data->id == 1 ? RK3506_GRF_SOC_CON11 : + RK3506_GRF_SOC_CON8; + regmap_write(data->grf, reg, RK3506_GMAC_RMII_MODE); + + return 0; +} + +static int rk3506_set_gmac_speed(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_plat(dev); + struct rockchip_platform_data *data = pdata->priv_pdata; + u32 val, reg; + + switch (eqos->phy->speed) { + case SPEED_10: + val = RK3506_GMAC_CLK_RMII_DIV20; + break; + case SPEED_100: + val = RK3506_GMAC_CLK_RMII_DIV2; + break; + default: + return -EINVAL; + } + + reg = data->id == 1 ? RK3506_GRF_SOC_CON11 : + RK3506_GRF_SOC_CON8; + regmap_write(data->grf, reg, val); + + return 0; +} + +static void rk3506_set_clock_selection(struct udevice *dev, bool enable) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct rockchip_platform_data *data = pdata->priv_pdata; + u32 val, reg; + + val = data->clock_input ? RK3506_GMAC_CLK_SELECT_IO : + RK3506_GMAC_CLK_SELECT_CRU; + val |= enable ? RK3506_GMAC_CLK_RMII_NOGATE : + RK3506_GMAC_CLK_RMII_GATE; + + reg = data->id == 1 ? RK3506_GRF_SOC_CON11 : + RK3506_GRF_SOC_CON8; + regmap_write(data->grf, reg, val); +} + #define RK3528_VO_GRF_GMAC_CON 0x0018 #define RK3528_VPU_GRF_GMAC_CON5 0x0018 #define RK3528_VPU_GRF_GMAC_CON6 0x001c @@ -535,6 +609,18 @@ static void rk3588_set_clock_selection(struct udevice *dev, bool enable) static const struct rk_gmac_ops rk_gmac_ops[] = { { + .compatible = "rockchip,rk3506-gmac", + .set_to_rgmii = rk3506_set_to_rgmii, + .set_to_rmii = rk3506_set_to_rmii, + .set_gmac_speed = rk3506_set_gmac_speed, + .set_clock_selection = rk3506_set_clock_selection, + .regs = { + 0xff4c8000, /* gmac0 */ + 0xff4d0000, /* gmac1 */ + 0x0, /* sentinel */ + }, + }, + { .compatible = "rockchip,rk3528-gmac", .set_to_rgmii = rk3528_set_to_rgmii, .set_to_rmii = rk3528_set_to_rmii, diff --git a/drivers/net/dwc_eth_xgmac.c b/drivers/net/dwc_eth_xgmac.c index 458b87af7a2..2ab5ec5f0d9 100644 --- a/drivers/net/dwc_eth_xgmac.c +++ b/drivers/net/dwc_eth_xgmac.c @@ -497,20 +497,6 @@ static int xgmac_start(struct udevice *dev) xgmac->reg_access_ok = true; - ret = wait_for_bit_le32(&xgmac->dma_regs->mode, - XGMAC_DMA_MODE_SWR, false, - xgmac->config->swr_wait, false); - if (ret) { - pr_err("%s XGMAC_DMA_MODE_SWR stuck: %d\n", dev->name, ret); - goto err_stop_resets; - } - - ret = xgmac->config->ops->xgmac_calibrate_pads(dev); - if (ret < 0) { - pr_err("%s xgmac_calibrate_pads() failed: %d\n", dev->name, ret); - goto err_stop_resets; - } - /* * if PHY was already connected and configured, * don't need to reconnect/reconfigure again @@ -559,6 +545,20 @@ static int xgmac_start(struct udevice *dev) goto err_shutdown_phy; } + ret = wait_for_bit_le32(&xgmac->dma_regs->mode, + XGMAC_DMA_MODE_SWR, false, + xgmac->config->swr_wait, false); + if (ret) { + pr_err("%s XGMAC_DMA_MODE_SWR stuck: %d\n", dev->name, ret); + goto err_stop_resets; + } + + ret = xgmac->config->ops->xgmac_calibrate_pads(dev); + if (ret < 0) { + pr_err("%s xgmac_calibrate_pads() failed: %d\n", dev->name, ret); + goto err_stop_resets; + } + /* Configure MTL */ /* Enable Store and Forward mode for TX */ diff --git a/drivers/net/dwmac_s700.c b/drivers/net/dwmac_s700.c index 969d247b4f3..76daab961c0 100644 --- a/drivers/net/dwmac_s700.c +++ b/drivers/net/dwmac_s700.c @@ -5,7 +5,6 @@ * Actions DWMAC specific glue layer */ -#include <asm/global_data.h> #include <asm/io.h> #include <dm.h> #include <clk.h> @@ -24,8 +23,6 @@ #define RMII_REF_CLK_MFP_CTL0 (0x0 << 6) #define CLKO_25M_EN_MFP_CTL3 BIT(30) -DECLARE_GLOBAL_DATA_PTR; - static void dwmac_board_setup(void) { clrbits_le32(MFP_CTL0, (RMII_TXD01_MFP_CTL0 | RMII_RXD01_MFP_CTL0 | diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 1c51e936b5b..3d32bad0831 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -18,7 +18,6 @@ #include <net.h> #include <netdev.h> #include <asm/cache.h> -#include <asm/global_data.h> #include <linux/delay.h> #include <power/regulator.h> @@ -36,8 +35,6 @@ #include "fec_mxc.h" #include <eth_phy.h> -DECLARE_GLOBAL_DATA_PTR; - /* * Timeout the transfer after 5 mS. This is usually a bit more, since * the code in the tightloops this timeout is used in adds some overhead. diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index c8cfe7448d4..2b6080dd9ee 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -11,7 +11,6 @@ #include <net.h> #include <phy.h> #include <syscon.h> -#include <asm/global_data.h> #include <asm/arch-rockchip/periph.h> #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/hardware.h> @@ -28,7 +27,6 @@ #include <linux/bitops.h> #include "designware.h" -DECLARE_GLOBAL_DATA_PTR; #define DELAY_ENABLE(soc, tx, rx) \ (((tx) ? soc##_TXCLK_DLY_ENA_GMAC_ENABLE : soc##_TXCLK_DLY_ENA_GMAC_DISABLE) | \ ((rx) ? soc##_RXCLK_DLY_ENA_GMAC_ENABLE : soc##_RXCLK_DLY_ENA_GMAC_DISABLE)) diff --git a/drivers/net/mdio-mt7531-mmio.c b/drivers/net/mdio-mt7531-mmio.c index 5a0725010f2..930454a9b0e 100644 --- a/drivers/net/mdio-mt7531-mmio.c +++ b/drivers/net/mdio-mt7531-mmio.c @@ -6,6 +6,8 @@ #include <linux/iopoll.h> #include <miiphy.h> +#include "mdio-mt7531-mmio.h" + #define MT7531_PHY_IAC 0x701c #define MT7531_PHY_ACS_ST BIT(31) #define MT7531_MDIO_REG_ADDR_CL22 GENMASK(29, 25) @@ -25,11 +27,7 @@ #define MT7531_MDIO_TIMEOUT 100000 #define MT7531_MDIO_SLEEP 20 -struct mt7531_mdio_priv { - phys_addr_t switch_regs; -}; - -static int mt7531_mdio_wait_busy(struct mt7531_mdio_priv *priv) +static int mt7531_mdio_wait_busy(struct mt7531_mdio_mmio_priv *priv) { unsigned int busy; @@ -38,7 +36,7 @@ static int mt7531_mdio_wait_busy(struct mt7531_mdio_priv *priv) MT7531_MDIO_SLEEP, MT7531_MDIO_TIMEOUT); } -static int mt7531_mdio_read(struct mt7531_mdio_priv *priv, int addr, int devad, int reg) +static int mt7531_mdio_read(struct mt7531_mdio_mmio_priv *priv, int addr, int devad, int reg) { u32 val; @@ -75,7 +73,7 @@ static int mt7531_mdio_read(struct mt7531_mdio_priv *priv, int addr, int devad, return val & MT7531_MDIO_RW_DATA; } -static int mt7531_mdio_write(struct mt7531_mdio_priv *priv, int addr, int devad, +static int mt7531_mdio_write(struct mt7531_mdio_mmio_priv *priv, int addr, int devad, int reg, u16 value) { u32 val; @@ -115,7 +113,7 @@ static int mt7531_mdio_write(struct mt7531_mdio_priv *priv, int addr, int devad, int mt7531_mdio_mmio_read(struct mii_dev *bus, int addr, int devad, int reg) { - struct mt7531_mdio_priv *priv = bus->priv; + struct mt7531_mdio_mmio_priv *priv = bus->priv; return mt7531_mdio_read(priv, addr, devad, reg); } @@ -123,14 +121,14 @@ int mt7531_mdio_mmio_read(struct mii_dev *bus, int addr, int devad, int reg) int mt7531_mdio_mmio_write(struct mii_dev *bus, int addr, int devad, int reg, u16 value) { - struct mt7531_mdio_priv *priv = bus->priv; + struct mt7531_mdio_mmio_priv *priv = bus->priv; return mt7531_mdio_write(priv, addr, devad, reg, value); } static int dm_mt7531_mdio_read(struct udevice *dev, int addr, int devad, int reg) { - struct mt7531_mdio_priv *priv = dev_get_priv(dev); + struct mt7531_mdio_mmio_priv *priv = dev_get_priv(dev); return mt7531_mdio_read(priv, addr, devad, reg); } @@ -138,7 +136,7 @@ static int dm_mt7531_mdio_read(struct udevice *dev, int addr, int devad, int reg static int dm_mt7531_mdio_write(struct udevice *dev, int addr, int devad, int reg, u16 value) { - struct mt7531_mdio_priv *priv = dev_get_priv(dev); + struct mt7531_mdio_mmio_priv *priv = dev_get_priv(dev); return mt7531_mdio_write(priv, addr, devad, reg, value); } @@ -150,7 +148,7 @@ static const struct mdio_ops mt7531_mdio_ops = { static int mt7531_mdio_probe(struct udevice *dev) { - struct mt7531_mdio_priv *priv = dev_get_priv(dev); + struct mt7531_mdio_mmio_priv *priv = dev_get_priv(dev); ofnode switch_node; switch_node = ofnode_get_parent(dev_ofnode(dev)); @@ -169,5 +167,5 @@ U_BOOT_DRIVER(mt7531_mdio) = { .id = UCLASS_MDIO, .probe = mt7531_mdio_probe, .ops = &mt7531_mdio_ops, - .priv_auto = sizeof(struct mt7531_mdio_priv), + .priv_auto = sizeof(struct mt7531_mdio_mmio_priv), }; diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c index 1640868c24a..baa18202d6e 100644 --- a/drivers/net/mvneta.c +++ b/drivers/net/mvneta.c @@ -20,7 +20,6 @@ #include <config.h> #include <malloc.h> #include <asm/cache.h> -#include <asm/global_data.h> #include <asm/io.h> #include <dm/device_compat.h> #include <dm/devres.h> @@ -37,8 +36,6 @@ #include <linux/mbus.h> #include <asm-generic/gpio.h> -DECLARE_GLOBAL_DATA_PTR; - #define MVNETA_NR_CPUS 1 #define ETH_HLEN 14 /* Total octets in header */ diff --git a/drivers/net/octeontx/smi.c b/drivers/net/octeontx/smi.c index 217bcac2ce2..5a822b64427 100644 --- a/drivers/net/octeontx/smi.c +++ b/drivers/net/octeontx/smi.c @@ -10,15 +10,12 @@ #include <pci.h> #include <pci_ids.h> #include <phy.h> -#include <asm/global_data.h> #include <asm/io.h> #include <linux/ctype.h> #include <linux/delay.h> #define PCI_DEVICE_ID_OCTEONTX_SMI 0xA02B -DECLARE_GLOBAL_DATA_PTR; - enum octeontx_smi_mode { CLAUSE22 = 0, CLAUSE45 = 1, diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 709f1c91eb2..5d2277a4602 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -91,6 +91,7 @@ menuconfig PHY_AQUANTIA config PHY_AQUANTIA_UPLOAD_FW bool "Aquantia firmware loading support" depends on PHY_AQUANTIA + depends on SUPPORTS_FW_LOADER select FW_LOADER help Aquantia PHYs use firmware which can be either loaded automatically diff --git a/drivers/net/phy/airoha/Kconfig b/drivers/net/phy/airoha/Kconfig index 999564e4848..da8747939e3 100644 --- a/drivers/net/phy/airoha/Kconfig +++ b/drivers/net/phy/airoha/Kconfig @@ -5,7 +5,8 @@ menuconfig PHY_AIROHA config PHY_AIROHA_EN8811 bool "Airoha Ethernet EN8811H support" depends on PHY_AIROHA + depends on SUPPORTS_FW_LOADER select FW_LOADER help AIROHA EN8811H supported. - + AIROHA AN8811HB supported. diff --git a/drivers/net/phy/airoha/air_en8811.c b/drivers/net/phy/airoha/air_en8811.c index 1a628ede82b..0b974472732 100644 --- a/drivers/net/phy/airoha/air_en8811.c +++ b/drivers/net/phy/airoha/air_en8811.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Driver for the Airoha EN8811H 2.5 Gigabit PHY. + * Driver for the Airoha EN8811H and AN8811HB 2.5 Gigabit PHY. * * Limitations of the EN8811H: * - Only full duplex supported @@ -8,9 +8,8 @@ * * Source originated from linux air_en8811h.c * - * Copyright (C) 2025 Airoha Technology Corp. + * Copyright (C) 2025, 2026 Airoha Technology Corp. */ - #include <phy.h> #include <errno.h> #include <log.h> @@ -20,27 +19,15 @@ #include <asm/unaligned.h> #include <linux/iopoll.h> #include <linux/bitops.h> +#include <linux/bitfield.h> #include <linux/compat.h> #include <dm/device_compat.h> #include <u-boot/crc.h> -#define EN8811H_PHY_ID 0x03a2a411 - -#define AIR_FW_ADDR_DM 0x00000000 -#define AIR_FW_ADDR_DSP 0x00100000 - -#define EN8811H_MD32_DM_SIZE 0x4000 -#define EN8811H_MD32_DSP_SIZE 0x20000 - -#define EN8811H_FW_CTRL_1 0x0f0018 -#define EN8811H_FW_CTRL_1_START 0x0 -#define EN8811H_FW_CTRL_1_FINISH 0x1 -#define EN8811H_FW_CTRL_2 0x800000 -#define EN8811H_FW_CTRL_2_LOADING BIT(11) - /* MII Registers */ #define AIR_AUX_CTRL_STATUS 0x1d #define AIR_AUX_CTRL_STATUS_SPEED_MASK GENMASK(4, 2) +#define AIR_AUX_CTRL_STATUS_SPEED_10 0x0 #define AIR_AUX_CTRL_STATUS_SPEED_100 0x4 #define AIR_AUX_CTRL_STATUS_SPEED_1000 0x8 #define AIR_AUX_CTRL_STATUS_SPEED_2500 0xc @@ -49,6 +36,7 @@ #define AIR_PHY_PAGE_STANDARD 0x0000 #define AIR_PHY_PAGE_EXTENDED_4 0x0004 +#define AIR_PBUS_MODE_ADDR_HIGH 0x1c /* MII Registers Page 4 */ #define AIR_BPBUS_MODE 0x10 #define AIR_BPBUS_MODE_ADDR_FIXED 0x0000 @@ -63,8 +51,16 @@ #define AIR_BPBUS_RD_DATA_LOW 0x18 /* Registers on MDIO_MMD_VEND1 */ -#define EN8811H_PHY_FW_STATUS 0x8009 -#define EN8811H_PHY_READY 0x02 +#define AIR_PHY_MCU_CMD_1 0x800c +#define AIR_PHY_MCU_CMD_1_MODE1 0x0 +#define AIR_PHY_MCU_CMD_2 0x800d +#define AIR_PHY_MCU_CMD_2_MODE1 0x0 +#define AIR_PHY_MCU_CMD_3 0x800e +#define AIR_PHY_MCU_CMD_3_MODE1 0x1101 +#define AIR_PHY_MCU_CMD_3_DOCMD 0x1100 +#define AIR_PHY_MCU_CMD_4 0x800f +#define AIR_PHY_MCU_CMD_4_MODE1 0x0002 +#define AIR_PHY_MCU_CMD_4_INTCLR 0x00e4 /* Registers on MDIO_MMD_VEND2 */ #define AIR_PHY_LED_BCR 0x021 @@ -77,7 +73,7 @@ #define AIR_PHY_LED_DUR_BLINK 0x023 -#define AIR_PHY_LED_ON(i) (0x024 + ((i) * 2)) +#define AIR_PHY_LED_ON(i) (0x024 + ((i) * 2)) #define AIR_PHY_LED_ON_MASK (GENMASK(6, 0) | BIT(8)) #define AIR_PHY_LED_ON_LINK1000 BIT(0) #define AIR_PHY_LED_ON_LINK100 BIT(1) @@ -90,7 +86,7 @@ #define AIR_PHY_LED_ON_POLARITY BIT(14) #define AIR_PHY_LED_ON_ENABLE BIT(15) -#define AIR_PHY_LED_BLINK(i) (0x025 + ((i) * 2)) +#define AIR_PHY_LED_BLINK(i) (0x025 + ((i) * 2)) #define AIR_PHY_LED_BLINK_1000TX BIT(0) #define AIR_PHY_LED_BLINK_1000RX BIT(1) #define AIR_PHY_LED_BLINK_100TX BIT(2) @@ -104,21 +100,101 @@ #define AIR_PHY_LED_BLINK_2500TX BIT(10) #define AIR_PHY_LED_BLINK_2500RX BIT(11) +/* Registers on BUCKPBUS */ +#define AIR_PHY_CONTROL 0x3a9c +#define AIR_PHY_CONTROL_SURGE_5R BIT(3) +#define AIR_PHY_CONTROL_INTERNAL BIT(11) + +/* Led definitions */ +#define EN8811H_LED_COUNT 3 + +/* Firmware registers */ +#define AIR_FW_ADDR_DM 0x00000000 +#define AIR_FW_ADDR_DSP 0x00100000 +#define EN8811H_FW_CTRL_1 0x0f0018 +#define EN8811H_FW_CTRL_1_START 0x0 +#define EN8811H_FW_CTRL_1_FINISH 0x1 +#define EN8811H_FW_CTRL_2 0x800000 +#define EN8811H_FW_CTRL_2_LOADING BIT(11) +#define EN8811H_PHY_FW_STATUS 0x8009 +#define EN8811H_PHY_READY 0x02 +#define AIR_PHY_FW_STATUS 0x8009 +#define AIR_PHY_READY 0x02 + +#define AIR_PHY_FW_CTRL_1 0x0f0018 +#define AIR_PHY_FW_CTRL_1_START 0x0 +#define AIR_PHY_FW_CTRL_1_FINISH 0x1 + +/* EN8811H */ +#define EN8811H_PHY_ID 0x03a2a411 +#define EN8811H_MD32_DM_SIZE 0x4000 +#define EN8811H_MD32_DSP_SIZE 0x20000 #define EN8811H_FW_VERSION 0x3b3c #define EN8811H_POLARITY 0xca0f8 #define EN8811H_POLARITY_TX_NORMAL BIT(0) #define EN8811H_POLARITY_RX_REVERSE BIT(1) - #define EN8811H_CLK_CGM 0xcf958 #define EN8811H_CLK_CGM_CKO BIT(26) #define EN8811H_HWTRAP1 0xcf914 #define EN8811H_HWTRAP1_CKO BIT(12) -#define clear_bit(bit, bitmap) __clear_bit(bit, bitmap) - -/* Led definitions */ -#define EN8811H_LED_COUNT 3 +/* AN8811HB */ +#define AN8811HB_PHY_ID 0xc0ff04a0 +#define AIR_MD32_DM_SIZE 0x8000 +#define AIR_MD32_DSP_SIZE 0x20000 +#define AIR_PHY_MD32FW_VERSION 0x3b3c + +#define AN8811HB_GPIO_OUTPUT 0x5cf8b8 +#define AN8811HB_GPIO_OUTPUT_MASK GENMASK(15, 0) +#define AN8811HB_GPIO_OUTPUT_345 (BIT(3) | BIT(4) | BIT(5)) +#define AN8811HB_GPIO_OUTPUT_0115 (BIT(0) | BIT(1) | BIT(15)) +#define AN8811HB_GPIO_SEL_1 0x5cf8bc +#define AN8811HB_GPIO_SEL_1_0_MASK GENMASK(2, 0) +#define AN8811HB_GPIO_SEL_1_1_MASK GENMASK(6, 4) +#define AN8811HB_GPIO_SEL_1_0 FIELD_PREP(AN8811HB_GPIO_SEL_1_0_MASK, 1) +#define AN8811HB_GPIO_SEL_1_1 FIELD_PREP(AN8811HB_GPIO_SEL_1_1_MASK, 0) +#define AN8811HB_GPIO_SEL_2 0x5cf8c0 +#define AN8811HB_GPIO_SEL_2_15_MASK GENMASK(30, 28) +#define AN8811HB_GPIO_SEL_2_15 FIELD_PREP(AN8811HB_GPIO_SEL_2_15_MASK, 2) + +#define AN8811HB_CRC_PM_SET1 0xf020c +#define AN8811HB_CRC_PM_MON2 0xf0218 +#define AN8811HB_CRC_PM_MON3 0xf021c +#define AN8811HB_CRC_DM_SET1 0xf0224 +#define AN8811HB_CRC_DM_MON2 0xf0230 +#define AN8811HB_CRC_DM_MON3 0xf0234 +#define AN8811HB_CRC_RD_EN BIT(0) +#define AN8811HB_CRC_ST (BIT(0) | BIT(1)) +#define AN8811HB_CRC_CHECK_PASS BIT(0) + +#define AN8811HB_TX_POLARITY 0x5ce004 +#define AN8811HB_TX_POLARITY_NORMAL BIT(7) +#define AN8811HB_RX_POLARITY 0x5ce61c +#define AN8811HB_RX_POLARITY_NORMAL BIT(7) + +#define AN8811HB_HWTRAP1 0x5cf910 +#define AN8811HB_HWTRAP2 0x5cf914 +#define AN8811HB_HWTRAP2_CKO BIT(28) +#define AN8811HB_HWTRAP2_PKG (BIT(12) | BIT(13) | BIT(14)) +#define AN8811HB_PRO_ID 0x5cf920 +#define AN8811HB_PRO_ID_VERSION GENMASK(3, 0) + +#define AN8811HB_CLK_DRV 0x5cf9e4 +#define AN8811HB_CLK_DRV_CKO_MASK GENMASK(14, 12) +#define AN8811HB_CLK_DRV_CKOPWD BIT(12) +#define AN8811HB_CLK_DRV_CKO_LDPWD BIT(13) +#define AN8811HB_CLK_DRV_CKO_LPPWD BIT(14) + +#define AN8811HB_MCU_SW_RST 0x5cf9f8 +#define AN8811HB_MCU_SW_RST_HOLD BIT(16) +#define AN8811HB_MCU_SW_RST_RUN (BIT(16) | BIT(0)) +#define AN8811HB_MCU_SW_START 0x5cf9fc +#define AN8811HB_MCU_SW_START_EN BIT(16) + +#define clear_bit(bit, bitmap) __clear_bit(bit, bitmap) + +#define SCRIPT_NAME(name) #name "_load_firmware" struct led { unsigned long rules; @@ -191,11 +267,48 @@ enum air_led_trigger_netdev_modes { #define AIR_PHY_LED_DUR (AIR_PHY_LED_DUR_UNIT << AIR_PHY_LED_DUR_BLINK_64MS) struct en8811h_priv { - int firmware_version; + u32 firmware_version; bool mcu_needs_restart; struct led led[EN8811H_LED_COUNT]; + u32 pro_id; + u32 pkg_sel; + u32 mem_size; + const char *script_name; }; +static int air_pbus_reg_write(struct phy_device *phydev, + u32 pbus_reg, u32 pbus_data) +{ + int pbus_addr = (phydev->addr) + 8; + struct mii_dev *bus = phydev->bus; + int ret; + + ret = bus->write(bus, pbus_addr, MDIO_DEVAD_NONE, + AIR_EXT_PAGE_ACCESS, + (pbus_reg >> 16)); + if (ret < 0) + return ret; + + ret = bus->write(bus, pbus_addr, MDIO_DEVAD_NONE, + AIR_PBUS_MODE_ADDR_HIGH, + ((pbus_reg & GENMASK(15, 6)) >> 6)); + if (ret < 0) + return ret; + + ret = bus->write(bus, pbus_addr, MDIO_DEVAD_NONE, + ((pbus_reg & GENMASK(5, 2)) >> 2), + (pbus_data & GENMASK(15, 0))); + if (ret < 0) + return ret; + + ret = bus->write(bus, pbus_addr, MDIO_DEVAD_NONE, 0x10, + ((pbus_data & GENMASK(31, 16)) >> 16)); + if (ret < 0) + return ret; + + return ret; +} + static int air_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address, u32 pbus_data) { @@ -359,8 +472,8 @@ restore_page: static int air_write_buf(struct phy_device *phydev, unsigned long address, unsigned long array_size, const unsigned char *buffer) { - unsigned int offset; int ret, saved_page; + u32 offset; u16 val; saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); @@ -419,18 +532,144 @@ static int en8811h_wait_mcu_ready(struct phy_device *phydev) return ret; } -int en8811h_read_fw(void **fw, size_t *fwsize) +static int an8811hb_check_crc(struct phy_device *phydev, + u32 set1, u32 mon2, u32 mon3) +{ + int ret, retry = 10; + u32 pbus_value; + + /* Configure CRC */ + ret = air_buckpbus_reg_modify(phydev, set1, AN8811HB_CRC_RD_EN, + AN8811HB_CRC_RD_EN); + if (ret < 0) + return ret; + + ret = air_buckpbus_reg_read(phydev, set1, &pbus_value); + if (ret < 0) + return ret; + + debug("%d: reg 0x%x val 0x%x!\n", __LINE__, set1, pbus_value); + + do { + mdelay(300); + + ret = air_buckpbus_reg_read(phydev, mon2, &pbus_value); + if (ret < 0) + return ret; + + debug("%d: reg 0x%x val 0x%x!\n", __LINE__, mon2, pbus_value); + + if (pbus_value & AN8811HB_CRC_ST) { + ret = air_buckpbus_reg_read(phydev, mon3, &pbus_value); + if (ret < 0) + return ret; + + debug("%d: reg 0x%x val 0x%x!\n", __LINE__, mon3, + pbus_value); + + if (pbus_value & AN8811HB_CRC_CHECK_PASS) + debug("CRC Check PASS!\n"); + else + dev_err(phydev->dev, "CRC Check FAIL!(0x%lx)\n", + pbus_value & AN8811HB_CRC_CHECK_PASS); + + break; + } + + if (!retry) { + dev_err(phydev->dev, + "CRC Check is not ready.(Status %u)\n", + pbus_value); + return -ENODEV; + } + } while (--retry); + + ret = air_buckpbus_reg_modify(phydev, set1, AN8811HB_CRC_RD_EN, 0); + if (ret < 0) + return ret; + + ret = air_buckpbus_reg_read(phydev, set1, &pbus_value); + if (ret < 0) + return ret; + + debug("%d: reg 0x%x val 0x%x!\n", __LINE__, set1, pbus_value); + + return ret; +} + +static int an8811hb_mcu_assert(struct phy_device *phydev) +{ + int ret; + + ret = air_pbus_reg_write(phydev, AN8811HB_MCU_SW_RST, + AN8811HB_MCU_SW_RST_HOLD); + if (ret < 0) + return ret; + + ret = air_pbus_reg_write(phydev, AN8811HB_MCU_SW_START, 0); + if (ret < 0) + return ret; + + debug("MCU asserted\n"); + mdelay(50); + + return ret; +} + +static int an8811hb_mcu_deassert(struct phy_device *phydev) +{ + int ret; + + ret = air_pbus_reg_write(phydev, AN8811HB_MCU_SW_START, + AN8811HB_MCU_SW_START_EN); + if (ret < 0) + return ret; + + ret = air_pbus_reg_write(phydev, AN8811HB_MCU_SW_RST, + AN8811HB_MCU_SW_RST_RUN); + if (ret < 0) + return ret; + + debug("MCU deasserted\n"); + mdelay(50); + + return ret; +} + +static int an8811hb_surge_protect_cfg(struct phy_device *phydev) +{ + ofnode node = phy_get_ofnode(phydev); + int ret = 0; + + if (!ofnode_read_bool(node, "airoha,surge-5r")) { + debug("Surge Protection mode - 0R\n"); + return ret; + } + + ret = air_buckpbus_reg_modify(phydev, AIR_PHY_CONTROL, + AIR_PHY_CONTROL_SURGE_5R, + AIR_PHY_CONTROL_SURGE_5R); + if (ret < 0) + return ret; + + debug("Surge Protection mode - 5R\n"); + + return ret; +} + +static int en8811h_read_fw(void **fw, size_t *fwsize, struct en8811h_priv *priv) { + const char *script_name = priv->script_name; + u32 mem_size = priv->mem_size; void *buffer; int ret; - buffer = malloc(EN8811H_MD32_DM_SIZE + EN8811H_MD32_DSP_SIZE); + buffer = malloc(mem_size); if (!buffer) return -ENOMEM; - ret = request_firmware_into_buf_via_script(buffer, - EN8811H_MD32_DM_SIZE + EN8811H_MD32_DSP_SIZE, - "en8811h_load_firmware", fwsize); + ret = request_firmware_into_buf_via_script(buffer, mem_size, + script_name, fwsize); if (ret) { free(buffer); return ret; @@ -450,7 +689,10 @@ static int en8811h_load_firmware(struct phy_device *phydev) void *buffer; int ret; - ret = en8811h_read_fw(&buffer, &fw_size); + priv->script_name = SCRIPT_NAME(en8811h); + priv->mem_size = EN8811H_MD32_DM_SIZE + EN8811H_MD32_DSP_SIZE; + + ret = en8811h_read_fw(&buffer, &fw_size, priv); if (ret < 0) { dev_err(phydev->dev, "Failed to get firmware data\n"); return -EINVAL; @@ -496,9 +738,12 @@ static int en8811h_load_firmware(struct phy_device *phydev) goto en8811h_load_firmware_out; ret = en8811h_wait_mcu_ready(phydev); + if (ret < 0) + goto en8811h_load_firmware_out; air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION, &priv->firmware_version); + dev_info(phydev->dev, "MD32 firmware version: %08x\n", priv->firmware_version); @@ -510,6 +755,130 @@ en8811h_load_firmware_out: return ret; } +static int an8811hb_load_firmware(struct phy_device *phydev) +{ + struct en8811h_priv *priv = phydev->priv; + int ret, retry = 10; + size_t fw_size; + void *buffer; + u32 reg_val; + + ret = an8811hb_mcu_assert(phydev); + if (ret < 0) + return ret; + + ret = an8811hb_mcu_deassert(phydev); + if (ret < 0) + return ret; + + priv->script_name = SCRIPT_NAME(an8811hb); + priv->mem_size = AIR_MD32_DM_SIZE + AIR_MD32_DSP_SIZE; + + ret = en8811h_read_fw(&buffer, &fw_size, priv); + if (ret < 0) + goto an8811hb_load_firmware_out; + + ret = air_buckpbus_reg_write(phydev, AIR_PHY_FW_CTRL_1, + AIR_PHY_FW_CTRL_1_START); + if (ret < 0) + goto an8811hb_load_firmware_out; + + ret = air_write_buf(phydev, AIR_FW_ADDR_DM, AIR_MD32_DM_SIZE, + (unsigned char *)buffer); + if (ret < 0) + goto an8811hb_load_firmware_out; + + ret = an8811hb_check_crc(phydev, AN8811HB_CRC_DM_SET1, + AN8811HB_CRC_DM_MON2, AN8811HB_CRC_DM_MON3); + if (ret < 0) + goto an8811hb_load_firmware_out; + + ret = air_write_buf(phydev, AIR_FW_ADDR_DSP, AIR_MD32_DSP_SIZE, + (unsigned char *)buffer + AIR_MD32_DM_SIZE); + if (ret < 0) + goto an8811hb_load_firmware_out; + + ret = an8811hb_check_crc(phydev, AN8811HB_CRC_PM_SET1, + AN8811HB_CRC_PM_MON2, AN8811HB_CRC_PM_MON3); + if (ret < 0) + goto an8811hb_load_firmware_out; + + ret = air_buckpbus_reg_write(phydev, AIR_PHY_FW_CTRL_1, + AIR_PHY_FW_CTRL_1_FINISH); + if (ret < 0) + goto an8811hb_load_firmware_out; + + ret = an8811hb_surge_protect_cfg(phydev); + if (ret < 0) { + dev_err(phydev->dev, "an8811hb_surge_protect_cfg fail. (ret=%d)\n", ret); + goto an8811hb_load_firmware_out; + } + + do { + mdelay(300); + + ret = air_buckpbus_reg_read(phydev, AIR_PHY_FW_CTRL_1, ®_val); + if (ret < 0) + goto an8811hb_load_firmware_out; + + if (reg_val == AIR_PHY_FW_CTRL_1_FINISH) + break; + + debug("%d: reg 0x%x val 0x%x!\n", __LINE__, AIR_PHY_FW_CTRL_1, + reg_val); + + ret = air_buckpbus_reg_write(phydev, AIR_PHY_FW_CTRL_1, + AIR_PHY_FW_CTRL_1_FINISH); + if (ret < 0) + goto an8811hb_load_firmware_out; + + } while (--retry); + + ret = en8811h_wait_mcu_ready(phydev); + if (ret < 0) + goto an8811hb_load_firmware_out; + + air_buckpbus_reg_read(phydev, AIR_PHY_MD32FW_VERSION, + &priv->firmware_version); + + debug("MD32 firmware version: %08x\n", priv->firmware_version); + +an8811hb_load_firmware_out: + free(buffer); + if (ret < 0) + dev_err(phydev->dev, "Firmware loading failed: %d\n", ret); + + return ret; +} + +int an8811hb_cko_cfg(struct phy_device *phydev) +{ + ofnode node = phy_get_ofnode(phydev); + u32 pbus_value; + int ret = 0; + + if (!ofnode_read_bool(node, "airoha,phy-output-clock")) { + ret = air_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV, + AN8811HB_CLK_DRV_CKO_MASK, + AN8811HB_CLK_DRV_CKOPWD | + AN8811HB_CLK_DRV_CKO_LDPWD | + AN8811HB_CLK_DRV_CKO_LPPWD); + if (ret < 0) + return ret; + + debug("CKO Output mode - Disabled\n"); + } else { + ret = air_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value); + if (ret < 0) + return ret; + + debug("CKO Output %dMHz - Enabled\n", + (pbus_value & AN8811HB_HWTRAP2_CKO) ? 50 : 25); + } + + return ret; +} + static int en8811h_restart_mcu(struct phy_device *phydev) { int ret; @@ -613,13 +982,30 @@ static int air_led_init(struct phy_device *phydev, u8 index, u8 state, u8 pol) return 0; } +/** + * air_leds_init - Initialize and configure LEDs for a phy device. + * + * @phydev: Pointer to the phy_device structure. + * @num: Number of LEDs to initialize. + * @dur: Duration for LED blink in milliseconds. It sets the duration + * for both the ON and OFF periods (OFF period will be half of `dur`). + * @mode: LED operation mode. Supported modes are: + * - AIR_LED_MODE_DISABLE: Disables LED control. + * - AIR_LED_MODE_USER_DEFINE: Enables user-defined LED control. + * + * Initializes and configures LEDs on a phy device with a specified blink duration + * and mode. Supports disabling or enabling user-defined control. + * Return: + * On success, returns 0. On error, it returns a negative value that denotes + * the error code. + */ + static int air_leds_init(struct phy_device *phydev, int num, u16 dur, int mode) { struct en8811h_priv *priv = phydev->priv; int ret, i; - ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK, - dur); + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK, dur); if (ret < 0) return ret; @@ -707,10 +1093,121 @@ static int en8811h_config(struct phy_device *phydev) pbus_value |= EN8811H_POLARITY_TX_NORMAL; ret = air_buckpbus_reg_modify(phydev, EN8811H_POLARITY, EN8811H_POLARITY_RX_REVERSE | - EN8811H_POLARITY_TX_NORMAL, pbus_value); + EN8811H_POLARITY_TX_NORMAL, + pbus_value); + if (ret < 0) + return ret; + + ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR, + AIR_LED_MODE_USER_DEFINE); + if (ret < 0) { + dev_err(phydev->dev, "Failed to disable leds: %d\n", ret); + return ret; + } + + return 0; +} + +static int an8811hb_config(struct phy_device *phydev) +{ + struct en8811h_priv *priv = phydev->priv; + u32 pbus_value = 0; + ofnode node; + int ret = 0; + + node = phy_get_ofnode(phydev); + if (!ofnode_valid(node)) + return 0; + + /* If restart happened in .probe(), no need to restart now */ + if (priv->mcu_needs_restart) { + ret = an8811hb_mcu_assert(phydev); + if (ret < 0) + return ret; + + ret = an8811hb_mcu_deassert(phydev); + if (ret < 0) + return ret; + + ret = en8811h_restart_mcu(phydev); + if (ret < 0) + return ret; + } else { + ret = an8811hb_load_firmware(phydev); + if (ret) { + dev_err(phydev->dev, "Load firmware fail.\n"); + return ret; + } + /* Next calls to .config() mcu needs to restart */ + priv->mcu_needs_restart = true; + } + + ret = air_buckpbus_reg_read(phydev, AN8811HB_PRO_ID, &pbus_value); + if (ret < 0) + return ret; + priv->pro_id = (pbus_value & AN8811HB_PRO_ID_VERSION) + 1; + + ret = air_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value); + if (ret < 0) + return ret; + priv->pkg_sel = (pbus_value & AN8811HB_HWTRAP2_PKG) >> 12; + debug("%s(%d) Version: E%d\n", + priv->pkg_sel ? "AN8811HBCN" : "AN8811HBN", priv->pkg_sel, + priv->pro_id); + + /* Serdes polarity */ + pbus_value = 0; + if (ofnode_read_bool(node, "airoha,pnswap-rx")) + pbus_value &= ~AN8811HB_RX_POLARITY_NORMAL; + else + pbus_value |= AN8811HB_RX_POLARITY_NORMAL; + + debug("1 pbus_value 0x%x\n", pbus_value); + ret = air_buckpbus_reg_modify(phydev, AN8811HB_RX_POLARITY, + AN8811HB_RX_POLARITY_NORMAL, pbus_value); + if (ret < 0) + return ret; + + pbus_value = 0; + if (ofnode_read_bool(node, "airoha,pnswap-tx")) + pbus_value &= ~AN8811HB_TX_POLARITY_NORMAL; + else + pbus_value |= AN8811HB_TX_POLARITY_NORMAL; + + debug("2 pbus_value 0x%x\n", pbus_value); + ret = air_buckpbus_reg_modify(phydev, AN8811HB_TX_POLARITY, + AN8811HB_TX_POLARITY_NORMAL, pbus_value); if (ret < 0) return ret; + /* Configure led gpio pins as output */ + if (priv->pkg_sel) { + ret = air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT, + AN8811HB_GPIO_OUTPUT_MASK, + AN8811HB_GPIO_OUTPUT_0115); + if (ret < 0) + return ret; + ret = air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_SEL_1, + AN8811HB_GPIO_SEL_1_0_MASK | + AN8811HB_GPIO_SEL_1_1_MASK, + AN8811HB_GPIO_SEL_1_0 | + AN8811HB_GPIO_SEL_1_1); + if (ret < 0) + return ret; + + ret = air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_SEL_2, + AN8811HB_GPIO_SEL_2_15_MASK, + AN8811HB_GPIO_SEL_2_15); + if (ret < 0) + return ret; + } else { + ret = air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT, + AN8811HB_GPIO_OUTPUT_345, + AN8811HB_GPIO_OUTPUT_345); + if (ret < 0) + return ret; + } + ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR, AIR_LED_MODE_USER_DEFINE); if (ret < 0) { @@ -718,9 +1215,91 @@ static int en8811h_config(struct phy_device *phydev) return ret; } + /* Co-Clock Output */ + ret = an8811hb_cko_cfg(phydev); + if (ret) + return ret; + + printf("AN8811HB initialize OK !\n"); + + return 0; +} + +static int an8811hb_update_duplex(struct phy_device *phydev) +{ + int lpa; + + if (phydev->autoneg == AUTONEG_ENABLE) { + lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA); + if (lpa < 0) + return lpa; + + switch (phydev->speed) { + case SPEED_2500: + case SPEED_1000: + phydev->duplex = DUPLEX_FULL; + break; + case SPEED_100: + phydev->duplex = (lpa & LPA_100FULL) ? DUPLEX_FULL : + DUPLEX_HALF; + break; + case SPEED_10: + phydev->duplex = (lpa & LPA_10FULL) ? DUPLEX_FULL : + DUPLEX_HALF; + break; + } + } else { + int bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + + if (phydev->speed == SPEED_2500) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : + DUPLEX_HALF; + } + return 0; } +static int an8811hb_parse_status(struct phy_device *phydev) +{ + int ret = 0, reg_value; + + reg_value = phy_read(phydev, MDIO_DEVAD_NONE, AIR_AUX_CTRL_STATUS); + if (reg_value < 0) + return reg_value; + + switch (reg_value & AIR_AUX_CTRL_STATUS_SPEED_MASK) { + case AIR_AUX_CTRL_STATUS_SPEED_2500: + phydev->speed = SPEED_2500; + break; + case AIR_AUX_CTRL_STATUS_SPEED_1000: + phydev->speed = SPEED_1000; + break; + case AIR_AUX_CTRL_STATUS_SPEED_100: + phydev->speed = SPEED_100; + break; + case AIR_AUX_CTRL_STATUS_SPEED_10: + phydev->speed = SPEED_10; + break; + default: + dev_err(phydev->dev, + "Auto-neg error, defaulting to 2500M/FD\n"); + phydev->speed = SPEED_2500; + phydev->duplex = DUPLEX_FULL; + return 0; + } + + /* Update duplex mode based on speed and negotiation status */ + ret = an8811hb_update_duplex(phydev); + if (ret < 0) + return ret; + + debug("Speed: %d, %s duplex\n", phydev->speed, + (phydev->duplex) ? "full" : "half"); + return ret; +} + static int en8811h_parse_status(struct phy_device *phydev) { int ret = 0, reg_value; @@ -742,7 +1321,8 @@ static int en8811h_parse_status(struct phy_device *phydev) phydev->speed = SPEED_100; break; default: - dev_err(phydev->dev, "Auto-neg error, defaulting to 2500M/FD\n"); + dev_err(phydev->dev, + "Auto-neg error, defaulting to 2500M/FD\n"); phydev->speed = SPEED_2500; break; } @@ -752,24 +1332,35 @@ static int en8811h_parse_status(struct phy_device *phydev) static int en8811h_startup(struct phy_device *phydev) { + u32 phy_id = phydev->phy_id; int ret = 0; ret = genphy_update_link(phydev); if (ret) return ret; - return en8811h_parse_status(phydev); + if (phy_id == EN8811H_PHY_ID) + ret = en8811h_parse_status(phydev); + else if (phy_id == AN8811HB_PHY_ID) + ret = an8811hb_parse_status(phydev); + + return ret; } static int en8811h_probe(struct phy_device *phydev) { struct en8811h_priv *priv; + int phy_id; priv = malloc(sizeof(*priv)); if (!priv) return -ENOMEM; memset(priv, 0, sizeof(*priv)); + debug("%s driver is probed.\n", phydev->drv->name); + get_phy_id(phydev->bus, phydev->addr, MDIO_DEVAD_NONE, &phy_id); + debug("phy id is 0x%x.\n", phy_id); + priv->led[0].rules = AIR_DEFAULT_TRIGGER_LED0; priv->led[1].rules = AIR_DEFAULT_TRIGGER_LED1; priv->led[2].rules = AIR_DEFAULT_TRIGGER_LED2; @@ -782,12 +1373,12 @@ static int en8811h_probe(struct phy_device *phydev) return 0; } -static int en8811h_read_page(struct phy_device *phydev) +static int air_phy_read_page(struct phy_device *phydev) { return phy_read(phydev, MDIO_DEVAD_NONE, AIR_EXT_PAGE_ACCESS); } -static int en8811h_write_page(struct phy_device *phydev, int page) +static int air_phy_write_page(struct phy_device *phydev, int page) { return phy_write(phydev, MDIO_DEVAD_NONE, AIR_EXT_PAGE_ACCESS, page); } @@ -798,8 +1389,20 @@ U_BOOT_PHY_DRIVER(en8811h) = { .mask = 0x0ffffff0, .config = &en8811h_config, .probe = &en8811h_probe, - .read_page = &en8811h_read_page, - .write_page = &en8811h_write_page, + .read_page = &air_phy_read_page, + .write_page = &air_phy_write_page, + .startup = &en8811h_startup, + .shutdown = &genphy_shutdown, +}; + +U_BOOT_PHY_DRIVER(an8811hb) = { + .name = "Airoha AN8811HB", + .uid = AN8811HB_PHY_ID, + .mask = 0x0ffffff0, + .config = &an8811hb_config, + .probe = &en8811h_probe, + .read_page = &air_phy_read_page, + .write_page = &air_phy_write_page, .startup = &en8811h_startup, .shutdown = &genphy_shutdown, }; diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 772cde1c520..7ce03b59b6a 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -257,14 +257,14 @@ static int dp83867_config(struct phy_device *phydev) dp83867 = (struct dp83867_private *)phydev->priv; - ret = dp83867_of_init(phydev); + /* Reset PHY to clear any stale state after warm reboot */ + ret = phy_reset(phydev); if (ret) return ret; - /* Restart the PHY. */ - val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL); - phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL, - val | DP83867_SW_RESTART); + ret = dp83867_of_init(phydev); + if (ret) + return ret; /* Mode 1 or 2 workaround */ if (dp83867->rxctrl_strap_quirk) { diff --git a/drivers/net/phy/fixed.c b/drivers/net/phy/fixed.c index 11d36164976..4ab709a14d5 100644 --- a/drivers/net/phy/fixed.c +++ b/drivers/net/phy/fixed.c @@ -10,9 +10,6 @@ #include <phy.h> #include <dm.h> #include <fdt_support.h> -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; static int fixedphy_probe(struct phy_device *phydev) { diff --git a/drivers/net/phy/mediatek/Kconfig b/drivers/net/phy/mediatek/Kconfig index 933271f01fa..1ead391c7b6 100644 --- a/drivers/net/phy/mediatek/Kconfig +++ b/drivers/net/phy/mediatek/Kconfig @@ -6,6 +6,7 @@ config MTK_NET_PHYLIB config PHY_MEDIATEK_2P5GE bool "MediaTek built-in 2.5Gb ethernet PHYs" depends on OF_CONTROL && (TARGET_MT7987 || TARGET_MT7988) + depends on SUPPORTS_FW_LOADER select FW_LOADER select MTK_NET_PHYLIB help diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c index f357e0f1c77..1a7116f4ddd 100644 --- a/drivers/net/phy/micrel_ksz90x1.c +++ b/drivers/net/phy/micrel_ksz90x1.c @@ -407,6 +407,9 @@ static int ksz9031_config(struct phy_device *phydev) if (ret) return ret; + /* soft reset */ + phy_reset(phydev); + ksz90x1_workaround_asymmetric_pause(phydev); /* add an option to disable the gigabit feature of this PHY */ diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index b58283fe3d5..d7e0c4fe02d 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -17,7 +17,6 @@ #include <miiphy.h> #include <phy.h> #include <errno.h> -#include <asm/global_data.h> #include <asm-generic/gpio.h> #include <dm/device_compat.h> #include <dm/of_extra.h> @@ -26,8 +25,6 @@ #include <linux/err.h> #include <linux/compiler.h> -DECLARE_GLOBAL_DATA_PTR; - /* Generic PHY support and helper functions */ /** diff --git a/drivers/net/phy/xilinx_gmii2rgmii.c b/drivers/net/phy/xilinx_gmii2rgmii.c index e44b7b75bd5..f5a7dd349c9 100644 --- a/drivers/net/phy/xilinx_gmii2rgmii.c +++ b/drivers/net/phy/xilinx_gmii2rgmii.c @@ -8,9 +8,6 @@ #include <dm.h> #include <log.h> #include <phy.h> -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_GMII2RGMII_REG 0x10 #define ZYNQ_GMII2RGMII_SPEED_MASK (BMCR_SPEED1000 | BMCR_SPEED100) diff --git a/drivers/net/rswitch.c b/drivers/net/rswitch.c index c51908ed8f3..52fc3edd4e0 100644 --- a/drivers/net/rswitch.c +++ b/drivers/net/rswitch.c @@ -9,6 +9,7 @@ #include <asm/io.h> #include <clk.h> +#include <cpu_func.h> #include <dm.h> #include <dm/device-internal.h> #include <dm/device_compat.h> @@ -23,6 +24,7 @@ #include <log.h> #include <malloc.h> #include <miiphy.h> +#include <phys2bus.h> #define RSWITCH_SLEEP_US 1000 #define RSWITCH_TIMEOUT_US 1000000 @@ -587,9 +589,11 @@ static void rswitch_bat_desc_init(struct rswitch_port_priv *priv) rswitch_flush_dcache((uintptr_t)priv->bat_desc, desc_size); } -static void rswitch_tx_desc_init(struct rswitch_port_priv *priv) +static void rswitch_tx_desc_init(struct udevice *dev) { + struct rswitch_port_priv *priv = dev_get_priv(dev); const u32 desc_size = RSWITCH_NUM_TX_DESC * sizeof(struct rswitch_desc); + dma_addr_t tx_desc_ba; u64 tx_desc_addr; int i; @@ -603,21 +607,25 @@ static void rswitch_tx_desc_init(struct rswitch_port_priv *priv) /* Mark the end of the descriptors */ priv->tx_desc[RSWITCH_NUM_TX_DESC - 1].die_dt = DT_LINKFIX; tx_desc_addr = (uintptr_t)priv->tx_desc; - priv->tx_desc[RSWITCH_NUM_TX_DESC - 1].dptrl = lower_32_bits(tx_desc_addr); - priv->tx_desc[RSWITCH_NUM_TX_DESC - 1].dptrh = upper_32_bits(tx_desc_addr); + tx_desc_ba = dev_phys_to_bus(dev, (phys_addr_t)tx_desc_addr); + + priv->tx_desc[RSWITCH_NUM_TX_DESC - 1].dptrl = lower_32_bits(tx_desc_ba); + priv->tx_desc[RSWITCH_NUM_TX_DESC - 1].dptrh = upper_32_bits(tx_desc_ba); rswitch_flush_dcache(tx_desc_addr, desc_size); /* Point the controller to the TX descriptor list */ priv->bat_desc[RSWITCH_TX_CHAIN_INDEX].die_dt = DT_LINKFIX; - priv->bat_desc[RSWITCH_TX_CHAIN_INDEX].dptrl = lower_32_bits(tx_desc_addr); - priv->bat_desc[RSWITCH_TX_CHAIN_INDEX].dptrh = upper_32_bits(tx_desc_addr); + priv->bat_desc[RSWITCH_TX_CHAIN_INDEX].dptrl = lower_32_bits(tx_desc_ba); + priv->bat_desc[RSWITCH_TX_CHAIN_INDEX].dptrh = upper_32_bits(tx_desc_ba); rswitch_flush_dcache((uintptr_t)&priv->bat_desc[RSWITCH_TX_CHAIN_INDEX], sizeof(struct rswitch_desc)); } -static void rswitch_rx_desc_init(struct rswitch_port_priv *priv) +static void rswitch_rx_desc_init(struct udevice *dev) { + struct rswitch_port_priv *priv = dev_get_priv(dev); const u32 desc_size = RSWITCH_NUM_RX_DESC * sizeof(struct rswitch_rxdesc); + dma_addr_t packet_ba, next_rx_desc_ba, rx_desc_ba; int i; u64 packet_addr; u64 next_rx_desc_addr; @@ -631,26 +639,29 @@ static void rswitch_rx_desc_init(struct rswitch_port_priv *priv) priv->rx_desc[i].data.die_dt = DT_FEMPTY; priv->rx_desc[i].data.info_ds = PKTSIZE_ALIGN; packet_addr = (uintptr_t)priv->rx_desc[i].packet; - priv->rx_desc[i].data.dptrl = lower_32_bits(packet_addr); - priv->rx_desc[i].data.dptrh = upper_32_bits(packet_addr); + packet_ba = dev_phys_to_bus(dev, (phys_addr_t)packet_addr); + priv->rx_desc[i].data.dptrl = lower_32_bits(packet_ba); + priv->rx_desc[i].data.dptrh = upper_32_bits(packet_ba); priv->rx_desc[i].link.die_dt = DT_LINKFIX; next_rx_desc_addr = (uintptr_t)&priv->rx_desc[i + 1]; - priv->rx_desc[i].link.dptrl = lower_32_bits(next_rx_desc_addr); - priv->rx_desc[i].link.dptrh = upper_32_bits(next_rx_desc_addr); + next_rx_desc_ba = dev_phys_to_bus(dev, (phys_addr_t)next_rx_desc_addr); + priv->rx_desc[i].link.dptrl = lower_32_bits(next_rx_desc_ba); + priv->rx_desc[i].link.dptrh = upper_32_bits(next_rx_desc_ba); } /* Mark the end of the descriptors */ priv->rx_desc[RSWITCH_NUM_RX_DESC - 1].link.die_dt = DT_LINKFIX; rx_desc_addr = (uintptr_t)priv->rx_desc; - priv->rx_desc[RSWITCH_NUM_RX_DESC - 1].link.dptrl = lower_32_bits(rx_desc_addr); - priv->rx_desc[RSWITCH_NUM_RX_DESC - 1].link.dptrh = upper_32_bits(rx_desc_addr); + rx_desc_ba = dev_phys_to_bus(dev, (phys_addr_t)rx_desc_addr); + priv->rx_desc[RSWITCH_NUM_RX_DESC - 1].link.dptrl = lower_32_bits(rx_desc_ba); + priv->rx_desc[RSWITCH_NUM_RX_DESC - 1].link.dptrh = upper_32_bits(rx_desc_ba); rswitch_flush_dcache(rx_desc_addr, desc_size); /* Point the controller to the rx descriptor list */ priv->bat_desc[RSWITCH_RX_CHAIN_INDEX].die_dt = DT_LINKFIX; - priv->bat_desc[RSWITCH_RX_CHAIN_INDEX].dptrl = lower_32_bits(rx_desc_addr); - priv->bat_desc[RSWITCH_RX_CHAIN_INDEX].dptrh = upper_32_bits(rx_desc_addr); + priv->bat_desc[RSWITCH_RX_CHAIN_INDEX].dptrl = lower_32_bits(rx_desc_ba); + priv->bat_desc[RSWITCH_RX_CHAIN_INDEX].dptrh = upper_32_bits(rx_desc_ba); rswitch_flush_dcache((uintptr_t)&priv->bat_desc[RSWITCH_RX_CHAIN_INDEX], sizeof(struct rswitch_desc)); } @@ -741,9 +752,11 @@ static int rswitch_gwca_axi_ram_reset(struct rswitch_gwca *gwca) RSWITCH_SLEEP_US, RSWITCH_TIMEOUT_US); } -static int rswitch_gwca_init(struct rswitch_port_priv *priv) +static int rswitch_gwca_init(struct udevice *dev) { + struct rswitch_port_priv *priv = dev_get_priv(dev); struct rswitch_gwca *gwca = &priv->gwca; + dma_addr_t bat_desc_ba; int ret; ret = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); @@ -765,9 +778,11 @@ static int rswitch_gwca_init(struct rswitch_port_priv *priv) /* Setting flow */ writel(GWVCC_VEM_SC_TAG, gwca->addr + GWVCC); writel(0, gwca->addr + GWTTFC); - writel(upper_32_bits((uintptr_t)priv->bat_desc) & GWDCBAC0_DCBAUP, + + bat_desc_ba = dev_phys_to_bus(dev, (phys_addr_t)(priv->bat_desc)); + writel(upper_32_bits(bat_desc_ba) & GWDCBAC0_DCBAUP, gwca->addr + GWDCBAC0 + priv->drv_data->gwdcbac_offset); - writel(lower_32_bits((uintptr_t)priv->bat_desc), + writel(lower_32_bits(bat_desc_ba), gwca->addr + GWDCBAC1 + priv->drv_data->gwdcbac_offset); writel(GWDCC_DQT | GWDCC_BALR, gwca->addr + GWDCC(RSWITCH_TX_CHAIN_INDEX)); writel(GWDCC_BALR, gwca->addr + GWDCC(RSWITCH_RX_CHAIN_INDEX)); @@ -844,8 +859,9 @@ static int rswitch_etha_init(struct rswitch_port_priv *priv) return 0; } -static int rswitch_init(struct rswitch_port_priv *priv) +static int rswitch_start(struct udevice *dev) { + struct rswitch_port_priv *priv = dev_get_priv(dev); struct rswitch_etha *etha = &priv->etha; int ret; @@ -875,8 +891,8 @@ static int rswitch_init(struct rswitch_port_priv *priv) return ret; rswitch_bat_desc_init(priv); - rswitch_tx_desc_init(priv); - rswitch_rx_desc_init(priv); + rswitch_tx_desc_init(dev); + rswitch_rx_desc_init(dev); rswitch_clock_enable(priv); @@ -886,7 +902,7 @@ static int rswitch_init(struct rswitch_port_priv *priv) rswitch_mfwd_init(priv); - ret = rswitch_gwca_init(priv); + ret = rswitch_gwca_init(dev); if (ret) return ret; @@ -897,23 +913,12 @@ static int rswitch_init(struct rswitch_port_priv *priv) return 0; } -static int rswitch_start(struct udevice *dev) -{ - struct rswitch_port_priv *priv = dev_get_priv(dev); - int ret; - - ret = rswitch_init(priv); - if (ret) - return ret; - - return 0; -} - #define RSWITCH_TX_TIMEOUT_MS 1000 static int rswitch_send(struct udevice *dev, void *packet, int len) { struct rswitch_port_priv *priv = dev_get_priv(dev); struct rswitch_desc *desc = &priv->tx_desc[priv->tx_desc_index]; + dma_addr_t bpacket = dev_phys_to_bus(dev, (phys_addr_t)packet); struct rswitch_gwca *gwca = &priv->gwca; u32 gwtrc_index, start; @@ -923,8 +928,8 @@ static int rswitch_send(struct udevice *dev, void *packet, int len) memset(desc, 0x0, sizeof(*desc)); desc->die_dt = DT_FSINGLE; desc->info_ds = len; - desc->dptrl = lower_32_bits((uintptr_t)packet); - desc->dptrh = upper_32_bits((uintptr_t)packet); + desc->dptrl = lower_32_bits(bpacket); + desc->dptrh = upper_32_bits(bpacket); rswitch_flush_dcache((uintptr_t)desc, sizeof(*desc)); /* Start transmission */ @@ -954,6 +959,7 @@ static int rswitch_recv(struct udevice *dev, int flags, uchar **packetp) { struct rswitch_port_priv *priv = dev_get_priv(dev); struct rswitch_rxdesc *desc = &priv->rx_desc[priv->rx_desc_index]; + dma_addr_t dpacket; u8 *packet; int len; @@ -963,7 +969,9 @@ static int rswitch_recv(struct udevice *dev, int flags, uchar **packetp) return -EAGAIN; len = desc->data.info_ds & RX_DS; - packet = (u8 *)(((uintptr_t)(desc->data.dptrh) << 32) | (uintptr_t)desc->data.dptrl); + dpacket = ((u64)(desc->data.dptrh) << 32) | (u64)(desc->data.dptrl); + packet = (u8 *)(uintptr_t)dev_bus_to_phys(dev, dpacket); + rswitch_invalidate_dcache((uintptr_t)packet, len); *packetp = packet; diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index edcae88a3fc..5b093623619 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -270,6 +270,7 @@ static struct { {"RTL-8100e", 0x32, 0xff7e1880,}, {"RTL-8168h/8111h", 0x54, 0xff7e1880,}, {"RTL-8125B", 0x64, 0xff7e1880,}, + {"RTL-8125d", 0x6a, 0xff7e5880,}, }; enum _DescStatusBit { diff --git a/drivers/net/sandbox-raw.c b/drivers/net/sandbox-raw.c index 1d716716778..c3d40f0b59e 100644 --- a/drivers/net/sandbox-raw.c +++ b/drivers/net/sandbox-raw.c @@ -12,9 +12,6 @@ #include <env.h> #include <malloc.h> #include <net.h> -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; static int reply_arp; static struct in_addr arp_ip; diff --git a/drivers/net/sandbox.c b/drivers/net/sandbox.c index 2011fd31f41..0ea50c484c0 100644 --- a/drivers/net/sandbox.c +++ b/drivers/net/sandbox.c @@ -10,7 +10,6 @@ #include <log.h> #include <malloc.h> #include <asm/eth.h> -#include <asm/global_data.h> #include <asm/test.h> #include <asm/types.h> @@ -84,8 +83,6 @@ struct icmphdr { #define ICMP_ECHO_REPLY 0 #define IPPROTO_ICMP 1 -DECLARE_GLOBAL_DATA_PTR; - static const u8 null_ethaddr[6]; static bool skip_timeout; diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c index d4abc9a0411..40c98e72e4d 100644 --- a/drivers/net/ti/keystone_net.c +++ b/drivers/net/ti/keystone_net.c @@ -7,7 +7,6 @@ */ #include <command.h> #include <console.h> -#include <asm/global_data.h> #include <linux/delay.h> #include <linux/printk.h> @@ -26,8 +25,6 @@ #include "cpsw_mdio.h" -DECLARE_GLOBAL_DATA_PTR; - #ifdef KEYSTONE2_EMAC_GIG_ENABLE #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x) #else diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index fb48feb4469..e9cc5db52d2 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -15,7 +15,6 @@ #include <log.h> #include <net.h> #include <malloc.h> -#include <asm/global_data.h> #include <asm/io.h> #include <phy.h> #include <miiphy.h> @@ -23,8 +22,6 @@ #include <linux/delay.h> #include <eth_phy.h> -DECLARE_GLOBAL_DATA_PTR; - /* Link setup */ #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */ #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */ diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 407b022508c..a50d5aee03f 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -64,6 +64,7 @@ #define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */ #define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */ #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */ +#define ZYNQ_GEM_NWCFG_NBC 0x00000020 /* No broadcast */ #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */ #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */ #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */ @@ -76,6 +77,7 @@ #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ ZYNQ_GEM_NWCFG_FDEN | \ + ZYNQ_GEM_NWCFG_NBC | \ ZYNQ_GEM_NWCFG_FSREM) #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ @@ -256,6 +258,7 @@ struct zynq_gem_priv { struct clk pclk; u32 max_speed; bool dma_64bit; + bool cache_on; u32 clk_en_info; struct reset_ctl_bulk resets; }; @@ -691,6 +694,7 @@ static int zynq_gem_send(struct udevice *dev, void *ptr, int len) { dma_addr_t addr; u32 size; + int ret; struct zynq_gem_priv *priv = dev_get_priv(dev); struct zynq_gem_regs *regs = priv->iobase; struct emac_bd *current_bd = &priv->tx_bd[1]; @@ -722,7 +726,8 @@ static int zynq_gem_send(struct udevice *dev, void *ptr, int len) addr = (ulong) ptr; addr &= ~(ARCH_DMA_MINALIGN - 1); size = roundup(len, ARCH_DMA_MINALIGN); - flush_dcache_range(addr, addr + size); + if (priv->cache_on) + flush_dcache_range(addr, addr + size); barrier(); /* Start transmit */ @@ -732,8 +737,13 @@ static int zynq_gem_send(struct udevice *dev, void *ptr, int len) if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) printf("TX buffers exhausted in mid frame\n"); - return wait_for_bit_le32(®s->txsr, ZYNQ_GEM_TSR_DONE, - true, 20000, true); + ret = wait_for_bit_le32(®s->txsr, ZYNQ_GEM_TSR_DONE, + true, 20000, true); + + /* Clear the transfer complete */ + setbits_le32(®s->txsr, ZYNQ_GEM_TSR_DONE); + + return ret; } /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ @@ -769,7 +779,8 @@ static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp) *packetp = (uchar *)(uintptr_t)addr; - invalidate_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN)); + if (priv->cache_on) + invalidate_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN)); barrier(); return frame_len; @@ -802,8 +813,8 @@ static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) #else addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; #endif - flush_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, - ARCH_DMA_MINALIGN)); + if (priv->cache_on) + flush_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN)); barrier(); if ((++priv->rxbd_current) >= RX_BUF) @@ -926,7 +937,8 @@ static int zynq_gem_probe(struct udevice *dev) memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); ulong addr = (ulong)priv->rxbuffers; - flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN)); + if (priv->cache_on) + flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN)); barrier(); /* Align bd_space to MMU_SECTION_SHIFT */ @@ -936,8 +948,9 @@ static int zynq_gem_probe(struct udevice *dev) goto err1; } - mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, - BD_SPACE, DCACHE_OFF); + if (priv->cache_on) + mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, + BD_SPACE, DCACHE_OFF); /* Initialize the bd spaces for tx and rx bd's */ priv->tx_bd = (struct emac_bd *)bd_space; @@ -1050,6 +1063,9 @@ static int zynq_gem_of_to_plat(struct udevice *dev) /* Hardcode for now */ priv->phyaddr = -1; + if (!dev_read_bool(dev, "dma-coherent")) + priv->cache_on = true; + if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &phandle_args)) { fdt_addr_t addr; diff --git a/drivers/pci/pci_octeontx.c b/drivers/pci/pci_octeontx.c index 875cf7f7115..6752112a878 100644 --- a/drivers/pci/pci_octeontx.c +++ b/drivers/pci/pci_octeontx.c @@ -11,14 +11,11 @@ #include <log.h> #include <malloc.h> #include <pci.h> -#include <asm/global_data.h> #include <asm/io.h> #include <linux/ioport.h> -DECLARE_GLOBAL_DATA_PTR; - /* * This driver supports multiple types of operations / host bridges / busses: * diff --git a/drivers/pci/pcie_dw_meson.c b/drivers/pci/pcie_dw_meson.c index 483b07ce078..1eff6d1b0ed 100644 --- a/drivers/pci/pcie_dw_meson.c +++ b/drivers/pci/pcie_dw_meson.c @@ -16,7 +16,6 @@ #include <power-domain.h> #include <reset.h> #include <syscon.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm-generic/gpio.h> #include <dm/device_compat.h> @@ -27,8 +26,6 @@ #include "pcie_dw_common.h" -DECLARE_GLOBAL_DATA_PTR; - /** * struct meson_pcie - Amlogic Meson DW PCIe controller state * diff --git a/drivers/pci/pcie_dw_qcom.c b/drivers/pci/pcie_dw_qcom.c index 978754e8472..10c45aaba20 100644 --- a/drivers/pci/pcie_dw_qcom.c +++ b/drivers/pci/pcie_dw_qcom.c @@ -10,7 +10,6 @@ #include <syscon.h> #include <malloc.h> #include <power/regulator.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm-generic/gpio.h> #include <dm/device_compat.h> @@ -21,8 +20,6 @@ #include "pcie_dw_common.h" -DECLARE_GLOBAL_DATA_PTR; - struct qcom_pcie; struct qcom_pcie_ops { diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c index 208aa30463a..61117fa95e6 100644 --- a/drivers/pci/pcie_dw_rockchip.c +++ b/drivers/pci/pcie_dw_rockchip.c @@ -13,7 +13,6 @@ #include <reset.h> #include <syscon.h> #include <asm/arch-rockchip/clock.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm-generic/gpio.h> #include <dm/device_compat.h> @@ -24,8 +23,6 @@ #include "pcie_dw_common.h" -DECLARE_GLOBAL_DATA_PTR; - /** * struct rk_pcie - RK DW PCIe controller state * diff --git a/drivers/pci/pcie_dw_ti.c b/drivers/pci/pcie_dw_ti.c index dc6e65273b7..37c295fdd38 100644 --- a/drivers/pci/pcie_dw_ti.c +++ b/drivers/pci/pcie_dw_ti.c @@ -10,7 +10,6 @@ #include <power-domain.h> #include <regmap.h> #include <syscon.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm-generic/gpio.h> #include <dm/device_compat.h> @@ -20,8 +19,6 @@ #include "pcie_dw_common.h" -DECLARE_GLOBAL_DATA_PTR; - #define PCIE_VENDORID_MASK GENMASK(15, 0) #define PCIE_DEVICEID_SHIFT 16 diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 11c4ccbfc55..8d853ecf2c2 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -728,15 +728,31 @@ static int imx_pcie_dm_write_config(struct udevice *dev, pci_dev_t bdf, static int imx_pcie_dm_probe(struct udevice *dev) { struct imx_pcie_priv *priv = dev_get_priv(dev); + int ret; #if CONFIG_IS_ENABLED(DM_REGULATOR) device_get_supply_regulator(dev, "vpcie-supply", &priv->vpcie); #endif /* if PERST# valid from dt then assert it */ - gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio, - GPIOD_IS_OUT); - priv->reset_active_high = dev_read_bool(dev, "reset-gpio-active-high"); + ret = gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio, + GPIOD_IS_OUT); + if (!ret) { + /* + * Legacy property, invert assert logic based on + * reset-gpio-active-high. This won't work if flags are not + * matching the reset-gpio-active-high. + */ + priv->reset_active_high = dev_read_bool(dev, "reset-gpio-active-high"); + } else { + /* + * Linux kernel upstream property, assert active level based on + * GPIO flags, thus leave priv->reset_active_high=0. + */ + gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio, + GPIOD_IS_OUT); + } + if (dm_gpio_is_valid(&priv->reset_gpio)) { dm_gpio_set_value(&priv->reset_gpio, priv->reset_active_high ? 0 : 1); diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 1be33095b9c..db7c4f47916 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -6,7 +6,6 @@ */ #include <log.h> -#include <asm/global_data.h> #include <asm/io.h> #include <errno.h> #include <malloc.h> @@ -16,8 +15,6 @@ #endif #include "pcie_layerscape.h" -DECLARE_GLOBAL_DATA_PTR; - LIST_HEAD(ls_pcie_list); unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset) diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index b7f692f6450..d5f4930e181 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -7,9 +7,11 @@ #ifndef _PCIE_LAYERSCAPE_H_ #define _PCIE_LAYERSCAPE_H_ -#include <pci.h> +#include <fdtdec.h> +#include <pci.h> #include <linux/sizes.h> +#include <linux/types.h> #include <asm/arch-fsl-layerscape/svr.h> #include <asm/arch-ls102xa/svr.h> diff --git a/drivers/pci/pcie_starfive_jh7110.c b/drivers/pci/pcie_starfive_jh7110.c index 0908ae16b67..88a2bf84538 100644 --- a/drivers/pci/pcie_starfive_jh7110.c +++ b/drivers/pci/pcie_starfive_jh7110.c @@ -15,7 +15,6 @@ #include <regmap.h> #include <reset.h> #include <syscon.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm-generic/gpio.h> #include <dm/device_compat.h> @@ -39,12 +38,11 @@ #define STG_SYSCON_RP_NEP_OFFSET 0xe8 #define STG_SYSCON_K_RP_NEP_MASK BIT(8) -DECLARE_GLOBAL_DATA_PTR; - struct starfive_pcie { struct pcie_plda plda; struct clk_bulk clks; struct reset_ctl_bulk rsts; + struct gpio_desc power_gpio; struct gpio_desc reset_gpio; struct regmap *regmap; unsigned int stg_pcie_base; @@ -184,6 +182,10 @@ static int starfive_pcie_parse_dt(struct udevice *dev) dev_err(dev, "reset-gpio is not valid\n"); return -EINVAL; } + + gpio_request_by_name(dev, "enable-gpios", 0, &priv->power_gpio, + GPIOD_IS_OUT); + return 0; } @@ -205,6 +207,9 @@ static int starfive_pcie_init_port(struct udevice *dev) goto err_deassert_clk; } + if (dm_gpio_is_valid(&priv->power_gpio)) + dm_gpio_set_value(&priv->power_gpio, 1); + dm_gpio_set_value(&priv->reset_gpio, 1); /* Disable physical functions except #0 */ for (i = 1; i < PLDA_FUNC_NUM; i++) { diff --git a/drivers/pci_endpoint/pci_ep-uclass.c b/drivers/pci_endpoint/pci_ep-uclass.c index 902d1a51eaa..b71defe4019 100644 --- a/drivers/pci_endpoint/pci_ep-uclass.c +++ b/drivers/pci_endpoint/pci_ep-uclass.c @@ -13,12 +13,9 @@ #include <dm.h> #include <errno.h> -#include <asm/global_data.h> #include <linux/log2.h> #include <pci_ep.h> -DECLARE_GLOBAL_DATA_PTR; - int pci_ep_write_header(struct udevice *dev, uint fn, struct pci_ep_header *hdr) { struct pci_ep_ops *ops = pci_ep_get_ops(dev); diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig index 549ddbf5046..8c0ab80fbbc 100644 --- a/drivers/phy/cadence/Kconfig +++ b/drivers/phy/cadence/Kconfig @@ -9,3 +9,10 @@ config PHY_CADENCE_TORRENT depends on DM_RESET help Enable this to support the Cadence Torrent PHY driver + +config SPL_PHY_CADENCE_TORRENT + bool "Cadence Torrent PHY Driver" + depends on SPL_DM_RESET + help + Enable this to support the Cadence Torrent PHY driver at SPL + stage. diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index a4121423873..b074d58f9f6 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -7,7 +7,6 @@ #include <dm.h> #include <fdtdec.h> -#include <asm/global_data.h> #include <asm/io.h> #include <dm/device_compat.h> #include <linux/err.h> @@ -18,8 +17,6 @@ #define COMPHY_MAX_CHIP 4 -DECLARE_GLOBAL_DATA_PTR; - static const char *get_speed_string(u32 speed) { static const char * const speed_strings[] = { diff --git a/drivers/phy/omap-usb2-phy.c b/drivers/phy/omap-usb2-phy.c index 2be0178882a..6df4ff4eb05 100644 --- a/drivers/phy/omap-usb2-phy.c +++ b/drivers/phy/omap-usb2-phy.c @@ -6,7 +6,6 @@ * Written by Jean-Jacques Hiblot <[email protected]> */ -#include <asm/global_data.h> #include <asm/io.h> #include <dm.h> #include <errno.h> @@ -39,8 +38,6 @@ #define USB2PHY_USE_CHG_DET_REG BIT(29) #define USB2PHY_DIS_CHG_DET BIT(28) -DECLARE_GLOBAL_DATA_PTR; - struct omap_usb2_phy { struct regmap *pwr_regmap; ulong flags; diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index 4ea6600ce7f..f80b2789333 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -421,6 +421,22 @@ static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = { { /* sentinel */ } }; +static const struct rockchip_usb2phy_cfg rk3506_phy_cfgs[] = { + { + .reg = 0xff2b0000, + .clkout_ctl_phy = { 0x041c, 7, 2, 0, 0x27 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0060, 1, 0, 2, 1 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0070, 1, 0, 2, 1 }, + } + }, + }, + { /* sentinel */ } +}; + static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = { { .reg = 0xffdf0000, @@ -541,6 +557,10 @@ static const struct udevice_id rockchip_usb2phy_ids[] = { .data = (ulong)&rk3399_usb2phy_cfgs, }, { + .compatible = "rockchip,rk3506-usb2phy", + .data = (ulong)&rk3506_phy_cfgs, + }, + { .compatible = "rockchip,rk3528-usb2phy", .data = (ulong)&rk3528_phy_cfgs, }, diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index d602f965d6a..82353ae7678 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -399,6 +399,14 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); param_write(priv->phy_grf, &cfg->usb_mode_set, true); + switch (priv->id) { + case 0: + param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true); + break; + case 1: + param_write(priv->pipe_grf, &cfg->u3otg1_port_en, true); + break; + } break; case PHY_TYPE_SATA: writel(0x41, priv->mmio + 0x38); diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c index 660037034ec..5775101c4cb 100644 --- a/drivers/phy/rockchip/phy-rockchip-pcie.c +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c @@ -9,7 +9,6 @@ #include <clk.h> #include <dm.h> -#include <asm/global_data.h> #include <dm/device_compat.h> #include <generic-phy.h> #include <reset.h> @@ -19,8 +18,6 @@ #include <linux/iopoll.h> #include <asm/arch-rockchip/clock.h> -DECLARE_GLOBAL_DATA_PTR; - /* * The higher 16-bit of this register is used for write protection * only if BIT(x + 16) set to 1 the BIT(x) can be written. diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c index 66d1d32d25c..305d5b0dd48 100644 --- a/drivers/phy/rockchip/phy-rockchip-typec.c +++ b/drivers/phy/rockchip/phy-rockchip-typec.c @@ -10,7 +10,6 @@ #include <clk.h> #include <dm.h> -#include <asm/global_data.h> #include <dm/device_compat.h> #include <dm/lists.h> #include <generic-phy.h> @@ -21,8 +20,6 @@ #include <linux/iopoll.h> #include <asm/arch-rockchip/clock.h> -DECLARE_GLOBAL_DATA_PTR; - #define usleep_range(a, b) udelay((b)) #define CMN_SSM_BANDGAP (0x21 << 2) diff --git a/drivers/phy/ti/Kconfig b/drivers/phy/ti/Kconfig index 111085f235d..df750b26d66 100644 --- a/drivers/phy/ti/Kconfig +++ b/drivers/phy/ti/Kconfig @@ -7,3 +7,13 @@ config PHY_J721E_WIZ signals to the SERDES (Sierra/Torrent). This driver configures three clock selects (pll0, pll1, dig) and resets for each of the lanes. + +config SPL_PHY_J721E_WIZ + bool "TI J721E WIZ (SERDES Wrapper) support" + depends on ARCH_K3 + help + This option enables support for WIZ module present in TI's J721E + SoC at SPL stage. WIZ is a serdes wrapper used to configure some + of the input signals to the SERDES (Sierra/Torrent). This driver + configures three clock selects (pll0, pll1, dig) and resets for + each of the lanes. diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index ea90713ec6c..578edbf8168 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -291,6 +291,15 @@ config PINCTRL_SANDBOX Currently, this driver actually does nothing but print debug messages when pinctrl operations are invoked. +config PINCTRL_SCMI + bool "Support SCMI pin controllers" + depends on PINCTRL_FULL && SCMI_FIRMWARE + help + This is for pinctrl over the SCMI protocol. This allows the + initial pin configuration to be set up from the device tree. The + gpio_scmi driver is built on top of this driver if GPIO is + required. + config PINCTRL_SINGLE bool "Single register pin-control and pin-multiplex driver" depends on DM @@ -345,7 +354,7 @@ config SPL_PINCTRL_STMFX config PINCTRL_TH1520 bool "T-Head TH1520 pinctrl driver" - depends on DM && PINCTRL_FULL + depends on DM && PINCTRL_GENERIC select PINCONF help Support pin multiplexing and configuration control blocks on the @@ -386,6 +395,14 @@ config PINCTRL_ZYNQMP Generic Pinctrl framework and is compatible with the Linux driver, i.e. it uses the same device tree configuration. +config SPL_PINCTRL_ZYNQMP + bool "Xilinx ZynqMP pin control driver in SPL" + depends on SPL_DM && SPL_PINCTRL_GENERIC && ARCH_ZYNQMP + default PINCTRL_ZYNQMP + help + Support pin multiplexing control in SPL on Xilinx ZynqMP. Only "pins" + can be muxed; "groups" are not supported. + endif source "drivers/pinctrl/broadcom/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 33ff7b95ef2..29fb9b484d0 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_PINCTRL_MSCC) += mscc/ obj-$(CONFIG_ARCH_MVEBU) += mvebu/ obj-$(CONFIG_ARCH_NEXELL) += nexell/ obj-$(CONFIG_PINCTRL_QE) += pinctrl-qe-io.o +obj-$(CONFIG_PINCTRL_SCMI) += pinctrl-scmi.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o obj-$(CONFIG_PINCTRL_STM32) += pinctrl_stm32.o @@ -36,5 +37,5 @@ obj-$(CONFIG_$(PHASE_)PINCTRL_SX150X) += pinctrl-sx150x.o obj-$(CONFIG_$(PHASE_)PINCTRL_STMFX) += pinctrl-stmfx.o obj-$(CONFIG_PINCTRL_TH1520) += pinctrl-th1520.o obj-y += broadcom/ -obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o +obj-$(CONFIG_$(PHASE_)PINCTRL_ZYNQMP) += pinctrl-zynqmp.o obj-$(CONFIG_PINCTRL_STARFIVE) += starfive/ diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 8a588d17c4b..cf72a7df62c 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -38,6 +38,14 @@ config PINCTRL_MT8188 bool "MT8188 SoC pinctrl driver" select PINCTRL_MTK +config PINCTRL_MT8195 + bool "MT8195 SoC pinctrl driver" + select PINCTRL_MTK + +config PINCTRL_MT8189 + bool "MT8189 SoC pinctrl driver" + select PINCTRL_MTK + config PINCTRL_MT8365 bool "MT8365 SoC pinctrl driver" select PINCTRL_MTK diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index b9116c073ea..f90c74314f4 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -11,6 +11,8 @@ obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o obj-$(CONFIG_PINCTRL_MT7987) += pinctrl-mt7987.o obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o obj-$(CONFIG_PINCTRL_MT8188) += pinctrl-mt8188.o +obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o +obj-$(CONFIG_PINCTRL_MT8189) += pinctrl-mt8189.o obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/drivers/pinctrl/mediatek/pinctrl-mt7981.c index 0d48994bd89..8875c276f36 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c @@ -1070,6 +1070,7 @@ static const struct mtk_pinctrl_soc mt7981_data = { .gpio_mode = 0, .base_names = mt7981_pinctrl_register_base_names, .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names), + .rev = MTK_PINCTRL_V1, .base_calc = 1, }; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/drivers/pinctrl/mediatek/pinctrl-mt7986.c index 61ce2ec8ac1..3288cc93972 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c @@ -755,6 +755,7 @@ static const struct mtk_pinctrl_soc mt7986_data = { .gpio_mode = 0, .base_names = mt7986_pinctrl_register_base_names, .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), + .rev = MTK_PINCTRL_V1, .base_calc = 1, }; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7987.c b/drivers/pinctrl/mediatek/pinctrl-mt7987.c index 92b43cf3b55..0c90c1ceec5 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7987.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7987.c @@ -712,6 +712,7 @@ static const struct mtk_pinctrl_soc mt7987_data = { .gpio_mode = 0, .base_names = mt7987_pinctrl_register_base_names, .nbase_names = ARRAY_SIZE(mt7987_pinctrl_register_base_names), + .rev = MTK_PINCTRL_V1, .base_calc = 1, }; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/drivers/pinctrl/mediatek/pinctrl-mt7988.c index 74655493414..43982d7a859 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7988.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7988.c @@ -1250,6 +1250,7 @@ static const struct mtk_pinctrl_soc mt7988_data = { .gpio_mode = 0, .base_names = mt7988_pinctrl_register_base_names, .nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names), + .rev = MTK_PINCTRL_V1, .base_calc = 1, }; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8188.c b/drivers/pinctrl/mediatek/pinctrl-mt8188.c index 386d4d4a922..256053f269f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8188.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8188.c @@ -1339,6 +1339,7 @@ U_BOOT_DRIVER(mt8188_pinctrl) = { .id = UCLASS_PINCTRL, .of_match = mt8188_pctrl_match, .ops = &mtk_pinctrl_ops, + .bind = mtk_pinctrl_common_bind, .probe = mtk_pinctrl_mt8188_probe, .priv_auto = sizeof(struct mtk_pinctrl_priv), }; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8189.c b/drivers/pinctrl/mediatek/pinctrl-mt8189.c new file mode 100644 index 00000000000..a64440d8bb3 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt8189.c @@ -0,0 +1,1277 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 MediaTek Inc. + * Author: Bo-Chen Chen <[email protected]> + */ +#include <dm.h> +#include "pinctrl-mtk-common.h" + +enum { + IO_BASE, + IO_BASE_LM, + IO_BASE_RB0, + IO_BASE_RB1, + IO_BASE_BM0, + IO_BASE_BM1, + IO_BASE_BM2, + IO_BASE_LT0, + IO_BASE_LT1, + IO_BASE_RT, + IO_BASE_EINT0, + IO_BASE_EINT1, + IO_BASE_EINT2, + IO_BASE_EINT3, + IO_BASE_EINT4, +}; + +#define PIN_FIELD_IOCFG0(s_pin, e_pin, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_BASE_CALC(s_pin, e_pin, IO_BASE, s_addr, x_addrs, s_bit, \ + x_bits, 32, 0) + +#define PIN_FIELD_BASE(pin, i_base, s_addr, s_bit, x_bits) \ + PIN_FIELD_BASE_CALC(pin, pin, i_base, s_addr, 0x10, s_bit, x_bits, \ + 32, 0) + +static const struct mtk_pin_field_calc mt8189_pin_mode_range[] = { + PIN_FIELD_IOCFG0(0, 182, 0x0300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt8189_pin_dir_range[] = { + PIN_FIELD_IOCFG0(0, 182, 0x0000, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_di_range[] = { + PIN_FIELD_IOCFG0(0, 182, 0x0200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_do_range[] = { + PIN_FIELD_IOCFG0(0, 182, 0x0100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_smt_range[] = { + PIN_FIELD_BASE(0, IO_BASE_RB0, 0x00e0, 5, 1), + PIN_FIELD_BASE(1, IO_BASE_RB1, 0x00c0, 3, 1), + PIN_FIELD_BASE(2, IO_BASE_RB1, 0x00c0, 4, 1), + PIN_FIELD_BASE(3, IO_BASE_RB1, 0x00c0, 5, 1), + PIN_FIELD_BASE(4, IO_BASE_RB1, 0x00c0, 6, 1), + PIN_FIELD_BASE(5, IO_BASE_RB1, 0x00c0, 7, 1), + PIN_FIELD_BASE(6, IO_BASE_RB0, 0x00e0, 6, 1), + PIN_FIELD_BASE(7, IO_BASE_RB0, 0x00e0, 7, 1), + PIN_FIELD_BASE(8, IO_BASE_RB0, 0x00e0, 8, 1), + PIN_FIELD_BASE(9, IO_BASE_RB0, 0x00e0, 9, 1), + PIN_FIELD_BASE(10, IO_BASE_RB0, 0x00e0, 10, 1), + PIN_FIELD_BASE(11, IO_BASE_RB0, 0x00e0, 11, 1), + PIN_FIELD_BASE(12, IO_BASE_BM1, 0x00e0, 5, 1), + PIN_FIELD_BASE(13, IO_BASE_BM1, 0x00e0, 6, 1), + PIN_FIELD_BASE(14, IO_BASE_BM2, 0x00f0, 0, 1), + PIN_FIELD_BASE(15, IO_BASE_BM2, 0x00f0, 1, 1), + PIN_FIELD_BASE(16, IO_BASE_BM1, 0x00e0, 7, 1), + PIN_FIELD_BASE(17, IO_BASE_BM1, 0x00e0, 8, 1), + PIN_FIELD_BASE(18, IO_BASE_RB0, 0x00e0, 0, 1), + PIN_FIELD_BASE(19, IO_BASE_RB0, 0x00e0, 2, 1), + PIN_FIELD_BASE(20, IO_BASE_RB0, 0x00e0, 1, 1), + PIN_FIELD_BASE(21, IO_BASE_RB0, 0x00e0, 3, 1), + PIN_FIELD_BASE(22, IO_BASE_RT, 0x00f0, 0, 1), + PIN_FIELD_BASE(23, IO_BASE_RT, 0x00f0, 1, 1), + PIN_FIELD_BASE(24, IO_BASE_RT, 0x00f0, 2, 1), + PIN_FIELD_BASE(25, IO_BASE_LM, 0x00c0, 2, 1), + PIN_FIELD_BASE(26, IO_BASE_LM, 0x00c0, 1, 1), + PIN_FIELD_BASE(27, IO_BASE_BM1, 0x00e0, 1, 1), + PIN_FIELD_BASE(28, IO_BASE_BM1, 0x00e0, 2, 1), + PIN_FIELD_BASE(29, IO_BASE_LM, 0x00c0, 0, 1), + PIN_FIELD_BASE(30, IO_BASE_BM1, 0x00e0, 0, 1), + PIN_FIELD_BASE(31, IO_BASE_BM2, 0x00f0, 19, 1), + PIN_FIELD_BASE(32, IO_BASE_BM0, 0x00c0, 30, 1), + PIN_FIELD_BASE(33, IO_BASE_BM2, 0x00f0, 21, 1), + PIN_FIELD_BASE(34, IO_BASE_BM2, 0x00f0, 20, 1), + PIN_FIELD_BASE(35, IO_BASE_BM2, 0x00f0, 23, 1), + PIN_FIELD_BASE(36, IO_BASE_BM2, 0x00f0, 22, 1), + PIN_FIELD_BASE(37, IO_BASE_BM2, 0x00f0, 25, 1), + PIN_FIELD_BASE(38, IO_BASE_BM2, 0x00f0, 24, 1), + PIN_FIELD_BASE(39, IO_BASE_BM2, 0x00f0, 5, 1), + PIN_FIELD_BASE(40, IO_BASE_BM2, 0x00f0, 2, 1), + PIN_FIELD_BASE(41, IO_BASE_BM2, 0x00f0, 3, 1), + PIN_FIELD_BASE(42, IO_BASE_BM2, 0x00f0, 4, 1), + PIN_FIELD_BASE(43, IO_BASE_BM2, 0x00f0, 6, 1), + PIN_FIELD_BASE(44, IO_BASE_RB0, 0x00e0, 20, 1), + PIN_FIELD_BASE(45, IO_BASE_RB0, 0x00e0, 21, 1), + PIN_FIELD_BASE(46, IO_BASE_RB0, 0x00e0, 22, 1), + PIN_FIELD_BASE(47, IO_BASE_RB0, 0x00e0, 23, 1), + PIN_FIELD_BASE(48, IO_BASE_LM, 0x00c0, 5, 1), + PIN_FIELD_BASE(49, IO_BASE_LM, 0x00c0, 4, 1), + PIN_FIELD_BASE(50, IO_BASE_LM, 0x00c0, 3, 1), + PIN_FIELD_BASE(51, IO_BASE_RB1, 0x00c0, 8, 1), + PIN_FIELD_BASE(52, IO_BASE_RB1, 0x00c0, 10, 1), + PIN_FIELD_BASE(53, IO_BASE_RB1, 0x00c0, 9, 1), + PIN_FIELD_BASE(54, IO_BASE_RB1, 0x00c0, 11, 1), + PIN_FIELD_BASE(55, IO_BASE_LM, 0x00c0, 6, 1), + PIN_FIELD_BASE(56, IO_BASE_LM, 0x00c0, 7, 1), + PIN_FIELD_BASE(57, IO_BASE_BM1, 0x00e0, 13, 1), + PIN_FIELD_BASE(58, IO_BASE_BM1, 0x00e0, 17, 1), + PIN_FIELD_BASE(59, IO_BASE_BM1, 0x00e0, 14, 1), + PIN_FIELD_BASE(60, IO_BASE_BM1, 0x00e0, 18, 1), + PIN_FIELD_BASE(61, IO_BASE_BM1, 0x00e0, 15, 1), + PIN_FIELD_BASE(62, IO_BASE_BM1, 0x00e0, 19, 1), + PIN_FIELD_BASE(63, IO_BASE_BM1, 0x00e0, 16, 1), + PIN_FIELD_BASE(64, IO_BASE_BM1, 0x00e0, 20, 1), + PIN_FIELD_BASE(65, IO_BASE_RT, 0x00f0, 10, 1), + PIN_FIELD_BASE(66, IO_BASE_RT, 0x00f0, 12, 1), + PIN_FIELD_BASE(67, IO_BASE_RT, 0x00f0, 11, 1), + PIN_FIELD_BASE(68, IO_BASE_RT, 0x00f0, 13, 1), + PIN_FIELD_BASE(69, IO_BASE_BM1, 0x00e0, 22, 1), + PIN_FIELD_BASE(70, IO_BASE_BM1, 0x00e0, 21, 1), + PIN_FIELD_BASE(71, IO_BASE_BM1, 0x00e0, 24, 1), + PIN_FIELD_BASE(72, IO_BASE_BM1, 0x00e0, 23, 1), + PIN_FIELD_BASE(73, IO_BASE_BM1, 0x00e0, 26, 1), + PIN_FIELD_BASE(74, IO_BASE_BM1, 0x00e0, 25, 1), + PIN_FIELD_BASE(75, IO_BASE_BM2, 0x00f0, 13, 1), + PIN_FIELD_BASE(76, IO_BASE_BM1, 0x00e0, 27, 1), + PIN_FIELD_BASE(77, IO_BASE_RB1, 0x00c0, 13, 1), + PIN_FIELD_BASE(78, IO_BASE_RB1, 0x00c0, 12, 1), + PIN_FIELD_BASE(79, IO_BASE_RB1, 0x00c0, 15, 1), + PIN_FIELD_BASE(80, IO_BASE_RB1, 0x00c0, 14, 1), + PIN_FIELD_BASE(81, IO_BASE_BM1, 0x00e0, 29, 1), + PIN_FIELD_BASE(82, IO_BASE_BM1, 0x00e0, 28, 1), + PIN_FIELD_BASE(83, IO_BASE_BM1, 0x00e0, 30, 1), + PIN_FIELD_BASE(84, IO_BASE_RB0, 0x00e0, 24, 1), + PIN_FIELD_BASE(85, IO_BASE_RB0, 0x00e0, 25, 1), + PIN_FIELD_BASE(86, IO_BASE_RB0, 0x00e0, 26, 1), + PIN_FIELD_BASE(87, IO_BASE_RB0, 0x00e0, 27, 1), + PIN_FIELD_BASE(88, IO_BASE_LT0, 0x0120, 20, 1), + PIN_FIELD_BASE(89, IO_BASE_LT0, 0x0120, 19, 1), + PIN_FIELD_BASE(90, IO_BASE_LT0, 0x0120, 22, 1), + PIN_FIELD_BASE(91, IO_BASE_LT0, 0x0120, 21, 1), + PIN_FIELD_BASE(92, IO_BASE_LT0, 0x0120, 16, 1), + PIN_FIELD_BASE(93, IO_BASE_LT0, 0x0120, 17, 1), + PIN_FIELD_BASE(94, IO_BASE_LT0, 0x0120, 23, 1), + PIN_FIELD_BASE(95, IO_BASE_LT0, 0x0120, 15, 1), + PIN_FIELD_BASE(96, IO_BASE_LT0, 0x0120, 18, 1), + PIN_FIELD_BASE(97, IO_BASE_LT0, 0x0120, 0, 1), + PIN_FIELD_BASE(98, IO_BASE_LT0, 0x0120, 5, 1), + PIN_FIELD_BASE(99, IO_BASE_LT0, 0x0120, 3, 1), + PIN_FIELD_BASE(100, IO_BASE_LT0, 0x0120, 4, 1), + PIN_FIELD_BASE(101, IO_BASE_LT0, 0x0120, 1, 1), + PIN_FIELD_BASE(102, IO_BASE_LT0, 0x0120, 2, 1), + PIN_FIELD_BASE(103, IO_BASE_RB0, 0x00e0, 15, 1), + PIN_FIELD_BASE(104, IO_BASE_RB0, 0x00e0, 12, 1), + PIN_FIELD_BASE(105, IO_BASE_RB0, 0x00e0, 14, 1), + PIN_FIELD_BASE(106, IO_BASE_RB0, 0x00e0, 13, 1), + PIN_FIELD_BASE(107, IO_BASE_RB0, 0x00e0, 19, 1), + PIN_FIELD_BASE(108, IO_BASE_RB0, 0x00e0, 16, 1), + PIN_FIELD_BASE(109, IO_BASE_RB0, 0x00e0, 18, 1), + PIN_FIELD_BASE(110, IO_BASE_RB0, 0x00e0, 17, 1), + PIN_FIELD_BASE(111, IO_BASE_RB0, 0x00e0, 4, 1), + PIN_FIELD_BASE(112, IO_BASE_RB1, 0x00c0, 0, 1), + PIN_FIELD_BASE(113, IO_BASE_RB1, 0x00c0, 1, 1), + PIN_FIELD_BASE(114, IO_BASE_RB1, 0x00c0, 2, 1), + PIN_FIELD_BASE(115, IO_BASE_BM1, 0x00e0, 9, 1), + PIN_FIELD_BASE(116, IO_BASE_BM1, 0x00e0, 12, 1), + PIN_FIELD_BASE(117, IO_BASE_BM1, 0x00e0, 10, 1), + PIN_FIELD_BASE(118, IO_BASE_BM1, 0x00e0, 11, 1), + PIN_FIELD_BASE(119, IO_BASE_BM0, 0x00c0, 26, 1), + PIN_FIELD_BASE(120, IO_BASE_BM0, 0x00c0, 25, 1), + PIN_FIELD_BASE(121, IO_BASE_BM0, 0x00c0, 24, 1), + PIN_FIELD_BASE(122, IO_BASE_BM0, 0x00c0, 23, 1), + PIN_FIELD_BASE(123, IO_BASE_BM0, 0x00c0, 19, 1), + PIN_FIELD_BASE(124, IO_BASE_BM0, 0x00c0, 18, 1), + PIN_FIELD_BASE(125, IO_BASE_BM0, 0x00c0, 17, 1), + PIN_FIELD_BASE(126, IO_BASE_BM0, 0x00c0, 16, 1), + PIN_FIELD_BASE(127, IO_BASE_BM0, 0x00c0, 22, 1), + PIN_FIELD_BASE(128, IO_BASE_BM0, 0x00c0, 15, 1), + PIN_FIELD_BASE(129, IO_BASE_BM0, 0x00c0, 20, 1), + PIN_FIELD_BASE(130, IO_BASE_BM0, 0x00c0, 27, 1), + PIN_FIELD_BASE(131, IO_BASE_BM0, 0x00c0, 13, 1), + PIN_FIELD_BASE(132, IO_BASE_BM0, 0x00c0, 14, 1), + PIN_FIELD_BASE(133, IO_BASE_BM0, 0x00c0, 28, 1), + PIN_FIELD_BASE(134, IO_BASE_BM0, 0x00c0, 21, 1), + PIN_FIELD_BASE(135, IO_BASE_BM0, 0x00c0, 11, 1), + PIN_FIELD_BASE(136, IO_BASE_BM0, 0x00c0, 12, 1), + PIN_FIELD_BASE(137, IO_BASE_BM1, 0x00e0, 3, 1), + PIN_FIELD_BASE(138, IO_BASE_BM1, 0x00e0, 4, 1), + PIN_FIELD_BASE(139, IO_BASE_BM0, 0x00c0, 3, 1), + PIN_FIELD_BASE(140, IO_BASE_BM0, 0x00c0, 4, 1), + PIN_FIELD_BASE(141, IO_BASE_BM0, 0x00c0, 0, 1), + PIN_FIELD_BASE(142, IO_BASE_BM0, 0x00c0, 1, 1), + PIN_FIELD_BASE(143, IO_BASE_BM0, 0x00c0, 2, 1), + PIN_FIELD_BASE(144, IO_BASE_BM0, 0x00c0, 5, 1), + PIN_FIELD_BASE(145, IO_BASE_BM0, 0x00c0, 6, 1), + PIN_FIELD_BASE(146, IO_BASE_BM0, 0x00c0, 7, 1), + PIN_FIELD_BASE(147, IO_BASE_BM0, 0x00c0, 8, 1), + PIN_FIELD_BASE(148, IO_BASE_BM0, 0x00c0, 9, 1), + PIN_FIELD_BASE(149, IO_BASE_BM0, 0x00c0, 10, 1), + PIN_FIELD_BASE(150, IO_BASE_BM2, 0x00f0, 14, 1), + PIN_FIELD_BASE(151, IO_BASE_BM0, 0x00c0, 29, 1), + PIN_FIELD_BASE(152, IO_BASE_BM2, 0x00f0, 15, 1), + PIN_FIELD_BASE(153, IO_BASE_BM2, 0x00f0, 16, 1), + PIN_FIELD_BASE(154, IO_BASE_BM2, 0x00f0, 17, 1), + PIN_FIELD_BASE(155, IO_BASE_BM2, 0x00f0, 18, 1), + PIN_FIELD_BASE(156, IO_BASE_LT0, 0x0120, 12, 1), + PIN_FIELD_BASE(157, IO_BASE_LT0, 0x0120, 11, 1), + PIN_FIELD_BASE(158, IO_BASE_LT0, 0x0120, 10, 1), + PIN_FIELD_BASE(159, IO_BASE_LT1, 0x0090, 2, 1), + PIN_FIELD_BASE(160, IO_BASE_LT0, 0x0120, 14, 1), + PIN_FIELD_BASE(161, IO_BASE_LT0, 0x0120, 7, 1), + PIN_FIELD_BASE(162, IO_BASE_LT0, 0x0120, 6, 1), + PIN_FIELD_BASE(163, IO_BASE_LT1, 0x0090, 1, 1), + PIN_FIELD_BASE(164, IO_BASE_LT0, 0x0120, 9, 1), + PIN_FIELD_BASE(165, IO_BASE_LT0, 0x0120, 8, 1), + PIN_FIELD_BASE(166, IO_BASE_LT1, 0x0090, 0, 1), + PIN_FIELD_BASE(167, IO_BASE_LT0, 0x0120, 13, 1), + PIN_FIELD_BASE(168, IO_BASE_BM2, 0x00f0, 8, 1), + PIN_FIELD_BASE(169, IO_BASE_BM2, 0x00f0, 7, 1), + PIN_FIELD_BASE(170, IO_BASE_BM2, 0x00f0, 9, 1), + PIN_FIELD_BASE(171, IO_BASE_BM2, 0x00f0, 10, 1), + PIN_FIELD_BASE(172, IO_BASE_BM2, 0x00f0, 11, 1), + PIN_FIELD_BASE(173, IO_BASE_BM2, 0x00f0, 12, 1), + PIN_FIELD_BASE(174, IO_BASE_RT, 0x00f0, 5, 1), + PIN_FIELD_BASE(175, IO_BASE_RT, 0x00f0, 4, 1), + PIN_FIELD_BASE(176, IO_BASE_RT, 0x00f0, 6, 1), + PIN_FIELD_BASE(177, IO_BASE_RT, 0x00f0, 7, 1), + PIN_FIELD_BASE(178, IO_BASE_RT, 0x00f0, 8, 1), + PIN_FIELD_BASE(179, IO_BASE_RT, 0x00f0, 9, 1), + PIN_FIELD_BASE(180, IO_BASE_LT0, 0x0120, 24, 1), + PIN_FIELD_BASE(181, IO_BASE_LT0, 0x0120, 25, 1), + PIN_FIELD_BASE(182, IO_BASE_RT, 0x00f0, 3, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_ies_range[] = { + PIN_FIELD_BASE(0, IO_BASE_RB0, 0x0050, 5, 1), + PIN_FIELD_BASE(1, IO_BASE_RB1, 0x0050, 3, 1), + PIN_FIELD_BASE(2, IO_BASE_RB1, 0x0050, 4, 1), + PIN_FIELD_BASE(3, IO_BASE_RB1, 0x0050, 5, 1), + PIN_FIELD_BASE(4, IO_BASE_RB1, 0x0050, 6, 1), + PIN_FIELD_BASE(5, IO_BASE_RB1, 0x0050, 7, 1), + PIN_FIELD_BASE(6, IO_BASE_RB0, 0x0050, 6, 1), + PIN_FIELD_BASE(7, IO_BASE_RB0, 0x0050, 7, 1), + PIN_FIELD_BASE(8, IO_BASE_RB0, 0x0050, 8, 1), + PIN_FIELD_BASE(9, IO_BASE_RB0, 0x0050, 9, 1), + PIN_FIELD_BASE(10, IO_BASE_RB0, 0x0050, 10, 1), + PIN_FIELD_BASE(11, IO_BASE_RB0, 0x0050, 11, 1), + PIN_FIELD_BASE(12, IO_BASE_BM1, 0x0070, 5, 1), + PIN_FIELD_BASE(13, IO_BASE_BM1, 0x0070, 6, 1), + PIN_FIELD_BASE(14, IO_BASE_BM2, 0x0050, 0, 1), + PIN_FIELD_BASE(15, IO_BASE_BM2, 0x0050, 1, 1), + PIN_FIELD_BASE(16, IO_BASE_BM1, 0x0070, 7, 1), + PIN_FIELD_BASE(17, IO_BASE_BM1, 0x0070, 8, 1), + PIN_FIELD_BASE(18, IO_BASE_RB0, 0x0050, 0, 1), + PIN_FIELD_BASE(19, IO_BASE_RB0, 0x0050, 2, 1), + PIN_FIELD_BASE(20, IO_BASE_RB0, 0x0050, 1, 1), + PIN_FIELD_BASE(21, IO_BASE_RB0, 0x0050, 3, 1), + PIN_FIELD_BASE(22, IO_BASE_RT, 0x0040, 0, 1), + PIN_FIELD_BASE(23, IO_BASE_RT, 0x0040, 1, 1), + PIN_FIELD_BASE(24, IO_BASE_RT, 0x0040, 2, 1), + PIN_FIELD_BASE(25, IO_BASE_LM, 0x0050, 2, 1), + PIN_FIELD_BASE(26, IO_BASE_LM, 0x0050, 1, 1), + PIN_FIELD_BASE(27, IO_BASE_BM1, 0x0070, 1, 1), + PIN_FIELD_BASE(28, IO_BASE_BM1, 0x0070, 2, 1), + PIN_FIELD_BASE(29, IO_BASE_LM, 0x0050, 0, 1), + PIN_FIELD_BASE(30, IO_BASE_BM1, 0x0070, 0, 1), + PIN_FIELD_BASE(31, IO_BASE_BM2, 0x0050, 19, 1), + PIN_FIELD_BASE(32, IO_BASE_BM0, 0x0050, 30, 1), + PIN_FIELD_BASE(33, IO_BASE_BM2, 0x0050, 21, 1), + PIN_FIELD_BASE(34, IO_BASE_BM2, 0x0050, 20, 1), + PIN_FIELD_BASE(35, IO_BASE_BM2, 0x0050, 23, 1), + PIN_FIELD_BASE(36, IO_BASE_BM2, 0x0050, 22, 1), + PIN_FIELD_BASE(37, IO_BASE_BM2, 0x0050, 25, 1), + PIN_FIELD_BASE(38, IO_BASE_BM2, 0x0050, 24, 1), + PIN_FIELD_BASE(39, IO_BASE_BM2, 0x0050, 5, 1), + PIN_FIELD_BASE(40, IO_BASE_BM2, 0x0050, 2, 1), + PIN_FIELD_BASE(41, IO_BASE_BM2, 0x0050, 3, 1), + PIN_FIELD_BASE(42, IO_BASE_BM2, 0x0050, 4, 1), + PIN_FIELD_BASE(43, IO_BASE_BM2, 0x0050, 6, 1), + PIN_FIELD_BASE(44, IO_BASE_RB0, 0x0050, 20, 1), + PIN_FIELD_BASE(45, IO_BASE_RB0, 0x0050, 21, 1), + PIN_FIELD_BASE(46, IO_BASE_RB0, 0x0050, 22, 1), + PIN_FIELD_BASE(47, IO_BASE_RB0, 0x0050, 23, 1), + PIN_FIELD_BASE(48, IO_BASE_LM, 0x0050, 5, 1), + PIN_FIELD_BASE(49, IO_BASE_LM, 0x0050, 4, 1), + PIN_FIELD_BASE(50, IO_BASE_LM, 0x0050, 3, 1), + PIN_FIELD_BASE(51, IO_BASE_RB1, 0x0050, 8, 1), + PIN_FIELD_BASE(52, IO_BASE_RB1, 0x0050, 10, 1), + PIN_FIELD_BASE(53, IO_BASE_RB1, 0x0050, 9, 1), + PIN_FIELD_BASE(54, IO_BASE_RB1, 0x0050, 11, 1), + PIN_FIELD_BASE(55, IO_BASE_LM, 0x0050, 6, 1), + PIN_FIELD_BASE(56, IO_BASE_LM, 0x0050, 7, 1), + PIN_FIELD_BASE(57, IO_BASE_BM1, 0x0070, 13, 1), + PIN_FIELD_BASE(58, IO_BASE_BM1, 0x0070, 17, 1), + PIN_FIELD_BASE(59, IO_BASE_BM1, 0x0070, 14, 1), + PIN_FIELD_BASE(60, IO_BASE_BM1, 0x0070, 18, 1), + PIN_FIELD_BASE(61, IO_BASE_BM1, 0x0070, 15, 1), + PIN_FIELD_BASE(62, IO_BASE_BM1, 0x0070, 19, 1), + PIN_FIELD_BASE(63, IO_BASE_BM1, 0x0070, 16, 1), + PIN_FIELD_BASE(64, IO_BASE_BM1, 0x0070, 20, 1), + PIN_FIELD_BASE(65, IO_BASE_RT, 0x0040, 10, 1), + PIN_FIELD_BASE(66, IO_BASE_RT, 0x0040, 12, 1), + PIN_FIELD_BASE(67, IO_BASE_RT, 0x0040, 11, 1), + PIN_FIELD_BASE(68, IO_BASE_RT, 0x0040, 13, 1), + PIN_FIELD_BASE(69, IO_BASE_BM1, 0x0070, 22, 1), + PIN_FIELD_BASE(70, IO_BASE_BM1, 0x0070, 21, 1), + PIN_FIELD_BASE(71, IO_BASE_BM1, 0x0070, 24, 1), + PIN_FIELD_BASE(72, IO_BASE_BM1, 0x0070, 23, 1), + PIN_FIELD_BASE(73, IO_BASE_BM1, 0x0070, 26, 1), + PIN_FIELD_BASE(74, IO_BASE_BM1, 0x0070, 25, 1), + PIN_FIELD_BASE(75, IO_BASE_BM2, 0x0050, 13, 1), + PIN_FIELD_BASE(76, IO_BASE_BM1, 0x0070, 27, 1), + PIN_FIELD_BASE(77, IO_BASE_RB1, 0x0050, 13, 1), + PIN_FIELD_BASE(78, IO_BASE_RB1, 0x0050, 12, 1), + PIN_FIELD_BASE(79, IO_BASE_RB1, 0x0050, 15, 1), + PIN_FIELD_BASE(80, IO_BASE_RB1, 0x0050, 14, 1), + PIN_FIELD_BASE(81, IO_BASE_BM1, 0x0070, 29, 1), + PIN_FIELD_BASE(82, IO_BASE_BM1, 0x0070, 28, 1), + PIN_FIELD_BASE(83, IO_BASE_BM1, 0x0070, 30, 1), + PIN_FIELD_BASE(84, IO_BASE_RB0, 0x0050, 24, 1), + PIN_FIELD_BASE(85, IO_BASE_RB0, 0x0050, 25, 1), + PIN_FIELD_BASE(86, IO_BASE_RB0, 0x0050, 26, 1), + PIN_FIELD_BASE(87, IO_BASE_RB0, 0x0050, 27, 1), + PIN_FIELD_BASE(88, IO_BASE_LT0, 0x0060, 20, 1), + PIN_FIELD_BASE(89, IO_BASE_LT0, 0x0060, 19, 1), + PIN_FIELD_BASE(90, IO_BASE_LT0, 0x0060, 22, 1), + PIN_FIELD_BASE(91, IO_BASE_LT0, 0x0060, 21, 1), + PIN_FIELD_BASE(92, IO_BASE_LT0, 0x0060, 16, 1), + PIN_FIELD_BASE(93, IO_BASE_LT0, 0x0060, 17, 1), + PIN_FIELD_BASE(94, IO_BASE_LT0, 0x0060, 23, 1), + PIN_FIELD_BASE(95, IO_BASE_LT0, 0x0060, 15, 1), + PIN_FIELD_BASE(96, IO_BASE_LT0, 0x0060, 18, 1), + PIN_FIELD_BASE(97, IO_BASE_LT0, 0x0060, 0, 1), + PIN_FIELD_BASE(98, IO_BASE_LT0, 0x0060, 5, 1), + PIN_FIELD_BASE(99, IO_BASE_LT0, 0x0060, 3, 1), + PIN_FIELD_BASE(100, IO_BASE_LT0, 0x0060, 4, 1), + PIN_FIELD_BASE(101, IO_BASE_LT0, 0x0060, 1, 1), + PIN_FIELD_BASE(102, IO_BASE_LT0, 0x0060, 2, 1), + PIN_FIELD_BASE(103, IO_BASE_RB0, 0x0050, 15, 1), + PIN_FIELD_BASE(104, IO_BASE_RB0, 0x0050, 12, 1), + PIN_FIELD_BASE(105, IO_BASE_RB0, 0x0050, 14, 1), + PIN_FIELD_BASE(106, IO_BASE_RB0, 0x0050, 13, 1), + PIN_FIELD_BASE(107, IO_BASE_RB0, 0x0050, 19, 1), + PIN_FIELD_BASE(108, IO_BASE_RB0, 0x0050, 16, 1), + PIN_FIELD_BASE(109, IO_BASE_RB0, 0x0050, 18, 1), + PIN_FIELD_BASE(110, IO_BASE_RB0, 0x0050, 17, 1), + PIN_FIELD_BASE(111, IO_BASE_RB0, 0x0050, 4, 1), + PIN_FIELD_BASE(112, IO_BASE_RB1, 0x0050, 0, 1), + PIN_FIELD_BASE(113, IO_BASE_RB1, 0x0050, 1, 1), + PIN_FIELD_BASE(114, IO_BASE_RB1, 0x0050, 2, 1), + PIN_FIELD_BASE(115, IO_BASE_BM1, 0x0070, 9, 1), + PIN_FIELD_BASE(116, IO_BASE_BM1, 0x0070, 12, 1), + PIN_FIELD_BASE(117, IO_BASE_BM1, 0x0070, 10, 1), + PIN_FIELD_BASE(118, IO_BASE_BM1, 0x0070, 11, 1), + PIN_FIELD_BASE(119, IO_BASE_BM0, 0x0050, 26, 1), + PIN_FIELD_BASE(120, IO_BASE_BM0, 0x0050, 25, 1), + PIN_FIELD_BASE(121, IO_BASE_BM0, 0x0050, 24, 1), + PIN_FIELD_BASE(122, IO_BASE_BM0, 0x0050, 23, 1), + PIN_FIELD_BASE(123, IO_BASE_BM0, 0x0050, 19, 1), + PIN_FIELD_BASE(124, IO_BASE_BM0, 0x0050, 18, 1), + PIN_FIELD_BASE(125, IO_BASE_BM0, 0x0050, 17, 1), + PIN_FIELD_BASE(126, IO_BASE_BM0, 0x0050, 16, 1), + PIN_FIELD_BASE(127, IO_BASE_BM0, 0x0050, 22, 1), + PIN_FIELD_BASE(128, IO_BASE_BM0, 0x0050, 15, 1), + PIN_FIELD_BASE(129, IO_BASE_BM0, 0x0050, 20, 1), + PIN_FIELD_BASE(130, IO_BASE_BM0, 0x0050, 27, 1), + PIN_FIELD_BASE(131, IO_BASE_BM0, 0x0050, 13, 1), + PIN_FIELD_BASE(132, IO_BASE_BM0, 0x0050, 14, 1), + PIN_FIELD_BASE(133, IO_BASE_BM0, 0x0050, 28, 1), + PIN_FIELD_BASE(134, IO_BASE_BM0, 0x0050, 21, 1), + PIN_FIELD_BASE(135, IO_BASE_BM0, 0x0050, 11, 1), + PIN_FIELD_BASE(136, IO_BASE_BM0, 0x0050, 12, 1), + PIN_FIELD_BASE(137, IO_BASE_BM1, 0x0070, 3, 1), + PIN_FIELD_BASE(138, IO_BASE_BM1, 0x0070, 4, 1), + PIN_FIELD_BASE(139, IO_BASE_BM0, 0x0050, 3, 1), + PIN_FIELD_BASE(140, IO_BASE_BM0, 0x0050, 4, 1), + PIN_FIELD_BASE(141, IO_BASE_BM0, 0x0050, 0, 1), + PIN_FIELD_BASE(142, IO_BASE_BM0, 0x0050, 1, 1), + PIN_FIELD_BASE(143, IO_BASE_BM0, 0x0050, 2, 1), + PIN_FIELD_BASE(144, IO_BASE_BM0, 0x0050, 5, 1), + PIN_FIELD_BASE(145, IO_BASE_BM0, 0x0050, 6, 1), + PIN_FIELD_BASE(146, IO_BASE_BM0, 0x0050, 7, 1), + PIN_FIELD_BASE(147, IO_BASE_BM0, 0x0050, 8, 1), + PIN_FIELD_BASE(148, IO_BASE_BM0, 0x0050, 9, 1), + PIN_FIELD_BASE(149, IO_BASE_BM0, 0x0050, 10, 1), + PIN_FIELD_BASE(150, IO_BASE_BM2, 0x0050, 14, 1), + PIN_FIELD_BASE(151, IO_BASE_BM0, 0x0050, 29, 1), + PIN_FIELD_BASE(152, IO_BASE_BM2, 0x0050, 15, 1), + PIN_FIELD_BASE(153, IO_BASE_BM2, 0x0050, 16, 1), + PIN_FIELD_BASE(154, IO_BASE_BM2, 0x0050, 17, 1), + PIN_FIELD_BASE(155, IO_BASE_BM2, 0x0050, 18, 1), + PIN_FIELD_BASE(156, IO_BASE_LT0, 0x0060, 12, 1), + PIN_FIELD_BASE(157, IO_BASE_LT0, 0x0060, 11, 1), + PIN_FIELD_BASE(158, IO_BASE_LT0, 0x0060, 10, 1), + PIN_FIELD_BASE(159, IO_BASE_LT1, 0x0020, 2, 1), + PIN_FIELD_BASE(160, IO_BASE_LT0, 0x0060, 14, 1), + PIN_FIELD_BASE(161, IO_BASE_LT0, 0x0060, 7, 1), + PIN_FIELD_BASE(162, IO_BASE_LT0, 0x0060, 6, 1), + PIN_FIELD_BASE(163, IO_BASE_LT1, 0x0020, 1, 1), + PIN_FIELD_BASE(164, IO_BASE_LT0, 0x0060, 9, 1), + PIN_FIELD_BASE(165, IO_BASE_LT0, 0x0060, 8, 1), + PIN_FIELD_BASE(166, IO_BASE_LT1, 0x0020, 0, 1), + PIN_FIELD_BASE(167, IO_BASE_LT0, 0x0060, 13, 1), + PIN_FIELD_BASE(168, IO_BASE_BM2, 0x0050, 8, 1), + PIN_FIELD_BASE(169, IO_BASE_BM2, 0x0050, 7, 1), + PIN_FIELD_BASE(170, IO_BASE_BM2, 0x0050, 9, 1), + PIN_FIELD_BASE(171, IO_BASE_BM2, 0x0050, 10, 1), + PIN_FIELD_BASE(172, IO_BASE_BM2, 0x0050, 11, 1), + PIN_FIELD_BASE(173, IO_BASE_BM2, 0x0050, 12, 1), + PIN_FIELD_BASE(174, IO_BASE_RT, 0x0040, 5, 1), + PIN_FIELD_BASE(175, IO_BASE_RT, 0x0040, 4, 1), + PIN_FIELD_BASE(176, IO_BASE_RT, 0x0040, 6, 1), + PIN_FIELD_BASE(177, IO_BASE_RT, 0x0040, 7, 1), + PIN_FIELD_BASE(178, IO_BASE_RT, 0x0040, 8, 1), + PIN_FIELD_BASE(179, IO_BASE_RT, 0x0040, 9, 1), + PIN_FIELD_BASE(180, IO_BASE_LT0, 0x0060, 24, 1), + PIN_FIELD_BASE(181, IO_BASE_LT0, 0x0060, 25, 1), + PIN_FIELD_BASE(182, IO_BASE_RT, 0x0040, 3, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_pupd_range[] = { + PIN_FIELD_BASE(44, IO_BASE_RB0, 0x0090, 0, 1), + PIN_FIELD_BASE(45, IO_BASE_RB0, 0x0090, 1, 1), + PIN_FIELD_BASE(46, IO_BASE_RB0, 0x0090, 2, 1), + PIN_FIELD_BASE(47, IO_BASE_RB0, 0x0090, 3, 1), + PIN_FIELD_BASE(156, IO_BASE_LT0, 0x00a0, 6, 1), + PIN_FIELD_BASE(157, IO_BASE_LT0, 0x00a0, 5, 1), + PIN_FIELD_BASE(158, IO_BASE_LT0, 0x00a0, 4, 1), + PIN_FIELD_BASE(159, IO_BASE_LT1, 0x0050, 2, 1), + PIN_FIELD_BASE(160, IO_BASE_LT0, 0x00a0, 8, 1), + PIN_FIELD_BASE(161, IO_BASE_LT0, 0x00a0, 1, 1), + PIN_FIELD_BASE(162, IO_BASE_LT0, 0x00a0, 0, 1), + PIN_FIELD_BASE(163, IO_BASE_LT1, 0x0050, 1, 1), + PIN_FIELD_BASE(164, IO_BASE_LT0, 0x00a0, 3, 1), + PIN_FIELD_BASE(165, IO_BASE_LT0, 0x00a0, 2, 1), + PIN_FIELD_BASE(166, IO_BASE_LT1, 0x0050, 0, 1), + PIN_FIELD_BASE(167, IO_BASE_LT0, 0x00a0, 7, 1), + PIN_FIELD_BASE(168, IO_BASE_BM2, 0x0090, 1, 1), + PIN_FIELD_BASE(169, IO_BASE_BM2, 0x0090, 0, 1), + PIN_FIELD_BASE(170, IO_BASE_BM2, 0x0090, 2, 1), + PIN_FIELD_BASE(171, IO_BASE_BM2, 0x0090, 3, 1), + PIN_FIELD_BASE(172, IO_BASE_BM2, 0x0090, 4, 1), + PIN_FIELD_BASE(173, IO_BASE_BM2, 0x0090, 5, 1), + PIN_FIELD_BASE(174, IO_BASE_RT, 0x0080, 1, 1), + PIN_FIELD_BASE(175, IO_BASE_RT, 0x0080, 0, 1), + PIN_FIELD_BASE(176, IO_BASE_RT, 0x0080, 2, 1), + PIN_FIELD_BASE(177, IO_BASE_RT, 0x0080, 3, 1), + PIN_FIELD_BASE(178, IO_BASE_RT, 0x0080, 4, 1), + PIN_FIELD_BASE(179, IO_BASE_RT, 0x0080, 5, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_r0_range[] = { + PIN_FIELD_BASE(44, IO_BASE_RB0, 0x00b0, 0, 1), + PIN_FIELD_BASE(45, IO_BASE_RB0, 0x00b0, 1, 1), + PIN_FIELD_BASE(46, IO_BASE_RB0, 0x00b0, 2, 1), + PIN_FIELD_BASE(47, IO_BASE_RB0, 0x00b0, 3, 1), + PIN_FIELD_BASE(156, IO_BASE_LT0, 0x00c0, 6, 1), + PIN_FIELD_BASE(157, IO_BASE_LT0, 0x00c0, 5, 1), + PIN_FIELD_BASE(158, IO_BASE_LT0, 0x00c0, 4, 1), + PIN_FIELD_BASE(159, IO_BASE_LT1, 0x0060, 2, 1), + PIN_FIELD_BASE(160, IO_BASE_LT0, 0x00c0, 8, 1), + PIN_FIELD_BASE(161, IO_BASE_LT0, 0x00c0, 1, 1), + PIN_FIELD_BASE(162, IO_BASE_LT0, 0x00c0, 0, 1), + PIN_FIELD_BASE(163, IO_BASE_LT1, 0x0060, 1, 1), + PIN_FIELD_BASE(164, IO_BASE_LT0, 0x00c0, 3, 1), + PIN_FIELD_BASE(165, IO_BASE_LT0, 0x00c0, 2, 1), + PIN_FIELD_BASE(166, IO_BASE_LT1, 0x0060, 0, 1), + PIN_FIELD_BASE(167, IO_BASE_LT0, 0x00c0, 7, 1), + PIN_FIELD_BASE(168, IO_BASE_BM2, 0x00b0, 1, 1), + PIN_FIELD_BASE(169, IO_BASE_BM2, 0x00b0, 0, 1), + PIN_FIELD_BASE(170, IO_BASE_BM2, 0x00b0, 2, 1), + PIN_FIELD_BASE(171, IO_BASE_BM2, 0x00b0, 3, 1), + PIN_FIELD_BASE(172, IO_BASE_BM2, 0x00b0, 4, 1), + PIN_FIELD_BASE(173, IO_BASE_BM2, 0x00b0, 5, 1), + PIN_FIELD_BASE(174, IO_BASE_RT, 0x00a0, 1, 1), + PIN_FIELD_BASE(175, IO_BASE_RT, 0x00a0, 0, 1), + PIN_FIELD_BASE(176, IO_BASE_RT, 0x00a0, 2, 1), + PIN_FIELD_BASE(177, IO_BASE_RT, 0x00a0, 3, 1), + PIN_FIELD_BASE(178, IO_BASE_RT, 0x00a0, 4, 1), + PIN_FIELD_BASE(179, IO_BASE_RT, 0x00a0, 5, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_r1_range[] = { + PIN_FIELD_BASE(44, IO_BASE_RB0, 0x00c0, 0, 1), + PIN_FIELD_BASE(45, IO_BASE_RB0, 0x00c0, 1, 1), + PIN_FIELD_BASE(46, IO_BASE_RB0, 0x00c0, 2, 1), + PIN_FIELD_BASE(47, IO_BASE_RB0, 0x00c0, 3, 1), + PIN_FIELD_BASE(156, IO_BASE_LT0, 0x00d0, 6, 1), + PIN_FIELD_BASE(157, IO_BASE_LT0, 0x00d0, 5, 1), + PIN_FIELD_BASE(158, IO_BASE_LT0, 0x00d0, 4, 1), + PIN_FIELD_BASE(159, IO_BASE_LT1, 0x0070, 2, 1), + PIN_FIELD_BASE(160, IO_BASE_LT0, 0x00d0, 8, 1), + PIN_FIELD_BASE(161, IO_BASE_LT0, 0x00d0, 1, 1), + PIN_FIELD_BASE(162, IO_BASE_LT0, 0x00d0, 0, 1), + PIN_FIELD_BASE(163, IO_BASE_LT1, 0x0070, 1, 1), + PIN_FIELD_BASE(164, IO_BASE_LT0, 0x00d0, 3, 1), + PIN_FIELD_BASE(165, IO_BASE_LT0, 0x00d0, 2, 1), + PIN_FIELD_BASE(166, IO_BASE_LT1, 0x0070, 0, 1), + PIN_FIELD_BASE(167, IO_BASE_LT0, 0x00d0, 7, 1), + PIN_FIELD_BASE(168, IO_BASE_BM2, 0x00c0, 1, 1), + PIN_FIELD_BASE(169, IO_BASE_BM2, 0x00c0, 0, 1), + PIN_FIELD_BASE(170, IO_BASE_BM2, 0x00c0, 2, 1), + PIN_FIELD_BASE(171, IO_BASE_BM2, 0x00c0, 3, 1), + PIN_FIELD_BASE(172, IO_BASE_BM2, 0x00c0, 4, 1), + PIN_FIELD_BASE(173, IO_BASE_BM2, 0x00c0, 5, 1), + PIN_FIELD_BASE(174, IO_BASE_RT, 0x00b0, 1, 1), + PIN_FIELD_BASE(175, IO_BASE_RT, 0x00b0, 0, 1), + PIN_FIELD_BASE(176, IO_BASE_RT, 0x00b0, 2, 1), + PIN_FIELD_BASE(177, IO_BASE_RT, 0x00b0, 3, 1), + PIN_FIELD_BASE(178, IO_BASE_RT, 0x00b0, 4, 1), + PIN_FIELD_BASE(179, IO_BASE_RT, 0x00b0, 5, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_pu_range[] = { + PIN_FIELD_BASE(0, IO_BASE_RB0, 0x00a0, 5, 1), + PIN_FIELD_BASE(1, IO_BASE_RB1, 0x0090, 3, 1), + PIN_FIELD_BASE(2, IO_BASE_RB1, 0x0090, 4, 1), + PIN_FIELD_BASE(3, IO_BASE_RB1, 0x0090, 5, 1), + PIN_FIELD_BASE(4, IO_BASE_RB1, 0x0090, 6, 1), + PIN_FIELD_BASE(5, IO_BASE_RB1, 0x0090, 7, 1), + PIN_FIELD_BASE(6, IO_BASE_RB0, 0x00a0, 6, 1), + PIN_FIELD_BASE(7, IO_BASE_RB0, 0x00a0, 7, 1), + PIN_FIELD_BASE(8, IO_BASE_RB0, 0x00a0, 8, 1), + PIN_FIELD_BASE(9, IO_BASE_RB0, 0x00a0, 9, 1), + PIN_FIELD_BASE(10, IO_BASE_RB0, 0x00a0, 10, 1), + PIN_FIELD_BASE(11, IO_BASE_RB0, 0x00a0, 11, 1), + PIN_FIELD_BASE(12, IO_BASE_BM1, 0x00b0, 5, 1), + PIN_FIELD_BASE(13, IO_BASE_BM1, 0x00b0, 6, 1), + PIN_FIELD_BASE(14, IO_BASE_BM2, 0x00a0, 0, 1), + PIN_FIELD_BASE(15, IO_BASE_BM2, 0x00a0, 1, 1), + PIN_FIELD_BASE(16, IO_BASE_BM1, 0x00b0, 7, 1), + PIN_FIELD_BASE(17, IO_BASE_BM1, 0x00b0, 8, 1), + PIN_FIELD_BASE(18, IO_BASE_RB0, 0x00a0, 0, 1), + PIN_FIELD_BASE(19, IO_BASE_RB0, 0x00a0, 2, 1), + PIN_FIELD_BASE(20, IO_BASE_RB0, 0x00a0, 1, 1), + PIN_FIELD_BASE(21, IO_BASE_RB0, 0x00a0, 3, 1), + PIN_FIELD_BASE(22, IO_BASE_RT, 0x0090, 0, 1), + PIN_FIELD_BASE(23, IO_BASE_RT, 0x0090, 1, 1), + PIN_FIELD_BASE(24, IO_BASE_RT, 0x0090, 2, 1), + PIN_FIELD_BASE(25, IO_BASE_LM, 0x0090, 2, 1), + PIN_FIELD_BASE(26, IO_BASE_LM, 0x0090, 1, 1), + PIN_FIELD_BASE(27, IO_BASE_BM1, 0x00b0, 1, 1), + PIN_FIELD_BASE(28, IO_BASE_BM1, 0x00b0, 2, 1), + PIN_FIELD_BASE(29, IO_BASE_LM, 0x0090, 0, 1), + PIN_FIELD_BASE(30, IO_BASE_BM1, 0x00b0, 0, 1), + PIN_FIELD_BASE(31, IO_BASE_BM2, 0x00a0, 13, 1), + PIN_FIELD_BASE(32, IO_BASE_BM0, 0x0090, 30, 1), + PIN_FIELD_BASE(33, IO_BASE_BM2, 0x00a0, 15, 1), + PIN_FIELD_BASE(34, IO_BASE_BM2, 0x00a0, 14, 1), + PIN_FIELD_BASE(35, IO_BASE_BM2, 0x00a0, 17, 1), + PIN_FIELD_BASE(36, IO_BASE_BM2, 0x00a0, 16, 1), + PIN_FIELD_BASE(37, IO_BASE_BM2, 0x00a0, 19, 1), + PIN_FIELD_BASE(38, IO_BASE_BM2, 0x00a0, 18, 1), + PIN_FIELD_BASE(39, IO_BASE_BM2, 0x00a0, 5, 1), + PIN_FIELD_BASE(40, IO_BASE_BM2, 0x00a0, 2, 1), + PIN_FIELD_BASE(41, IO_BASE_BM2, 0x00a0, 3, 1), + PIN_FIELD_BASE(42, IO_BASE_BM2, 0x00a0, 4, 1), + PIN_FIELD_BASE(43, IO_BASE_BM2, 0x00a0, 6, 1), + PIN_FIELD_BASE(48, IO_BASE_LM, 0x0090, 5, 1), + PIN_FIELD_BASE(49, IO_BASE_LM, 0x0090, 4, 1), + PIN_FIELD_BASE(50, IO_BASE_LM, 0x0090, 3, 1), + PIN_FIELD_BASE(51, IO_BASE_RB1, 0x0090, 8, 1), + PIN_FIELD_BASE(52, IO_BASE_RB1, 0x0090, 10, 1), + PIN_FIELD_BASE(53, IO_BASE_RB1, 0x0090, 9, 1), + PIN_FIELD_BASE(54, IO_BASE_RB1, 0x0090, 11, 1), + PIN_FIELD_BASE(55, IO_BASE_LM, 0x0090, 6, 1), + PIN_FIELD_BASE(56, IO_BASE_LM, 0x0090, 7, 1), + PIN_FIELD_BASE(57, IO_BASE_BM1, 0x00b0, 13, 1), + PIN_FIELD_BASE(58, IO_BASE_BM1, 0x00b0, 17, 1), + PIN_FIELD_BASE(59, IO_BASE_BM1, 0x00b0, 14, 1), + PIN_FIELD_BASE(60, IO_BASE_BM1, 0x00b0, 18, 1), + PIN_FIELD_BASE(61, IO_BASE_BM1, 0x00b0, 15, 1), + PIN_FIELD_BASE(62, IO_BASE_BM1, 0x00b0, 19, 1), + PIN_FIELD_BASE(63, IO_BASE_BM1, 0x00b0, 16, 1), + PIN_FIELD_BASE(64, IO_BASE_BM1, 0x00b0, 20, 1), + PIN_FIELD_BASE(65, IO_BASE_RT, 0x0090, 4, 1), + PIN_FIELD_BASE(66, IO_BASE_RT, 0x0090, 6, 1), + PIN_FIELD_BASE(67, IO_BASE_RT, 0x0090, 5, 1), + PIN_FIELD_BASE(68, IO_BASE_RT, 0x0090, 7, 1), + PIN_FIELD_BASE(69, IO_BASE_BM1, 0x00b0, 22, 1), + PIN_FIELD_BASE(70, IO_BASE_BM1, 0x00b0, 21, 1), + PIN_FIELD_BASE(71, IO_BASE_BM1, 0x00b0, 24, 1), + PIN_FIELD_BASE(72, IO_BASE_BM1, 0x00b0, 23, 1), + PIN_FIELD_BASE(73, IO_BASE_BM1, 0x00b0, 26, 1), + PIN_FIELD_BASE(74, IO_BASE_BM1, 0x00b0, 25, 1), + PIN_FIELD_BASE(75, IO_BASE_BM2, 0x00a0, 7, 1), + PIN_FIELD_BASE(76, IO_BASE_BM1, 0x00b0, 27, 1), + PIN_FIELD_BASE(77, IO_BASE_RB1, 0x0090, 13, 1), + PIN_FIELD_BASE(78, IO_BASE_RB1, 0x0090, 12, 1), + PIN_FIELD_BASE(79, IO_BASE_RB1, 0x0090, 15, 1), + PIN_FIELD_BASE(80, IO_BASE_RB1, 0x0090, 14, 1), + PIN_FIELD_BASE(81, IO_BASE_BM1, 0x00b0, 29, 1), + PIN_FIELD_BASE(82, IO_BASE_BM1, 0x00b0, 28, 1), + PIN_FIELD_BASE(83, IO_BASE_BM1, 0x00b0, 30, 1), + PIN_FIELD_BASE(84, IO_BASE_RB0, 0x00a0, 22, 1), + PIN_FIELD_BASE(85, IO_BASE_RB0, 0x00a0, 23, 1), + PIN_FIELD_BASE(86, IO_BASE_RB0, 0x00a0, 24, 1), + PIN_FIELD_BASE(87, IO_BASE_RB0, 0x00a0, 25, 1), + PIN_FIELD_BASE(88, IO_BASE_LT0, 0x00b0, 11, 1), + PIN_FIELD_BASE(89, IO_BASE_LT0, 0x00b0, 10, 1), + PIN_FIELD_BASE(90, IO_BASE_LT0, 0x00b0, 13, 1), + PIN_FIELD_BASE(91, IO_BASE_LT0, 0x00b0, 12, 1), + PIN_FIELD_BASE(92, IO_BASE_LT0, 0x00b0, 7, 1), + PIN_FIELD_BASE(93, IO_BASE_LT0, 0x00b0, 8, 1), + PIN_FIELD_BASE(94, IO_BASE_LT0, 0x00b0, 14, 1), + PIN_FIELD_BASE(95, IO_BASE_LT0, 0x00b0, 6, 1), + PIN_FIELD_BASE(96, IO_BASE_LT0, 0x00b0, 9, 1), + PIN_FIELD_BASE(97, IO_BASE_LT0, 0x00b0, 0, 1), + PIN_FIELD_BASE(98, IO_BASE_LT0, 0x00b0, 5, 1), + PIN_FIELD_BASE(99, IO_BASE_LT0, 0x00b0, 3, 1), + PIN_FIELD_BASE(100, IO_BASE_LT0, 0x00b0, 4, 1), + PIN_FIELD_BASE(101, IO_BASE_LT0, 0x00b0, 1, 1), + PIN_FIELD_BASE(102, IO_BASE_LT0, 0x00b0, 2, 1), + PIN_FIELD_BASE(103, IO_BASE_RB0, 0x00a0, 15, 1), + PIN_FIELD_BASE(104, IO_BASE_RB0, 0x00a0, 12, 1), + PIN_FIELD_BASE(105, IO_BASE_RB0, 0x00a0, 14, 1), + PIN_FIELD_BASE(106, IO_BASE_RB0, 0x00a0, 13, 1), + PIN_FIELD_BASE(107, IO_BASE_RB0, 0x00a0, 19, 1), + PIN_FIELD_BASE(108, IO_BASE_RB0, 0x00a0, 16, 1), + PIN_FIELD_BASE(109, IO_BASE_RB0, 0x00a0, 18, 1), + PIN_FIELD_BASE(110, IO_BASE_RB0, 0x00a0, 17, 1), + PIN_FIELD_BASE(111, IO_BASE_RB0, 0x00a0, 4, 1), + PIN_FIELD_BASE(112, IO_BASE_RB1, 0x0090, 0, 1), + PIN_FIELD_BASE(113, IO_BASE_RB1, 0x0090, 1, 1), + PIN_FIELD_BASE(114, IO_BASE_RB1, 0x0090, 2, 1), + PIN_FIELD_BASE(115, IO_BASE_BM1, 0x00b0, 9, 1), + PIN_FIELD_BASE(116, IO_BASE_BM1, 0x00b0, 12, 1), + PIN_FIELD_BASE(117, IO_BASE_BM1, 0x00b0, 10, 1), + PIN_FIELD_BASE(118, IO_BASE_BM1, 0x00b0, 11, 1), + PIN_FIELD_BASE(119, IO_BASE_BM0, 0x0090, 26, 1), + PIN_FIELD_BASE(120, IO_BASE_BM0, 0x0090, 25, 1), + PIN_FIELD_BASE(121, IO_BASE_BM0, 0x0090, 24, 1), + PIN_FIELD_BASE(122, IO_BASE_BM0, 0x0090, 23, 1), + PIN_FIELD_BASE(123, IO_BASE_BM0, 0x0090, 19, 1), + PIN_FIELD_BASE(124, IO_BASE_BM0, 0x0090, 18, 1), + PIN_FIELD_BASE(125, IO_BASE_BM0, 0x0090, 17, 1), + PIN_FIELD_BASE(126, IO_BASE_BM0, 0x0090, 16, 1), + PIN_FIELD_BASE(127, IO_BASE_BM0, 0x0090, 22, 1), + PIN_FIELD_BASE(128, IO_BASE_BM0, 0x0090, 15, 1), + PIN_FIELD_BASE(129, IO_BASE_BM0, 0x0090, 20, 1), + PIN_FIELD_BASE(130, IO_BASE_BM0, 0x0090, 27, 1), + PIN_FIELD_BASE(131, IO_BASE_BM0, 0x0090, 13, 1), + PIN_FIELD_BASE(132, IO_BASE_BM0, 0x0090, 14, 1), + PIN_FIELD_BASE(133, IO_BASE_BM0, 0x0090, 28, 1), + PIN_FIELD_BASE(134, IO_BASE_BM0, 0x0090, 21, 1), + PIN_FIELD_BASE(135, IO_BASE_BM0, 0x0090, 11, 1), + PIN_FIELD_BASE(136, IO_BASE_BM0, 0x0090, 12, 1), + PIN_FIELD_BASE(137, IO_BASE_BM1, 0x00b0, 3, 1), + PIN_FIELD_BASE(138, IO_BASE_BM1, 0x00b0, 4, 1), + PIN_FIELD_BASE(139, IO_BASE_BM0, 0x0090, 3, 1), + PIN_FIELD_BASE(140, IO_BASE_BM0, 0x0090, 4, 1), + PIN_FIELD_BASE(141, IO_BASE_BM0, 0x0090, 0, 1), + PIN_FIELD_BASE(142, IO_BASE_BM0, 0x0090, 1, 1), + PIN_FIELD_BASE(143, IO_BASE_BM0, 0x0090, 2, 1), + PIN_FIELD_BASE(144, IO_BASE_BM0, 0x0090, 5, 1), + PIN_FIELD_BASE(145, IO_BASE_BM0, 0x0090, 6, 1), + PIN_FIELD_BASE(146, IO_BASE_BM0, 0x0090, 7, 1), + PIN_FIELD_BASE(147, IO_BASE_BM0, 0x0090, 8, 1), + PIN_FIELD_BASE(148, IO_BASE_BM0, 0x0090, 9, 1), + PIN_FIELD_BASE(149, IO_BASE_BM0, 0x0090, 10, 1), + PIN_FIELD_BASE(150, IO_BASE_BM2, 0x00a0, 8, 1), + PIN_FIELD_BASE(151, IO_BASE_BM0, 0x0090, 29, 1), + PIN_FIELD_BASE(152, IO_BASE_BM2, 0x00a0, 9, 1), + PIN_FIELD_BASE(153, IO_BASE_BM2, 0x00a0, 10, 1), + PIN_FIELD_BASE(154, IO_BASE_BM2, 0x00a0, 11, 1), + PIN_FIELD_BASE(155, IO_BASE_BM2, 0x00a0, 12, 1), + PIN_FIELD_BASE(180, IO_BASE_LT0, 0x00b0, 15, 1), + PIN_FIELD_BASE(181, IO_BASE_LT0, 0x00b0, 16, 1), + PIN_FIELD_BASE(182, IO_BASE_RT, 0x0090, 3, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_pd_range[] = { + PIN_FIELD_BASE(0, IO_BASE_RB0, 0x0080, 5, 1), + PIN_FIELD_BASE(1, IO_BASE_RB1, 0x0080, 3, 1), + PIN_FIELD_BASE(2, IO_BASE_RB1, 0x0080, 4, 1), + PIN_FIELD_BASE(3, IO_BASE_RB1, 0x0080, 5, 1), + PIN_FIELD_BASE(4, IO_BASE_RB1, 0x0080, 6, 1), + PIN_FIELD_BASE(5, IO_BASE_RB1, 0x0080, 7, 1), + PIN_FIELD_BASE(6, IO_BASE_RB0, 0x0080, 6, 1), + PIN_FIELD_BASE(7, IO_BASE_RB0, 0x0080, 7, 1), + PIN_FIELD_BASE(8, IO_BASE_RB0, 0x0080, 8, 1), + PIN_FIELD_BASE(9, IO_BASE_RB0, 0x0080, 9, 1), + PIN_FIELD_BASE(10, IO_BASE_RB0, 0x0080, 10, 1), + PIN_FIELD_BASE(11, IO_BASE_RB0, 0x0080, 11, 1), + PIN_FIELD_BASE(12, IO_BASE_BM1, 0x00a0, 5, 1), + PIN_FIELD_BASE(13, IO_BASE_BM1, 0x00a0, 6, 1), + PIN_FIELD_BASE(14, IO_BASE_BM2, 0x0080, 0, 1), + PIN_FIELD_BASE(15, IO_BASE_BM2, 0x0080, 1, 1), + PIN_FIELD_BASE(16, IO_BASE_BM1, 0x00a0, 7, 1), + PIN_FIELD_BASE(17, IO_BASE_BM1, 0x00a0, 8, 1), + PIN_FIELD_BASE(18, IO_BASE_RB0, 0x0080, 0, 1), + PIN_FIELD_BASE(19, IO_BASE_RB0, 0x0080, 2, 1), + PIN_FIELD_BASE(20, IO_BASE_RB0, 0x0080, 1, 1), + PIN_FIELD_BASE(21, IO_BASE_RB0, 0x0080, 3, 1), + PIN_FIELD_BASE(22, IO_BASE_RT, 0x0070, 0, 1), + PIN_FIELD_BASE(23, IO_BASE_RT, 0x0070, 1, 1), + PIN_FIELD_BASE(24, IO_BASE_RT, 0x0070, 2, 1), + PIN_FIELD_BASE(25, IO_BASE_LM, 0x0080, 2, 1), + PIN_FIELD_BASE(26, IO_BASE_LM, 0x0080, 1, 1), + PIN_FIELD_BASE(27, IO_BASE_BM1, 0x00a0, 1, 1), + PIN_FIELD_BASE(28, IO_BASE_BM1, 0x00a0, 2, 1), + PIN_FIELD_BASE(29, IO_BASE_LM, 0x0080, 0, 1), + PIN_FIELD_BASE(30, IO_BASE_BM1, 0x00a0, 0, 1), + PIN_FIELD_BASE(31, IO_BASE_BM2, 0x0080, 13, 1), + PIN_FIELD_BASE(32, IO_BASE_BM0, 0x0080, 30, 1), + PIN_FIELD_BASE(33, IO_BASE_BM2, 0x0080, 15, 1), + PIN_FIELD_BASE(34, IO_BASE_BM2, 0x0080, 14, 1), + PIN_FIELD_BASE(35, IO_BASE_BM2, 0x0080, 17, 1), + PIN_FIELD_BASE(36, IO_BASE_BM2, 0x0080, 16, 1), + PIN_FIELD_BASE(37, IO_BASE_BM2, 0x0080, 19, 1), + PIN_FIELD_BASE(38, IO_BASE_BM2, 0x0080, 18, 1), + PIN_FIELD_BASE(39, IO_BASE_BM2, 0x0080, 5, 1), + PIN_FIELD_BASE(40, IO_BASE_BM2, 0x0080, 2, 1), + PIN_FIELD_BASE(41, IO_BASE_BM2, 0x0080, 3, 1), + PIN_FIELD_BASE(42, IO_BASE_BM2, 0x0080, 4, 1), + PIN_FIELD_BASE(43, IO_BASE_BM2, 0x0080, 6, 1), + PIN_FIELD_BASE(48, IO_BASE_LM, 0x0080, 5, 1), + PIN_FIELD_BASE(49, IO_BASE_LM, 0x0080, 4, 1), + PIN_FIELD_BASE(50, IO_BASE_LM, 0x0080, 3, 1), + PIN_FIELD_BASE(51, IO_BASE_RB1, 0x0080, 8, 1), + PIN_FIELD_BASE(52, IO_BASE_RB1, 0x0080, 10, 1), + PIN_FIELD_BASE(53, IO_BASE_RB1, 0x0080, 9, 1), + PIN_FIELD_BASE(54, IO_BASE_RB1, 0x0080, 11, 1), + PIN_FIELD_BASE(55, IO_BASE_LM, 0x0080, 6, 1), + PIN_FIELD_BASE(56, IO_BASE_LM, 0x0080, 7, 1), + PIN_FIELD_BASE(57, IO_BASE_BM1, 0x00a0, 13, 1), + PIN_FIELD_BASE(58, IO_BASE_BM1, 0x00a0, 17, 1), + PIN_FIELD_BASE(59, IO_BASE_BM1, 0x00a0, 14, 1), + PIN_FIELD_BASE(60, IO_BASE_BM1, 0x00a0, 18, 1), + PIN_FIELD_BASE(61, IO_BASE_BM1, 0x00a0, 15, 1), + PIN_FIELD_BASE(62, IO_BASE_BM1, 0x00a0, 19, 1), + PIN_FIELD_BASE(63, IO_BASE_BM1, 0x00a0, 16, 1), + PIN_FIELD_BASE(64, IO_BASE_BM1, 0x00a0, 20, 1), + PIN_FIELD_BASE(65, IO_BASE_RT, 0x0070, 4, 1), + PIN_FIELD_BASE(66, IO_BASE_RT, 0x0070, 6, 1), + PIN_FIELD_BASE(67, IO_BASE_RT, 0x0070, 5, 1), + PIN_FIELD_BASE(68, IO_BASE_RT, 0x0070, 7, 1), + PIN_FIELD_BASE(69, IO_BASE_BM1, 0x00a0, 22, 1), + PIN_FIELD_BASE(70, IO_BASE_BM1, 0x00a0, 21, 1), + PIN_FIELD_BASE(71, IO_BASE_BM1, 0x00a0, 24, 1), + PIN_FIELD_BASE(72, IO_BASE_BM1, 0x00a0, 23, 1), + PIN_FIELD_BASE(73, IO_BASE_BM1, 0x00a0, 26, 1), + PIN_FIELD_BASE(74, IO_BASE_BM1, 0x00a0, 25, 1), + PIN_FIELD_BASE(75, IO_BASE_BM2, 0x0080, 7, 1), + PIN_FIELD_BASE(76, IO_BASE_BM1, 0x00a0, 27, 1), + PIN_FIELD_BASE(77, IO_BASE_RB1, 0x0080, 13, 1), + PIN_FIELD_BASE(78, IO_BASE_RB1, 0x0080, 12, 1), + PIN_FIELD_BASE(79, IO_BASE_RB1, 0x0080, 15, 1), + PIN_FIELD_BASE(80, IO_BASE_RB1, 0x0080, 14, 1), + PIN_FIELD_BASE(81, IO_BASE_BM1, 0x00a0, 29, 1), + PIN_FIELD_BASE(82, IO_BASE_BM1, 0x00a0, 28, 1), + PIN_FIELD_BASE(83, IO_BASE_BM1, 0x00a0, 30, 1), + PIN_FIELD_BASE(84, IO_BASE_RB0, 0x0080, 22, 1), + PIN_FIELD_BASE(85, IO_BASE_RB0, 0x0080, 23, 1), + PIN_FIELD_BASE(86, IO_BASE_RB0, 0x0080, 24, 1), + PIN_FIELD_BASE(87, IO_BASE_RB0, 0x0080, 25, 1), + PIN_FIELD_BASE(88, IO_BASE_LT0, 0x0090, 11, 1), + PIN_FIELD_BASE(89, IO_BASE_LT0, 0x0090, 10, 1), + PIN_FIELD_BASE(90, IO_BASE_LT0, 0x0090, 13, 1), + PIN_FIELD_BASE(91, IO_BASE_LT0, 0x0090, 12, 1), + PIN_FIELD_BASE(92, IO_BASE_LT0, 0x0090, 7, 1), + PIN_FIELD_BASE(93, IO_BASE_LT0, 0x0090, 8, 1), + PIN_FIELD_BASE(94, IO_BASE_LT0, 0x0090, 14, 1), + PIN_FIELD_BASE(95, IO_BASE_LT0, 0x0090, 6, 1), + PIN_FIELD_BASE(96, IO_BASE_LT0, 0x0090, 9, 1), + PIN_FIELD_BASE(97, IO_BASE_LT0, 0x0090, 0, 1), + PIN_FIELD_BASE(98, IO_BASE_LT0, 0x0090, 5, 1), + PIN_FIELD_BASE(99, IO_BASE_LT0, 0x0090, 3, 1), + PIN_FIELD_BASE(100, IO_BASE_LT0, 0x0090, 4, 1), + PIN_FIELD_BASE(101, IO_BASE_LT0, 0x0090, 1, 1), + PIN_FIELD_BASE(102, IO_BASE_LT0, 0x0090, 2, 1), + PIN_FIELD_BASE(103, IO_BASE_RB0, 0x0080, 15, 1), + PIN_FIELD_BASE(104, IO_BASE_RB0, 0x0080, 12, 1), + PIN_FIELD_BASE(105, IO_BASE_RB0, 0x0080, 14, 1), + PIN_FIELD_BASE(106, IO_BASE_RB0, 0x0080, 13, 1), + PIN_FIELD_BASE(107, IO_BASE_RB0, 0x0080, 19, 1), + PIN_FIELD_BASE(108, IO_BASE_RB0, 0x0080, 16, 1), + PIN_FIELD_BASE(109, IO_BASE_RB0, 0x0080, 18, 1), + PIN_FIELD_BASE(110, IO_BASE_RB0, 0x0080, 17, 1), + PIN_FIELD_BASE(111, IO_BASE_RB0, 0x0080, 4, 1), + PIN_FIELD_BASE(112, IO_BASE_RB1, 0x0080, 0, 1), + PIN_FIELD_BASE(113, IO_BASE_RB1, 0x0080, 1, 1), + PIN_FIELD_BASE(114, IO_BASE_RB1, 0x0080, 2, 1), + PIN_FIELD_BASE(115, IO_BASE_BM1, 0x00a0, 9, 1), + PIN_FIELD_BASE(116, IO_BASE_BM1, 0x00a0, 12, 1), + PIN_FIELD_BASE(117, IO_BASE_BM1, 0x00a0, 10, 1), + PIN_FIELD_BASE(118, IO_BASE_BM1, 0x00a0, 11, 1), + PIN_FIELD_BASE(119, IO_BASE_BM0, 0x0080, 26, 1), + PIN_FIELD_BASE(120, IO_BASE_BM0, 0x0080, 25, 1), + PIN_FIELD_BASE(121, IO_BASE_BM0, 0x0080, 24, 1), + PIN_FIELD_BASE(122, IO_BASE_BM0, 0x0080, 23, 1), + PIN_FIELD_BASE(123, IO_BASE_BM0, 0x0080, 19, 1), + PIN_FIELD_BASE(124, IO_BASE_BM0, 0x0080, 18, 1), + PIN_FIELD_BASE(125, IO_BASE_BM0, 0x0080, 17, 1), + PIN_FIELD_BASE(126, IO_BASE_BM0, 0x0080, 16, 1), + PIN_FIELD_BASE(127, IO_BASE_BM0, 0x0080, 22, 1), + PIN_FIELD_BASE(128, IO_BASE_BM0, 0x0080, 15, 1), + PIN_FIELD_BASE(129, IO_BASE_BM0, 0x0080, 20, 1), + PIN_FIELD_BASE(130, IO_BASE_BM0, 0x0080, 27, 1), + PIN_FIELD_BASE(131, IO_BASE_BM0, 0x0080, 13, 1), + PIN_FIELD_BASE(132, IO_BASE_BM0, 0x0080, 14, 1), + PIN_FIELD_BASE(133, IO_BASE_BM0, 0x0080, 28, 1), + PIN_FIELD_BASE(134, IO_BASE_BM0, 0x0080, 21, 1), + PIN_FIELD_BASE(135, IO_BASE_BM0, 0x0080, 11, 1), + PIN_FIELD_BASE(136, IO_BASE_BM0, 0x0080, 12, 1), + PIN_FIELD_BASE(137, IO_BASE_BM1, 0x00a0, 3, 1), + PIN_FIELD_BASE(138, IO_BASE_BM1, 0x00a0, 4, 1), + PIN_FIELD_BASE(139, IO_BASE_BM0, 0x0080, 3, 1), + PIN_FIELD_BASE(140, IO_BASE_BM0, 0x0080, 4, 1), + PIN_FIELD_BASE(141, IO_BASE_BM0, 0x0080, 0, 1), + PIN_FIELD_BASE(142, IO_BASE_BM0, 0x0080, 1, 1), + PIN_FIELD_BASE(143, IO_BASE_BM0, 0x0080, 2, 1), + PIN_FIELD_BASE(144, IO_BASE_BM0, 0x0080, 5, 1), + PIN_FIELD_BASE(145, IO_BASE_BM0, 0x0080, 6, 1), + PIN_FIELD_BASE(146, IO_BASE_BM0, 0x0080, 7, 1), + PIN_FIELD_BASE(147, IO_BASE_BM0, 0x0080, 8, 1), + PIN_FIELD_BASE(148, IO_BASE_BM0, 0x0080, 9, 1), + PIN_FIELD_BASE(149, IO_BASE_BM0, 0x0080, 10, 1), + PIN_FIELD_BASE(150, IO_BASE_BM2, 0x0080, 8, 1), + PIN_FIELD_BASE(151, IO_BASE_BM0, 0x0080, 29, 1), + PIN_FIELD_BASE(152, IO_BASE_BM2, 0x0080, 9, 1), + PIN_FIELD_BASE(153, IO_BASE_BM2, 0x0080, 10, 1), + PIN_FIELD_BASE(154, IO_BASE_BM2, 0x0080, 11, 1), + PIN_FIELD_BASE(155, IO_BASE_BM2, 0x0080, 12, 1), + PIN_FIELD_BASE(180, IO_BASE_LT0, 0x0090, 15, 1), + PIN_FIELD_BASE(181, IO_BASE_LT0, 0x0090, 16, 1), + PIN_FIELD_BASE(182, IO_BASE_RT, 0x0070, 3, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_drv_range[] = { + PIN_FIELD_BASE(0, IO_BASE_RB0, 0x0000, 15, 3), + PIN_FIELD_BASE(1, IO_BASE_RB1, 0x0000, 9, 3), + PIN_FIELD_BASE(2, IO_BASE_RB1, 0x0000, 12, 3), + PIN_FIELD_BASE(3, IO_BASE_RB1, 0x0000, 15, 3), + PIN_FIELD_BASE(4, IO_BASE_RB1, 0x0000, 18, 3), + PIN_FIELD_BASE(5, IO_BASE_RB1, 0x0000, 21, 3), + PIN_FIELD_BASE(6, IO_BASE_RB0, 0x0000, 18, 3), + PIN_FIELD_BASE(7, IO_BASE_RB0, 0x0000, 21, 3), + PIN_FIELD_BASE(8, IO_BASE_RB0, 0x0000, 24, 3), + PIN_FIELD_BASE(9, IO_BASE_RB0, 0x0000, 27, 3), + PIN_FIELD_BASE(10, IO_BASE_RB0, 0x0010, 0, 3), + PIN_FIELD_BASE(11, IO_BASE_RB0, 0x0010, 3, 3), + PIN_FIELD_BASE(12, IO_BASE_BM1, 0x0000, 15, 3), + PIN_FIELD_BASE(13, IO_BASE_BM1, 0x0000, 18, 3), + PIN_FIELD_BASE(14, IO_BASE_BM2, 0x0000, 0, 3), + PIN_FIELD_BASE(15, IO_BASE_BM2, 0x0000, 3, 3), + PIN_FIELD_BASE(16, IO_BASE_BM1, 0x0000, 21, 3), + PIN_FIELD_BASE(17, IO_BASE_BM1, 0x0000, 24, 3), + PIN_FIELD_BASE(18, IO_BASE_RB0, 0x0000, 0, 3), + PIN_FIELD_BASE(19, IO_BASE_RB0, 0x0000, 6, 3), + PIN_FIELD_BASE(20, IO_BASE_RB0, 0x0000, 3, 3), + PIN_FIELD_BASE(21, IO_BASE_RB0, 0x0000, 9, 3), + PIN_FIELD_BASE(22, IO_BASE_RT, 0x0000, 0, 3), + PIN_FIELD_BASE(23, IO_BASE_RT, 0x0000, 3, 3), + PIN_FIELD_BASE(24, IO_BASE_RT, 0x0000, 6, 3), + PIN_FIELD_BASE(25, IO_BASE_LM, 0x0000, 6, 3), + PIN_FIELD_BASE(26, IO_BASE_LM, 0x0000, 3, 3), + PIN_FIELD_BASE(27, IO_BASE_BM1, 0x0000, 3, 3), + PIN_FIELD_BASE(28, IO_BASE_BM1, 0x0000, 6, 3), + PIN_FIELD_BASE(29, IO_BASE_LM, 0x0000, 0, 3), + PIN_FIELD_BASE(30, IO_BASE_BM1, 0x0000, 0, 3), + PIN_FIELD_BASE(31, IO_BASE_BM2, 0x0010, 27, 3), + PIN_FIELD_BASE(32, IO_BASE_BM0, 0x0030, 0, 3), + PIN_FIELD_BASE(33, IO_BASE_BM2, 0x0020, 3, 3), + PIN_FIELD_BASE(34, IO_BASE_BM2, 0x0020, 0, 3), + PIN_FIELD_BASE(35, IO_BASE_BM2, 0x0020, 9, 3), + PIN_FIELD_BASE(36, IO_BASE_BM2, 0x0020, 6, 3), + PIN_FIELD_BASE(37, IO_BASE_BM2, 0x0020, 15, 3), + PIN_FIELD_BASE(38, IO_BASE_BM2, 0x0020, 12, 3), + PIN_FIELD_BASE(39, IO_BASE_BM2, 0x0000, 15, 3), + PIN_FIELD_BASE(40, IO_BASE_BM2, 0x0000, 6, 3), + PIN_FIELD_BASE(41, IO_BASE_BM2, 0x0000, 9, 3), + PIN_FIELD_BASE(42, IO_BASE_BM2, 0x0000, 12, 3), + PIN_FIELD_BASE(43, IO_BASE_BM2, 0x0000, 18, 3), + PIN_FIELD_BASE(44, IO_BASE_RB0, 0x0020, 0, 3), + PIN_FIELD_BASE(45, IO_BASE_RB0, 0x0020, 3, 3), + PIN_FIELD_BASE(46, IO_BASE_RB0, 0x0020, 6, 3), + PIN_FIELD_BASE(47, IO_BASE_RB0, 0x0020, 9, 3), + PIN_FIELD_BASE(48, IO_BASE_LM, 0x0000, 15, 3), + PIN_FIELD_BASE(49, IO_BASE_LM, 0x0000, 12, 3), + PIN_FIELD_BASE(50, IO_BASE_LM, 0x0000, 9, 3), + PIN_FIELD_BASE(51, IO_BASE_RB1, 0x0000, 24, 3), + PIN_FIELD_BASE(52, IO_BASE_RB1, 0x0010, 0, 3), + PIN_FIELD_BASE(53, IO_BASE_RB1, 0x0000, 27, 3), + PIN_FIELD_BASE(54, IO_BASE_RB1, 0x0010, 3, 3), + PIN_FIELD_BASE(55, IO_BASE_LM, 0x0000, 18, 3), + PIN_FIELD_BASE(56, IO_BASE_LM, 0x0000, 21, 3), + PIN_FIELD_BASE(57, IO_BASE_BM1, 0x0010, 9, 3), + PIN_FIELD_BASE(58, IO_BASE_BM1, 0x0010, 21, 3), + PIN_FIELD_BASE(59, IO_BASE_BM1, 0x0010, 12, 3), + PIN_FIELD_BASE(60, IO_BASE_BM1, 0x0010, 24, 3), + PIN_FIELD_BASE(61, IO_BASE_BM1, 0x0010, 15, 3), + PIN_FIELD_BASE(62, IO_BASE_BM1, 0x0010, 27, 3), + PIN_FIELD_BASE(63, IO_BASE_BM1, 0x0010, 18, 3), + PIN_FIELD_BASE(64, IO_BASE_BM1, 0x0020, 0, 3), + PIN_FIELD_BASE(65, IO_BASE_RT, 0x0010, 0, 3), + PIN_FIELD_BASE(66, IO_BASE_RT, 0x0010, 6, 3), + PIN_FIELD_BASE(67, IO_BASE_RT, 0x0010, 3, 3), + PIN_FIELD_BASE(68, IO_BASE_RT, 0x0010, 9, 3), + PIN_FIELD_BASE(69, IO_BASE_BM1, 0x0020, 6, 3), + PIN_FIELD_BASE(70, IO_BASE_BM1, 0x0020, 3, 3), + PIN_FIELD_BASE(71, IO_BASE_BM1, 0x0020, 12, 3), + PIN_FIELD_BASE(72, IO_BASE_BM1, 0x0020, 9, 3), + PIN_FIELD_BASE(73, IO_BASE_BM1, 0x0020, 18, 3), + PIN_FIELD_BASE(74, IO_BASE_BM1, 0x0020, 15, 3), + PIN_FIELD_BASE(75, IO_BASE_BM2, 0x0010, 9, 3), + PIN_FIELD_BASE(76, IO_BASE_BM1, 0x0020, 21, 3), + PIN_FIELD_BASE(77, IO_BASE_RB1, 0x0010, 9, 3), + PIN_FIELD_BASE(78, IO_BASE_RB1, 0x0010, 6, 3), + PIN_FIELD_BASE(79, IO_BASE_RB1, 0x0010, 15, 3), + PIN_FIELD_BASE(80, IO_BASE_RB1, 0x0010, 12, 3), + PIN_FIELD_BASE(81, IO_BASE_BM1, 0x0020, 27, 3), + PIN_FIELD_BASE(82, IO_BASE_BM1, 0x0020, 24, 3), + PIN_FIELD_BASE(83, IO_BASE_BM1, 0x0030, 0, 3), + PIN_FIELD_BASE(84, IO_BASE_RB0, 0x0020, 12, 3), + PIN_FIELD_BASE(85, IO_BASE_RB0, 0x0020, 15, 3), + PIN_FIELD_BASE(86, IO_BASE_RB0, 0x0020, 18, 3), + PIN_FIELD_BASE(87, IO_BASE_RB0, 0x0020, 21, 3), + PIN_FIELD_BASE(88, IO_BASE_LT0, 0x0020, 0, 3), + PIN_FIELD_BASE(89, IO_BASE_LT0, 0x0010, 27, 3), + PIN_FIELD_BASE(90, IO_BASE_LT0, 0x0020, 6, 3), + PIN_FIELD_BASE(91, IO_BASE_LT0, 0x0020, 3, 3), + PIN_FIELD_BASE(92, IO_BASE_LT0, 0x0010, 18, 3), + PIN_FIELD_BASE(93, IO_BASE_LT0, 0x0010, 21, 3), + PIN_FIELD_BASE(94, IO_BASE_LT0, 0x0020, 9, 3), + PIN_FIELD_BASE(95, IO_BASE_LT0, 0x0010, 15, 3), + PIN_FIELD_BASE(96, IO_BASE_LT0, 0x0010, 24, 3), + PIN_FIELD_BASE(97, IO_BASE_LT0, 0x0000, 0, 3), + PIN_FIELD_BASE(98, IO_BASE_LT0, 0x0000, 15, 3), + PIN_FIELD_BASE(99, IO_BASE_LT0, 0x0000, 9, 3), + PIN_FIELD_BASE(100, IO_BASE_LT0, 0x0000, 12, 3), + PIN_FIELD_BASE(101, IO_BASE_LT0, 0x0000, 3, 3), + PIN_FIELD_BASE(102, IO_BASE_LT0, 0x0000, 6, 3), + PIN_FIELD_BASE(103, IO_BASE_RB0, 0x0010, 15, 3), + PIN_FIELD_BASE(104, IO_BASE_RB0, 0x0010, 6, 3), + PIN_FIELD_BASE(105, IO_BASE_RB0, 0x0010, 12, 3), + PIN_FIELD_BASE(106, IO_BASE_RB0, 0x0010, 9, 3), + PIN_FIELD_BASE(107, IO_BASE_RB0, 0x0010, 27, 3), + PIN_FIELD_BASE(108, IO_BASE_RB0, 0x0010, 18, 3), + PIN_FIELD_BASE(109, IO_BASE_RB0, 0x0010, 24, 3), + PIN_FIELD_BASE(110, IO_BASE_RB0, 0x0010, 21, 3), + PIN_FIELD_BASE(111, IO_BASE_RB0, 0x0000, 12, 3), + PIN_FIELD_BASE(112, IO_BASE_RB1, 0x0000, 0, 3), + PIN_FIELD_BASE(113, IO_BASE_RB1, 0x0000, 3, 3), + PIN_FIELD_BASE(114, IO_BASE_RB1, 0x0000, 6, 3), + PIN_FIELD_BASE(115, IO_BASE_BM1, 0x0000, 27, 3), + PIN_FIELD_BASE(116, IO_BASE_BM1, 0x0010, 6, 3), + PIN_FIELD_BASE(117, IO_BASE_BM1, 0x0010, 0, 3), + PIN_FIELD_BASE(118, IO_BASE_BM1, 0x0010, 3, 3), + PIN_FIELD_BASE(119, IO_BASE_BM0, 0x0020, 18, 3), + PIN_FIELD_BASE(120, IO_BASE_BM0, 0x0020, 15, 3), + PIN_FIELD_BASE(121, IO_BASE_BM0, 0x0020, 12, 3), + PIN_FIELD_BASE(122, IO_BASE_BM0, 0x0020, 9, 3), + PIN_FIELD_BASE(123, IO_BASE_BM0, 0x0010, 27, 3), + PIN_FIELD_BASE(124, IO_BASE_BM0, 0x0010, 24, 3), + PIN_FIELD_BASE(125, IO_BASE_BM0, 0x0010, 21, 3), + PIN_FIELD_BASE(126, IO_BASE_BM0, 0x0010, 18, 3), + PIN_FIELD_BASE(127, IO_BASE_BM0, 0x0020, 6, 3), + PIN_FIELD_BASE(128, IO_BASE_BM0, 0x0010, 15, 3), + PIN_FIELD_BASE(129, IO_BASE_BM0, 0x0020, 0, 3), + PIN_FIELD_BASE(130, IO_BASE_BM0, 0x0020, 21, 3), + PIN_FIELD_BASE(131, IO_BASE_BM0, 0x0010, 9, 3), + PIN_FIELD_BASE(132, IO_BASE_BM0, 0x0010, 12, 3), + PIN_FIELD_BASE(133, IO_BASE_BM0, 0x0020, 24, 3), + PIN_FIELD_BASE(134, IO_BASE_BM0, 0x0020, 3, 3), + PIN_FIELD_BASE(135, IO_BASE_BM0, 0x0010, 3, 3), + PIN_FIELD_BASE(136, IO_BASE_BM0, 0x0010, 6, 3), + PIN_FIELD_BASE(137, IO_BASE_BM1, 0x0000, 9, 3), + PIN_FIELD_BASE(138, IO_BASE_BM1, 0x0000, 12, 3), + PIN_FIELD_BASE(139, IO_BASE_BM0, 0x0000, 9, 3), + PIN_FIELD_BASE(140, IO_BASE_BM0, 0x0000, 12, 3), + PIN_FIELD_BASE(141, IO_BASE_BM0, 0x0000, 0, 3), + PIN_FIELD_BASE(142, IO_BASE_BM0, 0x0000, 3, 3), + PIN_FIELD_BASE(143, IO_BASE_BM0, 0x0000, 6, 3), + PIN_FIELD_BASE(144, IO_BASE_BM0, 0x0000, 15, 3), + PIN_FIELD_BASE(145, IO_BASE_BM0, 0x0000, 18, 3), + PIN_FIELD_BASE(146, IO_BASE_BM0, 0x0000, 21, 3), + PIN_FIELD_BASE(147, IO_BASE_BM0, 0x0000, 24, 3), + PIN_FIELD_BASE(148, IO_BASE_BM0, 0x0000, 27, 3), + PIN_FIELD_BASE(149, IO_BASE_BM0, 0x0010, 0, 3), + PIN_FIELD_BASE(150, IO_BASE_BM2, 0x0010, 12, 3), + PIN_FIELD_BASE(151, IO_BASE_BM0, 0x0020, 27, 3), + PIN_FIELD_BASE(152, IO_BASE_BM2, 0x0010, 15, 3), + PIN_FIELD_BASE(153, IO_BASE_BM2, 0x0010, 18, 3), + PIN_FIELD_BASE(154, IO_BASE_BM2, 0x0010, 21, 3), + PIN_FIELD_BASE(155, IO_BASE_BM2, 0x0010, 24, 3), + PIN_FIELD_BASE(156, IO_BASE_LT0, 0x0010, 6, 3), + PIN_FIELD_BASE(157, IO_BASE_LT0, 0x0010, 3, 3), + PIN_FIELD_BASE(158, IO_BASE_LT0, 0x0010, 0, 3), + PIN_FIELD_BASE(159, IO_BASE_LT1, 0x0000, 6, 3), + PIN_FIELD_BASE(160, IO_BASE_LT0, 0x0010, 12, 3), + PIN_FIELD_BASE(161, IO_BASE_LT0, 0x0000, 21, 3), + PIN_FIELD_BASE(162, IO_BASE_LT0, 0x0000, 18, 3), + PIN_FIELD_BASE(163, IO_BASE_LT1, 0x0000, 3, 3), + PIN_FIELD_BASE(164, IO_BASE_LT0, 0x0000, 27, 3), + PIN_FIELD_BASE(165, IO_BASE_LT0, 0x0000, 24, 3), + PIN_FIELD_BASE(166, IO_BASE_LT1, 0x0000, 0, 3), + PIN_FIELD_BASE(167, IO_BASE_LT0, 0x0010, 9, 3), + PIN_FIELD_BASE(168, IO_BASE_BM2, 0x0000, 24, 3), + PIN_FIELD_BASE(169, IO_BASE_BM2, 0x0000, 21, 3), + PIN_FIELD_BASE(170, IO_BASE_BM2, 0x0000, 27, 3), + PIN_FIELD_BASE(171, IO_BASE_BM2, 0x0010, 0, 3), + PIN_FIELD_BASE(172, IO_BASE_BM2, 0x0010, 3, 3), + PIN_FIELD_BASE(173, IO_BASE_BM2, 0x0010, 6, 3), + PIN_FIELD_BASE(174, IO_BASE_RT, 0x0000, 15, 3), + PIN_FIELD_BASE(175, IO_BASE_RT, 0x0000, 12, 3), + PIN_FIELD_BASE(176, IO_BASE_RT, 0x0000, 18, 3), + PIN_FIELD_BASE(177, IO_BASE_RT, 0x0000, 21, 3), + PIN_FIELD_BASE(178, IO_BASE_RT, 0x0000, 24, 3), + PIN_FIELD_BASE(179, IO_BASE_RT, 0x0000, 27, 3), + PIN_FIELD_BASE(180, IO_BASE_LT0, 0x0020, 12, 3), + PIN_FIELD_BASE(181, IO_BASE_LT0, 0x0020, 15, 3), + PIN_FIELD_BASE(182, IO_BASE_RT, 0x0000, 9, 3), +}; + +static const struct mtk_pin_reg_calc mt8189_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8189_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8189_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8189_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8189_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8189_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8189_pin_ies_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8189_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8189_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8189_pin_r1_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8189_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8189_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8189_pin_drv_range), +}; + +static const char * const mt8189_pinctrl_register_base_names[] = { + [IO_BASE] = "base", + [IO_BASE_LM] = "lm", + [IO_BASE_RB0] = "rb0", + [IO_BASE_RB1] = "rb1", + [IO_BASE_BM0] = "bm0", + [IO_BASE_BM1] = "bm1", + [IO_BASE_BM2] = "bm2", + [IO_BASE_LT0] = "lt0", + [IO_BASE_LT1] = "lt1", + [IO_BASE_RT] = "rt", + [IO_BASE_EINT0] = "eint0", + [IO_BASE_EINT1] = "eint1", + [IO_BASE_EINT2] = "eint2", + [IO_BASE_EINT3] = "eint3", + [IO_BASE_EINT4] = "eint4", +}; + +static const struct mtk_pin_desc mt8189_pins[] = { + MTK_TYPED_PIN(0, "GPIO00", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(1, "GPIO01", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(2, "GPIO02", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(3, "GPIO03", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(4, "GPIO04", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(5, "GPIO05", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(6, "GPIO06", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(7, "GPIO07", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(8, "GPIO08", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(9, "GPIO09", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(10, "GPIO10", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(11, "GPIO11", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(12, "GPIO12", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(13, "GPIO13", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(14, "GPIO14", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(15, "GPIO15", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(16, "GPIO16", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(17, "GPIO17", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(18, "GPIO18", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(19, "GPIO19", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(20, "GPIO20", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(21, "GPIO21", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(22, "GPIO22", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(23, "GPIO23", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(24, "GPIO24", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(25, "GPIO25", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(26, "GPIO26", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(27, "GPIO27", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(28, "GPIO28", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(29, "GPIO29", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(30, "GPIO30", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(31, "GPIO31", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(32, "GPIO32", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(33, "GPIO33", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(34, "GPIO34", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(35, "GPIO35", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(36, "GPIO36", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(37, "GPIO37", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(38, "GPIO38", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(39, "GPIO39", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(40, "GPIO40", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(41, "GPIO41", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(42, "GPIO42", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(43, "GPIO43", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(44, "GPIO44", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(45, "GPIO45", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(46, "GPIO46", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(47, "GPIO47", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(48, "GPIO48", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(49, "GPIO49", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(50, "GPIO50", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(51, "GPIO51", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(52, "GPIO52", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(53, "GPIO53", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(54, "GPIO54", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(55, "GPIO55", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(56, "GPIO56", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(57, "GPIO57", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(58, "GPIO58", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(59, "GPIO59", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(60, "GPIO60", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(61, "GPIO61", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(62, "GPIO62", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(63, "GPIO63", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(64, "GPIO64", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(65, "GPIO65", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(66, "GPIO66", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(67, "GPIO67", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(68, "GPIO68", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(69, "GPIO69", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(70, "GPIO70", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(71, "GPIO71", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(72, "GPIO72", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(73, "GPIO73", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(74, "GPIO74", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(75, "GPIO75", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(76, "GPIO76", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(77, "GPIO77", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(78, "GPIO78", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(79, "GPIO79", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(80, "GPIO80", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(81, "GPIO81", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(82, "GPIO82", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(83, "GPIO83", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(84, "GPIO84", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(85, "GPIO85", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(86, "GPIO86", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(87, "GPIO87", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(88, "GPIO88", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(89, "GPIO89", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(90, "GPIO90", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(91, "GPIO91", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(92, "GPIO92", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(93, "GPIO93", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(94, "GPIO94", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(95, "GPIO95", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(96, "GPIO96", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(97, "GPIO97", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(98, "GPIO98", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(99, "GPIO99", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(100, "GPIO100", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(101, "GPIO101", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(102, "GPIO102", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(103, "GPIO103", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(104, "GPIO104", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(105, "GPIO105", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(106, "GPIO106", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(107, "GPIO107", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(108, "GPIO108", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(109, "GPIO109", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(110, "GPIO110", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(111, "GPIO111", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(112, "GPIO112", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(113, "GPIO113", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(114, "GPIO114", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(115, "GPIO115", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(116, "GPIO116", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(117, "GPIO117", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(118, "GPIO118", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(119, "GPIO119", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(120, "GPIO120", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(121, "GPIO121", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(122, "GPIO122", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(123, "GPIO123", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(124, "GPIO124", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(125, "GPIO125", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(126, "GPIO126", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(127, "GPIO127", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(128, "GPIO128", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(129, "GPIO129", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(130, "GPIO130", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(131, "GPIO131", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(132, "GPIO132", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(133, "GPIO133", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(134, "GPIO134", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(135, "GPIO135", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(136, "GPIO136", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(137, "GPIO137", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(138, "GPIO138", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(139, "GPIO139", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(140, "GPIO140", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(141, "GPIO141", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(142, "GPIO142", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(143, "GPIO143", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(144, "GPIO144", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(145, "GPIO145", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(146, "GPIO146", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(147, "GPIO147", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(148, "GPIO148", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(149, "GPIO149", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(150, "GPIO150", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(151, "GPIO151", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(152, "GPIO152", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(153, "GPIO153", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(154, "GPIO154", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(155, "GPIO155", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(156, "GPIO156", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(157, "GPIO157", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(158, "GPIO158", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(159, "GPIO159", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(160, "GPIO160", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(161, "GPIO161", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(162, "GPIO162", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(163, "GPIO163", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(164, "GPIO164", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(165, "GPIO165", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(166, "GPIO166", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(167, "GPIO167", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(168, "GPIO168", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(169, "GPIO169", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(170, "GPIO170", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(171, "GPIO171", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(172, "GPIO172", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(173, "GPIO173", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(174, "GPIO174", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(175, "GPIO175", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(176, "GPIO176", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(177, "GPIO177", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(178, "GPIO178", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(179, "GPIO179", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(180, "GPIO180", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(181, "GPIO181", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(182, "GPIO182", DRV_GRP4, DRV_GRP0), +}; + +static const struct mtk_io_type_desc mt8189_io_type_desc[] = { + [IO_TYPE_GRP0] = { + .name = "mt8189", + .bias_set = mtk_pinconf_bias_set_v1, + .drive_set = mtk_pinconf_drive_set_v1, + .input_enable = mtk_pinconf_input_enable_v1, + }, +}; + +static struct mtk_pinctrl_soc mt8189_data = { + .name = "mt8189_pinctrl", + .reg_cal = mt8189_reg_cals, + .pins = mt8189_pins, + .npins = ARRAY_SIZE(mt8189_pins), + .io_type = mt8189_io_type_desc, + .ntype = ARRAY_SIZE(mt8189_io_type_desc), + .base_names = mt8189_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt8189_pinctrl_register_base_names), + .base_calc = 1, + .rev = MTK_PINCTRL_V1, +}; + +static int mtk_pinctrl_mt8189_probe(struct udevice *dev) +{ + return mtk_pinctrl_common_probe(dev, &mt8189_data); +} + +static const struct udevice_id mt8189_pctrl_match[] = { + { .compatible = "mediatek,mt8189-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(mt8189_pinctrl) = { + .name = "mt8189_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = mt8189_pctrl_match, + .ops = &mtk_pinctrl_ops, + .bind = mtk_pinctrl_common_bind, + .probe = mtk_pinctrl_mt8189_probe, + .priv_auto = sizeof(struct mtk_pinctrl_priv), +}; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8195.c b/drivers/pinctrl/mediatek/pinctrl-mt8195.c new file mode 100644 index 00000000000..db619766a99 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt8195.c @@ -0,0 +1,1080 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * The MT8195 driver based on Linux generic pinctrl binding. + * + * Copyright (C) 2026 MediaTek Inc. + * Author: Chris Chen <[email protected]> + */ +#include <dm.h> +#include "pinctrl-mtk-common.h" + +#define PIN_FIELD_IOCFG0(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_BASE_CALC(_s_pin, _e_pin, IOCFG0_BASE, _s_addr, _x_addrs, \ + _s_bit, _x_bits, 32, 0) + +#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits) \ + PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 0) + +#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits) \ + PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 1) + +#define MT8195_TYPE0_PIN(_number, _name) \ + MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0) + +#define MT8195_TYPE1_PIN(_number, _name) \ + MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1) + +enum { + IOCFG0_BASE, + IOCFG_BM_BASE, + IOCFG_BL_BASE, + IOCFG_BR_BASE, + IOCFG_LM_BASE, + IOCFG_RB_BASE, + IOCFG_TL_BASE, + EINT_BASE, +}; + +static const char * const mt8195_pinctrl_register_base_names[] = { + "iocfg0", "iocfg_bm", "iocfg_bl", + "iocfg_br", "iocfg_lm", "iocfg_rb", + "iocfg_tl", "eint", +}; + +static const struct mtk_pin_field_calc mt8195_pin_mode_range[] = { + PIN_FIELD_IOCFG0(0, 144, 0x300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt8195_pin_dir_range[] = { + PIN_FIELD_IOCFG0(0, 144, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_di_range[] = { + PIN_FIELD_IOCFG0(0, 144, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_do_range[] = { + PIN_FIELD_IOCFG0(0, 144, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_LM_BASE, 0x040, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, IOCFG_LM_BASE, 0x040, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, IOCFG_LM_BASE, 0x040, 0x10, 2, 1), + PIN_FIELD_BASE(3, 3, IOCFG_LM_BASE, 0x040, 0x10, 3, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LM_BASE, 0x040, 0x10, 4, 1), + PIN_FIELD_BASE(5, 5, IOCFG_LM_BASE, 0x040, 0x10, 5, 1), + PIN_FIELD_BASE(6, 6, IOCFG_LM_BASE, 0x040, 0x10, 6, 1), + PIN_FIELD_BASE(7, 7, IOCFG_LM_BASE, 0x040, 0x10, 7, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LM_BASE, 0x040, 0x10, 13, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LM_BASE, 0x040, 0x10, 8, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LM_BASE, 0x040, 0x10, 14, 1), + PIN_FIELD_BASE(11, 11, IOCFG_LM_BASE, 0x040, 0x10, 9, 1), + PIN_FIELD_BASE(12, 12, IOCFG_LM_BASE, 0x040, 0x10, 15, 1), + PIN_FIELD_BASE(13, 13, IOCFG_LM_BASE, 0x040, 0x10, 10, 1), + PIN_FIELD_BASE(14, 14, IOCFG_LM_BASE, 0x040, 0x10, 16, 1), + PIN_FIELD_BASE(15, 15, IOCFG_LM_BASE, 0x040, 0x10, 11, 1), + PIN_FIELD_BASE(16, 16, IOCFG_LM_BASE, 0x040, 0x10, 17, 1), + PIN_FIELD_BASE(17, 17, IOCFG_LM_BASE, 0x040, 0x10, 12, 1), + PIN_FIELD_BASE(18, 18, IOCFG_BL_BASE, 0x040, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, IOCFG_BL_BASE, 0x040, 0x10, 12, 1), + PIN_FIELD_BASE(20, 20, IOCFG_BL_BASE, 0x040, 0x10, 11, 1), + PIN_FIELD_BASE(21, 21, IOCFG_BL_BASE, 0x040, 0x10, 10, 1), + PIN_FIELD_BASE(22, 22, IOCFG_BL_BASE, 0x040, 0x10, 0, 1), + PIN_FIELD_BASE(23, 23, IOCFG_BL_BASE, 0x040, 0x10, 1, 1), + PIN_FIELD_BASE(24, 24, IOCFG_BL_BASE, 0x040, 0x10, 2, 1), + PIN_FIELD_BASE(25, 25, IOCFG_BL_BASE, 0x040, 0x10, 4, 1), + PIN_FIELD_BASE(26, 26, IOCFG_BL_BASE, 0x040, 0x10, 3, 1), + PIN_FIELD_BASE(27, 27, IOCFG_BL_BASE, 0x040, 0x10, 6, 1), + PIN_FIELD_BASE(28, 28, IOCFG_BL_BASE, 0x040, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, IOCFG_BL_BASE, 0x040, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, IOCFG_BL_BASE, 0x040, 0x10, 9, 1), + PIN_FIELD_BASE(31, 31, IOCFG_BM_BASE, 0x060, 0x10, 13, 1), + PIN_FIELD_BASE(32, 32, IOCFG_BM_BASE, 0x060, 0x10, 12, 1), + PIN_FIELD_BASE(33, 33, IOCFG_BM_BASE, 0x060, 0x10, 11, 1), + PIN_FIELD_BASE(34, 34, IOCFG_BM_BASE, 0x060, 0x10, 14, 1), + PIN_FIELD_BASE(35, 35, IOCFG_BM_BASE, 0x060, 0x10, 15, 1), + PIN_FIELD_BASE(36, 36, IOCFG_BM_BASE, 0x070, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, IOCFG_BM_BASE, 0x070, 0x10, 6, 1), + PIN_FIELD_BASE(38, 38, IOCFG_BM_BASE, 0x070, 0x10, 4, 1), + PIN_FIELD_BASE(39, 39, IOCFG_BM_BASE, 0x070, 0x10, 5, 1), + PIN_FIELD_BASE(40, 40, IOCFG_BM_BASE, 0x070, 0x10, 8, 1), + PIN_FIELD_BASE(41, 41, IOCFG_BM_BASE, 0x070, 0x10, 7, 1), + PIN_FIELD_BASE(42, 42, IOCFG_BM_BASE, 0x070, 0x10, 10, 1), + PIN_FIELD_BASE(43, 43, IOCFG_BM_BASE, 0x070, 0x10, 9, 1), + PIN_FIELD_BASE(44, 44, IOCFG_BM_BASE, 0x070, 0x10, 20, 1), + PIN_FIELD_BASE(45, 45, IOCFG_BM_BASE, 0x070, 0x10, 21, 1), + PIN_FIELD_BASE(46, 46, IOCFG_BM_BASE, 0x060, 0x10, 18, 1), + PIN_FIELD_BASE(47, 47, IOCFG_BM_BASE, 0x060, 0x10, 16, 1), + PIN_FIELD_BASE(48, 48, IOCFG_BM_BASE, 0x060, 0x10, 19, 1), + PIN_FIELD_BASE(49, 49, IOCFG_BM_BASE, 0x060, 0x10, 17, 1), + PIN_FIELD_BASE(50, 50, IOCFG_BM_BASE, 0x060, 0x10, 25, 1), + PIN_FIELD_BASE(51, 51, IOCFG_BM_BASE, 0x060, 0x10, 20, 1), + PIN_FIELD_BASE(52, 52, IOCFG_BM_BASE, 0x060, 0x10, 26, 1), + PIN_FIELD_BASE(53, 53, IOCFG_BM_BASE, 0x060, 0x10, 21, 1), + PIN_FIELD_BASE(54, 54, IOCFG_BM_BASE, 0x060, 0x10, 22, 1), + PIN_FIELD_BASE(55, 55, IOCFG_BM_BASE, 0x060, 0x10, 23, 1), + PIN_FIELD_BASE(56, 56, IOCFG_BM_BASE, 0x060, 0x10, 24, 1), + PIN_FIELD_BASE(57, 57, IOCFG_BM_BASE, 0x060, 0x10, 29, 1), + PIN_FIELD_BASE(58, 58, IOCFG_BM_BASE, 0x060, 0x10, 27, 1), + PIN_FIELD_BASE(59, 59, IOCFG_BM_BASE, 0x060, 0x10, 30, 1), + PIN_FIELD_BASE(60, 60, IOCFG_BM_BASE, 0x060, 0x10, 28, 1), + PIN_FIELD_BASE(61, 61, IOCFG_BM_BASE, 0x060, 0x10, 8, 1), + PIN_FIELD_BASE(62, 62, IOCFG_BM_BASE, 0x060, 0x10, 7, 1), + PIN_FIELD_BASE(63, 63, IOCFG_BM_BASE, 0x060, 0x10, 10, 1), + PIN_FIELD_BASE(64, 64, IOCFG_BM_BASE, 0x060, 0x10, 9, 1), + PIN_FIELD_BASE(65, 65, IOCFG_BM_BASE, 0x070, 0x10, 1, 1), + PIN_FIELD_BASE(66, 66, IOCFG_BM_BASE, 0x060, 0x10, 31, 1), + PIN_FIELD_BASE(67, 67, IOCFG_BM_BASE, 0x070, 0x10, 0, 1), + PIN_FIELD_BASE(68, 68, IOCFG_BM_BASE, 0x070, 0x10, 2, 1), + PIN_FIELD_BASE(69, 69, IOCFG_BM_BASE, 0x060, 0x10, 0, 1), + PIN_FIELD_BASE(70, 70, IOCFG_BM_BASE, 0x060, 0x10, 6, 1), + PIN_FIELD_BASE(71, 71, IOCFG_BM_BASE, 0x060, 0x10, 4, 1), + PIN_FIELD_BASE(72, 72, IOCFG_BM_BASE, 0x060, 0x10, 5, 1), + PIN_FIELD_BASE(73, 73, IOCFG_BM_BASE, 0x060, 0x10, 1, 1), + PIN_FIELD_BASE(74, 74, IOCFG_BM_BASE, 0x060, 0x10, 2, 1), + PIN_FIELD_BASE(75, 75, IOCFG_BM_BASE, 0x060, 0x10, 3, 1), + PIN_FIELD_BASE(76, 76, IOCFG_BM_BASE, 0x070, 0x10, 11, 1), + PIN_FIELD_BASE(77, 77, IOCFG_BR_BASE, 0x030, 0x10, 1, 1), + PIN_FIELD_BASE(78, 78, IOCFG_BR_BASE, 0x030, 0x10, 2, 1), + PIN_FIELD_BASE(79, 79, IOCFG_BR_BASE, 0x030, 0x10, 9, 1), + PIN_FIELD_BASE(80, 80, IOCFG_BR_BASE, 0x030, 0x10, 10, 1), + PIN_FIELD_BASE(81, 81, IOCFG_BR_BASE, 0x030, 0x10, 11, 1), + PIN_FIELD_BASE(82, 82, IOCFG_BR_BASE, 0x030, 0x10, 12, 1), + PIN_FIELD_BASE(83, 83, IOCFG_BR_BASE, 0x030, 0x10, 13, 1), + PIN_FIELD_BASE(84, 84, IOCFG_BR_BASE, 0x030, 0x10, 14, 1), + PIN_FIELD_BASE(85, 85, IOCFG_BR_BASE, 0x030, 0x10, 15, 1), + PIN_FIELD_BASE(86, 86, IOCFG_BR_BASE, 0x030, 0x10, 16, 1), + PIN_FIELD_BASE(87, 87, IOCFG_BR_BASE, 0x030, 0x10, 3, 1), + PIN_FIELD_BASE(88, 88, IOCFG_BR_BASE, 0x030, 0x10, 4, 1), + PIN_FIELD_BASE(89, 89, IOCFG_BR_BASE, 0x030, 0x10, 5, 1), + PIN_FIELD_BASE(90, 90, IOCFG_BR_BASE, 0x030, 0x10, 6, 1), + PIN_FIELD_BASE(91, 91, IOCFG_BR_BASE, 0x030, 0x10, 7, 1), + PIN_FIELD_BASE(92, 92, IOCFG_BR_BASE, 0x030, 0x10, 8, 1), + PIN_FIELD_BASE(93, 93, IOCFG_BR_BASE, 0x030, 0x10, 18, 1), + PIN_FIELD_BASE(94, 94, IOCFG_BR_BASE, 0x030, 0x10, 19, 1), + PIN_FIELD_BASE(95, 95, IOCFG_BR_BASE, 0x030, 0x10, 17, 1), + PIN_FIELD_BASE(96, 96, IOCFG_BR_BASE, 0x030, 0x10, 0, 1), + PIN_FIELD_BASE(97, 97, IOCFG_BR_BASE, 0x030, 0x10, 20, 1), + PIN_FIELD_BASE(98, 98, IOCFG_BR_BASE, 0x030, 0x10, 28, 1), + PIN_FIELD_BASE(99, 99, IOCFG_BR_BASE, 0x030, 0x10, 27, 1), + PIN_FIELD_BASE(100, 100, IOCFG_BR_BASE, 0x030, 0x10, 30, 1), + PIN_FIELD_BASE(101, 101, IOCFG_BR_BASE, 0x030, 0x10, 29, 1), + PIN_FIELD_BASE(102, 102, IOCFG_BR_BASE, 0x040, 0x10, 0, 1), + PIN_FIELD_BASE(103, 103, IOCFG_BR_BASE, 0x030, 0x10, 31, 1), + PIN_FIELD_BASE(104, 104, IOCFG_BR_BASE, 0x030, 0x10, 25, 1), + PIN_FIELD_BASE(105, 105, IOCFG_BR_BASE, 0x030, 0x10, 26, 1), + PIN_FIELD_BASE(106, 106, IOCFG_BR_BASE, 0x030, 0x10, 23, 1), + PIN_FIELD_BASE(107, 107, IOCFG_BR_BASE, 0x030, 0x10, 24, 1), + PIN_FIELD_BASE(108, 108, IOCFG_BR_BASE, 0x030, 0x10, 22, 1), + PIN_FIELD_BASE(109, 109, IOCFG_BR_BASE, 0x030, 0x10, 21, 1), + PIN_FIELD_BASE(110, 110, IOCFG_RB_BASE, 0x010, 0x10, 1, 1), + PIN_FIELD_BASE(111, 111, IOCFG_RB_BASE, 0x010, 0x10, 0, 1), + PIN_FIELD_BASE(112, 112, IOCFG_RB_BASE, 0x010, 0x10, 2, 1), + PIN_FIELD_BASE(113, 113, IOCFG_RB_BASE, 0x010, 0x10, 3, 1), + PIN_FIELD_BASE(114, 114, IOCFG_RB_BASE, 0x010, 0x10, 4, 1), + PIN_FIELD_BASE(115, 115, IOCFG_RB_BASE, 0x010, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, IOCFG_TL_BASE, 0x030, 0x10, 9, 1), + PIN_FIELD_BASE(117, 117, IOCFG_TL_BASE, 0x030, 0x10, 8, 1), + PIN_FIELD_BASE(118, 118, IOCFG_TL_BASE, 0x030, 0x10, 7, 1), + PIN_FIELD_BASE(119, 119, IOCFG_TL_BASE, 0x030, 0x10, 6, 1), + PIN_FIELD_BASE(120, 120, IOCFG_TL_BASE, 0x030, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, IOCFG_TL_BASE, 0x030, 0x10, 1, 1), + PIN_FIELD_BASE(122, 122, IOCFG_TL_BASE, 0x030, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, IOCFG_TL_BASE, 0x030, 0x10, 5, 1), + PIN_FIELD_BASE(124, 124, IOCFG_TL_BASE, 0x030, 0x10, 4, 1), + PIN_FIELD_BASE(125, 125, IOCFG_TL_BASE, 0x030, 0x10, 3, 1), + PIN_FIELD_BASE(126, 126, IOCFG_TL_BASE, 0x030, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, IOCFG_TL_BASE, 0x030, 0x10, 10, 1), + PIN_FIELD_BASE(128, 128, IOCFG_BR_BASE, 0x040, 0x10, 3, 1), + PIN_FIELD_BASE(129, 129, IOCFG_BR_BASE, 0x040, 0x10, 1, 1), + PIN_FIELD_BASE(130, 130, IOCFG_BR_BASE, 0x040, 0x10, 4, 1), + PIN_FIELD_BASE(131, 131, IOCFG_BR_BASE, 0x040, 0x10, 2, 1), + PIN_FIELD_BASE(132, 132, IOCFG_TL_BASE, 0x030, 0x10, 13, 1), + PIN_FIELD_BASE(133, 133, IOCFG_TL_BASE, 0x030, 0x10, 12, 1), + PIN_FIELD_BASE(134, 134, IOCFG_TL_BASE, 0x030, 0x10, 15, 1), + PIN_FIELD_BASE(135, 135, IOCFG_TL_BASE, 0x030, 0x10, 14, 1), + PIN_FIELD_BASE(136, 136, IOCFG_BM_BASE, 0x070, 0x10, 13, 1), + PIN_FIELD_BASE(137, 137, IOCFG_BM_BASE, 0x070, 0x10, 12, 1), + PIN_FIELD_BASE(138, 138, IOCFG_BM_BASE, 0x070, 0x10, 15, 1), + PIN_FIELD_BASE(139, 139, IOCFG_BM_BASE, 0x070, 0x10, 14, 1), + PIN_FIELD_BASE(140, 140, IOCFG_BM_BASE, 0x070, 0x10, 17, 1), + PIN_FIELD_BASE(141, 141, IOCFG_BM_BASE, 0x070, 0x10, 16, 1), + PIN_FIELD_BASE(142, 142, IOCFG_BM_BASE, 0x070, 0x10, 19, 1), + PIN_FIELD_BASE(143, 143, IOCFG_BM_BASE, 0x070, 0x10, 18, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_smt_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_LM_BASE, 0x0d0, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, IOCFG_LM_BASE, 0x0d0, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, IOCFG_LM_BASE, 0x0d0, 0x10, 2, 1), + PIN_FIELD_BASE(3, 3, IOCFG_LM_BASE, 0x0d0, 0x10, 3, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LM_BASE, 0x0d0, 0x10, 4, 1), + PIN_FIELD_BASE(5, 5, IOCFG_LM_BASE, 0x0d0, 0x10, 5, 1), + PINS_FIELD_BASE(6, 7, IOCFG_LM_BASE, 0x0d0, 0x10, 6, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LM_BASE, 0x0d0, 0x10, 12, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LM_BASE, 0x0d0, 0x10, 7, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LM_BASE, 0x0d0, 0x10, 13, 1), + PIN_FIELD_BASE(11, 11, IOCFG_LM_BASE, 0x0d0, 0x10, 8, 1), + PIN_FIELD_BASE(12, 12, IOCFG_LM_BASE, 0x0d0, 0x10, 14, 1), + PIN_FIELD_BASE(13, 13, IOCFG_LM_BASE, 0x0d0, 0x10, 9, 1), + PIN_FIELD_BASE(14, 14, IOCFG_LM_BASE, 0x0d0, 0x10, 15, 1), + PIN_FIELD_BASE(15, 15, IOCFG_LM_BASE, 0x0d0, 0x10, 10, 1), + PIN_FIELD_BASE(16, 16, IOCFG_LM_BASE, 0x0d0, 0x10, 16, 1), + PIN_FIELD_BASE(17, 17, IOCFG_LM_BASE, 0x0d0, 0x10, 11, 1), + PIN_FIELD_BASE(18, 18, IOCFG_BL_BASE, 0x090, 0x10, 11, 1), + PIN_FIELD_BASE(19, 19, IOCFG_BL_BASE, 0x090, 0x10, 10, 1), + PIN_FIELD_BASE(20, 20, IOCFG_BL_BASE, 0x090, 0x10, 9, 1), + PIN_FIELD_BASE(21, 21, IOCFG_BL_BASE, 0x090, 0x10, 11, 1), + PIN_FIELD_BASE(22, 22, IOCFG_BL_BASE, 0x090, 0x10, 0, 1), + PIN_FIELD_BASE(23, 23, IOCFG_BL_BASE, 0x090, 0x10, 1, 1), + PIN_FIELD_BASE(24, 24, IOCFG_BL_BASE, 0x090, 0x10, 2, 1), + PIN_FIELD_BASE(25, 25, IOCFG_BL_BASE, 0x090, 0x10, 4, 1), + PIN_FIELD_BASE(26, 26, IOCFG_BL_BASE, 0x090, 0x10, 3, 1), + PIN_FIELD_BASE(27, 27, IOCFG_BL_BASE, 0x090, 0x10, 5, 1), + PIN_FIELD_BASE(28, 28, IOCFG_BL_BASE, 0x090, 0x10, 6, 1), + PIN_FIELD_BASE(29, 29, IOCFG_BL_BASE, 0x090, 0x10, 7, 1), + PIN_FIELD_BASE(30, 30, IOCFG_BL_BASE, 0x090, 0x10, 8, 1), + PINS_FIELD_BASE(31, 33, IOCFG_BM_BASE, 0x0f0, 0x10, 4, 1), + PIN_FIELD_BASE(34, 34, IOCFG_BM_BASE, 0x0f0, 0x10, 0, 1), + PIN_FIELD_BASE(35, 35, IOCFG_BM_BASE, 0x0f0, 0x10, 1, 1), + PIN_FIELD_BASE(36, 36, IOCFG_BM_BASE, 0x0f0, 0x10, 4, 1), + PIN_FIELD_BASE(37, 37, IOCFG_BM_BASE, 0x0f0, 0x10, 2, 1), + PINS_FIELD_BASE(38, 39, IOCFG_BM_BASE, 0x0f0, 0x10, 5, 1), + PIN_FIELD_BASE(40, 40, IOCFG_BM_BASE, 0x0f0, 0x10, 14, 1), + PIN_FIELD_BASE(41, 41, IOCFG_BM_BASE, 0x0f0, 0x10, 13, 1), + PIN_FIELD_BASE(42, 42, IOCFG_BM_BASE, 0x0f0, 0x10, 16, 1), + PIN_FIELD_BASE(43, 43, IOCFG_BM_BASE, 0x0f0, 0x10, 15, 1), + PIN_FIELD_BASE(44, 44, IOCFG_BM_BASE, 0x0f0, 0x10, 25, 1), + PIN_FIELD_BASE(45, 45, IOCFG_BM_BASE, 0x0f0, 0x10, 26, 1), + PINS_FIELD_BASE(46, 47, IOCFG_BM_BASE, 0x0f0, 0x10, 5, 1), + PINS_FIELD_BASE(48, 51, IOCFG_BM_BASE, 0x0f0, 0x10, 6, 1), + PINS_FIELD_BASE(52, 55, IOCFG_BM_BASE, 0x0f0, 0x10, 7, 1), + PINS_FIELD_BASE(56, 59, IOCFG_BM_BASE, 0x0f0, 0x10, 8, 1), + PINS_FIELD_BASE(60, 63, IOCFG_BM_BASE, 0x0f0, 0x10, 9, 1), + PIN_FIELD_BASE(64, 64, IOCFG_BM_BASE, 0x0f0, 0x10, 10, 1), + PINS_FIELD_BASE(65, 68, IOCFG_BM_BASE, 0x0f0, 0x10, 3, 1), + PINS_FIELD_BASE(69, 71, IOCFG_BM_BASE, 0x0f0, 0x10, 10, 1), + PINS_FIELD_BASE(72, 75, IOCFG_BM_BASE, 0x0f0, 0x10, 11, 1), + PIN_FIELD_BASE(76, 76, IOCFG_BM_BASE, 0x0f0, 0x10, 12, 1), + PIN_FIELD_BASE(77, 77, IOCFG_BR_BASE, 0x0e0, 0x10, 0, 1), + PIN_FIELD_BASE(78, 78, IOCFG_BR_BASE, 0x0e0, 0x10, 1, 1), + PIN_FIELD_BASE(79, 79, IOCFG_BR_BASE, 0x0e0, 0x10, 6, 1), + PIN_FIELD_BASE(80, 80, IOCFG_BR_BASE, 0x0e0, 0x10, 7, 1), + PIN_FIELD_BASE(81, 81, IOCFG_BR_BASE, 0x0e0, 0x10, 8, 1), + PIN_FIELD_BASE(82, 82, IOCFG_BR_BASE, 0x0e0, 0x10, 9, 1), + PIN_FIELD_BASE(83, 83, IOCFG_BR_BASE, 0x0e0, 0x10, 10, 1), + PIN_FIELD_BASE(84, 84, IOCFG_BR_BASE, 0x0e0, 0x10, 11, 1), + PINS_FIELD_BASE(85, 88, IOCFG_BR_BASE, 0x0e0, 0x10, 14, 1), + PIN_FIELD_BASE(89, 89, IOCFG_BR_BASE, 0x0e0, 0x10, 2, 1), + PIN_FIELD_BASE(90, 90, IOCFG_BR_BASE, 0x0e0, 0x10, 3, 1), + PIN_FIELD_BASE(91, 91, IOCFG_BR_BASE, 0x0e0, 0x10, 4, 1), + PIN_FIELD_BASE(92, 92, IOCFG_BR_BASE, 0x0e0, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, IOCFG_BR_BASE, 0x0e0, 0x10, 12, 1), + PIN_FIELD_BASE(94, 94, IOCFG_BR_BASE, 0x0e0, 0x10, 13, 1), + PINS_FIELD_BASE(95, 98, IOCFG_BR_BASE, 0x0e0, 0x10, 15, 1), + PINS_FIELD_BASE(99, 102, IOCFG_BR_BASE, 0x0e0, 0x10, 16, 1), + PINS_FIELD_BASE(103, 104, IOCFG_BR_BASE, 0x0e0, 0x10, 17, 1), + PIN_FIELD_BASE(105, 105, IOCFG_BR_BASE, 0x0e0, 0x10, 18, 1), + PINS_FIELD_BASE(106, 107, IOCFG_BR_BASE, 0x0e0, 0x10, 17, 1), + PINS_FIELD_BASE(108, 109, IOCFG_BR_BASE, 0x0e0, 0x10, 18, 1), + PIN_FIELD_BASE(110, 110, IOCFG_RB_BASE, 0x070, 0x10, 1, 1), + PIN_FIELD_BASE(111, 111, IOCFG_RB_BASE, 0x070, 0x10, 0, 1), + PIN_FIELD_BASE(112, 112, IOCFG_RB_BASE, 0x070, 0x10, 2, 1), + PIN_FIELD_BASE(113, 113, IOCFG_RB_BASE, 0x070, 0x10, 3, 1), + PIN_FIELD_BASE(114, 114, IOCFG_RB_BASE, 0x070, 0x10, 4, 1), + PIN_FIELD_BASE(115, 115, IOCFG_RB_BASE, 0x070, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, IOCFG_TL_BASE, 0x0c0, 0x10, 9, 1), + PIN_FIELD_BASE(117, 117, IOCFG_TL_BASE, 0x0c0, 0x10, 8, 1), + PIN_FIELD_BASE(118, 118, IOCFG_TL_BASE, 0x0c0, 0x10, 7, 1), + PIN_FIELD_BASE(119, 119, IOCFG_TL_BASE, 0x0c0, 0x10, 6, 1), + PIN_FIELD_BASE(120, 120, IOCFG_TL_BASE, 0x0c0, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, IOCFG_TL_BASE, 0x0c0, 0x10, 1, 1), + PIN_FIELD_BASE(122, 122, IOCFG_TL_BASE, 0x0c0, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, IOCFG_TL_BASE, 0x0c0, 0x10, 5, 1), + PIN_FIELD_BASE(124, 124, IOCFG_TL_BASE, 0x0c0, 0x10, 4, 1), + PIN_FIELD_BASE(125, 125, IOCFG_TL_BASE, 0x0c0, 0x10, 3, 1), + PIN_FIELD_BASE(126, 126, IOCFG_TL_BASE, 0x0c0, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, IOCFG_TL_BASE, 0x0c0, 0x10, 10, 1), + PIN_FIELD_BASE(128, 128, IOCFG_BR_BASE, 0x0e0, 0x10, 18, 1), + PINS_FIELD_BASE(129, 131, IOCFG_BR_BASE, 0x0e0, 0x10, 19, 1), + PIN_FIELD_BASE(132, 132, IOCFG_TL_BASE, 0x0c0, 0x10, 13, 1), + PIN_FIELD_BASE(133, 133, IOCFG_TL_BASE, 0x0c0, 0x10, 12, 1), + PIN_FIELD_BASE(134, 134, IOCFG_TL_BASE, 0x0c0, 0x10, 15, 1), + PIN_FIELD_BASE(135, 135, IOCFG_TL_BASE, 0x0c0, 0x10, 14, 1), + PIN_FIELD_BASE(136, 136, IOCFG_BM_BASE, 0x0f0, 0x10, 18, 1), + PIN_FIELD_BASE(137, 137, IOCFG_BM_BASE, 0x0f0, 0x10, 17, 1), + PIN_FIELD_BASE(138, 138, IOCFG_BM_BASE, 0x0f0, 0x10, 20, 1), + PIN_FIELD_BASE(139, 139, IOCFG_BM_BASE, 0x0f0, 0x10, 19, 1), + PIN_FIELD_BASE(140, 140, IOCFG_BM_BASE, 0x0f0, 0x10, 22, 1), + PIN_FIELD_BASE(141, 141, IOCFG_BM_BASE, 0x0f0, 0x10, 21, 1), + PIN_FIELD_BASE(142, 142, IOCFG_BM_BASE, 0x0f0, 0x10, 24, 1), + PIN_FIELD_BASE(143, 143, IOCFG_BM_BASE, 0x0f0, 0x10, 23, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_pu_range[] = { + PIN_FIELD_BASE(6, 6, IOCFG_LM_BASE, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, IOCFG_LM_BASE, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LM_BASE, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LM_BASE, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LM_BASE, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(11, 11, IOCFG_LM_BASE, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(12, 12, IOCFG_LM_BASE, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(13, 13, IOCFG_LM_BASE, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(14, 14, IOCFG_LM_BASE, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(15, 15, IOCFG_LM_BASE, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(16, 16, IOCFG_LM_BASE, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(17, 17, IOCFG_LM_BASE, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(18, 18, IOCFG_BL_BASE, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, IOCFG_BL_BASE, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(20, 20, IOCFG_BL_BASE, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(21, 21, IOCFG_BL_BASE, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(22, 22, IOCFG_BL_BASE, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(23, 23, IOCFG_BL_BASE, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(24, 24, IOCFG_BL_BASE, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(25, 25, IOCFG_BL_BASE, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(26, 26, IOCFG_BL_BASE, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(27, 27, IOCFG_BL_BASE, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(28, 28, IOCFG_BL_BASE, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, IOCFG_BL_BASE, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, IOCFG_BL_BASE, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(31, 31, IOCFG_BM_BASE, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(32, 32, IOCFG_BM_BASE, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(33, 33, IOCFG_BM_BASE, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(34, 34, IOCFG_BM_BASE, 0x00a0, 0x10, 14, 1), + PIN_FIELD_BASE(35, 35, IOCFG_BM_BASE, 0x00a0, 0x10, 15, 1), + PIN_FIELD_BASE(36, 36, IOCFG_BM_BASE, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, IOCFG_BM_BASE, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(38, 38, IOCFG_BM_BASE, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(39, 39, IOCFG_BM_BASE, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(40, 40, IOCFG_BM_BASE, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(41, 41, IOCFG_BM_BASE, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(42, 42, IOCFG_BM_BASE, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(43, 43, IOCFG_BM_BASE, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(44, 44, IOCFG_BM_BASE, 0x00b0, 0x10, 21, 1), + PIN_FIELD_BASE(45, 45, IOCFG_BM_BASE, 0x00b0, 0x10, 22, 1), + PIN_FIELD_BASE(46, 46, IOCFG_BM_BASE, 0x00a0, 0x10, 18, 1), + PIN_FIELD_BASE(47, 47, IOCFG_BM_BASE, 0x00a0, 0x10, 16, 1), + PIN_FIELD_BASE(48, 48, IOCFG_BM_BASE, 0x00a0, 0x10, 19, 1), + PIN_FIELD_BASE(49, 49, IOCFG_BM_BASE, 0x00a0, 0x10, 17, 1), + PIN_FIELD_BASE(50, 50, IOCFG_BM_BASE, 0x00a0, 0x10, 25, 1), + PIN_FIELD_BASE(51, 51, IOCFG_BM_BASE, 0x00a0, 0x10, 20, 1), + PIN_FIELD_BASE(52, 52, IOCFG_BM_BASE, 0x00a0, 0x10, 26, 1), + PIN_FIELD_BASE(53, 53, IOCFG_BM_BASE, 0x00a0, 0x10, 21, 1), + PIN_FIELD_BASE(54, 54, IOCFG_BM_BASE, 0x00a0, 0x10, 22, 1), + PIN_FIELD_BASE(55, 55, IOCFG_BM_BASE, 0x00a0, 0x10, 23, 1), + PIN_FIELD_BASE(56, 56, IOCFG_BM_BASE, 0x00a0, 0x10, 24, 1), + PIN_FIELD_BASE(57, 57, IOCFG_BM_BASE, 0x00a0, 0x10, 29, 1), + PIN_FIELD_BASE(58, 58, IOCFG_BM_BASE, 0x00a0, 0x10, 27, 1), + PIN_FIELD_BASE(59, 59, IOCFG_BM_BASE, 0x00a0, 0x10, 30, 1), + PIN_FIELD_BASE(60, 60, IOCFG_BM_BASE, 0x00a0, 0x10, 28, 1), + PIN_FIELD_BASE(61, 61, IOCFG_BM_BASE, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(62, 62, IOCFG_BM_BASE, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(63, 63, IOCFG_BM_BASE, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(64, 64, IOCFG_BM_BASE, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(65, 65, IOCFG_BM_BASE, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(66, 66, IOCFG_BM_BASE, 0x00a0, 0x10, 31, 1), + PIN_FIELD_BASE(67, 67, IOCFG_BM_BASE, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(68, 68, IOCFG_BM_BASE, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(69, 69, IOCFG_BM_BASE, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(70, 70, IOCFG_BM_BASE, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(71, 71, IOCFG_BM_BASE, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(72, 72, IOCFG_BM_BASE, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(73, 73, IOCFG_BM_BASE, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(74, 74, IOCFG_BM_BASE, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(75, 75, IOCFG_BM_BASE, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(76, 76, IOCFG_BM_BASE, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(97, 97, IOCFG_BR_BASE, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(98, 98, IOCFG_BR_BASE, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(99, 99, IOCFG_BR_BASE, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(100, 100, IOCFG_BR_BASE, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(101, 101, IOCFG_BR_BASE, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(102, 102, IOCFG_BR_BASE, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(103, 103, IOCFG_BR_BASE, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(108, 108, IOCFG_BR_BASE, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(109, 109, IOCFG_BR_BASE, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(128, 128, IOCFG_BR_BASE, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(129, 129, IOCFG_BR_BASE, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(130, 130, IOCFG_BR_BASE, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(131, 131, IOCFG_BR_BASE, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(132, 132, IOCFG_TL_BASE, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(133, 133, IOCFG_TL_BASE, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(134, 134, IOCFG_TL_BASE, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(135, 135, IOCFG_TL_BASE, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(136, 136, IOCFG_BM_BASE, 0x00b0, 0x10, 14, 1), + PIN_FIELD_BASE(137, 137, IOCFG_BM_BASE, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(138, 138, IOCFG_BM_BASE, 0x00b0, 0x10, 16, 1), + PIN_FIELD_BASE(139, 139, IOCFG_BM_BASE, 0x00b0, 0x10, 15, 1), + PIN_FIELD_BASE(140, 140, IOCFG_BM_BASE, 0x00b0, 0x10, 18, 1), + PIN_FIELD_BASE(141, 141, IOCFG_BM_BASE, 0x00b0, 0x10, 17, 1), + PIN_FIELD_BASE(142, 142, IOCFG_BM_BASE, 0x00b0, 0x10, 20, 1), + PIN_FIELD_BASE(143, 143, IOCFG_BM_BASE, 0x00b0, 0x10, 19, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_pd_range[] = { + PIN_FIELD_BASE(6, 6, IOCFG_LM_BASE, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, IOCFG_LM_BASE, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LM_BASE, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LM_BASE, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LM_BASE, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(11, 11, IOCFG_LM_BASE, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(12, 12, IOCFG_LM_BASE, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(13, 13, IOCFG_LM_BASE, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(14, 14, IOCFG_LM_BASE, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(15, 15, IOCFG_LM_BASE, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(16, 16, IOCFG_LM_BASE, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(17, 17, IOCFG_LM_BASE, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(18, 18, IOCFG_BL_BASE, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, IOCFG_BL_BASE, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(20, 20, IOCFG_BL_BASE, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(21, 21, IOCFG_BL_BASE, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(22, 22, IOCFG_BL_BASE, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(23, 23, IOCFG_BL_BASE, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(24, 24, IOCFG_BL_BASE, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(25, 25, IOCFG_BL_BASE, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(26, 26, IOCFG_BL_BASE, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(27, 27, IOCFG_BL_BASE, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(28, 28, IOCFG_BL_BASE, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, IOCFG_BL_BASE, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, IOCFG_BL_BASE, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(31, 31, IOCFG_BM_BASE, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(32, 32, IOCFG_BM_BASE, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(33, 33, IOCFG_BM_BASE, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(34, 34, IOCFG_BM_BASE, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(35, 35, IOCFG_BM_BASE, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(36, 36, IOCFG_BM_BASE, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, IOCFG_BM_BASE, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(38, 38, IOCFG_BM_BASE, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(39, 39, IOCFG_BM_BASE, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(40, 40, IOCFG_BM_BASE, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(41, 41, IOCFG_BM_BASE, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(42, 42, IOCFG_BM_BASE, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(43, 43, IOCFG_BM_BASE, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(44, 44, IOCFG_BM_BASE, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(45, 45, IOCFG_BM_BASE, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(46, 46, IOCFG_BM_BASE, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(47, 47, IOCFG_BM_BASE, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(48, 48, IOCFG_BM_BASE, 0x0080, 0x10, 19, 1), + PIN_FIELD_BASE(49, 49, IOCFG_BM_BASE, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(50, 50, IOCFG_BM_BASE, 0x0080, 0x10, 25, 1), + PIN_FIELD_BASE(51, 51, IOCFG_BM_BASE, 0x0080, 0x10, 20, 1), + PIN_FIELD_BASE(52, 52, IOCFG_BM_BASE, 0x0080, 0x10, 26, 1), + PIN_FIELD_BASE(53, 53, IOCFG_BM_BASE, 0x0080, 0x10, 21, 1), + PIN_FIELD_BASE(54, 54, IOCFG_BM_BASE, 0x0080, 0x10, 22, 1), + PIN_FIELD_BASE(55, 55, IOCFG_BM_BASE, 0x0080, 0x10, 23, 1), + PIN_FIELD_BASE(56, 56, IOCFG_BM_BASE, 0x0080, 0x10, 24, 1), + PIN_FIELD_BASE(57, 57, IOCFG_BM_BASE, 0x0080, 0x10, 29, 1), + PIN_FIELD_BASE(58, 58, IOCFG_BM_BASE, 0x0080, 0x10, 27, 1), + PIN_FIELD_BASE(59, 59, IOCFG_BM_BASE, 0x0080, 0x10, 30, 1), + PIN_FIELD_BASE(60, 60, IOCFG_BM_BASE, 0x0080, 0x10, 28, 1), + PIN_FIELD_BASE(61, 61, IOCFG_BM_BASE, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(62, 62, IOCFG_BM_BASE, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(63, 63, IOCFG_BM_BASE, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(64, 64, IOCFG_BM_BASE, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(65, 65, IOCFG_BM_BASE, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(66, 66, IOCFG_BM_BASE, 0x0080, 0x10, 31, 1), + PIN_FIELD_BASE(67, 67, IOCFG_BM_BASE, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(68, 68, IOCFG_BM_BASE, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(69, 69, IOCFG_BM_BASE, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(70, 70, IOCFG_BM_BASE, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(71, 71, IOCFG_BM_BASE, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(72, 72, IOCFG_BM_BASE, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(73, 73, IOCFG_BM_BASE, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(74, 74, IOCFG_BM_BASE, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(75, 75, IOCFG_BM_BASE, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(76, 76, IOCFG_BM_BASE, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(97, 97, IOCFG_BR_BASE, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(98, 98, IOCFG_BR_BASE, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(99, 99, IOCFG_BR_BASE, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(100, 100, IOCFG_BR_BASE, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(101, 101, IOCFG_BR_BASE, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(102, 102, IOCFG_BR_BASE, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(103, 103, IOCFG_BR_BASE, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(108, 108, IOCFG_BR_BASE, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(109, 109, IOCFG_BR_BASE, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(128, 128, IOCFG_BR_BASE, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(129, 129, IOCFG_BR_BASE, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(130, 130, IOCFG_BR_BASE, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(131, 131, IOCFG_BR_BASE, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(132, 132, IOCFG_TL_BASE, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(133, 133, IOCFG_TL_BASE, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(134, 134, IOCFG_TL_BASE, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(135, 135, IOCFG_TL_BASE, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(136, 136, IOCFG_BM_BASE, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(137, 137, IOCFG_BM_BASE, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(138, 138, IOCFG_BM_BASE, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(139, 139, IOCFG_BM_BASE, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(140, 140, IOCFG_BM_BASE, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(141, 141, IOCFG_BM_BASE, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(142, 142, IOCFG_BM_BASE, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(143, 143, IOCFG_BM_BASE, 0x0090, 0x10, 19, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_pupd_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_LM_BASE, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, IOCFG_LM_BASE, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, IOCFG_LM_BASE, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(3, 3, IOCFG_LM_BASE, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LM_BASE, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(5, 5, IOCFG_LM_BASE, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(77, 77, IOCFG_BR_BASE, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(78, 78, IOCFG_BR_BASE, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(79, 79, IOCFG_BR_BASE, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(80, 80, IOCFG_BR_BASE, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(81, 81, IOCFG_BR_BASE, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(82, 82, IOCFG_BR_BASE, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(83, 83, IOCFG_BR_BASE, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(84, 84, IOCFG_BR_BASE, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(85, 85, IOCFG_BR_BASE, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(86, 86, IOCFG_BR_BASE, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(87, 87, IOCFG_BR_BASE, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(88, 88, IOCFG_BR_BASE, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(89, 89, IOCFG_BR_BASE, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(90, 90, IOCFG_BR_BASE, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(91, 91, IOCFG_BR_BASE, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(92, 92, IOCFG_BR_BASE, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(93, 93, IOCFG_BR_BASE, 0x0060, 0x10, 18, 1), + PIN_FIELD_BASE(94, 94, IOCFG_BR_BASE, 0x0060, 0x10, 19, 1), + PIN_FIELD_BASE(95, 95, IOCFG_BR_BASE, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(96, 96, IOCFG_BR_BASE, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(104, 104, IOCFG_BR_BASE, 0x0060, 0x10, 22, 1), + PIN_FIELD_BASE(105, 105, IOCFG_BR_BASE, 0x0060, 0x10, 23, 1), + PIN_FIELD_BASE(106, 106, IOCFG_BR_BASE, 0x0060, 0x10, 20, 1), + PIN_FIELD_BASE(107, 107, IOCFG_BR_BASE, 0x0060, 0x10, 21, 1), + PIN_FIELD_BASE(110, 110, IOCFG_RB_BASE, 0x0020, 0x10, 1, 1), + PIN_FIELD_BASE(111, 111, IOCFG_RB_BASE, 0x0020, 0x10, 0, 1), + PIN_FIELD_BASE(112, 112, IOCFG_RB_BASE, 0x0020, 0x10, 2, 1), + PIN_FIELD_BASE(113, 113, IOCFG_RB_BASE, 0x0020, 0x10, 3, 1), + PIN_FIELD_BASE(114, 114, IOCFG_RB_BASE, 0x0020, 0x10, 4, 1), + PIN_FIELD_BASE(115, 115, IOCFG_RB_BASE, 0x0020, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, IOCFG_TL_BASE, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(117, 117, IOCFG_TL_BASE, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(118, 118, IOCFG_TL_BASE, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(119, 119, IOCFG_TL_BASE, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(120, 120, IOCFG_TL_BASE, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, IOCFG_TL_BASE, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(122, 122, IOCFG_TL_BASE, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, IOCFG_TL_BASE, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(124, 124, IOCFG_TL_BASE, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(125, 125, IOCFG_TL_BASE, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(126, 126, IOCFG_TL_BASE, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, IOCFG_TL_BASE, 0x0050, 0x10, 10, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_r0_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_LM_BASE, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, IOCFG_LM_BASE, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, IOCFG_LM_BASE, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(3, 3, IOCFG_LM_BASE, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LM_BASE, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(5, 5, IOCFG_LM_BASE, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(77, 77, IOCFG_BR_BASE, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(78, 78, IOCFG_BR_BASE, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(79, 79, IOCFG_BR_BASE, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(80, 80, IOCFG_BR_BASE, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(81, 81, IOCFG_BR_BASE, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(82, 82, IOCFG_BR_BASE, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(83, 83, IOCFG_BR_BASE, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(84, 84, IOCFG_BR_BASE, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(85, 85, IOCFG_BR_BASE, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(86, 86, IOCFG_BR_BASE, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(87, 87, IOCFG_BR_BASE, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(88, 88, IOCFG_BR_BASE, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(89, 89, IOCFG_BR_BASE, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(90, 90, IOCFG_BR_BASE, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(91, 91, IOCFG_BR_BASE, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(92, 92, IOCFG_BR_BASE, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(93, 93, IOCFG_BR_BASE, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(94, 94, IOCFG_BR_BASE, 0x0080, 0x10, 19, 1), + PIN_FIELD_BASE(95, 95, IOCFG_BR_BASE, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(96, 96, IOCFG_BR_BASE, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(104, 104, IOCFG_BR_BASE, 0x0080, 0x10, 22, 1), + PIN_FIELD_BASE(105, 105, IOCFG_BR_BASE, 0x0080, 0x10, 23, 1), + PIN_FIELD_BASE(106, 106, IOCFG_BR_BASE, 0x0080, 0x10, 20, 1), + PIN_FIELD_BASE(107, 107, IOCFG_BR_BASE, 0x0080, 0x10, 21, 1), + PIN_FIELD_BASE(110, 110, IOCFG_RB_BASE, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(111, 111, IOCFG_RB_BASE, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(112, 112, IOCFG_RB_BASE, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(113, 113, IOCFG_RB_BASE, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(114, 114, IOCFG_RB_BASE, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(115, 115, IOCFG_RB_BASE, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, IOCFG_TL_BASE, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(117, 117, IOCFG_TL_BASE, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(118, 118, IOCFG_TL_BASE, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(119, 119, IOCFG_TL_BASE, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(120, 120, IOCFG_TL_BASE, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, IOCFG_TL_BASE, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(122, 122, IOCFG_TL_BASE, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, IOCFG_TL_BASE, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(124, 124, IOCFG_TL_BASE, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(125, 125, IOCFG_TL_BASE, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(126, 126, IOCFG_TL_BASE, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, IOCFG_TL_BASE, 0x0070, 0x10, 10, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_r1_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_LM_BASE, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, IOCFG_LM_BASE, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, IOCFG_LM_BASE, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(3, 3, IOCFG_LM_BASE, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LM_BASE, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(5, 5, IOCFG_LM_BASE, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(77, 77, IOCFG_BR_BASE, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(78, 78, IOCFG_BR_BASE, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(79, 79, IOCFG_BR_BASE, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(80, 80, IOCFG_BR_BASE, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(81, 81, IOCFG_BR_BASE, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(82, 82, IOCFG_BR_BASE, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(83, 83, IOCFG_BR_BASE, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(84, 84, IOCFG_BR_BASE, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(85, 85, IOCFG_BR_BASE, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(86, 86, IOCFG_BR_BASE, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(87, 87, IOCFG_BR_BASE, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(88, 88, IOCFG_BR_BASE, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(89, 89, IOCFG_BR_BASE, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(90, 90, IOCFG_BR_BASE, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(91, 91, IOCFG_BR_BASE, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(92, 92, IOCFG_BR_BASE, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(93, 93, IOCFG_BR_BASE, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(94, 94, IOCFG_BR_BASE, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(95, 95, IOCFG_BR_BASE, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(96, 96, IOCFG_BR_BASE, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(104, 104, IOCFG_BR_BASE, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(105, 105, IOCFG_BR_BASE, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(106, 106, IOCFG_BR_BASE, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(107, 107, IOCFG_BR_BASE, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(110, 110, IOCFG_RB_BASE, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(111, 111, IOCFG_RB_BASE, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(112, 112, IOCFG_RB_BASE, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(113, 113, IOCFG_RB_BASE, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(114, 114, IOCFG_RB_BASE, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(115, 115, IOCFG_RB_BASE, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, IOCFG_TL_BASE, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(117, 117, IOCFG_TL_BASE, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(118, 118, IOCFG_TL_BASE, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(119, 119, IOCFG_TL_BASE, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(120, 120, IOCFG_TL_BASE, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, IOCFG_TL_BASE, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(122, 122, IOCFG_TL_BASE, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, IOCFG_TL_BASE, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(124, 124, IOCFG_TL_BASE, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(125, 125, IOCFG_TL_BASE, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(126, 126, IOCFG_TL_BASE, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, IOCFG_TL_BASE, 0x0080, 0x10, 10, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_drv_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_LM_BASE, 0x000, 0x10, 0, 3), + PIN_FIELD_BASE(1, 1, IOCFG_LM_BASE, 0x000, 0x10, 3, 3), + PIN_FIELD_BASE(2, 2, IOCFG_LM_BASE, 0x000, 0x10, 6, 3), + PIN_FIELD_BASE(3, 3, IOCFG_LM_BASE, 0x000, 0x10, 9, 3), + PIN_FIELD_BASE(4, 4, IOCFG_LM_BASE, 0x000, 0x10, 12, 3), + PIN_FIELD_BASE(5, 5, IOCFG_LM_BASE, 0x000, 0x10, 15, 3), + PINS_FIELD_BASE(6, 7, IOCFG_LM_BASE, 0x000, 0x10, 18, 3), + PIN_FIELD_BASE(8, 8, IOCFG_LM_BASE, 0x010, 0x10, 6, 3), + PIN_FIELD_BASE(9, 9, IOCFG_LM_BASE, 0x000, 0x10, 21, 3), + PIN_FIELD_BASE(10, 10, IOCFG_LM_BASE, 0x010, 0x10, 9, 3), + PIN_FIELD_BASE(11, 11, IOCFG_LM_BASE, 0x000, 0x10, 24, 3), + PIN_FIELD_BASE(12, 12, IOCFG_LM_BASE, 0x010, 0x10, 12, 3), + PIN_FIELD_BASE(13, 13, IOCFG_LM_BASE, 0x010, 0x10, 27, 3), + PIN_FIELD_BASE(14, 14, IOCFG_LM_BASE, 0x010, 0x10, 15, 3), + PIN_FIELD_BASE(15, 15, IOCFG_LM_BASE, 0x010, 0x10, 0, 3), + PIN_FIELD_BASE(16, 16, IOCFG_LM_BASE, 0x010, 0x10, 18, 3), + PIN_FIELD_BASE(17, 17, IOCFG_LM_BASE, 0x010, 0x10, 3, 3), + PIN_FIELD_BASE(18, 18, IOCFG_BL_BASE, 0x010, 0x10, 6, 3), + PIN_FIELD_BASE(19, 19, IOCFG_BL_BASE, 0x010, 0x10, 3, 3), + PIN_FIELD_BASE(20, 20, IOCFG_BL_BASE, 0x010, 0x10, 0, 3), + PIN_FIELD_BASE(21, 21, IOCFG_BL_BASE, 0x000, 0x10, 27, 3), + PIN_FIELD_BASE(22, 22, IOCFG_BL_BASE, 0x000, 0x10, 0, 3), + PIN_FIELD_BASE(23, 23, IOCFG_BL_BASE, 0x000, 0x10, 3, 3), + PIN_FIELD_BASE(24, 24, IOCFG_BL_BASE, 0x000, 0x10, 6, 3), + PIN_FIELD_BASE(25, 25, IOCFG_BL_BASE, 0x000, 0x10, 12, 3), + PIN_FIELD_BASE(26, 26, IOCFG_BL_BASE, 0x000, 0x10, 9, 3), + PIN_FIELD_BASE(27, 27, IOCFG_BL_BASE, 0x000, 0x10, 15, 3), + PIN_FIELD_BASE(28, 28, IOCFG_BL_BASE, 0x000, 0x10, 18, 3), + PIN_FIELD_BASE(29, 29, IOCFG_BL_BASE, 0x000, 0x10, 21, 3), + PIN_FIELD_BASE(30, 30, IOCFG_BL_BASE, 0x000, 0x10, 24, 3), + PINS_FIELD_BASE(31, 33, IOCFG_BM_BASE, 0x010, 0x10, 0, 3), + PIN_FIELD_BASE(34, 34, IOCFG_BM_BASE, 0x000, 0x10, 21, 3), + PIN_FIELD_BASE(35, 35, IOCFG_BM_BASE, 0x000, 0x10, 24, 3), + PIN_FIELD_BASE(36, 36, IOCFG_BM_BASE, 0x010, 0x10, 0, 3), + PIN_FIELD_BASE(37, 37, IOCFG_BM_BASE, 0x010, 0x10, 21, 3), + PINS_FIELD_BASE(38, 39, IOCFG_BM_BASE, 0x010, 0x10, 3, 3), + PIN_FIELD_BASE(40, 40, IOCFG_BM_BASE, 0x010, 0x10, 27, 3), + PIN_FIELD_BASE(41, 41, IOCFG_BM_BASE, 0x010, 0x10, 24, 3), + PIN_FIELD_BASE(42, 42, IOCFG_BM_BASE, 0x020, 0x10, 3, 3), + PIN_FIELD_BASE(43, 43, IOCFG_BM_BASE, 0x020, 0x10, 0, 3), + PIN_FIELD_BASE(44, 44, IOCFG_BM_BASE, 0x030, 0x10, 0, 3), + PIN_FIELD_BASE(45, 45, IOCFG_BM_BASE, 0x030, 0x10, 3, 3), + PINS_FIELD_BASE(46, 47, IOCFG_BM_BASE, 0x010, 0x10, 3, 3), + PINS_FIELD_BASE(48, 51, IOCFG_BM_BASE, 0x010, 0x10, 6, 3), + PINS_FIELD_BASE(52, 55, IOCFG_BM_BASE, 0x010, 0x10, 9, 3), + PINS_FIELD_BASE(56, 59, IOCFG_BM_BASE, 0x010, 0x10, 12, 3), + PINS_FIELD_BASE(60, 63, IOCFG_BM_BASE, 0x010, 0x10, 15, 3), + PIN_FIELD_BASE(64, 64, IOCFG_BM_BASE, 0x010, 0x10, 18, 3), + PINS_FIELD_BASE(65, 68, IOCFG_BM_BASE, 0x000, 0x10, 27, 3), + PIN_FIELD_BASE(69, 69, IOCFG_BM_BASE, 0x000, 0x10, 0, 3), + PIN_FIELD_BASE(70, 70, IOCFG_BM_BASE, 0x000, 0x10, 18, 3), + PIN_FIELD_BASE(71, 71, IOCFG_BM_BASE, 0x000, 0x10, 12, 3), + PIN_FIELD_BASE(72, 72, IOCFG_BM_BASE, 0x000, 0x10, 15, 3), + PIN_FIELD_BASE(73, 73, IOCFG_BM_BASE, 0x000, 0x10, 3, 3), + PIN_FIELD_BASE(74, 74, IOCFG_BM_BASE, 0x000, 0x10, 6, 3), + PIN_FIELD_BASE(75, 75, IOCFG_BM_BASE, 0x000, 0x10, 9, 3), + PIN_FIELD_BASE(76, 76, IOCFG_BM_BASE, 0x010, 0x10, 18, 3), + PIN_FIELD_BASE(77, 77, IOCFG_BR_BASE, 0x000, 0x10, 0, 3), + PIN_FIELD_BASE(78, 78, IOCFG_BR_BASE, 0x000, 0x10, 15, 3), + PIN_FIELD_BASE(79, 79, IOCFG_BR_BASE, 0x000, 0x10, 18, 3), + PIN_FIELD_BASE(80, 80, IOCFG_BR_BASE, 0x000, 0x10, 21, 3), + PIN_FIELD_BASE(81, 81, IOCFG_BR_BASE, 0x000, 0x10, 28, 3), + PIN_FIELD_BASE(82, 82, IOCFG_BR_BASE, 0x000, 0x10, 27, 3), + PIN_FIELD_BASE(83, 83, IOCFG_BR_BASE, 0x010, 0x10, 0, 3), + PIN_FIELD_BASE(84, 84, IOCFG_BR_BASE, 0x010, 0x10, 3, 3), + PINS_FIELD_BASE(85, 88, IOCFG_BR_BASE, 0x010, 0x10, 15, 3), + PIN_FIELD_BASE(89, 89, IOCFG_BR_BASE, 0x000, 0x10, 3, 3), + PIN_FIELD_BASE(90, 90, IOCFG_BR_BASE, 0x000, 0x10, 6, 3), + PIN_FIELD_BASE(91, 91, IOCFG_BR_BASE, 0x000, 0x10, 9, 3), + PIN_FIELD_BASE(92, 92, IOCFG_BR_BASE, 0x000, 0x10, 12, 3), + PIN_FIELD_BASE(93, 93, IOCFG_BR_BASE, 0x010, 0x10, 6, 3), + PIN_FIELD_BASE(94, 94, IOCFG_BR_BASE, 0x010, 0x10, 9, 3), + PINS_FIELD_BASE(95, 98, IOCFG_BR_BASE, 0x010, 0x10, 18, 3), + PINS_FIELD_BASE(99, 102, IOCFG_BR_BASE, 0x010, 0x10, 21, 3), + PINS_FIELD_BASE(103, 104, IOCFG_BR_BASE, 0x010, 0x10, 24, 3), + PIN_FIELD_BASE(105, 105, IOCFG_BR_BASE, 0x010, 0x10, 27, 3), + PINS_FIELD_BASE(106, 107, IOCFG_BR_BASE, 0x010, 0x10, 24, 3), + PINS_FIELD_BASE(108, 109, IOCFG_BR_BASE, 0x010, 0x10, 27, 3), + PIN_FIELD_BASE(110, 110, IOCFG_RB_BASE, 0x000, 0x10, 3, 3), + PIN_FIELD_BASE(111, 111, IOCFG_RB_BASE, 0x000, 0x10, 0, 3), + PIN_FIELD_BASE(112, 112, IOCFG_RB_BASE, 0x000, 0x10, 6, 3), + PIN_FIELD_BASE(113, 113, IOCFG_RB_BASE, 0x000, 0x10, 9, 3), + PIN_FIELD_BASE(114, 114, IOCFG_RB_BASE, 0x000, 0x10, 12, 3), + PIN_FIELD_BASE(115, 115, IOCFG_RB_BASE, 0x000, 0x10, 15, 3), + PIN_FIELD_BASE(116, 116, IOCFG_TL_BASE, 0x000, 0x10, 27, 3), + PIN_FIELD_BASE(117, 117, IOCFG_TL_BASE, 0x000, 0x10, 24, 3), + PIN_FIELD_BASE(118, 118, IOCFG_TL_BASE, 0x000, 0x10, 21, 3), + PIN_FIELD_BASE(119, 119, IOCFG_TL_BASE, 0x000, 0x10, 18, 3), + PIN_FIELD_BASE(120, 120, IOCFG_TL_BASE, 0x010, 0x10, 3, 3), + PIN_FIELD_BASE(121, 121, IOCFG_TL_BASE, 0x000, 0x10, 3, 3), + PIN_FIELD_BASE(122, 122, IOCFG_TL_BASE, 0x000, 0x10, 0, 3), + PIN_FIELD_BASE(123, 123, IOCFG_TL_BASE, 0x000, 0x10, 15, 3), + PIN_FIELD_BASE(124, 124, IOCFG_TL_BASE, 0x000, 0x10, 12, 3), + PIN_FIELD_BASE(125, 125, IOCFG_TL_BASE, 0x000, 0x10, 9, 3), + PIN_FIELD_BASE(126, 126, IOCFG_TL_BASE, 0x000, 0x10, 6, 3), + PIN_FIELD_BASE(127, 127, IOCFG_TL_BASE, 0x010, 0x10, 0, 3), + PIN_FIELD_BASE(128, 128, IOCFG_BR_BASE, 0x010, 0x10, 27, 3), + PINS_FIELD_BASE(129, 130, IOCFG_BR_BASE, 0x020, 0x10, 0, 3), + PINS_FIELD_BASE(131, 131, IOCFG_BR_BASE, 0x010, 0x10, 12, 3), + PIN_FIELD_BASE(132, 132, IOCFG_TL_BASE, 0x010, 0x10, 9, 3), + PIN_FIELD_BASE(133, 133, IOCFG_TL_BASE, 0x010, 0x10, 6, 3), + PIN_FIELD_BASE(134, 134, IOCFG_TL_BASE, 0x010, 0x10, 15, 3), + PIN_FIELD_BASE(135, 135, IOCFG_TL_BASE, 0x010, 0x10, 12, 3), + PIN_FIELD_BASE(136, 136, IOCFG_BM_BASE, 0x020, 0x10, 9, 3), + PIN_FIELD_BASE(137, 137, IOCFG_BM_BASE, 0x020, 0x10, 6, 3), + PIN_FIELD_BASE(138, 138, IOCFG_BM_BASE, 0x020, 0x10, 15, 3), + PIN_FIELD_BASE(139, 139, IOCFG_BM_BASE, 0x020, 0x10, 12, 3), + PIN_FIELD_BASE(140, 140, IOCFG_BM_BASE, 0x020, 0x10, 21, 3), + PIN_FIELD_BASE(141, 141, IOCFG_BM_BASE, 0x020, 0x10, 18, 3), + PIN_FIELD_BASE(142, 142, IOCFG_BM_BASE, 0x020, 0x10, 27, 3), + PIN_FIELD_BASE(143, 143, IOCFG_BM_BASE, 0x020, 0x10, 24, 3), +}; + +static const struct mtk_pin_reg_calc mt8195_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8195_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8195_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8195_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8195_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8195_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8195_pin_ies_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8195_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8195_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8195_pin_drv_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8195_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8195_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8195_pin_r1_range), +}; + +static const struct mtk_pin_desc mt8195_pins[] = { + MT8195_TYPE1_PIN(0, "GPIO_00"), + MT8195_TYPE1_PIN(1, "GPIO_01"), + MT8195_TYPE1_PIN(2, "GPIO_02"), + MT8195_TYPE1_PIN(3, "GPIO_03"), + MT8195_TYPE1_PIN(4, "GPIO_04"), + MT8195_TYPE1_PIN(5, "GPIO_05"), + MT8195_TYPE0_PIN(6, "GPIO_06"), + MT8195_TYPE0_PIN(7, "GPIO_07"), + MT8195_TYPE0_PIN(8, "SDA0"), + MT8195_TYPE0_PIN(9, "SCL0"), + MT8195_TYPE0_PIN(10, "SDA1"), + MT8195_TYPE0_PIN(11, "SCL1"), + MT8195_TYPE0_PIN(12, "SDA2"), + MT8195_TYPE0_PIN(13, "SCL2"), + MT8195_TYPE0_PIN(14, "SDA3"), + MT8195_TYPE0_PIN(15, "SCL3"), + MT8195_TYPE0_PIN(16, "SDA4"), + MT8195_TYPE0_PIN(17, "SCL4"), + MT8195_TYPE0_PIN(18, "DPTX_HPD"), + MT8195_TYPE0_PIN(19, "PCIE_WAKE_N"), + MT8195_TYPE0_PIN(20, "PCIE_PERESET_N"), + MT8195_TYPE0_PIN(21, "PCIE_CLKREQ_N"), + MT8195_TYPE0_PIN(22, "CMMCLK0"), + MT8195_TYPE0_PIN(23, "CMMCLK1"), + MT8195_TYPE0_PIN(24, "CMMCLK2"), + MT8195_TYPE0_PIN(25, "CMMRST"), + MT8195_TYPE0_PIN(26, "CMMPDN"), + MT8195_TYPE0_PIN(27, "HDMIRX_HTPLG"), + MT8195_TYPE0_PIN(28, "HDMIRX_PWR5V"), + MT8195_TYPE0_PIN(29, "HDMIRX_SCL"), + MT8195_TYPE0_PIN(30, "HDMIRX_SDA"), + MT8195_TYPE0_PIN(31, "HDMITX_PWR5V"), + MT8195_TYPE0_PIN(32, "HDMITX_HTPLG"), + MT8195_TYPE0_PIN(33, "HDMITX_CEC"), + MT8195_TYPE0_PIN(34, "HDMITX_SCL"), + MT8195_TYPE0_PIN(35, "HDMITX_SDA"), + MT8195_TYPE0_PIN(36, "PMIC_RTC32K_CK"), + MT8195_TYPE0_PIN(37, "PMIC_WATCHDOG"), + MT8195_TYPE0_PIN(38, "PMIC_SRCLKEN_IN0"), + MT8195_TYPE0_PIN(39, "PMIC_SRCLKEN_IN1"), + MT8195_TYPE0_PIN(40, "PWRAP_SPI_CSN"), + MT8195_TYPE0_PIN(41, "PWRAP_SPI_CK"), + MT8195_TYPE0_PIN(42, "PWRAP_SPI_MO"), + MT8195_TYPE0_PIN(43, "PWRAP_SPI_MI"), + MT8195_TYPE0_PIN(44, "SPMI_M_SCL"), + MT8195_TYPE0_PIN(45, "SPMI_M_SDA"), + MT8195_TYPE0_PIN(46, "I2SIN_MCK"), + MT8195_TYPE0_PIN(47, "I2SIN_BCK"), + MT8195_TYPE0_PIN(48, "I2SIN_WS"), + MT8195_TYPE0_PIN(49, "I2SIN_D0"), + MT8195_TYPE0_PIN(50, "I2SO1_MCK"), + MT8195_TYPE0_PIN(51, "I2SO1_BCK"), + MT8195_TYPE0_PIN(52, "I2SO1_WS"), + MT8195_TYPE0_PIN(53, "I2SO1_D0"), + MT8195_TYPE0_PIN(54, "I2SO1_D1"), + MT8195_TYPE0_PIN(55, "I2SO1_D2"), + MT8195_TYPE0_PIN(56, "I2SO1_D3"), + MT8195_TYPE0_PIN(57, "I2SO2_MCK"), + MT8195_TYPE0_PIN(58, "I2SO2_BCK"), + MT8195_TYPE0_PIN(59, "I2SO2_WS"), + MT8195_TYPE0_PIN(60, "I2SO2_D0"), + MT8195_TYPE0_PIN(61, "DMIC1_SCK"), + MT8195_TYPE0_PIN(62, "DMIC1_DAT"), + MT8195_TYPE0_PIN(63, "DMIC2_SCK"), + MT8195_TYPE0_PIN(64, "DMIC2_DAT"), + MT8195_TYPE0_PIN(65, "PCM_DO"), + MT8195_TYPE0_PIN(66, "PCM_CLK"), + MT8195_TYPE0_PIN(67, "PCM_DI"), + MT8195_TYPE0_PIN(68, "PCM_SYNC"), + MT8195_TYPE0_PIN(69, "AUD_CLK_MOSI"), + MT8195_TYPE0_PIN(70, "AUD_SYNC_MOSI"), + MT8195_TYPE0_PIN(71, "AUD_DAT_MOSI0"), + MT8195_TYPE0_PIN(72, "AUD_DAT_MOSI1"), + MT8195_TYPE0_PIN(73, "AUD_DAT_MISO0"), + MT8195_TYPE0_PIN(74, "AUD_DAT_MISO1"), + MT8195_TYPE0_PIN(75, "AUD_DAT_MISO2"), + MT8195_TYPE0_PIN(76, "SCP_VREQ_VAO"), + MT8195_TYPE1_PIN(77, "DGI_D0"), + MT8195_TYPE1_PIN(78, "DGI_D1"), + MT8195_TYPE1_PIN(79, "DGI_D2"), + MT8195_TYPE1_PIN(80, "DGI_D3"), + MT8195_TYPE1_PIN(81, "DGI_D4"), + MT8195_TYPE1_PIN(82, "DGI_D5"), + MT8195_TYPE1_PIN(83, "DGI_D6"), + MT8195_TYPE1_PIN(84, "DGI_D7"), + MT8195_TYPE1_PIN(85, "DGI_D8"), + MT8195_TYPE1_PIN(86, "DGI_D9"), + MT8195_TYPE1_PIN(87, "DGI_D10"), + MT8195_TYPE1_PIN(88, "DGI_D11"), + MT8195_TYPE1_PIN(89, "DGI_D12"), + MT8195_TYPE1_PIN(90, "DGI_D13"), + MT8195_TYPE1_PIN(91, "DGI_D14"), + MT8195_TYPE1_PIN(92, "DGI_D15"), + MT8195_TYPE1_PIN(93, "DGI_HSYNC"), + MT8195_TYPE1_PIN(94, "DGI_VSYNC"), + MT8195_TYPE1_PIN(95, "DGI_DE"), + MT8195_TYPE1_PIN(96, "DGI_CK"), + MT8195_TYPE0_PIN(97, "DISP_PWM0"), + MT8195_TYPE0_PIN(98, "UART0_TXD"), + MT8195_TYPE0_PIN(99, "UART0_RXD"), + MT8195_TYPE0_PIN(100, "UART1_RTS"), + MT8195_TYPE0_PIN(101, "UART1_CTS"), + MT8195_TYPE0_PIN(102, "UART1_TXD"), + MT8195_TYPE0_PIN(103, "UART1_RXD"), + MT8195_TYPE1_PIN(104, "KPROW0"), + MT8195_TYPE1_PIN(105, "KPROW1"), + MT8195_TYPE1_PIN(106, "KPCOL0"), + MT8195_TYPE1_PIN(107, "KPCOL1"), + MT8195_TYPE0_PIN(108, "DSI_LCM_RST"), + MT8195_TYPE0_PIN(109, "DSI_DSI_TE"), + MT8195_TYPE1_PIN(110, "MSDC1_CMD"), + MT8195_TYPE1_PIN(111, "MSDC1_CLK"), + MT8195_TYPE1_PIN(112, "MSDC1_DAT0"), + MT8195_TYPE1_PIN(113, "MSDC1_DAT1"), + MT8195_TYPE1_PIN(114, "MSDC1_DAT2"), + MT8195_TYPE1_PIN(115, "MSDC1_DAT3"), + MT8195_TYPE1_PIN(116, "EMMC_DAT7"), + MT8195_TYPE1_PIN(117, "EMMC_DAT6"), + MT8195_TYPE1_PIN(118, "EMMC_DAT5"), + MT8195_TYPE1_PIN(119, "EMMC_DAT4"), + MT8195_TYPE1_PIN(120, "EMMC_RSTB"), + MT8195_TYPE1_PIN(121, "EMMC_CMD"), + MT8195_TYPE1_PIN(122, "EMMC_CLK"), + MT8195_TYPE1_PIN(123, "EMMC_DAT3"), + MT8195_TYPE1_PIN(124, "EMMC_DAT2"), + MT8195_TYPE1_PIN(125, "EMMC_DAT1"), + MT8195_TYPE1_PIN(126, "EMMC_DAT0"), + MT8195_TYPE1_PIN(127, "EMMC_DSL"), + MT8195_TYPE0_PIN(128, "USB_IDDIG"), + MT8195_TYPE0_PIN(129, "USB_DRV_VBUS"), + MT8195_TYPE0_PIN(130, "USB_IDDIG_1P"), + MT8195_TYPE0_PIN(131, "USB_DRV_VBUS_1P"), + MT8195_TYPE0_PIN(132, "SPIM0_CSB"), + MT8195_TYPE0_PIN(133, "SPIM0_CLK"), + MT8195_TYPE0_PIN(134, "SPIM0_MO"), + MT8195_TYPE0_PIN(135, "SPIM0_MI"), + MT8195_TYPE0_PIN(136, "SPIM1_CSB"), + MT8195_TYPE0_PIN(137, "SPIM1_CLK"), + MT8195_TYPE0_PIN(138, "SPIM1_MO"), + MT8195_TYPE0_PIN(139, "SPIM1_MI"), + MT8195_TYPE0_PIN(140, "SPIM2_CSB"), + MT8195_TYPE0_PIN(141, "SPIM2_CLK"), + MT8195_TYPE0_PIN(142, "SPIM2_MO"), + MT8195_TYPE0_PIN(143, "SPIM2_MI"), +}; + +static const struct mtk_io_type_desc mt8195_io_type_desc[] = { + [IO_TYPE_GRP0] = { + .name = "mt8195", + .bias_set = mtk_pinconf_bias_set_pu_pd, + .drive_set = mtk_pinconf_drive_set_v1, + .input_enable = mtk_pinconf_input_enable_v1, + }, + [IO_TYPE_GRP1] = { + .name = "MSDC", + .bias_set = mtk_pinconf_bias_set_pupd_r1_r0, + .drive_set = mtk_pinconf_drive_set_v1, + .input_enable = mtk_pinconf_input_enable_v1, + }, +}; + +/* List all groups consisting of these pins dedicated to the enablement of + * certain hardware block and the corresponding mode for all of the pins. + * The hardware probably has multiple combinations of these pinouts. + */ + +/* UART0_0_RXD_TXD */ +static int mt8195_uart0_0_rxd_txd_pins[] = { 99, 98 }; +static int mt8195_uart0_0_rxd_txd_funcs[] = { 1, 1 }; +/* UART1_0 */ +static int mt8195_uart1_0_pins[] = { 103, 102 }; +static int mt8195_uart1_0_funcs[] = { 1, 1 }; +/* MSDC0 */ +static int mt8195_msdc0_pins[] = { 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126 }; +static int mt8195_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; +/* i2c0 */ +static int mt8195_i2c0_pins[] = { 8, 9 }; +static int mt8195_i2c0_funcs[] = { 1, 1 }; +/* i2c1 */ +static int mt8195_i2c1_pins[] = {10, 11 }; +static int mt8195_i2c1_funcs[] = { 1, 1 }; +/* i2c2 */ +static int mt8195_i2c2_pins[] = { 12, 13 }; +static int mt8195_i2c2_funcs[] = { 1, 1 }; +/* i2c3 */ +static int mt8195_i2c3_pins[] = { 14, 15 }; +static int mt8195_i2c3_funcs[] = { 1, 1 }; +/* i2c4 */ +static int mt8195_i2c4_pins[] = { 16, 17 }; +static int mt8195_i2c4_funcs[] = { 1, 1 }; +/* i2c5 */ +static int mt8195_i2c5_pins[] = { 30, 29 }; +static int mt8195_i2c5_funcs[] = { 3, 3 }; +/* i2c6 */ +static int mt8195_i2c6_pins[] = { 25, 26 }; +static int mt8195_i2c6_funcs[] = { 4, 4 }; +/* spi0 */ +static int mt8195_spi0_pins[] = { 132, 133, 134, 135 }; +static int mt8195_spi0_funcs[] = { 1, 1, 1, 1 }; +/* spi1 */ +static int mt8195_spi1_pins[] = { 136, 137, 138, 139 }; +static int mt8195_spi1_funcs[] = { 1, 1, 1, 1 }; +/* spi2 */ +static int mt8195_spi2_pins[] = { 140, 141, 142, 143 }; +static int mt8195_spi2_funcs[] = { 1, 1, 1, 1 }; + +static const struct mtk_group_desc mt8195_groups[] = { + PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8195_uart0_0_rxd_txd), + PINCTRL_PIN_GROUP("uart1_0", mt8195_uart1_0), + PINCTRL_PIN_GROUP("msdc0", mt8195_msdc0), + PINCTRL_PIN_GROUP("i2c0", mt8195_i2c0), + PINCTRL_PIN_GROUP("i2c1", mt8195_i2c1), + PINCTRL_PIN_GROUP("i2c2", mt8195_i2c2), + PINCTRL_PIN_GROUP("i2c3", mt8195_i2c3), + PINCTRL_PIN_GROUP("i2c4", mt8195_i2c4), + PINCTRL_PIN_GROUP("i2c5", mt8195_i2c5), + PINCTRL_PIN_GROUP("i2c6", mt8195_i2c6), + PINCTRL_PIN_GROUP("spi0", mt8195_spi0), + PINCTRL_PIN_GROUP("spi1", mt8195_spi1), + PINCTRL_PIN_GROUP("spi2", mt8195_spi2), +}; + +static const char *const mt8195_uart_groups[] = { + "uart0_0_rxd_txd", "uart1_0", +}; + +static const char *const mt8195_msdc_groups[] = { + "msdc0", +}; + +static const char *const mt8195_i2c_groups[] = { + "i2c0", "i2c1", "i2c2", "i2c3", "i2c4", "i2c5", "i2c6" +}; + +static const char *const mt8195_spi_groups[] = { + "spi0", "spi1", "spi2", +}; + +static const struct mtk_function_desc mt8195_functions[] = { + { "uart", mt8195_uart_groups, ARRAY_SIZE(mt8195_uart_groups) }, + { "msdc", mt8195_msdc_groups, ARRAY_SIZE(mt8195_msdc_groups) }, + { "i2c", mt8195_i2c_groups, ARRAY_SIZE(mt8195_i2c_groups) }, + { "spi", mt8195_spi_groups, ARRAY_SIZE(mt8195_spi_groups) }, +}; + +static struct mtk_pinctrl_soc mt8195_data = { + .name = "mt8195_pinctrl", + .reg_cal = mt8195_reg_cals, + .pins = mt8195_pins, + .npins = ARRAY_SIZE(mt8195_pins), + .grps = mt8195_groups, + .ngrps = ARRAY_SIZE(mt8195_groups), + .funcs = mt8195_functions, + .nfuncs = ARRAY_SIZE(mt8195_functions), + .io_type = mt8195_io_type_desc, + .ntype = ARRAY_SIZE(mt8195_io_type_desc), + .base_names = mt8195_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt8195_pinctrl_register_base_names), + .base_calc = 1, + .rev = MTK_PINCTRL_V1, +}; + +static int mtk_pinctrl_mt8195_probe(struct udevice *dev) +{ + return mtk_pinctrl_common_probe(dev, &mt8195_data); +} + +static const struct udevice_id mt8195_pctrl_match[] = { + { .compatible = "mediatek,mt8195-pinctrl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mt8195_pinctrl) = { + .name = "mt8195_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = mt8195_pctrl_match, + .ops = &mtk_pinctrl_ops, + .bind = mtk_pinctrl_common_bind, + .probe = mtk_pinctrl_mt8195_probe, + .priv_auto = sizeof(struct mtk_pinctrl_priv), +}; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c index a6985e48858..0ce99b92a9f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c @@ -596,6 +596,7 @@ U_BOOT_DRIVER(mt8365_pinctrl) = { .id = UCLASS_PINCTRL, .of_match = mt8365_pctrl_match, .ops = &mtk_pinctrl_ops, + .bind = mtk_pinctrl_common_bind, .probe = mtk_pinctrl_mt8365_probe, .priv_auto = sizeof(struct mtk_pinctrl_priv), }; diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index e991e03ea41..d152e216634 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -856,6 +856,9 @@ int mtk_pinctrl_common_probe(struct udevice *dev, if (!base_calc) nbase_names = 1; + if (nbase_names > MAX_BASE_CALC) + return -ENOSPC; + for (i = 0; i < nbase_names; i++) { if (soc->base_names) addr = dev_read_addr_name(dev, soc->base_names[i]); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h index 15ab3c1bf07..58f13613633 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -9,7 +9,7 @@ #define MTK_PINCTRL_V0 0x0 #define MTK_PINCTRL_V1 0x1 #define BASE_CALC_NONE 0 -#define MAX_BASE_CALC 10 +#define MAX_BASE_CALC 15 #define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), } diff --git a/drivers/pinctrl/mtmips/pinctrl-mt7628.c b/drivers/pinctrl/mtmips/pinctrl-mt7628.c index dc7acec4a77..be3a28eb94d 100644 --- a/drivers/pinctrl/mtmips/pinctrl-mt7628.c +++ b/drivers/pinctrl/mtmips/pinctrl-mt7628.c @@ -6,15 +6,12 @@ */ #include <dm.h> -#include <asm/global_data.h> #include <dm/pinctrl.h> #include <linux/bitops.h> #include <linux/io.h> #include "pinctrl-mtmips-common.h" -DECLARE_GLOBAL_DATA_PTR; - #define AGPIO_OFS 0 #define GPIOMODE1_OFS 0x24 #define GPIOMODE2_OFS 0x28 diff --git a/drivers/pinctrl/nexell/pinctrl-nexell.c b/drivers/pinctrl/nexell/pinctrl-nexell.c index d5be7baf50d..af1acd91649 100644 --- a/drivers/pinctrl/nexell/pinctrl-nexell.c +++ b/drivers/pinctrl/nexell/pinctrl-nexell.c @@ -7,13 +7,10 @@ #include <dm.h> #include <errno.h> -#include <asm/global_data.h> #include <asm/io.h> #include "pinctrl-nexell.h" #include "pinctrl-s5pxx18.h" -DECLARE_GLOBAL_DATA_PTR; - /* given a pin-name, return the address of pin config registers */ unsigned long pin_to_bank_base(struct udevice *dev, const char *pin_name, u32 *pin) diff --git a/drivers/pinctrl/nexell/pinctrl-s5pxx18.c b/drivers/pinctrl/nexell/pinctrl-s5pxx18.c index a6ae5764fbc..aeed3f1e1e1 100644 --- a/drivers/pinctrl/nexell/pinctrl-s5pxx18.c +++ b/drivers/pinctrl/nexell/pinctrl-s5pxx18.c @@ -9,15 +9,12 @@ #include <dm.h> #include <errno.h> -#include <asm/global_data.h> #include <asm/io.h> #include <dm/pinctrl.h> #include <dm/root.h> #include "pinctrl-nexell.h" #include "pinctrl-s5pxx18.h" -DECLARE_GLOBAL_DATA_PTR; - static void nx_gpio_set_bit(u32 *value, u32 bit, int enable) { register u32 newvalue; diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig index 84d9a3641ff..b2a19557a27 100644 --- a/drivers/pinctrl/nxp/Kconfig +++ b/drivers/pinctrl/nxp/Kconfig @@ -103,13 +103,13 @@ config PINCTRL_IMX8M registers. config PINCTRL_IMX93 - bool "IMX8M pinctrl driver" + bool "IMX93/1 pinctrl driver" depends on ARCH_IMX9 && PINCTRL_FULL select PINCTRL_IMX_MMIO help - Say Y here to enable the imx8m pinctrl driver + Say Y here to enable the imx9[3,1] pinctrl driver - This provides a simple pinctrl driver for i.MX8M SoC familiy. + This provides a simple pinctrl driver for i.MX9[3,1] SoC. This feature depends on device tree configuration. This driver is different from the linux one, this is a simple implementation, only parses the 'fsl,pins' property and configure related diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile index 7d861ae52c1..7f1cc5a182f 100644 --- a/drivers/pinctrl/nxp/Makefile +++ b/drivers/pinctrl/nxp/Makefile @@ -7,7 +7,7 @@ obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o obj-$(CONFIG_PINCTRL_IMX8ULP) += pinctrl-imx8ulp.o obj-$(CONFIG_PINCTRL_IMX8) += pinctrl-imx8.o obj-$(CONFIG_PINCTRL_IMX8M) += pinctrl-imx8m.o -obj-$(CONFIG_PINCTRL_IMX93) += pinctrl-imx93.o +obj-$(CONFIG_PINCTRL_IMX93) += pinctrl-imx9.o obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_VYBRID) += pinctrl-vf610.o obj-$(CONFIG_PINCTRL_IMXRT) += pinctrl-imxrt.o diff --git a/drivers/pinctrl/nxp/pinctrl-imx-mmio.c b/drivers/pinctrl/nxp/pinctrl-imx-mmio.c index 2f4228a9fc5..7cdbbbba747 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx-mmio.c +++ b/drivers/pinctrl/nxp/pinctrl-imx-mmio.c @@ -5,7 +5,6 @@ #include <malloc.h> #include <mapmem.h> -#include <asm/global_data.h> #include <dm/device_compat.h> #include <dm/devres.h> #include <linux/bitops.h> @@ -16,8 +15,6 @@ #include "pinctrl-imx.h" -DECLARE_GLOBAL_DATA_PTR; - int imx_pinctrl_set_state_mmio(struct udevice *dev, struct udevice *config) { struct imx_pinctrl_priv *priv = dev_get_priv(dev); diff --git a/drivers/pinctrl/nxp/pinctrl-imx-scmi.c b/drivers/pinctrl/nxp/pinctrl-imx-scmi.c index 781835c6852..dcd76fdc571 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx-scmi.c +++ b/drivers/pinctrl/nxp/pinctrl-imx-scmi.c @@ -17,6 +17,7 @@ #define DAISY_OFFSET_IMX95 0x408 #define DAISY_OFFSET_IMX94 0x608 +#define DAISY_OFFSET_IMX952 0x460 /* SCMI pin control types */ #define PINCTRL_TYPE_MUX 192 @@ -69,7 +70,7 @@ static int imx_pinconf_scmi_set(struct udevice *dev, u32 mux_ofs, u32 mux, u32 c in.attributes = num_cfgs << PINCTRL_NUM_CFGS_SHIFT; msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_PINCTRL, - SCMI_MSG_PINCTRL_CONFIG_SET, in, out); + SCMI_PINCTRL_SETTINGS_CONFIGURE, in, out); ret = devm_scmi_process_msg(dev, &msg); if (ret || out.status) { @@ -136,6 +137,8 @@ static int imx_scmi_pinctrl_probe(struct udevice *dev) priv->daisy_offset = DAISY_OFFSET_IMX95; else if (IS_ENABLED(CONFIG_IMX94)) priv->daisy_offset = DAISY_OFFSET_IMX94; + else if (IS_ENABLED(CONFIG_IMX952)) + priv->daisy_offset = DAISY_OFFSET_IMX952; else return -EINVAL; @@ -144,7 +147,8 @@ static int imx_scmi_pinctrl_probe(struct udevice *dev) static int imx_scmi_pinctrl_bind(struct udevice *dev) { - if (IS_ENABLED(CONFIG_IMX95) || IS_ENABLED(CONFIG_IMX94)) + if (IS_ENABLED(CONFIG_IMX95) || IS_ENABLED(CONFIG_IMX94) || + IS_ENABLED(CONFIG_IMX952)) return 0; return -ENODEV; diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c index 7d91ccfb26f..d8011768581 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx.c +++ b/drivers/pinctrl/nxp/pinctrl-imx.c @@ -5,7 +5,6 @@ #include <malloc.h> #include <mapmem.h> -#include <asm/global_data.h> #include <dm/device_compat.h> #include <dm/devres.h> #include <linux/bitops.h> @@ -16,8 +15,6 @@ #include "pinctrl-imx.h" -DECLARE_GLOBAL_DATA_PTR; - int imx_pinctrl_set_state_common(struct udevice *dev, struct udevice *config, int pin_size, u32 **pin_data, int *npins) { diff --git a/drivers/pinctrl/nxp/pinctrl-imx.h b/drivers/pinctrl/nxp/pinctrl-imx.h index 9adf999d3bb..569bb869abd 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx.h +++ b/drivers/pinctrl/nxp/pinctrl-imx.h @@ -6,6 +6,14 @@ #ifndef __DRIVERS_PINCTRL_IMX_H #define __DRIVERS_PINCTRL_IMX_H +#define PINCTRL_PIN(a, b) { .number = a, .name = b } +#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) + +struct imx_pinctrl_pin_desc { + unsigned int number; + const char *name; +}; + /** * @base: the address to the controller in virtual memory * @input_sel_base: the address of the select input in virtual memory. diff --git a/drivers/pinctrl/nxp/pinctrl-imx8.c b/drivers/pinctrl/nxp/pinctrl-imx8.c index 9b3b5aec07a..23865ee6428 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx8.c +++ b/drivers/pinctrl/nxp/pinctrl-imx8.c @@ -9,14 +9,11 @@ #include <asm/io.h> #include <firmware/imx/sci/sci.h> #include <misc.h> -#include <asm/global_data.h> #include <dm/device.h> #include <dm/pinctrl.h> #include "pinctrl-imx.h" -DECLARE_GLOBAL_DATA_PTR; - #define PADRING_IFMUX_EN_SHIFT 31 #define PADRING_IFMUX_EN_MASK BIT(31) #define PADRING_GP_EN_SHIFT 30 diff --git a/drivers/pinctrl/nxp/pinctrl-imx8m.c b/drivers/pinctrl/nxp/pinctrl-imx8m.c index d9c63b3aca6..6eec1a277b3 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx8m.c +++ b/drivers/pinctrl/nxp/pinctrl-imx8m.c @@ -4,21 +4,83 @@ */ #include <dm/device.h> +#include <dm/device_compat.h> #include <dm/pinctrl.h> +#include <linux/bitops.h> +#include <linux/types.h> +#include <asm/io.h> #include "pinctrl-imx.h" static struct imx_pinctrl_soc_info imx8mq_pinctrl_soc_info __section(".data"); static const struct udevice_id imx8m_pinctrl_match[] = { +#if IS_ENABLED(CONFIG_IMX8MQ) { .compatible = "fsl,imx8mq-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info }, +#endif +#if IS_ENABLED(CONFIG_IMX8MM) { .compatible = "fsl,imx8mm-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info }, +#endif +#if IS_ENABLED(CONFIG_IMX8MN) { .compatible = "fsl,imx8mn-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info }, +#endif +#if IS_ENABLED(CONFIG_IMX8MP) { .compatible = "fsl,imx8mp-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info }, +#endif { /* sentinel */ } }; +#if CONFIG_IS_ENABLED(CMD_PINMUX) + +#if IS_ENABLED(CONFIG_IMX8MP) +#include "pinctrl-imx8mp.c" +#elif IS_ENABLED(CONFIG_IMX8MN) +#include "pinctrl-imx8mn.c" +#elif IS_ENABLED(CONFIG_IMX8MM) +#include "pinctrl-imx8mm.c" +#elif IS_ENABLED(CONFIG_IMX8MQ) +#include "pinctrl-imx8mq.c" +#endif + +static int imx8m_get_pins_count(struct udevice *dev) +{ + return ARRAY_SIZE(imx8m_pinctrl_pads); +} + +static const char *imx8m_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + /* sanity checking */ + if (selector != imx8m_pinctrl_pads[selector].number) { + dev_err(dev, + "selector(%u) not match with imx8m_pinctrl_pads[selector].number(%u)\n", + selector, imx8m_pinctrl_pads[selector].number); + return NULL; + } + + return imx8m_pinctrl_pads[selector].name; +} + +static int imx8m_get_pin_muxing(struct udevice *dev, unsigned int selector, + char *buf, int size) +{ + struct imx_pinctrl_priv *priv = dev_get_priv(dev); + struct imx_pinctrl_soc_info *info = priv->info; + u32 mux_reg = selector << 2; + u32 mux_mode = readl(info->base + mux_reg); + + snprintf(buf, size, "Function(%d) at: 0x%p", mux_mode & 0x7, info->base + mux_reg); + + return 0; +} +#endif + static const struct pinctrl_ops imx8m_pinctrl_ops = { +#if CONFIG_IS_ENABLED(CMD_PINMUX) + .get_pin_name = imx8m_get_pin_name, + .get_pins_count = imx8m_get_pins_count, + .get_pin_muxing = imx8m_get_pin_muxing, +#endif .set_state = imx_pinctrl_set_state_mmio, }; diff --git a/drivers/pinctrl/nxp/pinctrl-imx8mm.c b/drivers/pinctrl/nxp/pinctrl-imx8mm.c new file mode 100644 index 00000000000..9aa2303b618 --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-imx8mm.c @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 NXP + */ + +#include "pinctrl-imx.h" + +enum imx8mm_pads { + RESERVE0 = 0, + RESERVE1 = 1, + RESERVE2 = 2, + RESERVE3 = 3, + RESERVE4 = 4, + RESERVE5 = 5, + RESERVE6 = 6, + RESERVE7 = 7, + RESERVE8 = 8, + RESERVE9 = 9, + GPIO1_IO00 = 10, + GPIO1_IO01 = 11, + GPIO1_IO02 = 12, + GPIO1_IO03 = 13, + GPIO1_IO04 = 14, + GPIO1_IO05 = 15, + GPIO1_IO06 = 16, + GPIO1_IO07 = 17, + GPIO1_IO08 = 18, + GPIO1_IO09 = 19, + GPIO1_IO10 = 20, + GPIO1_IO11 = 21, + GPIO1_IO12 = 22, + GPIO1_IO13 = 23, + GPIO1_IO14 = 24, + GPIO1_IO15 = 25, + ENET_MDC = 26, + ENET_MDIO = 27, + ENET_TD3 = 28, + ENET_TD2 = 29, + ENET_TD1 = 30, + ENET_TD0 = 31, + ENET_TX_CTL = 32, + ENET_TXC = 33, + ENET_RX_CTL = 34, + ENET_RXC = 35, + ENET_RD0 = 36, + ENET_RD1 = 37, + ENET_RD2 = 38, + ENET_RD3 = 39, + SD1_CLK = 40, + SD1_CMD = 41, + SD1_DATA0 = 42, + SD1_DATA1 = 43, + SD1_DATA2 = 44, + SD1_DATA3 = 45, + SD1_DATA4 = 46, + SD1_DATA5 = 47, + SD1_DATA6 = 48, + SD1_DATA7 = 49, + SD1_RESET_B = 50, + SD1_STROBE = 51, + SD2_CD_B = 52, + SD2_CLK = 53, + SD2_CMD = 54, + SD2_DATA0 = 55, + SD2_DATA1 = 56, + SD2_DATA2 = 57, + SD2_DATA3 = 58, + SD2_RESET_B = 59, + SD2_WP = 60, + NAND_ALE = 61, + NAND_CE0 = 62, + NAND_CE1 = 63, + NAND_CE2 = 64, + NAND_CE3 = 65, + NAND_CLE = 66, + NAND_DATA00 = 67, + NAND_DATA01 = 68, + NAND_DATA02 = 69, + NAND_DATA03 = 70, + NAND_DATA04 = 71, + NAND_DATA05 = 72, + NAND_DATA06 = 73, + NAND_DATA07 = 74, + NAND_DQS = 75, + NAND_RE_B = 76, + NAND_READY_B = 77, + NAND_WE_B = 78, + NAND_WP_B = 79, + SAI5_RXFS = 80, + SAI5_RXC = 81, + SAI5_RXD0 = 82, + SAI5_RXD1 = 83, + SAI5_RXD2 = 84, + SAI5_RXD3 = 85, + SAI5_MCLK = 86, + SAI1_RXFS = 87, + SAI1_RXC = 88, + SAI1_RXD0 = 89, + SAI1_RXD1 = 90, + SAI1_RXD2 = 91, + SAI1_RXD3 = 92, + SAI1_RXD4 = 93, + SAI1_RXD5 = 94, + SAI1_RXD6 = 95, + SAI1_RXD7 = 96, + SAI1_TXFS = 97, + SAI1_TXC = 98, + SAI1_TXD0 = 99, + SAI1_TXD1 = 100, + SAI1_TXD2 = 101, + SAI1_TXD3 = 102, + SAI1_TXD4 = 103, + SAI1_TXD5 = 104, + SAI1_TXD6 = 105, + SAI1_TXD7 = 106, + SAI1_MCLK = 107, + SAI2_RXFS = 108, + SAI2_RXC = 109, + SAI2_RXD0 = 110, + SAI2_TXFS = 111, + SAI2_TXC = 112, + SAI2_TXD0 = 113, + SAI2_MCLK = 114, + SAI3_RXFS = 115, + SAI3_RXC = 116, + SAI3_RXD = 117, + SAI3_TXFS = 118, + SAI3_TXC = 119, + SAI3_TXD = 120, + SAI3_MCLK = 121, + SPDIF_TX = 122, + SPDIF_RX = 123, + SPDIF_EXT_CLK = 124, + ECSPI1_SCLK = 125, + ECSPI1_MOSI = 126, + ECSPI1_MISO = 127, + ECSPI1_SS0 = 128, + ECSPI2_SCLK = 129, + ECSPI2_MOSI = 130, + ECSPI2_MISO = 131, + ECSPI2_SS0 = 132, + I2C1_SCL = 133, + I2C1_SDA = 134, + I2C2_SCL = 135, + I2C2_SDA = 136, + I2C3_SCL = 137, + I2C3_SDA = 138, + I2C4_SCL = 139, + I2C4_SDA = 140, + UART1_RXD = 141, + UART1_TXD = 142, + UART2_RXD = 143, + UART2_TXD = 144, + UART3_RXD = 145, + UART3_TXD = 146, + UART4_RXD = 147, + UART4_TXD = 148, +}; + +static const struct imx_pinctrl_pin_desc imx8m_pinctrl_pads[] = { + IMX_PINCTRL_PIN(RESERVE0), + IMX_PINCTRL_PIN(RESERVE1), + IMX_PINCTRL_PIN(RESERVE2), + IMX_PINCTRL_PIN(RESERVE3), + IMX_PINCTRL_PIN(RESERVE4), + IMX_PINCTRL_PIN(RESERVE5), + IMX_PINCTRL_PIN(RESERVE6), + IMX_PINCTRL_PIN(RESERVE7), + IMX_PINCTRL_PIN(RESERVE8), + IMX_PINCTRL_PIN(RESERVE9), + IMX_PINCTRL_PIN(GPIO1_IO00), + IMX_PINCTRL_PIN(GPIO1_IO01), + IMX_PINCTRL_PIN(GPIO1_IO02), + IMX_PINCTRL_PIN(GPIO1_IO03), + IMX_PINCTRL_PIN(GPIO1_IO04), + IMX_PINCTRL_PIN(GPIO1_IO05), + IMX_PINCTRL_PIN(GPIO1_IO06), + IMX_PINCTRL_PIN(GPIO1_IO07), + IMX_PINCTRL_PIN(GPIO1_IO08), + IMX_PINCTRL_PIN(GPIO1_IO09), + IMX_PINCTRL_PIN(GPIO1_IO10), + IMX_PINCTRL_PIN(GPIO1_IO11), + IMX_PINCTRL_PIN(GPIO1_IO12), + IMX_PINCTRL_PIN(GPIO1_IO13), + IMX_PINCTRL_PIN(GPIO1_IO14), + IMX_PINCTRL_PIN(GPIO1_IO15), + IMX_PINCTRL_PIN(ENET_MDC), + IMX_PINCTRL_PIN(ENET_MDIO), + IMX_PINCTRL_PIN(ENET_TD3), + IMX_PINCTRL_PIN(ENET_TD2), + IMX_PINCTRL_PIN(ENET_TD1), + IMX_PINCTRL_PIN(ENET_TD0), + IMX_PINCTRL_PIN(ENET_TX_CTL), + IMX_PINCTRL_PIN(ENET_TXC), + IMX_PINCTRL_PIN(ENET_RX_CTL), + IMX_PINCTRL_PIN(ENET_RXC), + IMX_PINCTRL_PIN(ENET_RD0), + IMX_PINCTRL_PIN(ENET_RD1), + IMX_PINCTRL_PIN(ENET_RD2), + IMX_PINCTRL_PIN(ENET_RD3), + IMX_PINCTRL_PIN(SD1_CLK), + IMX_PINCTRL_PIN(SD1_CMD), + IMX_PINCTRL_PIN(SD1_DATA0), + IMX_PINCTRL_PIN(SD1_DATA1), + IMX_PINCTRL_PIN(SD1_DATA2), + IMX_PINCTRL_PIN(SD1_DATA3), + IMX_PINCTRL_PIN(SD1_DATA4), + IMX_PINCTRL_PIN(SD1_DATA5), + IMX_PINCTRL_PIN(SD1_DATA6), + IMX_PINCTRL_PIN(SD1_DATA7), + IMX_PINCTRL_PIN(SD1_RESET_B), + IMX_PINCTRL_PIN(SD1_STROBE), + IMX_PINCTRL_PIN(SD2_CD_B), + IMX_PINCTRL_PIN(SD2_CLK), + IMX_PINCTRL_PIN(SD2_CMD), + IMX_PINCTRL_PIN(SD2_DATA0), + IMX_PINCTRL_PIN(SD2_DATA1), + IMX_PINCTRL_PIN(SD2_DATA2), + IMX_PINCTRL_PIN(SD2_DATA3), + IMX_PINCTRL_PIN(SD2_RESET_B), + IMX_PINCTRL_PIN(SD2_WP), + IMX_PINCTRL_PIN(NAND_ALE), + IMX_PINCTRL_PIN(NAND_CE0), + IMX_PINCTRL_PIN(NAND_CE1), + IMX_PINCTRL_PIN(NAND_CE2), + IMX_PINCTRL_PIN(NAND_CE3), + IMX_PINCTRL_PIN(NAND_CLE), + IMX_PINCTRL_PIN(NAND_DATA00), + IMX_PINCTRL_PIN(NAND_DATA01), + IMX_PINCTRL_PIN(NAND_DATA02), + IMX_PINCTRL_PIN(NAND_DATA03), + IMX_PINCTRL_PIN(NAND_DATA04), + IMX_PINCTRL_PIN(NAND_DATA05), + IMX_PINCTRL_PIN(NAND_DATA06), + IMX_PINCTRL_PIN(NAND_DATA07), + IMX_PINCTRL_PIN(NAND_DQS), + IMX_PINCTRL_PIN(NAND_RE_B), + IMX_PINCTRL_PIN(NAND_READY_B), + IMX_PINCTRL_PIN(NAND_WE_B), + IMX_PINCTRL_PIN(NAND_WP_B), + IMX_PINCTRL_PIN(SAI5_RXFS), + IMX_PINCTRL_PIN(SAI5_RXC), + IMX_PINCTRL_PIN(SAI5_RXD0), + IMX_PINCTRL_PIN(SAI5_RXD1), + IMX_PINCTRL_PIN(SAI5_RXD2), + IMX_PINCTRL_PIN(SAI5_RXD3), + IMX_PINCTRL_PIN(SAI5_MCLK), + IMX_PINCTRL_PIN(SAI1_RXFS), + IMX_PINCTRL_PIN(SAI1_RXC), + IMX_PINCTRL_PIN(SAI1_RXD0), + IMX_PINCTRL_PIN(SAI1_RXD1), + IMX_PINCTRL_PIN(SAI1_RXD2), + IMX_PINCTRL_PIN(SAI1_RXD3), + IMX_PINCTRL_PIN(SAI1_RXD4), + IMX_PINCTRL_PIN(SAI1_RXD5), + IMX_PINCTRL_PIN(SAI1_RXD6), + IMX_PINCTRL_PIN(SAI1_RXD7), + IMX_PINCTRL_PIN(SAI1_TXFS), + IMX_PINCTRL_PIN(SAI1_TXC), + IMX_PINCTRL_PIN(SAI1_TXD0), + IMX_PINCTRL_PIN(SAI1_TXD1), + IMX_PINCTRL_PIN(SAI1_TXD2), + IMX_PINCTRL_PIN(SAI1_TXD3), + IMX_PINCTRL_PIN(SAI1_TXD4), + IMX_PINCTRL_PIN(SAI1_TXD5), + IMX_PINCTRL_PIN(SAI1_TXD6), + IMX_PINCTRL_PIN(SAI1_TXD7), + IMX_PINCTRL_PIN(SAI1_MCLK), + IMX_PINCTRL_PIN(SAI2_RXFS), + IMX_PINCTRL_PIN(SAI2_RXC), + IMX_PINCTRL_PIN(SAI2_RXD0), + IMX_PINCTRL_PIN(SAI2_TXFS), + IMX_PINCTRL_PIN(SAI2_TXC), + IMX_PINCTRL_PIN(SAI2_TXD0), + IMX_PINCTRL_PIN(SAI2_MCLK), + IMX_PINCTRL_PIN(SAI3_RXFS), + IMX_PINCTRL_PIN(SAI3_RXC), + IMX_PINCTRL_PIN(SAI3_RXD), + IMX_PINCTRL_PIN(SAI3_TXFS), + IMX_PINCTRL_PIN(SAI3_TXC), + IMX_PINCTRL_PIN(SAI3_TXD), + IMX_PINCTRL_PIN(SAI3_MCLK), + IMX_PINCTRL_PIN(SPDIF_TX), + IMX_PINCTRL_PIN(SPDIF_RX), + IMX_PINCTRL_PIN(SPDIF_EXT_CLK), + IMX_PINCTRL_PIN(ECSPI1_SCLK), + IMX_PINCTRL_PIN(ECSPI1_MOSI), + IMX_PINCTRL_PIN(ECSPI1_MISO), + IMX_PINCTRL_PIN(ECSPI1_SS0), + IMX_PINCTRL_PIN(ECSPI2_SCLK), + IMX_PINCTRL_PIN(ECSPI2_MOSI), + IMX_PINCTRL_PIN(ECSPI2_MISO), + IMX_PINCTRL_PIN(ECSPI2_SS0), + IMX_PINCTRL_PIN(I2C1_SCL), + IMX_PINCTRL_PIN(I2C1_SDA), + IMX_PINCTRL_PIN(I2C2_SCL), + IMX_PINCTRL_PIN(I2C2_SDA), + IMX_PINCTRL_PIN(I2C3_SCL), + IMX_PINCTRL_PIN(I2C3_SDA), + IMX_PINCTRL_PIN(I2C4_SCL), + IMX_PINCTRL_PIN(I2C4_SDA), + IMX_PINCTRL_PIN(UART1_RXD), + IMX_PINCTRL_PIN(UART1_TXD), + IMX_PINCTRL_PIN(UART2_RXD), + IMX_PINCTRL_PIN(UART2_TXD), + IMX_PINCTRL_PIN(UART3_RXD), + IMX_PINCTRL_PIN(UART3_TXD), + IMX_PINCTRL_PIN(UART4_RXD), + IMX_PINCTRL_PIN(UART4_TXD), +}; diff --git a/drivers/pinctrl/nxp/pinctrl-imx8mn.c b/drivers/pinctrl/nxp/pinctrl-imx8mn.c new file mode 100644 index 00000000000..a3e22cf72ee --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-imx8mn.c @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 NXP + */ + +#include "pinctrl-imx.h" + +enum imx8mn_pads { + RESERVE0 = 0, + RESERVE1 = 1, + RESERVE2 = 2, + RESERVE3 = 3, + RESERVE4 = 4, + RESERVE5 = 5, + RESERVE6 = 6, + RESERVE7 = 7, + BOOT_MODE2 = 8, + BOOT_MODE3 = 9, + GPIO1_IO00 = 10, + GPIO1_IO01 = 11, + GPIO1_IO02 = 12, + GPIO1_IO03 = 13, + GPIO1_IO04 = 14, + GPIO1_IO05 = 15, + GPIO1_IO06 = 16, + GPIO1_IO07 = 17, + GPIO1_IO08 = 18, + GPIO1_IO09 = 19, + GPIO1_IO10 = 20, + GPIO1_IO11 = 21, + GPIO1_IO12 = 22, + GPIO1_IO13 = 23, + GPIO1_IO14 = 24, + GPIO1_IO15 = 25, + ENET_MDC = 26, + ENET_MDIO = 27, + ENET_TD3 = 28, + ENET_TD2 = 29, + ENET_TD1 = 30, + ENET_TD0 = 31, + ENET_TX_CTL = 32, + ENET_TXC = 33, + ENET_RX_CTL = 34, + ENET_RXC = 35, + ENET_RD0 = 36, + ENET_RD1 = 37, + ENET_RD2 = 38, + ENET_RD3 = 39, + SD1_CLK = 40, + SD1_CMD = 41, + SD1_DATA0 = 42, + SD1_DATA1 = 43, + SD1_DATA2 = 44, + SD1_DATA3 = 45, + SD1_DATA4 = 46, + SD1_DATA5 = 47, + SD1_DATA6 = 48, + SD1_DATA7 = 49, + SD1_RESET_B = 50, + SD1_STROBE = 51, + SD2_CD_B = 52, + SD2_CLK = 53, + SD2_CMD = 54, + SD2_DATA0 = 55, + SD2_DATA1 = 56, + SD2_DATA2 = 57, + SD2_DATA3 = 58, + SD2_RESET_B = 59, + SD2_WP = 60, + NAND_ALE = 61, + NAND_CE0 = 62, + NAND_CE1 = 63, + NAND_CE2 = 64, + NAND_CE3 = 65, + NAND_CLE = 66, + NAND_DATA00 = 67, + NAND_DATA01 = 68, + NAND_DATA02 = 69, + NAND_DATA03 = 70, + NAND_DATA04 = 71, + NAND_DATA05 = 72, + NAND_DATA06 = 73, + NAND_DATA07 = 74, + NAND_DQS = 75, + NAND_RE_B = 76, + NAND_READY_B = 77, + NAND_WE_B = 78, + NAND_WP_B = 79, + SAI5_RXFS = 80, + SAI5_RXC = 81, + SAI5_RXD0 = 82, + SAI5_RXD1 = 83, + SAI5_RXD2 = 84, + SAI5_RXD3 = 85, + SAI5_MCLK = 86, + SAI1_RXFS = 87, + SAI1_RXC = 88, + SAI1_RXD0 = 89, + SAI1_RXD1 = 90, + SAI1_RXD2 = 91, + SAI1_RXD3 = 92, + SAI1_RXD4 = 93, + SAI1_RXD5 = 94, + SAI1_RXD6 = 95, + SAI1_RXD7 = 96, + SAI1_TXFS = 97, + SAI1_TXC = 98, + SAI1_TXD0 = 99, + SAI1_TXD1 = 100, + SAI1_TXD2 = 101, + SAI1_TXD3 = 102, + SAI1_TXD4 = 103, + SAI1_TXD5 = 104, + SAI1_TXD6 = 105, + SAI1_TXD7 = 106, + SAI1_MCLK = 107, + SAI2_RXFS = 108, + SAI2_RXC = 109, + SAI2_RXD0 = 110, + SAI2_TXFS = 111, + SAI2_TXC = 112, + SAI2_TXD0 = 113, + SAI2_MCLK = 114, + SAI3_RXFS = 115, + SAI3_RXC = 116, + SAI3_RXD = 117, + SAI3_TXFS = 118, + SAI3_TXC = 119, + SAI3_TXD = 120, + SAI3_MCLK = 121, + SPDIF_TX = 122, + SPDIF_RX = 123, + SPDIF_EXT_CLK = 124, + ECSPI1_SCLK = 125, + ECSPI1_MOSI = 126, + ECSPI1_MISO = 127, + ECSPI1_SS0 = 128, + ECSPI2_SCLK = 129, + ECSPI2_MOSI = 130, + ECSPI2_MISO = 131, + ECSPI2_SS0 = 132, + I2C1_SCL = 133, + I2C1_SDA = 134, + I2C2_SCL = 135, + I2C2_SDA = 136, + I2C3_SCL = 137, + I2C3_SDA = 138, + I2C4_SCL = 139, + I2C4_SDA = 140, + UART1_RXD = 141, + UART1_TXD = 142, + UART2_RXD = 143, + UART2_TXD = 144, + UART3_RXD = 145, + UART3_TXD = 146, + UART4_RXD = 147, + UART4_TXD = 148, +}; + +static const struct imx_pinctrl_pin_desc imx8m_pinctrl_pads[] = { + IMX_PINCTRL_PIN(RESERVE0), + IMX_PINCTRL_PIN(RESERVE1), + IMX_PINCTRL_PIN(RESERVE2), + IMX_PINCTRL_PIN(RESERVE3), + IMX_PINCTRL_PIN(RESERVE4), + IMX_PINCTRL_PIN(RESERVE5), + IMX_PINCTRL_PIN(RESERVE6), + IMX_PINCTRL_PIN(RESERVE7), + IMX_PINCTRL_PIN(BOOT_MODE2), + IMX_PINCTRL_PIN(BOOT_MODE3), + IMX_PINCTRL_PIN(GPIO1_IO00), + IMX_PINCTRL_PIN(GPIO1_IO01), + IMX_PINCTRL_PIN(GPIO1_IO02), + IMX_PINCTRL_PIN(GPIO1_IO03), + IMX_PINCTRL_PIN(GPIO1_IO04), + IMX_PINCTRL_PIN(GPIO1_IO05), + IMX_PINCTRL_PIN(GPIO1_IO06), + IMX_PINCTRL_PIN(GPIO1_IO07), + IMX_PINCTRL_PIN(GPIO1_IO08), + IMX_PINCTRL_PIN(GPIO1_IO09), + IMX_PINCTRL_PIN(GPIO1_IO10), + IMX_PINCTRL_PIN(GPIO1_IO11), + IMX_PINCTRL_PIN(GPIO1_IO12), + IMX_PINCTRL_PIN(GPIO1_IO13), + IMX_PINCTRL_PIN(GPIO1_IO14), + IMX_PINCTRL_PIN(GPIO1_IO15), + IMX_PINCTRL_PIN(ENET_MDC), + IMX_PINCTRL_PIN(ENET_MDIO), + IMX_PINCTRL_PIN(ENET_TD3), + IMX_PINCTRL_PIN(ENET_TD2), + IMX_PINCTRL_PIN(ENET_TD1), + IMX_PINCTRL_PIN(ENET_TD0), + IMX_PINCTRL_PIN(ENET_TX_CTL), + IMX_PINCTRL_PIN(ENET_TXC), + IMX_PINCTRL_PIN(ENET_RX_CTL), + IMX_PINCTRL_PIN(ENET_RXC), + IMX_PINCTRL_PIN(ENET_RD0), + IMX_PINCTRL_PIN(ENET_RD1), + IMX_PINCTRL_PIN(ENET_RD2), + IMX_PINCTRL_PIN(ENET_RD3), + IMX_PINCTRL_PIN(SD1_CLK), + IMX_PINCTRL_PIN(SD1_CMD), + IMX_PINCTRL_PIN(SD1_DATA0), + IMX_PINCTRL_PIN(SD1_DATA1), + IMX_PINCTRL_PIN(SD1_DATA2), + IMX_PINCTRL_PIN(SD1_DATA3), + IMX_PINCTRL_PIN(SD1_DATA4), + IMX_PINCTRL_PIN(SD1_DATA5), + IMX_PINCTRL_PIN(SD1_DATA6), + IMX_PINCTRL_PIN(SD1_DATA7), + IMX_PINCTRL_PIN(SD1_RESET_B), + IMX_PINCTRL_PIN(SD1_STROBE), + IMX_PINCTRL_PIN(SD2_CD_B), + IMX_PINCTRL_PIN(SD2_CLK), + IMX_PINCTRL_PIN(SD2_CMD), + IMX_PINCTRL_PIN(SD2_DATA0), + IMX_PINCTRL_PIN(SD2_DATA1), + IMX_PINCTRL_PIN(SD2_DATA2), + IMX_PINCTRL_PIN(SD2_DATA3), + IMX_PINCTRL_PIN(SD2_RESET_B), + IMX_PINCTRL_PIN(SD2_WP), + IMX_PINCTRL_PIN(NAND_ALE), + IMX_PINCTRL_PIN(NAND_CE0), + IMX_PINCTRL_PIN(NAND_CE1), + IMX_PINCTRL_PIN(NAND_CE2), + IMX_PINCTRL_PIN(NAND_CE3), + IMX_PINCTRL_PIN(NAND_CLE), + IMX_PINCTRL_PIN(NAND_DATA00), + IMX_PINCTRL_PIN(NAND_DATA01), + IMX_PINCTRL_PIN(NAND_DATA02), + IMX_PINCTRL_PIN(NAND_DATA03), + IMX_PINCTRL_PIN(NAND_DATA04), + IMX_PINCTRL_PIN(NAND_DATA05), + IMX_PINCTRL_PIN(NAND_DATA06), + IMX_PINCTRL_PIN(NAND_DATA07), + IMX_PINCTRL_PIN(NAND_DQS), + IMX_PINCTRL_PIN(NAND_RE_B), + IMX_PINCTRL_PIN(NAND_READY_B), + IMX_PINCTRL_PIN(NAND_WE_B), + IMX_PINCTRL_PIN(NAND_WP_B), + IMX_PINCTRL_PIN(SAI5_RXFS), + IMX_PINCTRL_PIN(SAI5_RXC), + IMX_PINCTRL_PIN(SAI5_RXD0), + IMX_PINCTRL_PIN(SAI5_RXD1), + IMX_PINCTRL_PIN(SAI5_RXD2), + IMX_PINCTRL_PIN(SAI5_RXD3), + IMX_PINCTRL_PIN(SAI5_MCLK), + IMX_PINCTRL_PIN(SAI1_RXFS), + IMX_PINCTRL_PIN(SAI1_RXC), + IMX_PINCTRL_PIN(SAI1_RXD0), + IMX_PINCTRL_PIN(SAI1_RXD1), + IMX_PINCTRL_PIN(SAI1_RXD2), + IMX_PINCTRL_PIN(SAI1_RXD3), + IMX_PINCTRL_PIN(SAI1_RXD4), + IMX_PINCTRL_PIN(SAI1_RXD5), + IMX_PINCTRL_PIN(SAI1_RXD6), + IMX_PINCTRL_PIN(SAI1_RXD7), + IMX_PINCTRL_PIN(SAI1_TXFS), + IMX_PINCTRL_PIN(SAI1_TXC), + IMX_PINCTRL_PIN(SAI1_TXD0), + IMX_PINCTRL_PIN(SAI1_TXD1), + IMX_PINCTRL_PIN(SAI1_TXD2), + IMX_PINCTRL_PIN(SAI1_TXD3), + IMX_PINCTRL_PIN(SAI1_TXD4), + IMX_PINCTRL_PIN(SAI1_TXD5), + IMX_PINCTRL_PIN(SAI1_TXD6), + IMX_PINCTRL_PIN(SAI1_TXD7), + IMX_PINCTRL_PIN(SAI1_MCLK), + IMX_PINCTRL_PIN(SAI2_RXFS), + IMX_PINCTRL_PIN(SAI2_RXC), + IMX_PINCTRL_PIN(SAI2_RXD0), + IMX_PINCTRL_PIN(SAI2_TXFS), + IMX_PINCTRL_PIN(SAI2_TXC), + IMX_PINCTRL_PIN(SAI2_TXD0), + IMX_PINCTRL_PIN(SAI2_MCLK), + IMX_PINCTRL_PIN(SAI3_RXFS), + IMX_PINCTRL_PIN(SAI3_RXC), + IMX_PINCTRL_PIN(SAI3_RXD), + IMX_PINCTRL_PIN(SAI3_TXFS), + IMX_PINCTRL_PIN(SAI3_TXC), + IMX_PINCTRL_PIN(SAI3_TXD), + IMX_PINCTRL_PIN(SAI3_MCLK), + IMX_PINCTRL_PIN(SPDIF_TX), + IMX_PINCTRL_PIN(SPDIF_RX), + IMX_PINCTRL_PIN(SPDIF_EXT_CLK), + IMX_PINCTRL_PIN(ECSPI1_SCLK), + IMX_PINCTRL_PIN(ECSPI1_MOSI), + IMX_PINCTRL_PIN(ECSPI1_MISO), + IMX_PINCTRL_PIN(ECSPI1_SS0), + IMX_PINCTRL_PIN(ECSPI2_SCLK), + IMX_PINCTRL_PIN(ECSPI2_MOSI), + IMX_PINCTRL_PIN(ECSPI2_MISO), + IMX_PINCTRL_PIN(ECSPI2_SS0), + IMX_PINCTRL_PIN(I2C1_SCL), + IMX_PINCTRL_PIN(I2C1_SDA), + IMX_PINCTRL_PIN(I2C2_SCL), + IMX_PINCTRL_PIN(I2C2_SDA), + IMX_PINCTRL_PIN(I2C3_SCL), + IMX_PINCTRL_PIN(I2C3_SDA), + IMX_PINCTRL_PIN(I2C4_SCL), + IMX_PINCTRL_PIN(I2C4_SDA), + IMX_PINCTRL_PIN(UART1_RXD), + IMX_PINCTRL_PIN(UART1_TXD), + IMX_PINCTRL_PIN(UART2_RXD), + IMX_PINCTRL_PIN(UART2_TXD), + IMX_PINCTRL_PIN(UART3_RXD), + IMX_PINCTRL_PIN(UART3_TXD), + IMX_PINCTRL_PIN(UART4_RXD), + IMX_PINCTRL_PIN(UART4_TXD), +}; diff --git a/drivers/pinctrl/nxp/pinctrl-imx8mp.c b/drivers/pinctrl/nxp/pinctrl-imx8mp.c new file mode 100644 index 00000000000..7f02eba5355 --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-imx8mp.c @@ -0,0 +1,309 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 NXP + */ + +#include "pinctrl-imx.h" + +enum imx8mp_pads { + RESERVE0 = 0, + RESERVE1 = 1, + RESERVE2 = 2, + RESERVE3 = 3, + RESERVE4 = 4, + GPIO1_IO00 = 5, + GPIO1_IO01 = 6, + GPIO1_IO02 = 7, + GPIO1_IO03 = 8, + GPIO1_IO04 = 9, + GPIO1_IO05 = 10, + GPIO1_IO06 = 11, + GPIO1_IO07 = 12, + GPIO1_IO08 = 13, + GPIO1_IO09 = 14, + GPIO1_IO10 = 15, + GPIO1_IO11 = 16, + GPIO1_IO12 = 17, + GPIO1_IO13 = 18, + GPIO1_IO14 = 19, + GPIO1_IO15 = 20, + ENET_MDC = 21, + ENET_MDIO = 22, + ENET_TD3 = 23, + ENET_TD2 = 24, + ENET_TD1 = 25, + ENET_TD0 = 26, + ENET_TX_CTL = 27, + ENET_TXC = 28, + ENET_RX_CTL = 29, + ENET_RXC = 30, + ENET_RD0 = 31, + ENET_RD1 = 32, + ENET_RD2 = 33, + ENET_RD3 = 34, + SD1_CLK = 35, + SD1_CMD = 36, + SD1_DATA0 = 37, + SD1_DATA1 = 38, + SD1_DATA2 = 39, + SD1_DATA3 = 40, + SD1_DATA4 = 41, + SD1_DATA5 = 42, + SD1_DATA6 = 43, + SD1_DATA7 = 44, + SD1_RESET_B = 45, + SD1_STROBE = 46, + SD2_CD_B = 47, + SD2_CLK = 48, + SD2_CMD = 49, + SD2_DATA0 = 50, + SD2_DATA1 = 51, + SD2_DATA2 = 52, + SD2_DATA3 = 53, + SD2_RESET_B = 54, + SD2_WP = 55, + NAND_ALE = 56, + NAND_CE0_B = 57, + NAND_CE1_B = 58, + NAND_CE2_B = 59, + NAND_CE3_B = 60, + NAND_CLE = 61, + NAND_DATA00 = 62, + NAND_DATA01 = 63, + NAND_DATA02 = 64, + NAND_DATA03 = 65, + NAND_DATA04 = 66, + NAND_DATA05 = 67, + NAND_DATA06 = 68, + NAND_DATA07 = 69, + NAND_DQS = 70, + NAND_RE_B = 71, + NAND_READY_B = 72, + NAND_WE_B = 73, + NAND_WP_B = 74, + SAI5_RXFS = 75, + SAI5_RXC = 76, + SAI5_RXD0 = 77, + SAI5_RXD1 = 78, + SAI5_RXD2 = 79, + SAI5_RXD3 = 80, + SAI5_MCLK = 81, + SAI1_RXFS = 82, + SAI1_RXC = 83, + SAI1_RXD0 = 84, + SAI1_RXD1 = 85, + SAI1_RXD2 = 86, + SAI1_RXD3 = 87, + SAI1_RXD4 = 88, + SAI1_RXD5 = 89, + SAI1_RXD6 = 90, + SAI1_RXD7 = 91, + SAI1_TXFS = 92, + SAI1_TXC = 93, + SAI1_TXD0 = 94, + SAI1_TXD1 = 95, + SAI1_TXD2 = 96, + SAI1_TXD3 = 97, + SAI1_TXD4 = 98, + SAI1_TXD5 = 99, + SAI1_TXD6 = 100, + SAI1_TXD7 = 101, + SAI1_MCLK = 102, + SAI2_RXFS = 103, + SAI2_RXC = 104, + SAI2_RXD0 = 105, + SAI2_TXFS = 106, + SAI2_TXC = 107, + SAI2_TXD0 = 108, + SAI2_MCLK = 109, + SAI3_RXFS = 110, + SAI3_RXC = 111, + SAI3_RXD = 112, + SAI3_TXFS = 113, + SAI3_TXC = 114, + SAI3_TXD = 115, + SAI3_MCLK = 116, + SPDIF_TX = 117, + SPDIF_RX = 118, + SPDIF_EXT_CLK = 119, + ECSPI1_SCLK = 120, + ECSPI1_MOSI = 121, + ECSPI1_MISO = 122, + ECSPI1_SS0 = 123, + ECSPI2_SCLK = 124, + ECSPI2_MOSI = 125, + ECSPI2_MISO = 126, + ECSPI2_SS0 = 127, + I2C1_SCL = 128, + I2C1_SDA = 129, + I2C2_SCL = 130, + I2C2_SDA = 131, + I2C3_SCL = 132, + I2C3_SDA = 133, + I2C4_SCL = 134, + I2C4_SDA = 135, + UART1_RXD = 136, + UART1_TXD = 137, + UART2_RXD = 138, + UART2_TXD = 139, + UART3_RXD = 140, + UART3_TXD = 141, + UART4_RXD = 142, + UART4_TXD = 143, + HDMI_DDC_SCL = 144, + HDMI_DDC_SDA = 145, + HDMI_CEC = 146, + HDMI_HPD = 147, +}; + +/* Pad names for the pinmux subsystem */ +static const struct imx_pinctrl_pin_desc imx8m_pinctrl_pads[] = { + IMX_PINCTRL_PIN(RESERVE0), + IMX_PINCTRL_PIN(RESERVE1), + IMX_PINCTRL_PIN(RESERVE2), + IMX_PINCTRL_PIN(RESERVE3), + IMX_PINCTRL_PIN(RESERVE4), + IMX_PINCTRL_PIN(GPIO1_IO00), + IMX_PINCTRL_PIN(GPIO1_IO01), + IMX_PINCTRL_PIN(GPIO1_IO02), + IMX_PINCTRL_PIN(GPIO1_IO03), + IMX_PINCTRL_PIN(GPIO1_IO04), + IMX_PINCTRL_PIN(GPIO1_IO05), + IMX_PINCTRL_PIN(GPIO1_IO06), + IMX_PINCTRL_PIN(GPIO1_IO07), + IMX_PINCTRL_PIN(GPIO1_IO08), + IMX_PINCTRL_PIN(GPIO1_IO09), + IMX_PINCTRL_PIN(GPIO1_IO10), + IMX_PINCTRL_PIN(GPIO1_IO11), + IMX_PINCTRL_PIN(GPIO1_IO12), + IMX_PINCTRL_PIN(GPIO1_IO13), + IMX_PINCTRL_PIN(GPIO1_IO14), + IMX_PINCTRL_PIN(GPIO1_IO15), + IMX_PINCTRL_PIN(ENET_MDC), + IMX_PINCTRL_PIN(ENET_MDIO), + IMX_PINCTRL_PIN(ENET_TD3), + IMX_PINCTRL_PIN(ENET_TD2), + IMX_PINCTRL_PIN(ENET_TD1), + IMX_PINCTRL_PIN(ENET_TD0), + IMX_PINCTRL_PIN(ENET_TX_CTL), + IMX_PINCTRL_PIN(ENET_TXC), + IMX_PINCTRL_PIN(ENET_RX_CTL), + IMX_PINCTRL_PIN(ENET_RXC), + IMX_PINCTRL_PIN(ENET_RD0), + IMX_PINCTRL_PIN(ENET_RD1), + IMX_PINCTRL_PIN(ENET_RD2), + IMX_PINCTRL_PIN(ENET_RD3), + IMX_PINCTRL_PIN(SD1_CLK), + IMX_PINCTRL_PIN(SD1_CMD), + IMX_PINCTRL_PIN(SD1_DATA0), + IMX_PINCTRL_PIN(SD1_DATA1), + IMX_PINCTRL_PIN(SD1_DATA2), + IMX_PINCTRL_PIN(SD1_DATA3), + IMX_PINCTRL_PIN(SD1_DATA4), + IMX_PINCTRL_PIN(SD1_DATA5), + IMX_PINCTRL_PIN(SD1_DATA6), + IMX_PINCTRL_PIN(SD1_DATA7), + IMX_PINCTRL_PIN(SD1_RESET_B), + IMX_PINCTRL_PIN(SD1_STROBE), + IMX_PINCTRL_PIN(SD2_CD_B), + IMX_PINCTRL_PIN(SD2_CLK), + IMX_PINCTRL_PIN(SD2_CMD), + IMX_PINCTRL_PIN(SD2_DATA0), + IMX_PINCTRL_PIN(SD2_DATA1), + IMX_PINCTRL_PIN(SD2_DATA2), + IMX_PINCTRL_PIN(SD2_DATA3), + IMX_PINCTRL_PIN(SD2_RESET_B), + IMX_PINCTRL_PIN(SD2_WP), + IMX_PINCTRL_PIN(NAND_ALE), + IMX_PINCTRL_PIN(NAND_CE0_B), + IMX_PINCTRL_PIN(NAND_CE1_B), + IMX_PINCTRL_PIN(NAND_CE2_B), + IMX_PINCTRL_PIN(NAND_CE3_B), + IMX_PINCTRL_PIN(NAND_CLE), + IMX_PINCTRL_PIN(NAND_DATA00), + IMX_PINCTRL_PIN(NAND_DATA01), + IMX_PINCTRL_PIN(NAND_DATA02), + IMX_PINCTRL_PIN(NAND_DATA03), + IMX_PINCTRL_PIN(NAND_DATA04), + IMX_PINCTRL_PIN(NAND_DATA05), + IMX_PINCTRL_PIN(NAND_DATA06), + IMX_PINCTRL_PIN(NAND_DATA07), + IMX_PINCTRL_PIN(NAND_DQS), + IMX_PINCTRL_PIN(NAND_RE_B), + IMX_PINCTRL_PIN(NAND_READY_B), + IMX_PINCTRL_PIN(NAND_WE_B), + IMX_PINCTRL_PIN(NAND_WP_B), + IMX_PINCTRL_PIN(SAI5_RXFS), + IMX_PINCTRL_PIN(SAI5_RXC), + IMX_PINCTRL_PIN(SAI5_RXD0), + IMX_PINCTRL_PIN(SAI5_RXD1), + IMX_PINCTRL_PIN(SAI5_RXD2), + IMX_PINCTRL_PIN(SAI5_RXD3), + IMX_PINCTRL_PIN(SAI5_MCLK), + IMX_PINCTRL_PIN(SAI1_RXFS), + IMX_PINCTRL_PIN(SAI1_RXC), + IMX_PINCTRL_PIN(SAI1_RXD0), + IMX_PINCTRL_PIN(SAI1_RXD1), + IMX_PINCTRL_PIN(SAI1_RXD2), + IMX_PINCTRL_PIN(SAI1_RXD3), + IMX_PINCTRL_PIN(SAI1_RXD4), + IMX_PINCTRL_PIN(SAI1_RXD5), + IMX_PINCTRL_PIN(SAI1_RXD6), + IMX_PINCTRL_PIN(SAI1_RXD7), + IMX_PINCTRL_PIN(SAI1_TXFS), + IMX_PINCTRL_PIN(SAI1_TXC), + IMX_PINCTRL_PIN(SAI1_TXD0), + IMX_PINCTRL_PIN(SAI1_TXD1), + IMX_PINCTRL_PIN(SAI1_TXD2), + IMX_PINCTRL_PIN(SAI1_TXD3), + IMX_PINCTRL_PIN(SAI1_TXD4), + IMX_PINCTRL_PIN(SAI1_TXD5), + IMX_PINCTRL_PIN(SAI1_TXD6), + IMX_PINCTRL_PIN(SAI1_TXD7), + IMX_PINCTRL_PIN(SAI1_MCLK), + IMX_PINCTRL_PIN(SAI2_RXFS), + IMX_PINCTRL_PIN(SAI2_RXC), + IMX_PINCTRL_PIN(SAI2_RXD0), + IMX_PINCTRL_PIN(SAI2_TXFS), + IMX_PINCTRL_PIN(SAI2_TXC), + IMX_PINCTRL_PIN(SAI2_TXD0), + IMX_PINCTRL_PIN(SAI2_MCLK), + IMX_PINCTRL_PIN(SAI3_RXFS), + IMX_PINCTRL_PIN(SAI3_RXC), + IMX_PINCTRL_PIN(SAI3_RXD), + IMX_PINCTRL_PIN(SAI3_TXFS), + IMX_PINCTRL_PIN(SAI3_TXC), + IMX_PINCTRL_PIN(SAI3_TXD), + IMX_PINCTRL_PIN(SAI3_MCLK), + IMX_PINCTRL_PIN(SPDIF_TX), + IMX_PINCTRL_PIN(SPDIF_RX), + IMX_PINCTRL_PIN(SPDIF_EXT_CLK), + IMX_PINCTRL_PIN(ECSPI1_SCLK), + IMX_PINCTRL_PIN(ECSPI1_MOSI), + IMX_PINCTRL_PIN(ECSPI1_MISO), + IMX_PINCTRL_PIN(ECSPI1_SS0), + IMX_PINCTRL_PIN(ECSPI2_SCLK), + IMX_PINCTRL_PIN(ECSPI2_MOSI), + IMX_PINCTRL_PIN(ECSPI2_MISO), + IMX_PINCTRL_PIN(ECSPI2_SS0), + IMX_PINCTRL_PIN(I2C1_SCL), + IMX_PINCTRL_PIN(I2C1_SDA), + IMX_PINCTRL_PIN(I2C2_SCL), + IMX_PINCTRL_PIN(I2C2_SDA), + IMX_PINCTRL_PIN(I2C3_SCL), + IMX_PINCTRL_PIN(I2C3_SDA), + IMX_PINCTRL_PIN(I2C4_SCL), + IMX_PINCTRL_PIN(I2C4_SDA), + IMX_PINCTRL_PIN(UART1_RXD), + IMX_PINCTRL_PIN(UART1_TXD), + IMX_PINCTRL_PIN(UART2_RXD), + IMX_PINCTRL_PIN(UART2_TXD), + IMX_PINCTRL_PIN(UART3_RXD), + IMX_PINCTRL_PIN(UART3_TXD), + IMX_PINCTRL_PIN(UART4_RXD), + IMX_PINCTRL_PIN(UART4_TXD), + IMX_PINCTRL_PIN(HDMI_DDC_SCL), + IMX_PINCTRL_PIN(HDMI_DDC_SDA), + IMX_PINCTRL_PIN(HDMI_CEC), + IMX_PINCTRL_PIN(HDMI_HPD), +}; diff --git a/drivers/pinctrl/nxp/pinctrl-imx8mq.c b/drivers/pinctrl/nxp/pinctrl-imx8mq.c new file mode 100644 index 00000000000..bcc3e8ecbcf --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-imx8mq.c @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 NXP + */ + +#include "pinctrl-imx.h" + +enum imx8mq_pads { + RESERVE0 = 0, + RESERVE1 = 1, + RESERVE2 = 2, + RESERVE3 = 3, + RESERVE4 = 4, + PMIC_STBY_REQ_CCMSRCGPCMIX = 5, + PMIC_ON_REQ_SNVSMIX = 6, + ONOFF_SNVSMIX = 7, + POR_B_SNVSMIX = 8, + RTC_RESET_B_SNVSMIX = 9, + GPIO1_IO00 = 10, + GPIO1_IO01 = 11, + GPIO1_IO02 = 12, + GPIO1_IO03 = 13, + GPIO1_IO04 = 14, + GPIO1_IO05 = 15, + GPIO1_IO06 = 16, + GPIO1_IO07 = 17, + GPIO1_IO08 = 18, + GPIO1_IO09 = 19, + GPIO1_IO10 = 20, + GPIO1_IO11 = 21, + GPIO1_IO12 = 22, + GPIO1_IO13 = 23, + GPIO1_IO14 = 24, + GPIO1_IO15 = 25, + ENET_MDC = 26, + ENET_MDIO = 27, + ENET_TD3 = 28, + ENET_TD2 = 29, + ENET_TD1 = 30, + ENET_TD0 = 31, + ENET_TX_CTL = 32, + ENET_TXC = 33, + ENET_RX_CTL = 34, + ENET_RXC = 35, + ENET_RD0 = 36, + ENET_RD1 = 37, + ENET_RD2 = 38, + ENET_RD3 = 39, + SD1_CLK = 40, + SD1_CMD = 41, + SD1_DATA0 = 42, + SD1_DATA1 = 43, + SD1_DATA2 = 44, + SD1_DATA3 = 45, + SD1_DATA4 = 46, + SD1_DATA5 = 47, + SD1_DATA6 = 48, + SD1_DATA7 = 49, + SD1_RESET_B = 50, + SD1_STROBE = 51, + SD2_CD_B = 52, + SD2_CLK = 53, + SD2_CMD = 54, + SD2_DATA0 = 55, + SD2_DATA1 = 56, + SD2_DATA2 = 57, + SD2_DATA3 = 58, + SD2_RESET_B = 59, + SD2_WP = 60, + NAND_ALE = 61, + NAND_CE0_B = 62, + NAND_CE1_B = 63, + NAND_CE2_B = 64, + NAND_CE3_B = 65, + NAND_CLE = 66, + NAND_DATA00 = 67, + NAND_DATA01 = 68, + NAND_DATA02 = 69, + NAND_DATA03 = 70, + NAND_DATA04 = 71, + NAND_DATA05 = 72, + NAND_DATA06 = 73, + NAND_DATA07 = 74, + NAND_DQS = 75, + NAND_RE_B = 76, + NAND_READY_B = 77, + NAND_WE_B = 78, + NAND_WP_B = 79, + SAI5_RXFS = 80, + SAI5_RXC = 81, + SAI5_RXD0 = 82, + SAI5_RXD1 = 83, + SAI5_RXD2 = 84, + SAI5_RXD3 = 85, + SAI5_MCLK = 86, + SAI1_RXFS = 87, + SAI1_RXC = 88, + SAI1_RXD0 = 89, + SAI1_RXD1 = 90, + SAI1_RXD2 = 91, + SAI1_RXD3 = 92, + SAI1_RXD4 = 93, + SAI1_RXD5 = 94, + SAI1_RXD6 = 95, + SAI1_RXD7 = 96, + SAI1_TXFS = 97, + SAI1_TXC = 98, + SAI1_TXD0 = 99, + SAI1_TXD1 = 100, + SAI1_TXD2 = 101, + SAI1_TXD3 = 102, + SAI1_TXD4 = 103, + SAI1_TXD5 = 104, + SAI1_TXD6 = 105, + SAI1_TXD7 = 106, + SAI1_MCLK = 107, + SAI2_RXFS = 108, + SAI2_RXC = 109, + SAI2_RXD0 = 110, + SAI2_TXFS = 111, + SAI2_TXC = 112, + SAI2_TXD0 = 113, + SAI2_MCLK = 114, + SAI3_RXFS = 115, + SAI3_RXC = 116, + SAI3_RXD = 117, + SAI3_TXFS = 118, + SAI3_TXC = 119, + SAI3_TXD = 120, + SAI3_MCLK = 121, + SPDIF_TX = 122, + SPDIF_RX = 123, + SPDIF_EXT_CLK = 124, + ECSPI1_SCLK = 125, + ECSPI1_MOSI = 126, + ECSPI1_MISO = 127, + ECSPI1_SS0 = 128, + ECSPI2_SCLK = 129, + ECSPI2_MOSI = 130, + ECSPI2_MISO = 131, + ECSPI2_SS0 = 132, + I2C1_SCL = 133, + I2C1_SDA = 134, + I2C2_SCL = 135, + I2C2_SDA = 136, + I2C3_SCL = 137, + I2C3_SDA = 138, + I2C4_SCL = 139, + I2C4_SDA = 140, + UART1_RXD = 141, + UART1_TXD = 142, + UART2_RXD = 143, + UART2_TXD = 144, + UART3_RXD = 145, + UART3_TXD = 146, + UART4_RXD = 147, + UART4_TXD = 148, +}; + +static const struct imx_pinctrl_pin_desc imx8m_pinctrl_pads[] = { + IMX_PINCTRL_PIN(RESERVE0), + IMX_PINCTRL_PIN(RESERVE1), + IMX_PINCTRL_PIN(RESERVE2), + IMX_PINCTRL_PIN(RESERVE3), + IMX_PINCTRL_PIN(RESERVE4), + IMX_PINCTRL_PIN(PMIC_STBY_REQ_CCMSRCGPCMIX), + IMX_PINCTRL_PIN(PMIC_ON_REQ_SNVSMIX), + IMX_PINCTRL_PIN(ONOFF_SNVSMIX), + IMX_PINCTRL_PIN(POR_B_SNVSMIX), + IMX_PINCTRL_PIN(RTC_RESET_B_SNVSMIX), + IMX_PINCTRL_PIN(GPIO1_IO00), + IMX_PINCTRL_PIN(GPIO1_IO01), + IMX_PINCTRL_PIN(GPIO1_IO02), + IMX_PINCTRL_PIN(GPIO1_IO03), + IMX_PINCTRL_PIN(GPIO1_IO04), + IMX_PINCTRL_PIN(GPIO1_IO05), + IMX_PINCTRL_PIN(GPIO1_IO06), + IMX_PINCTRL_PIN(GPIO1_IO07), + IMX_PINCTRL_PIN(GPIO1_IO08), + IMX_PINCTRL_PIN(GPIO1_IO09), + IMX_PINCTRL_PIN(GPIO1_IO10), + IMX_PINCTRL_PIN(GPIO1_IO11), + IMX_PINCTRL_PIN(GPIO1_IO12), + IMX_PINCTRL_PIN(GPIO1_IO13), + IMX_PINCTRL_PIN(GPIO1_IO14), + IMX_PINCTRL_PIN(GPIO1_IO15), + IMX_PINCTRL_PIN(ENET_MDC), + IMX_PINCTRL_PIN(ENET_MDIO), + IMX_PINCTRL_PIN(ENET_TD3), + IMX_PINCTRL_PIN(ENET_TD2), + IMX_PINCTRL_PIN(ENET_TD1), + IMX_PINCTRL_PIN(ENET_TD0), + IMX_PINCTRL_PIN(ENET_TX_CTL), + IMX_PINCTRL_PIN(ENET_TXC), + IMX_PINCTRL_PIN(ENET_RX_CTL), + IMX_PINCTRL_PIN(ENET_RXC), + IMX_PINCTRL_PIN(ENET_RD0), + IMX_PINCTRL_PIN(ENET_RD1), + IMX_PINCTRL_PIN(ENET_RD2), + IMX_PINCTRL_PIN(ENET_RD3), + IMX_PINCTRL_PIN(SD1_CLK), + IMX_PINCTRL_PIN(SD1_CMD), + IMX_PINCTRL_PIN(SD1_DATA0), + IMX_PINCTRL_PIN(SD1_DATA1), + IMX_PINCTRL_PIN(SD1_DATA2), + IMX_PINCTRL_PIN(SD1_DATA3), + IMX_PINCTRL_PIN(SD1_DATA4), + IMX_PINCTRL_PIN(SD1_DATA5), + IMX_PINCTRL_PIN(SD1_DATA6), + IMX_PINCTRL_PIN(SD1_DATA7), + IMX_PINCTRL_PIN(SD1_RESET_B), + IMX_PINCTRL_PIN(SD1_STROBE), + IMX_PINCTRL_PIN(SD2_CD_B), + IMX_PINCTRL_PIN(SD2_CLK), + IMX_PINCTRL_PIN(SD2_CMD), + IMX_PINCTRL_PIN(SD2_DATA0), + IMX_PINCTRL_PIN(SD2_DATA1), + IMX_PINCTRL_PIN(SD2_DATA2), + IMX_PINCTRL_PIN(SD2_DATA3), + IMX_PINCTRL_PIN(SD2_RESET_B), + IMX_PINCTRL_PIN(SD2_WP), + IMX_PINCTRL_PIN(NAND_ALE), + IMX_PINCTRL_PIN(NAND_CE0_B), + IMX_PINCTRL_PIN(NAND_CE1_B), + IMX_PINCTRL_PIN(NAND_CE2_B), + IMX_PINCTRL_PIN(NAND_CE3_B), + IMX_PINCTRL_PIN(NAND_CLE), + IMX_PINCTRL_PIN(NAND_DATA00), + IMX_PINCTRL_PIN(NAND_DATA01), + IMX_PINCTRL_PIN(NAND_DATA02), + IMX_PINCTRL_PIN(NAND_DATA03), + IMX_PINCTRL_PIN(NAND_DATA04), + IMX_PINCTRL_PIN(NAND_DATA05), + IMX_PINCTRL_PIN(NAND_DATA06), + IMX_PINCTRL_PIN(NAND_DATA07), + IMX_PINCTRL_PIN(NAND_DQS), + IMX_PINCTRL_PIN(NAND_RE_B), + IMX_PINCTRL_PIN(NAND_READY_B), + IMX_PINCTRL_PIN(NAND_WE_B), + IMX_PINCTRL_PIN(NAND_WP_B), + IMX_PINCTRL_PIN(SAI5_RXFS), + IMX_PINCTRL_PIN(SAI5_RXC), + IMX_PINCTRL_PIN(SAI5_RXD0), + IMX_PINCTRL_PIN(SAI5_RXD1), + IMX_PINCTRL_PIN(SAI5_RXD2), + IMX_PINCTRL_PIN(SAI5_RXD3), + IMX_PINCTRL_PIN(SAI5_MCLK), + IMX_PINCTRL_PIN(SAI1_RXFS), + IMX_PINCTRL_PIN(SAI1_RXC), + IMX_PINCTRL_PIN(SAI1_RXD0), + IMX_PINCTRL_PIN(SAI1_RXD1), + IMX_PINCTRL_PIN(SAI1_RXD2), + IMX_PINCTRL_PIN(SAI1_RXD3), + IMX_PINCTRL_PIN(SAI1_RXD4), + IMX_PINCTRL_PIN(SAI1_RXD5), + IMX_PINCTRL_PIN(SAI1_RXD6), + IMX_PINCTRL_PIN(SAI1_RXD7), + IMX_PINCTRL_PIN(SAI1_TXFS), + IMX_PINCTRL_PIN(SAI1_TXC), + IMX_PINCTRL_PIN(SAI1_TXD0), + IMX_PINCTRL_PIN(SAI1_TXD1), + IMX_PINCTRL_PIN(SAI1_TXD2), + IMX_PINCTRL_PIN(SAI1_TXD3), + IMX_PINCTRL_PIN(SAI1_TXD4), + IMX_PINCTRL_PIN(SAI1_TXD5), + IMX_PINCTRL_PIN(SAI1_TXD6), + IMX_PINCTRL_PIN(SAI1_TXD7), + IMX_PINCTRL_PIN(SAI1_MCLK), + IMX_PINCTRL_PIN(SAI2_RXFS), + IMX_PINCTRL_PIN(SAI2_RXC), + IMX_PINCTRL_PIN(SAI2_RXD0), + IMX_PINCTRL_PIN(SAI2_TXFS), + IMX_PINCTRL_PIN(SAI2_TXC), + IMX_PINCTRL_PIN(SAI2_TXD0), + IMX_PINCTRL_PIN(SAI2_MCLK), + IMX_PINCTRL_PIN(SAI3_RXFS), + IMX_PINCTRL_PIN(SAI3_RXC), + IMX_PINCTRL_PIN(SAI3_RXD), + IMX_PINCTRL_PIN(SAI3_TXFS), + IMX_PINCTRL_PIN(SAI3_TXC), + IMX_PINCTRL_PIN(SAI3_TXD), + IMX_PINCTRL_PIN(SAI3_MCLK), + IMX_PINCTRL_PIN(SPDIF_TX), + IMX_PINCTRL_PIN(SPDIF_RX), + IMX_PINCTRL_PIN(SPDIF_EXT_CLK), + IMX_PINCTRL_PIN(ECSPI1_SCLK), + IMX_PINCTRL_PIN(ECSPI1_MOSI), + IMX_PINCTRL_PIN(ECSPI1_MISO), + IMX_PINCTRL_PIN(ECSPI1_SS0), + IMX_PINCTRL_PIN(ECSPI2_SCLK), + IMX_PINCTRL_PIN(ECSPI2_MOSI), + IMX_PINCTRL_PIN(ECSPI2_MISO), + IMX_PINCTRL_PIN(ECSPI2_SS0), + IMX_PINCTRL_PIN(I2C1_SCL), + IMX_PINCTRL_PIN(I2C1_SDA), + IMX_PINCTRL_PIN(I2C2_SCL), + IMX_PINCTRL_PIN(I2C2_SDA), + IMX_PINCTRL_PIN(I2C3_SCL), + IMX_PINCTRL_PIN(I2C3_SDA), + IMX_PINCTRL_PIN(I2C4_SCL), + IMX_PINCTRL_PIN(I2C4_SDA), + IMX_PINCTRL_PIN(UART1_RXD), + IMX_PINCTRL_PIN(UART1_TXD), + IMX_PINCTRL_PIN(UART2_RXD), + IMX_PINCTRL_PIN(UART2_TXD), + IMX_PINCTRL_PIN(UART3_RXD), + IMX_PINCTRL_PIN(UART3_TXD), + IMX_PINCTRL_PIN(UART4_RXD), + IMX_PINCTRL_PIN(UART4_TXD), +}; diff --git a/drivers/pinctrl/nxp/pinctrl-imx9.c b/drivers/pinctrl/nxp/pinctrl-imx9.c new file mode 100644 index 00000000000..de22e29e953 --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-imx9.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include <dm/device.h> +#include <dm/device_compat.h> +#include <dm/pinctrl.h> +#include <linux/bitops.h> +#include <linux/types.h> +#include <asm/io.h> + +#include "pinctrl-imx.h" + +static struct imx_pinctrl_soc_info imx9_pinctrl_soc_info __section(".data") = { + .flags = ZERO_OFFSET_VALID, +}; + +static const struct udevice_id imx9_pinctrl_match[] = { +#if IS_ENABLED(CONFIG_IMX93) + { .compatible = "fsl,imx93-iomuxc", .data = (ulong)&imx9_pinctrl_soc_info }, +#endif +#if IS_ENABLED(CONFIG_IMX91) + { .compatible = "fsl,imx91-iomuxc", .data = (ulong)&imx9_pinctrl_soc_info }, +#endif + { /* sentinel */ } +}; + +#if CONFIG_IS_ENABLED(CMD_PINMUX) + +#if IS_ENABLED(CONFIG_IMX93) +#include "pinctrl-imx93.c" +#elif IS_ENABLED(CONFIG_IMX91) +#include "pinctrl-imx91.c" +#endif + +static int imx9_get_pins_count(struct udevice *dev) +{ + return ARRAY_SIZE(imx9_pinctrl_pads); +} + +static const char *imx9_get_pin_name(struct udevice *dev, unsigned int selector) +{ + /* sanity checking */ + if (selector != imx9_pinctrl_pads[selector].number) { + dev_err(dev, + "selector(%u) not match with imx9_pinctrl_pads[selector].number(%u)\n", + selector, imx9_pinctrl_pads[selector].number); + return NULL; + } + + return imx9_pinctrl_pads[selector].name; +} + +static int imx9_get_pin_muxing(struct udevice *dev, unsigned int selector, + char *buf, int size) +{ + struct imx_pinctrl_priv *priv = dev_get_priv(dev); + struct imx_pinctrl_soc_info *info = priv->info; + u32 mux_reg = selector << 2; + u32 mux_mode = readl(info->base + mux_reg); + u32 sion = mux_mode >> 4; + + snprintf(buf, size, "Function(%d) SION(%d) at: 0x%p", mux_mode & 0x7, sion, + info->base + mux_reg); + + return 0; +} +#endif + +static const struct pinctrl_ops imx9_pinctrl_ops = { +#if CONFIG_IS_ENABLED(CMD_PINMUX) + .get_pin_name = imx9_get_pin_name, + .get_pins_count = imx9_get_pins_count, + .get_pin_muxing = imx9_get_pin_muxing, +#endif + .set_state = imx_pinctrl_set_state_mmio, +}; + +U_BOOT_DRIVER(imx9_pinctrl) = { + .name = "imx9-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(imx9_pinctrl_match), + .probe = imx_pinctrl_probe_mmio, + .remove = imx_pinctrl_remove_mmio, + .priv_auto = sizeof(struct imx_pinctrl_priv), + .ops = &imx9_pinctrl_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/pinctrl/nxp/pinctrl-imx91.c b/drivers/pinctrl/nxp/pinctrl-imx91.c new file mode 100644 index 00000000000..1dc63cda2fd --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-imx91.c @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 NXP + */ + +#include "pinctrl-imx.h" + +enum imx91_pads { + DAP_TDI = 0, + DAP_TMS_SWDIO = 1, + DAP_TCLK_SWCLK = 2, + DAP_TDO_TRACESWO = 3, + GPIO_IO00 = 4, + GPIO_IO01 = 5, + GPIO_IO02 = 6, + GPIO_IO03 = 7, + GPIO_IO04 = 8, + GPIO_IO05 = 9, + GPIO_IO06 = 10, + GPIO_IO07 = 11, + GPIO_IO08 = 12, + GPIO_IO09 = 13, + GPIO_IO10 = 14, + GPIO_IO11 = 15, + GPIO_IO12 = 16, + GPIO_IO13 = 17, + GPIO_IO14 = 18, + GPIO_IO15 = 19, + GPIO_IO16 = 20, + GPIO_IO17 = 21, + GPIO_IO18 = 22, + GPIO_IO19 = 23, + GPIO_IO20 = 24, + GPIO_IO21 = 25, + GPIO_IO22 = 26, + GPIO_IO23 = 27, + GPIO_IO24 = 28, + GPIO_IO25 = 29, + GPIO_IO26 = 30, + GPIO_IO27 = 31, + GPIO_IO28 = 32, + GPIO_IO29 = 33, + CCM_CLKO1 = 34, + CCM_CLKO2 = 35, + CCM_CLKO3 = 36, + CCM_CLKO4 = 37, + ENET1_MDC = 38, + ENET1_MDIO = 39, + ENET1_TD3 = 40, + ENET1_TD2 = 41, + ENET1_TD1 = 42, + ENET1_TD0 = 43, + ENET1_TX_CTL = 44, + ENET1_TXC = 45, + ENET1_RX_CTL = 46, + ENET1_RXC = 47, + ENET1_RD0 = 48, + ENET1_RD1 = 49, + ENET1_RD2 = 50, + ENET1_RD3 = 51, + ENET2_MDC = 52, + ENET2_MDIO = 53, + ENET2_TD3 = 54, + ENET2_TD2 = 55, + ENET2_TD1 = 56, + ENET2_TD0 = 57, + ENET2_TX_CTL = 58, + ENET2_TXC = 59, + ENET2_RX_CTL = 60, + ENET2_RXC = 61, + ENET2_RD0 = 62, + ENET2_RD1 = 63, + ENET2_RD2 = 64, + ENET2_RD3 = 65, + SD1_CLK = 66, + SD1_CMD = 67, + SD1_DATA0 = 68, + SD1_DATA1 = 69, + SD1_DATA2 = 70, + SD1_DATA3 = 71, + SD1_DATA4 = 72, + SD1_DATA5 = 73, + SD1_DATA6 = 74, + SD1_DATA7 = 75, + SD1_STROBE = 76, + SD2_VSELECT = 77, + SD3_CLK = 78, + SD3_CMD = 79, + SD3_DATA0 = 80, + SD3_DATA1 = 81, + SD3_DATA2 = 82, + SD3_DATA3 = 83, + SD2_CD_B = 84, + SD2_CLK = 85, + SD2_CMD = 86, + SD2_DATA0 = 87, + SD2_DATA1 = 88, + SD2_DATA2 = 89, + SD2_DATA3 = 90, + SD2_RESET_B = 91, + I2C1_SCL = 92, + I2C1_SDA = 93, + I2C2_SCL = 94, + I2C2_SDA = 95, + UART1_RXD = 96, + UART1_TXD = 97, + UART2_RXD = 98, + UART2_TXD = 99, + PDM_CLK = 100, + PDM_BIT_STREAM0 = 101, + PDM_BIT_STREAM1 = 102, + SAI1_TXFS = 103, + SAI1_TXC = 104, + SAI1_TXD0 = 105, + SAI1_RXD0 = 106, + WDOG_ANY = 107, +}; + +static const struct imx_pinctrl_pin_desc imx9_pinctrl_pads[] = { + IMX_PINCTRL_PIN(DAP_TDI), + IMX_PINCTRL_PIN(DAP_TMS_SWDIO), + IMX_PINCTRL_PIN(DAP_TCLK_SWCLK), + IMX_PINCTRL_PIN(DAP_TDO_TRACESWO), + IMX_PINCTRL_PIN(GPIO_IO00), + IMX_PINCTRL_PIN(GPIO_IO01), + IMX_PINCTRL_PIN(GPIO_IO02), + IMX_PINCTRL_PIN(GPIO_IO03), + IMX_PINCTRL_PIN(GPIO_IO04), + IMX_PINCTRL_PIN(GPIO_IO05), + IMX_PINCTRL_PIN(GPIO_IO06), + IMX_PINCTRL_PIN(GPIO_IO07), + IMX_PINCTRL_PIN(GPIO_IO08), + IMX_PINCTRL_PIN(GPIO_IO09), + IMX_PINCTRL_PIN(GPIO_IO10), + IMX_PINCTRL_PIN(GPIO_IO11), + IMX_PINCTRL_PIN(GPIO_IO12), + IMX_PINCTRL_PIN(GPIO_IO13), + IMX_PINCTRL_PIN(GPIO_IO14), + IMX_PINCTRL_PIN(GPIO_IO15), + IMX_PINCTRL_PIN(GPIO_IO16), + IMX_PINCTRL_PIN(GPIO_IO17), + IMX_PINCTRL_PIN(GPIO_IO18), + IMX_PINCTRL_PIN(GPIO_IO19), + IMX_PINCTRL_PIN(GPIO_IO20), + IMX_PINCTRL_PIN(GPIO_IO21), + IMX_PINCTRL_PIN(GPIO_IO22), + IMX_PINCTRL_PIN(GPIO_IO23), + IMX_PINCTRL_PIN(GPIO_IO24), + IMX_PINCTRL_PIN(GPIO_IO25), + IMX_PINCTRL_PIN(GPIO_IO26), + IMX_PINCTRL_PIN(GPIO_IO27), + IMX_PINCTRL_PIN(GPIO_IO28), + IMX_PINCTRL_PIN(GPIO_IO29), + IMX_PINCTRL_PIN(CCM_CLKO1), + IMX_PINCTRL_PIN(CCM_CLKO2), + IMX_PINCTRL_PIN(CCM_CLKO3), + IMX_PINCTRL_PIN(CCM_CLKO4), + IMX_PINCTRL_PIN(ENET1_MDC), + IMX_PINCTRL_PIN(ENET1_MDIO), + IMX_PINCTRL_PIN(ENET1_TD3), + IMX_PINCTRL_PIN(ENET1_TD2), + IMX_PINCTRL_PIN(ENET1_TD1), + IMX_PINCTRL_PIN(ENET1_TD0), + IMX_PINCTRL_PIN(ENET1_TX_CTL), + IMX_PINCTRL_PIN(ENET1_TXC), + IMX_PINCTRL_PIN(ENET1_RX_CTL), + IMX_PINCTRL_PIN(ENET1_RXC), + IMX_PINCTRL_PIN(ENET1_RD0), + IMX_PINCTRL_PIN(ENET1_RD1), + IMX_PINCTRL_PIN(ENET1_RD2), + IMX_PINCTRL_PIN(ENET1_RD3), + IMX_PINCTRL_PIN(ENET2_MDC), + IMX_PINCTRL_PIN(ENET2_MDIO), + IMX_PINCTRL_PIN(ENET2_TD3), + IMX_PINCTRL_PIN(ENET2_TD2), + IMX_PINCTRL_PIN(ENET2_TD1), + IMX_PINCTRL_PIN(ENET2_TD0), + IMX_PINCTRL_PIN(ENET2_TX_CTL), + IMX_PINCTRL_PIN(ENET2_TXC), + IMX_PINCTRL_PIN(ENET2_RX_CTL), + IMX_PINCTRL_PIN(ENET2_RXC), + IMX_PINCTRL_PIN(ENET2_RD0), + IMX_PINCTRL_PIN(ENET2_RD1), + IMX_PINCTRL_PIN(ENET2_RD2), + IMX_PINCTRL_PIN(ENET2_RD3), + IMX_PINCTRL_PIN(SD1_CLK), + IMX_PINCTRL_PIN(SD1_CMD), + IMX_PINCTRL_PIN(SD1_DATA0), + IMX_PINCTRL_PIN(SD1_DATA1), + IMX_PINCTRL_PIN(SD1_DATA2), + IMX_PINCTRL_PIN(SD1_DATA3), + IMX_PINCTRL_PIN(SD1_DATA4), + IMX_PINCTRL_PIN(SD1_DATA5), + IMX_PINCTRL_PIN(SD1_DATA6), + IMX_PINCTRL_PIN(SD1_DATA7), + IMX_PINCTRL_PIN(SD1_STROBE), + IMX_PINCTRL_PIN(SD2_VSELECT), + IMX_PINCTRL_PIN(SD3_CLK), + IMX_PINCTRL_PIN(SD3_CMD), + IMX_PINCTRL_PIN(SD3_DATA0), + IMX_PINCTRL_PIN(SD3_DATA1), + IMX_PINCTRL_PIN(SD3_DATA2), + IMX_PINCTRL_PIN(SD3_DATA3), + IMX_PINCTRL_PIN(SD2_CD_B), + IMX_PINCTRL_PIN(SD2_CLK), + IMX_PINCTRL_PIN(SD2_CMD), + IMX_PINCTRL_PIN(SD2_DATA0), + IMX_PINCTRL_PIN(SD2_DATA1), + IMX_PINCTRL_PIN(SD2_DATA2), + IMX_PINCTRL_PIN(SD2_DATA3), + IMX_PINCTRL_PIN(SD2_RESET_B), + IMX_PINCTRL_PIN(I2C1_SCL), + IMX_PINCTRL_PIN(I2C1_SDA), + IMX_PINCTRL_PIN(I2C2_SCL), + IMX_PINCTRL_PIN(I2C2_SDA), + IMX_PINCTRL_PIN(UART1_RXD), + IMX_PINCTRL_PIN(UART1_TXD), + IMX_PINCTRL_PIN(UART2_RXD), + IMX_PINCTRL_PIN(UART2_TXD), + IMX_PINCTRL_PIN(PDM_CLK), + IMX_PINCTRL_PIN(PDM_BIT_STREAM0), + IMX_PINCTRL_PIN(PDM_BIT_STREAM1), + IMX_PINCTRL_PIN(SAI1_TXFS), + IMX_PINCTRL_PIN(SAI1_TXC), + IMX_PINCTRL_PIN(SAI1_TXD0), + IMX_PINCTRL_PIN(SAI1_RXD0), + IMX_PINCTRL_PIN(WDOG_ANY), +}; diff --git a/drivers/pinctrl/nxp/pinctrl-imx93.c b/drivers/pinctrl/nxp/pinctrl-imx93.c index 5d250db1081..d13969856f6 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx93.c +++ b/drivers/pinctrl/nxp/pinctrl-imx93.c @@ -1,34 +1,228 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2022 NXP + * Copyright 2026 NXP */ -#include <dm/device.h> -#include <dm/pinctrl.h> - #include "pinctrl-imx.h" -static struct imx_pinctrl_soc_info imx93_pinctrl_soc_info __section(".data") = { - .flags = ZERO_OFFSET_VALID, -}; - -static const struct udevice_id imx93_pinctrl_match[] = { - { .compatible = "fsl,imx93-iomuxc", .data = (ulong)&imx93_pinctrl_soc_info }, - { .compatible = "fsl,imx91-iomuxc", .data = (ulong)&imx93_pinctrl_soc_info }, - { /* sentinel */ } -}; - -static const struct pinctrl_ops imx93_pinctrl_ops = { - .set_state = imx_pinctrl_set_state_mmio, +enum imx93_pads { + DAP_TDI = 0, + DAP_TMS_SWDIO = 1, + DAP_TCLK_SWCLK = 2, + DAP_TDO_TRACESWO = 3, + GPIO_IO00 = 4, + GPIO_IO01 = 5, + GPIO_IO02 = 6, + GPIO_IO03 = 7, + GPIO_IO04 = 8, + GPIO_IO05 = 9, + GPIO_IO06 = 10, + GPIO_IO07 = 11, + GPIO_IO08 = 12, + GPIO_IO09 = 13, + GPIO_IO10 = 14, + GPIO_IO11 = 15, + GPIO_IO12 = 16, + GPIO_IO13 = 17, + GPIO_IO14 = 18, + GPIO_IO15 = 19, + GPIO_IO16 = 20, + GPIO_IO17 = 21, + GPIO_IO18 = 22, + GPIO_IO19 = 23, + GPIO_IO20 = 24, + GPIO_IO21 = 25, + GPIO_IO22 = 26, + GPIO_IO23 = 27, + GPIO_IO24 = 28, + GPIO_IO25 = 29, + GPIO_IO26 = 30, + GPIO_IO27 = 31, + GPIO_IO28 = 32, + GPIO_IO29 = 33, + CCM_CLKO1 = 34, + CCM_CLKO2 = 35, + CCM_CLKO3 = 36, + CCM_CLKO4 = 37, + ENET1_MDC = 38, + ENET1_MDIO = 39, + ENET1_TD3 = 40, + ENET1_TD2 = 41, + ENET1_TD1 = 42, + ENET1_TD0 = 43, + ENET1_TX_CTL = 44, + ENET1_TXC = 45, + ENET1_RX_CTL = 46, + ENET1_RXC = 47, + ENET1_RD0 = 48, + ENET1_RD1 = 49, + ENET1_RD2 = 50, + ENET1_RD3 = 51, + ENET2_MDC = 52, + ENET2_MDIO = 53, + ENET2_TD3 = 54, + ENET2_TD2 = 55, + ENET2_TD1 = 56, + ENET2_TD0 = 57, + ENET2_TX_CTL = 58, + ENET2_TXC = 59, + ENET2_RX_CTL = 60, + ENET2_RXC = 61, + ENET2_RD0 = 62, + ENET2_RD1 = 63, + ENET2_RD2 = 64, + ENET2_RD3 = 65, + SD1_CLK = 66, + SD1_CMD = 67, + SD1_DATA0 = 68, + SD1_DATA1 = 69, + SD1_DATA2 = 70, + SD1_DATA3 = 71, + SD1_DATA4 = 72, + SD1_DATA5 = 73, + SD1_DATA6 = 74, + SD1_DATA7 = 75, + SD1_STROBE = 76, + SD2_VSELECT = 77, + SD3_CLK = 78, + SD3_CMD = 79, + SD3_DATA0 = 80, + SD3_DATA1 = 81, + SD3_DATA2 = 82, + SD3_DATA3 = 83, + SD2_CD_B = 84, + SD2_CLK = 85, + SD2_CMD = 86, + SD2_DATA0 = 87, + SD2_DATA1 = 88, + SD2_DATA2 = 89, + SD2_DATA3 = 90, + SD2_RESET_B = 91, + I2C1_SCL = 92, + I2C1_SDA = 93, + I2C2_SCL = 94, + I2C2_SDA = 95, + UART1_RXD = 96, + UART1_TXD = 97, + UART2_RXD = 98, + UART2_TXD = 99, + PDM_CLK = 100, + PDM_BIT_STREAM0 = 101, + PDM_BIT_STREAM1 = 102, + SAI1_TXFS = 103, + SAI1_TXC = 104, + SAI1_TXD0 = 105, + SAI1_RXD0 = 106, + WDOG_ANY = 107, }; -U_BOOT_DRIVER(imx93_pinctrl) = { - .name = "imx93-pinctrl", - .id = UCLASS_PINCTRL, - .of_match = of_match_ptr(imx93_pinctrl_match), - .probe = imx_pinctrl_probe_mmio, - .remove = imx_pinctrl_remove_mmio, - .priv_auto = sizeof(struct imx_pinctrl_priv), - .ops = &imx93_pinctrl_ops, - .flags = DM_FLAG_PRE_RELOC, +static const struct imx_pinctrl_pin_desc imx9_pinctrl_pads[] = { + IMX_PINCTRL_PIN(DAP_TDI), + IMX_PINCTRL_PIN(DAP_TMS_SWDIO), + IMX_PINCTRL_PIN(DAP_TCLK_SWCLK), + IMX_PINCTRL_PIN(DAP_TDO_TRACESWO), + IMX_PINCTRL_PIN(GPIO_IO00), + IMX_PINCTRL_PIN(GPIO_IO01), + IMX_PINCTRL_PIN(GPIO_IO02), + IMX_PINCTRL_PIN(GPIO_IO03), + IMX_PINCTRL_PIN(GPIO_IO04), + IMX_PINCTRL_PIN(GPIO_IO05), + IMX_PINCTRL_PIN(GPIO_IO06), + IMX_PINCTRL_PIN(GPIO_IO07), + IMX_PINCTRL_PIN(GPIO_IO08), + IMX_PINCTRL_PIN(GPIO_IO09), + IMX_PINCTRL_PIN(GPIO_IO10), + IMX_PINCTRL_PIN(GPIO_IO11), + IMX_PINCTRL_PIN(GPIO_IO12), + IMX_PINCTRL_PIN(GPIO_IO13), + IMX_PINCTRL_PIN(GPIO_IO14), + IMX_PINCTRL_PIN(GPIO_IO15), + IMX_PINCTRL_PIN(GPIO_IO16), + IMX_PINCTRL_PIN(GPIO_IO17), + IMX_PINCTRL_PIN(GPIO_IO18), + IMX_PINCTRL_PIN(GPIO_IO19), + IMX_PINCTRL_PIN(GPIO_IO20), + IMX_PINCTRL_PIN(GPIO_IO21), + IMX_PINCTRL_PIN(GPIO_IO22), + IMX_PINCTRL_PIN(GPIO_IO23), + IMX_PINCTRL_PIN(GPIO_IO24), + IMX_PINCTRL_PIN(GPIO_IO25), + IMX_PINCTRL_PIN(GPIO_IO26), + IMX_PINCTRL_PIN(GPIO_IO27), + IMX_PINCTRL_PIN(GPIO_IO28), + IMX_PINCTRL_PIN(GPIO_IO29), + IMX_PINCTRL_PIN(CCM_CLKO1), + IMX_PINCTRL_PIN(CCM_CLKO2), + IMX_PINCTRL_PIN(CCM_CLKO3), + IMX_PINCTRL_PIN(CCM_CLKO4), + IMX_PINCTRL_PIN(ENET1_MDC), + IMX_PINCTRL_PIN(ENET1_MDIO), + IMX_PINCTRL_PIN(ENET1_TD3), + IMX_PINCTRL_PIN(ENET1_TD2), + IMX_PINCTRL_PIN(ENET1_TD1), + IMX_PINCTRL_PIN(ENET1_TD0), + IMX_PINCTRL_PIN(ENET1_TX_CTL), + IMX_PINCTRL_PIN(ENET1_TXC), + IMX_PINCTRL_PIN(ENET1_RX_CTL), + IMX_PINCTRL_PIN(ENET1_RXC), + IMX_PINCTRL_PIN(ENET1_RD0), + IMX_PINCTRL_PIN(ENET1_RD1), + IMX_PINCTRL_PIN(ENET1_RD2), + IMX_PINCTRL_PIN(ENET1_RD3), + IMX_PINCTRL_PIN(ENET2_MDC), + IMX_PINCTRL_PIN(ENET2_MDIO), + IMX_PINCTRL_PIN(ENET2_TD3), + IMX_PINCTRL_PIN(ENET2_TD2), + IMX_PINCTRL_PIN(ENET2_TD1), + IMX_PINCTRL_PIN(ENET2_TD0), + IMX_PINCTRL_PIN(ENET2_TX_CTL), + IMX_PINCTRL_PIN(ENET2_TXC), + IMX_PINCTRL_PIN(ENET2_RX_CTL), + IMX_PINCTRL_PIN(ENET2_RXC), + IMX_PINCTRL_PIN(ENET2_RD0), + IMX_PINCTRL_PIN(ENET2_RD1), + IMX_PINCTRL_PIN(ENET2_RD2), + IMX_PINCTRL_PIN(ENET2_RD3), + IMX_PINCTRL_PIN(SD1_CLK), + IMX_PINCTRL_PIN(SD1_CMD), + IMX_PINCTRL_PIN(SD1_DATA0), + IMX_PINCTRL_PIN(SD1_DATA1), + IMX_PINCTRL_PIN(SD1_DATA2), + IMX_PINCTRL_PIN(SD1_DATA3), + IMX_PINCTRL_PIN(SD1_DATA4), + IMX_PINCTRL_PIN(SD1_DATA5), + IMX_PINCTRL_PIN(SD1_DATA6), + IMX_PINCTRL_PIN(SD1_DATA7), + IMX_PINCTRL_PIN(SD1_STROBE), + IMX_PINCTRL_PIN(SD2_VSELECT), + IMX_PINCTRL_PIN(SD3_CLK), + IMX_PINCTRL_PIN(SD3_CMD), + IMX_PINCTRL_PIN(SD3_DATA0), + IMX_PINCTRL_PIN(SD3_DATA1), + IMX_PINCTRL_PIN(SD3_DATA2), + IMX_PINCTRL_PIN(SD3_DATA3), + IMX_PINCTRL_PIN(SD2_CD_B), + IMX_PINCTRL_PIN(SD2_CLK), + IMX_PINCTRL_PIN(SD2_CMD), + IMX_PINCTRL_PIN(SD2_DATA0), + IMX_PINCTRL_PIN(SD2_DATA1), + IMX_PINCTRL_PIN(SD2_DATA2), + IMX_PINCTRL_PIN(SD2_DATA3), + IMX_PINCTRL_PIN(SD2_RESET_B), + IMX_PINCTRL_PIN(I2C1_SCL), + IMX_PINCTRL_PIN(I2C1_SDA), + IMX_PINCTRL_PIN(I2C2_SCL), + IMX_PINCTRL_PIN(I2C2_SDA), + IMX_PINCTRL_PIN(UART1_RXD), + IMX_PINCTRL_PIN(UART1_TXD), + IMX_PINCTRL_PIN(UART2_RXD), + IMX_PINCTRL_PIN(UART2_TXD), + IMX_PINCTRL_PIN(PDM_CLK), + IMX_PINCTRL_PIN(PDM_BIT_STREAM0), + IMX_PINCTRL_PIN(PDM_BIT_STREAM1), + IMX_PINCTRL_PIN(SAI1_TXFS), + IMX_PINCTRL_PIN(SAI1_TXC), + IMX_PINCTRL_PIN(SAI1_TXD0), + IMX_PINCTRL_PIN(SAI1_RXD0), + IMX_PINCTRL_PIN(WDOG_ANY), }; diff --git a/drivers/pinctrl/nxp/pinctrl-mxs.c b/drivers/pinctrl/nxp/pinctrl-mxs.c index 85ab5fdf640..8b764738014 100644 --- a/drivers/pinctrl/nxp/pinctrl-mxs.c +++ b/drivers/pinctrl/nxp/pinctrl-mxs.c @@ -5,7 +5,6 @@ */ #include <log.h> -#include <asm/global_data.h> #include <dm/device_compat.h> #include <dm/devres.h> #include <linux/io.h> @@ -15,8 +14,6 @@ #include <dm/read.h> #include "pinctrl-mxs.h" -DECLARE_GLOBAL_DATA_PTR; - struct mxs_pinctrl_priv { void __iomem *base; const struct mxs_regs *regs; diff --git a/drivers/pinctrl/pinctrl-scmi.c b/drivers/pinctrl/pinctrl-scmi.c new file mode 100644 index 00000000000..63d4f8ffeb5 --- /dev/null +++ b/drivers/pinctrl/pinctrl-scmi.c @@ -0,0 +1,365 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 Linaro Ltd. + */ + +#include <dm.h> +#include <dm/device_compat.h> +#include <dm/devres.h> +#include <dm/pinctrl.h> +#include <scmi_agent.h> +#include <scmi_agent-uclass.h> +#include <scmi_protocols.h> + +static const struct pinconf_param pinctrl_scmi_conf_params[] = { + { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0}, + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, + { "bias-high-impedance", PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0 }, + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 0 }, + { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 0 }, + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 0 }, + { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 }, + { "drive-open-source", PIN_CONFIG_DRIVE_OPEN_SOURCE, 0 }, + { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 }, + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, + { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, + { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, + { "input-schmitt", PIN_CONFIG_INPUT_SCHMITT, 0 }, + { "low-power-mode", PIN_CONFIG_LOW_POWER_MODE, 0 }, + { "output-mode", PIN_CONFIG_OUTPUT_ENABLE, 0 }, + { "output-value", PIN_CONFIG_OUTPUT, 0 }, + { "power-source", PIN_CONFIG_POWER_SOURCE, 0 }, + { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, + /* The SCMI spec also include "default", "pull-mode" and "input-value */ +}; + +static bool valid_selector(struct udevice *dev, enum select_type select_type, u32 selector) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + if (select_type == SCMI_PIN) + return selector < priv->num_pins; + if (select_type == SCMI_GROUP) + return selector < priv->num_groups; + if (select_type == SCMI_FUNCTION) + return selector < priv->num_functions; + + return false; +} + +static int pinctrl_scmi_get_pins_count(struct udevice *dev) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + return priv->num_pins; +} + +static int pinctrl_scmi_get_groups_count(struct udevice *dev) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + return priv->num_groups; +} + +static int pinctrl_scmi_get_functions_count(struct udevice *dev) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + return priv->num_functions; +} + +static const char *pinctrl_scmi_get_pin_name(struct udevice *dev, unsigned int selector) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + if (selector >= priv->num_pins) + return NULL; + + return (const char *)priv->pin_info[selector].name; +} + +static const char *pinctrl_scmi_get_group_name(struct udevice *dev, unsigned int selector) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + if (selector >= priv->num_groups) + return NULL; + + return (const char *)priv->group_info[selector].name; +} + +static const char *pinctrl_scmi_get_function_name(struct udevice *dev, unsigned int selector) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + if (selector >= priv->num_functions) + return NULL; + + return (const char *)priv->function_info[selector].name; +} + +static int pinctrl_scmi_pinmux_set(struct udevice *dev, u32 pin, u32 function) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + if (pin >= priv->num_pins || function >= priv->num_functions) + return -EINVAL; + + return scmi_pinctrl_set_function(dev, SCMI_PIN, pin, function); +} + +static int pinctrl_scmi_pinmux_group_set(struct udevice *dev, u32 group, u32 function) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + if (group >= priv->num_groups || function >= priv->num_functions) + return -EINVAL; + + return scmi_pinctrl_set_function(dev, SCMI_GROUP, group, function); +} + +static int pinctrl_scmi_set_state(struct udevice *dev, struct udevice *config) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + /* batch the setup into 20 lines at a go (there are 5 u32s in a config) */ + const int batch_count = 20 * 5; + u32 prev_type = -1u; + u32 prev_selector; + u32 *configs; + const u32 *prop; + int offset, cnt, len; + int ret = 0; + + prop = dev_read_prop(config, "pinmux", &len); + if (!prop) + return 0; + + if (len % sizeof(u32) * 5) { + dev_err(dev, "invalid pin configuration: len=%d\n", len); + return -FDT_ERR_BADSTRUCTURE; + } + + configs = kcalloc(batch_count, sizeof(u32), GFP_KERNEL); + if (!configs) + return -ENOMEM; + + offset = 0; + cnt = 0; + while (offset + 4 < len / sizeof(u32)) { + u32 select_type = fdt32_to_cpu(prop[offset]); + u32 selector = fdt32_to_cpu(prop[offset + 1]); + u32 function = fdt32_to_cpu(prop[offset + 2]); + u32 config_type = fdt32_to_cpu(prop[offset + 3]); + u32 config_value = fdt32_to_cpu(prop[offset + 4]); + + if (select_type > SCMI_GROUP || + !valid_selector(dev, select_type, selector) || + (function != SCMI_PINCTRL_FUNCTION_NONE && + function > priv->num_functions)) { + dev_err(dev, "invalid pinctrl data (%u %u %u %u %u)\n", + select_type, selector, function, config_type, + config_value); + ret = -EINVAL; + goto free; + } + + if (function != SCMI_PINCTRL_FUNCTION_NONE) { + if (cnt) { + ret = scmi_pinctrl_settings_configure(dev, + prev_type, + prev_selector, + cnt / 2, configs); + if (ret) + goto free; + prev_type = -1u; + cnt = 0; + } + scmi_pinctrl_set_function(dev, select_type, selector, function); + offset += 5; + continue; + } + + if (cnt == batch_count) + goto set; + + if (prev_type == -1u) + goto store; + + if (select_type == prev_type && selector == prev_selector) + goto store; +set: + ret = scmi_pinctrl_settings_configure(dev, prev_type, prev_selector, + cnt / 2, configs); + if (ret) + goto free; + cnt = 0; +store: + prev_type = select_type; + prev_selector = selector; + configs[cnt++] = config_type; + configs[cnt++] = config_value; + offset += 5; + } + + if (cnt) + ret = scmi_pinctrl_settings_configure(dev, prev_type, prev_selector, + cnt / 2, configs); +free: + kfree(configs); + if (ret) + dev_err(dev, "set_state() failed: %d\n", ret); + + return ret; +} + +static int get_pin_muxing(struct udevice *dev, unsigned int selector, + char *buf, int size) +{ + u32 value; + int ret; + + ret = scmi_pinctrl_settings_get_one(dev, SCMI_PIN, selector, + SCMI_PIN_INPUT_VALUE, &value); + if (ret) { + dev_err(dev, "settings_get() failed: %d\n", ret); + return ret; + } + + snprintf(buf, size, "%d", value); + return 0; +} + +static int pinctrl_scmi_pinconf_set(struct udevice *dev, u32 pin, u32 param, u32 argument) +{ + return scmi_pinctrl_settings_configure_one(dev, SCMI_PIN, pin, param, argument); +} + +static int pinctrl_scmi_pinconf_group_set(struct udevice *dev, u32 group, u32 param, u32 argument) +{ + return scmi_pinctrl_settings_configure_one(dev, SCMI_GROUP, group, param, argument); +} + +static struct pinctrl_ops scmi_pinctrl_ops = { + .get_pins_count = pinctrl_scmi_get_pins_count, + .get_pin_name = pinctrl_scmi_get_pin_name, + + .get_groups_count = pinctrl_scmi_get_groups_count, + .get_group_name = pinctrl_scmi_get_group_name, + + .get_functions_count = pinctrl_scmi_get_functions_count, + .get_function_name = pinctrl_scmi_get_function_name, + + .pinmux_set = pinctrl_scmi_pinmux_set, + .pinmux_group_set = pinctrl_scmi_pinmux_group_set, + + .pinconf_num_params = ARRAY_SIZE(pinctrl_scmi_conf_params), + .pinconf_params = pinctrl_scmi_conf_params, + + .pinconf_set = pinctrl_scmi_pinconf_set, + .pinconf_group_set = pinctrl_scmi_pinconf_group_set, + .set_state = pinctrl_scmi_set_state, + .get_pin_muxing = get_pin_muxing, +}; + +static int scmi_pinctrl_probe(struct udevice *dev) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + int ret; + int i; + + ret = devm_scmi_of_get_channel(dev); + if (ret) { + dev_err(dev, "get_channel() failed: %d\n", ret); + return ret; + } + + ret = scmi_pinctrl_protocol_attrs(dev, &priv->num_pins, + &priv->num_groups, + &priv->num_functions); + if (ret) { + dev_err(dev, "failed to get protocol attributes: %d\n", ret); + return ret; + } + + priv->pin_info = devm_kcalloc(dev, priv->num_pins, + sizeof(*priv->pin_info), GFP_KERNEL); + priv->group_info = devm_kcalloc(dev, priv->num_groups, + sizeof(*priv->group_info), GFP_KERNEL); + priv->function_info = devm_kcalloc(dev, priv->num_functions, + sizeof(*priv->function_info), GFP_KERNEL); + if (!priv->pin_info || !priv->group_info || !priv->function_info) + return -ENOMEM; + + for (i = 0; i < priv->num_pins; i++) { + ret = scmi_pinctrl_attrs(dev, SCMI_PIN, i, NULL, NULL, + priv->pin_info[i].name); + if (ret) + return ret; + } + + for (i = 0; i < priv->num_groups; i++) { + ret = scmi_pinctrl_attrs(dev, SCMI_GROUP, i, NULL, + &priv->group_info[i].num_pins, + priv->group_info[i].name); + if (ret) { + dev_err(dev, "loading group %d failed: %d\n", i, ret); + return ret; + } + priv->group_info[i].pins = devm_kcalloc(dev, + priv->group_info[i].num_pins, + sizeof(*priv->group_info[i].pins), + GFP_KERNEL); + if (!priv->group_info[i].pins) + return -ENOMEM; + + ret = scmi_pinctrl_list_associations(dev, SCMI_GROUP, i, + priv->group_info[i].pins, + priv->group_info[i].num_pins); + if (ret) { + dev_err(dev, "list association %d failed for group: %d\n", i, ret); + return ret; + } + } + + for (i = 0; i < priv->num_functions; i++) { + ret = scmi_pinctrl_attrs(dev, SCMI_FUNCTION, i, NULL, + &priv->function_info[i].num_groups, + priv->function_info[i].name); + if (ret) { + dev_err(dev, "loading function %d failed: %d\n", i, ret); + return ret; + } + priv->function_info[i].groups = devm_kcalloc(dev, + priv->function_info[i].num_groups, + sizeof(*priv->function_info[i].groups), + GFP_KERNEL); + if (!priv->function_info[i].groups) + return -ENOMEM; + + ret = scmi_pinctrl_list_associations(dev, SCMI_FUNCTION, i, + priv->function_info[i].groups, + priv->function_info[i].num_groups); + if (ret) { + dev_err(dev, "list association %d failed for function: %d\n", i, ret); + return ret; + } + } + + return 0; +} + +U_BOOT_DRIVER(pinctrl_scmi) = { + .name = "scmi_pinctrl", + .id = UCLASS_PINCTRL, + .ops = &scmi_pinctrl_ops, + .probe = scmi_pinctrl_probe, + .priv_auto = sizeof(struct pinctrl_scmi_priv), +}; + +static struct scmi_proto_match match[] = { + { .proto_id = SCMI_PROTOCOL_ID_PINCTRL }, + { /* Sentinel */ } +}; + +U_BOOT_SCMI_PROTO_DRIVER(pinctrl_scmi, match); + diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index 7c11ac4c8b8..0b936684f8a 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -19,15 +19,11 @@ #include <linux/compat.h> #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> -#define PINCTRL_GET_FUNC_GROUPS_RESP_LEN 12 -#define PINCTRL_GET_PIN_GROUPS_RESP_LEN 12 -#define NUM_GROUPS_PER_RESP 6 -#define NA_GROUP -1 -#define RESERVED_GROUP -2 +#define PINCTRL_GET_FUNC_GROUPS_RESP_LEN (sizeof(s16) * NUM_GROUPS_PER_RESP) +#define PINCTRL_GET_PIN_GROUPS_RESP_LEN (sizeof(s16) * NUM_GROUPS_PER_RESP) #define MAX_GROUP_PIN 50 #define MAX_PIN_GROUPS 50 #define MAX_GROUP_NAME_LEN 32 -#define MAX_FUNC_NAME_LEN 16 #define DRIVE_STRENGTH_2MA 2 #define DRIVE_STRENGTH_4MA 4 diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile index e17415e1ca6..0405df128df 100644 --- a/drivers/pinctrl/rockchip/Makefile +++ b/drivers/pinctrl/rockchip/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl-rk3308.o obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o +obj-$(CONFIG_ROCKCHIP_RK3506) += pinctrl-rk3506.o obj-$(CONFIG_ROCKCHIP_RK3528) += pinctrl-rk3528.o obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o obj-$(CONFIG_ROCKCHIP_RK3576) += pinctrl-rk3576.o diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3506.c b/drivers/pinctrl/rockchip/pinctrl-rk3506.c new file mode 100644 index 00000000000..969acb66f15 --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl-rk3506.c @@ -0,0 +1,462 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#include <dm.h> +#include <dm/pinctrl.h> +#include <regmap.h> +#include <syscon.h> + +#include "pinctrl-rockchip.h" +#include <dt-bindings/pinctrl/rockchip.h> + +static int rk3506_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, mask; + u8 bit; + u32 data, rmask; + + if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + regmap = priv->regmap_pmu; + else + regmap = priv->regmap_base; + + if (bank->bank_num == 1) + regmap = priv->regmap_ioc1; + else if (bank->bank_num == 4) + return 0; + + reg = bank->iomux[iomux_num].offset; + if ((pin % 8) >= 4) + reg += 0x4; + bit = (pin % 4) * 4; + mask = 0xf; + + if (bank->recalced_mask & BIT(pin)) + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); + + data = (mask << (bit + 16)); + rmask = data | (data >> 16); + data |= (mux & mask) << bit; + + return regmap_update_bits(regmap, reg, rmask, data); +} + +#define RK3506_DRV_BITS_PER_PIN 8 +#define RK3506_DRV_PINS_PER_REG 2 +#define RK3506_DRV_GPIO0_A_OFFSET 0x100 +#define RK3506_DRV_GPIO0_D_OFFSET 0x830 +#define RK3506_DRV_GPIO1_OFFSET 0x140 +#define RK3506_DRV_GPIO2_OFFSET 0x180 +#define RK3506_DRV_GPIO3_OFFSET 0x1c0 +#define RK3506_DRV_GPIO4_OFFSET 0x840 + +static int rk3506_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int ret = 0; + + switch (bank->bank_num) { + case 0: + *regmap = priv->regmap_pmu; + if (pin_num > 24) { + ret = -EINVAL; + } else if (pin_num < 24) { + *reg = RK3506_DRV_GPIO0_A_OFFSET; + } else { + *reg = RK3506_DRV_GPIO0_D_OFFSET; + *bit = 3; + + return 0; + } + break; + + case 1: + *regmap = priv->regmap_ioc1; + if (pin_num < 28) + *reg = RK3506_DRV_GPIO1_OFFSET; + else + ret = -EINVAL; + break; + + case 2: + *regmap = priv->regmap_base; + if (pin_num < 17) + *reg = RK3506_DRV_GPIO2_OFFSET; + else + ret = -EINVAL; + break; + + case 3: + *regmap = priv->regmap_base; + if (pin_num < 15) + *reg = RK3506_DRV_GPIO3_OFFSET; + else + ret = -EINVAL; + break; + + case 4: + *regmap = priv->regmap_base; + if (pin_num < 8 || pin_num > 11) { + ret = -EINVAL; + } else { + *reg = RK3506_DRV_GPIO4_OFFSET; + *bit = 10; + + return 0; + } + break; + + default: + ret = -EINVAL; + break; + } + + if (ret) { + debug("unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num); + return ret; + } + + *reg += ((pin_num / RK3506_DRV_PINS_PER_REG) * 4); + *bit = pin_num % RK3506_DRV_PINS_PER_REG; + *bit *= RK3506_DRV_BITS_PER_PIN; + + return 0; +} + +static int rk3506_set_drive(struct rockchip_pin_bank *bank, + int pin_num, int strength) +{ + struct regmap *regmap; + int reg, ret, i; + u32 data, rmask; + u8 bit; + int rmask_bits = RK3506_DRV_BITS_PER_PIN; + + ret = rk3506_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); + if (ret) + return ret; + + for (i = 0, ret = 1; i < strength; i++) + ret = (ret << 1) | 1; + + if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) { + rmask_bits = 2; + ret = strength; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << rmask_bits) - 1) << (bit + 16); + rmask = data | (data >> 16); + data |= (ret << bit); + + return regmap_update_bits(regmap, reg, rmask, data); +} + +#define RK3506_PULL_BITS_PER_PIN 2 +#define RK3506_PULL_PINS_PER_REG 8 +#define RK3506_PULL_GPIO0_A_OFFSET 0x200 +#define RK3506_PULL_GPIO0_D_OFFSET 0x830 +#define RK3506_PULL_GPIO1_OFFSET 0x210 +#define RK3506_PULL_GPIO2_OFFSET 0x220 +#define RK3506_PULL_GPIO3_OFFSET 0x230 +#define RK3506_PULL_GPIO4_OFFSET 0x840 + +static int rk3506_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int ret = 0; + + switch (bank->bank_num) { + case 0: + *regmap = priv->regmap_pmu; + if (pin_num > 24) { + ret = -EINVAL; + } else if (pin_num < 24) { + *reg = RK3506_PULL_GPIO0_A_OFFSET; + } else { + *reg = RK3506_PULL_GPIO0_D_OFFSET; + *bit = 5; + + return 0; + } + break; + + case 1: + *regmap = priv->regmap_ioc1; + if (pin_num < 28) + *reg = RK3506_PULL_GPIO1_OFFSET; + else + ret = -EINVAL; + break; + + case 2: + *regmap = priv->regmap_base; + if (pin_num < 17) + *reg = RK3506_PULL_GPIO2_OFFSET; + else + ret = -EINVAL; + break; + + case 3: + *regmap = priv->regmap_base; + if (pin_num < 15) + *reg = RK3506_PULL_GPIO3_OFFSET; + else + ret = -EINVAL; + break; + + case 4: + *regmap = priv->regmap_base; + if (pin_num < 8 || pin_num > 11) { + ret = -EINVAL; + } else { + *reg = RK3506_PULL_GPIO4_OFFSET; + *bit = 13; + + return 0; + } + break; + + default: + ret = -EINVAL; + break; + } + + if (ret) { + debug("unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num); + return ret; + } + + *reg += ((pin_num / RK3506_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RK3506_PULL_PINS_PER_REG; + *bit *= RK3506_PULL_BITS_PER_PIN; + + return 0; +} + +static int rk3506_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit, type; + u32 data, rmask; + + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) + return -EOPNOTSUPP; + + ret = rk3506_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + if (ret) + return ret; + type = bank->pull_type[pin_num / 8]; + + if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) + type = 1; + + ret = rockchip_translate_pull_value(type, pull); + if (ret < 0) { + debug("unsupported pull setting %d\n", pull); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << RK3506_PULL_BITS_PER_PIN) - 1) << (bit + 16); + rmask = data | (data >> 16); + data |= (ret << bit); + + return regmap_update_bits(regmap, reg, rmask, data); +} + +#define RK3506_SMT_BITS_PER_PIN 1 +#define RK3506_SMT_PINS_PER_REG 8 +#define RK3506_SMT_GPIO0_A_OFFSET 0x400 +#define RK3506_SMT_GPIO0_D_OFFSET 0x830 +#define RK3506_SMT_GPIO1_OFFSET 0x410 +#define RK3506_SMT_GPIO2_OFFSET 0x420 +#define RK3506_SMT_GPIO3_OFFSET 0x430 +#define RK3506_SMT_GPIO4_OFFSET 0x840 + +static int rk3506_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int ret = 0; + + switch (bank->bank_num) { + case 0: + *regmap = priv->regmap_pmu; + if (pin_num > 24) { + ret = -EINVAL; + } else if (pin_num < 24) { + *reg = RK3506_SMT_GPIO0_A_OFFSET; + } else { + *reg = RK3506_SMT_GPIO0_D_OFFSET; + *bit = 9; + + return 0; + } + break; + + case 1: + *regmap = priv->regmap_ioc1; + if (pin_num < 28) + *reg = RK3506_SMT_GPIO1_OFFSET; + else + ret = -EINVAL; + break; + + case 2: + *regmap = priv->regmap_base; + if (pin_num < 17) + *reg = RK3506_SMT_GPIO2_OFFSET; + else + ret = -EINVAL; + break; + + case 3: + *regmap = priv->regmap_base; + if (pin_num < 15) + *reg = RK3506_SMT_GPIO3_OFFSET; + else + ret = -EINVAL; + break; + + case 4: + *regmap = priv->regmap_base; + if (pin_num < 8 || pin_num > 11) { + ret = -EINVAL; + } else { + *reg = RK3506_SMT_GPIO4_OFFSET; + *bit = 8; + + return 0; + } + break; + + default: + ret = -EINVAL; + break; + } + + if (ret) { + debug("unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num); + return ret; + } + + *reg += ((pin_num / RK3506_SMT_PINS_PER_REG) * 4); + *bit = pin_num % RK3506_SMT_PINS_PER_REG; + *bit *= RK3506_SMT_BITS_PER_PIN; + + return 0; +} + +static int rk3506_set_schmitt(struct rockchip_pin_bank *bank, + int pin_num, int enable) +{ + struct regmap *regmap; + int reg, ret; + u32 data, rmask; + u8 bit; + + ret = rk3506_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit); + if (ret) + return ret; + + /* enable the write to the equivalent lower bits */ + data = ((1 << RK3506_SMT_BITS_PER_PIN) - 1) << (bit + 16); + rmask = data | (data >> 16); + data |= (enable << bit); + + if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) { + data = 0x3 << (bit + 16); + rmask = data | (data >> 16); + data |= ((enable ? 0x3 : 0) << bit); + } + + return regmap_update_bits(regmap, reg, rmask, data); +} + +static struct rockchip_mux_recalced_data rk3506_mux_recalced_data[] = { + { + .num = 0, + .pin = 24, + .reg = 0x830, + .bit = 0, + .mask = 0x3 + }, +}; + +static struct rockchip_pin_bank rk3506_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0", + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, + IOMUX_8WIDTH_2BIT | IOMUX_SOURCE_PMU, + 0x0, 0x8, 0x10, 0x830), + PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x20, 0x28, 0x30, 0x38), + PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x40, 0x48, 0x50, 0x58), + PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x60, 0x68, 0x70, 0x78), + PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x80, 0x88, 0x90, 0x98), +}; + +static const struct rockchip_pin_ctrl rk3506_pin_ctrl = { + .pin_banks = rk3506_pin_banks, + .nr_banks = ARRAY_SIZE(rk3506_pin_banks), + .iomux_recalced = rk3506_mux_recalced_data, + .niomux_recalced = ARRAY_SIZE(rk3506_mux_recalced_data), + .set_mux = rk3506_set_mux, + .set_pull = rk3506_set_pull, + .set_drive = rk3506_set_drive, + .set_schmitt = rk3506_set_schmitt, +}; + +static const struct udevice_id rk3506_pinctrl_ids[] = { + { + .compatible = "rockchip,rk3506-pinctrl", + .data = (ulong)&rk3506_pin_ctrl + }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3506_pinctrl) = { + .name = "rockchip_rk3506_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = rk3506_pinctrl_ids, + .priv_auto = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, +#endif + .probe = rockchip_pinctrl_probe, +}; diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index 4de67aba1c3..957dcb52059 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -10,6 +10,7 @@ #include <syscon.h> #include <fdtdec.h> #include <linux/bitops.h> +#include <linux/err.h> #include <linux/libfdt.h> #include "pinctrl-rockchip.h" @@ -641,37 +642,30 @@ int rockchip_pinctrl_probe(struct udevice *dev) { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); struct rockchip_pin_ctrl *ctrl; - struct udevice *syscon; - struct regmap *regmap; - int ret = 0; - /* get rockchip grf syscon phandle */ - ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", - &syscon); - if (ret) { - debug("unable to find rockchip,grf syscon device (%d)\n", ret); - return ret; + priv->regmap_base = + syscon_regmap_lookup_by_phandle(dev, "rockchip,grf"); + if (IS_ERR(priv->regmap_base)) { + debug("unable to find rockchip,grf regmap\n"); + return PTR_ERR(priv->regmap_base); } - /* get grf-reg base address */ - regmap = syscon_get_regmap(syscon); - if (!regmap) { - debug("unable to find rockchip grf regmap\n"); - return -ENODEV; + if (dev_read_bool(dev, "rockchip,pmu")) { + priv->regmap_pmu = + syscon_regmap_lookup_by_phandle(dev, "rockchip,pmu"); + if (IS_ERR(priv->regmap_pmu)) { + debug("unable to find rockchip,pmu regmap\n"); + return PTR_ERR(priv->regmap_pmu); + } } - priv->regmap_base = regmap; - - /* option: get pmu-reg base address */ - ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu", - &syscon); - if (!ret) { - /* get pmugrf-reg base address */ - regmap = syscon_get_regmap(syscon); - if (!regmap) { - debug("unable to find rockchip pmu regmap\n"); - return -ENODEV; + + if (dev_read_bool(dev, "rockchip,ioc1")) { + priv->regmap_ioc1 = + syscon_regmap_lookup_by_phandle(dev, "rockchip,ioc1"); + if (IS_ERR(priv->regmap_ioc1)) { + debug("unable to find rockchip,ioc1 regmap\n"); + return PTR_ERR(priv->regmap_ioc1); } - priv->regmap_pmu = regmap; } ctrl = rockchip_pinctrl_get_soc_data(dev); diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h index ba684baed24..568e6024b78 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h @@ -528,6 +528,7 @@ struct rockchip_pinctrl_priv { struct rockchip_pin_ctrl *ctrl; struct regmap *regmap_base; struct regmap *regmap_pmu; + struct regmap *regmap_ioc1; }; extern const struct pinctrl_ops rockchip_pinctrl_ops; diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig index 935f282d6c5..2f63a8e54e5 100644 --- a/drivers/power/domain/Kconfig +++ b/drivers/power/domain/Kconfig @@ -20,7 +20,7 @@ config APPLE_PMGR_POWER_DOMAIN config AGILEX5_PMGR_POWER_DOMAIN bool "Enable the Agilex5 PMGR power domain driver" - depends on SPL_POWER_DOMAIN && TARGET_SOCFPGA_SOC64 + depends on SPL_POWER_DOMAIN && ARCH_SOCFPGA_SOC64 help Enable support for power gating peripherals' SRAM specified in the handoff data values obtained from the bitstream to reduce diff --git a/drivers/power/domain/imx8m-power-domain.c b/drivers/power/domain/imx8m-power-domain.c index a7e64971a2a..1c731b897cc 100644 --- a/drivers/power/domain/imx8m-power-domain.c +++ b/drivers/power/domain/imx8m-power-domain.c @@ -7,7 +7,6 @@ #include <dm.h> #include <malloc.h> #include <power-domain-uclass.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/mach-imx/sys_proto.h> #include <dm/device-internal.h> @@ -22,8 +21,6 @@ #include <dt-bindings/power/imx8mp-power.h> #include <dt-bindings/power/imx8mq-power.h> -DECLARE_GLOBAL_DATA_PTR; - #define GPC_PGC_CPU_MAPPING 0x0ec #define IMX8MP_GPC_PGC_CPU_MAPPING 0x1cc diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index b1a5b1c2a1f..5bc14842e66 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -384,7 +384,7 @@ config DM_PMIC_TPS80031 config PMIC_STPMIC1 bool "Enable support for STMicroelectronics STPMIC1 PMIC" depends on DM_I2C - select SYSRESET_CMD_POWEROFF if CMD_POWEROFF && !ARM_PSCI_FW + select SYSRESET_CMD_POWEROFF if SYSRESET && CMD_POWEROFF && !ARM_PSCI_FW ---help--- The STPMIC1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches. It is accessed via an I2C interface. The device is used with STM32MP1 @@ -433,6 +433,14 @@ config PMIC_RAA215300 support and several voltage regulators. For now, this driver simply allows register access and will bind the sysreset driver (CONFIG_SYSRESET_RAA215300) if it is enabled. + +config DM_PMIC_MTK_PWRAP + bool "Enable driver for MediaTek PMIC Wrapper Support" + help + Say yes here to add support for MediaTek PMIC Wrapper found + on different MediaTek SoCs. The PMIC wrapper is a proprietary + hardware to connect the PMIC. + endif config PMIC_TPS65217 diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 6bebffb05a6..2cda5a892fd 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_PMIC_TPS65941) += tps65941.o obj-$(CONFIG_PMIC_RAA215300) += raa215300.o obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o obj-$(CONFIG_$(PHASE_)DM_PMIC_CPCAP) += cpcap.o +obj-$(CONFIG_DM_PMIC_MTK_PWRAP) += mtk-pwrap.o ifeq ($(CONFIG_$(PHASE_)POWER_LEGACY),y) obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o diff --git a/drivers/power/pmic/bd71837.c b/drivers/power/pmic/bd71837.c index a5df2570fc3..13642794765 100644 --- a/drivers/power/pmic/bd71837.c +++ b/drivers/power/pmic/bd71837.c @@ -7,14 +7,11 @@ #include <dm.h> #include <i2c.h> #include <log.h> -#include <asm/global_data.h> #include <linux/printk.h> #include <power/pmic.h> #include <power/regulator.h> #include <power/bd71837.h> -DECLARE_GLOBAL_DATA_PTR; - static const struct pmic_child_info pmic_children_info[] = { /* buck */ { .prefix = "b", .driver = BD718XX_REGULATOR_DRIVER}, diff --git a/drivers/power/pmic/cpcap.c b/drivers/power/pmic/cpcap.c index f2076afff43..b9d783773ed 100644 --- a/drivers/power/pmic/cpcap.c +++ b/drivers/power/pmic/cpcap.c @@ -14,7 +14,9 @@ static const struct pmic_child_info pmic_children_info[] = { { .prefix = "sw", .driver = CPCAP_SW_DRIVER }, + { .prefix = "SW", .driver = CPCAP_SW_DRIVER }, { .prefix = "v", .driver = CPCAP_LDO_DRIVER }, + { .prefix = "V", .driver = CPCAP_LDO_DRIVER }, { }, }; @@ -112,6 +114,8 @@ static struct dm_pmic_ops cpcap_ops = { static const struct udevice_id cpcap_ids[] = { { .compatible = "motorola,cpcap" }, { .compatible = "st,6556002" }, + { .compatible = "motorola,mapphone-cpcap" }, + { .compatible = "motorola,mot-cpcap" }, { } }; diff --git a/drivers/power/pmic/max77663.c b/drivers/power/pmic/max77663.c index c2a7cbf7e40..a06042e2918 100644 --- a/drivers/power/pmic/max77663.c +++ b/drivers/power/pmic/max77663.c @@ -46,7 +46,9 @@ static int max77663_bind(struct udevice *dev) ofnode regulators_node; int children, ret; - if (IS_ENABLED(CONFIG_SYSRESET_MAX77663)) { + if (IS_ENABLED(CONFIG_SYSRESET_MAX77663) && + (dev_read_bool(dev, "maxim,system-power-controller") || + dev_read_bool(dev, "system-power-controller"))) { ret = device_bind_driver_to_node(dev, MAX77663_RST_DRIVER, "sysreset", dev_ofnode(dev), NULL); diff --git a/drivers/power/pmic/max8907.c b/drivers/power/pmic/max8907.c index a7ef70177de..34bef0c8cd6 100644 --- a/drivers/power/pmic/max8907.c +++ b/drivers/power/pmic/max8907.c @@ -48,7 +48,8 @@ static int max8907_bind(struct udevice *dev) int children, ret; if (IS_ENABLED(CONFIG_SYSRESET_MAX8907) && - dev_read_bool(dev, "maxim,system-power-controller")) { + (dev_read_bool(dev, "maxim,system-power-controller") || + dev_read_bool(dev, "system-power-controller"))) { ret = device_bind_driver_to_node(dev, MAX8907_RST_DRIVER, "sysreset", dev_ofnode(dev), NULL); diff --git a/drivers/power/pmic/mc34708.c b/drivers/power/pmic/mc34708.c index 43badb5767a..0ec52e25a9e 100644 --- a/drivers/power/pmic/mc34708.c +++ b/drivers/power/pmic/mc34708.c @@ -9,11 +9,8 @@ #include <errno.h> #include <fsl_pmic.h> #include <i2c.h> -#include <asm/global_data.h> #include <power/pmic.h> -DECLARE_GLOBAL_DATA_PTR; - static int mc34708_reg_count(struct udevice *dev) { return PMIC_NUM_OF_REGS; diff --git a/drivers/power/pmic/mp5416.c b/drivers/power/pmic/mp5416.c index 9d44f0ae655..899c2beeb37 100644 --- a/drivers/power/pmic/mp5416.c +++ b/drivers/power/pmic/mp5416.c @@ -9,9 +9,6 @@ #include <power/pmic.h> #include <power/regulator.h> #include <power/mp5416.h> -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; static const struct pmic_child_info pmic_children_info[] = { /* buck */ diff --git a/drivers/power/pmic/mtk-pwrap.c b/drivers/power/pmic/mtk-pwrap.c new file mode 100644 index 00000000000..3e3a691d9e8 --- /dev/null +++ b/drivers/power/pmic/mtk-pwrap.c @@ -0,0 +1,896 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * MT6357 regulator driver + * + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Masson <[email protected]> + */ + +#include <asm/io.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <linux/bitfield.h> +#include <linux/err.h> +#include <power/pmic.h> +#include <power/mt6357.h> +#include <power/mt6359.h> +#include <time.h> + +static const struct pmic_child_info mt6357_pmic_children_info[] = { + { .prefix = "buck", .driver = MT6357_REGULATOR_DRIVER }, + { .prefix = "ldo", .driver = MT6357_REGULATOR_DRIVER }, + { } +}; + +static const struct pmic_child_info mt6359_pmic_children_info[] = { + { .prefix = "buck", .driver = MT6359_REGULATOR_DRIVER }, + { .prefix = "ldo", .driver = MT6359_REGULATOR_DRIVER }, + { } +}; + +/* macro for wrapper status */ +#define PWRAP_GET_WACS_RDATA GENMASK(15, 0) +#define PWRAP_GET_WACS_FSM GENMASK(18, 16) +#define PWRAP_GET_WACS_ARB_FSM GENMASK(3, 1) +#define PWRAP_STATE_SYNC_IDLE0 BIT(20) +#define PWRAP_STATE_INIT_DONE0 BIT(21) +#define PWRAP_STATE_INIT_DONE1 BIT(15) + +/* macro for WACS FSM */ +#define PWRAP_WACS_FSM_IDLE 0x00 +#define PWRAP_WACS_FSM_WFVLDCLR 0x06 + +/* macro for device wrapper default value */ +#define PWRAP_DEW_READ_TEST_VAL 0x5aa5 + +/* macro for manual command */ +#define PWRAP_MAN_CMD_SPI_WRITE BIT(13) +#define PWRAP_MAN_CMD_OP_CSH (0x0 << 8) +#define PWRAP_MAN_CMD_OP_CSL (0x1 << 8) +#define PWRAP_MAN_CMD_OP_OUTS (0x8 << 8) + +/* macro for Watch Dog Timer Source */ +#define PWRAP_WDT_SRC_MASK_ALL GENMASK(31, 0) + +/* Group of bits used for shown slave capability */ +#define PWRAP_SLV_CAP_SPI BIT(0) +#define PWRAP_SLV_CAP_DUALIO BIT(1) +#define HAS_CAP(_c, _x_val) (((_c) & (_x_val)) == (_x_val)) + +/* Group of bits used for shown pwrap capability */ +#define PWRAP_CAP_INT1_EN BIT(3) +#define PWRAP_CAP_WDT_SRC1 BIT(4) +#define PWRAP_CAP_ARB BIT(5) + +/* defines for slave device wrapper registers */ +enum dew_regs { + PWRAP_DEW_BASE, + PWRAP_DEW_DIO_EN, + PWRAP_DEW_READ_TEST, + PWRAP_DEW_WRITE_TEST, + PWRAP_DEW_CRC_EN, + PWRAP_DEW_CRC_VAL, + PWRAP_DEW_MON_GRP_SEL, + PWRAP_DEW_CIPHER_KEY_SEL, + PWRAP_DEW_CIPHER_IV_SEL, + PWRAP_DEW_CIPHER_RDY, + PWRAP_DEW_CIPHER_MODE, + PWRAP_DEW_CIPHER_SWRST, + + /* MT6323 only regs */ + PWRAP_DEW_CIPHER_EN, + PWRAP_DEW_RDDMY_NO, + + /* MT6358 only regs */ + PWRAP_SMT_CON1, + PWRAP_DRV_CON1, + PWRAP_FILTER_CON0, + PWRAP_GPIO_PULLEN0_CLR, + PWRAP_RG_SPI_CON0, + PWRAP_RG_SPI_RECORD0, + PWRAP_RG_SPI_CON2, + PWRAP_RG_SPI_CON3, + PWRAP_RG_SPI_CON4, + PWRAP_RG_SPI_CON5, + PWRAP_RG_SPI_CON6, + PWRAP_RG_SPI_CON7, + PWRAP_RG_SPI_CON8, + PWRAP_RG_SPI_CON13, + PWRAP_SPISLV_KEY, + + /* MT6359 only regs */ + PWRAP_DEW_CRC_SWRST, + PWRAP_DEW_RG_EN_RECORD, + PWRAP_DEW_RECORD_CMD0, + PWRAP_DEW_RECORD_CMD1, + PWRAP_DEW_RECORD_CMD2, + PWRAP_DEW_RECORD_CMD3, + PWRAP_DEW_RECORD_CMD4, + PWRAP_DEW_RECORD_CMD5, + PWRAP_DEW_RECORD_WDATA0, + PWRAP_DEW_RECORD_WDATA1, + PWRAP_DEW_RECORD_WDATA2, + PWRAP_DEW_RECORD_WDATA3, + PWRAP_DEW_RECORD_WDATA4, + PWRAP_DEW_RECORD_WDATA5, + PWRAP_DEW_RG_ADDR_TARGET, + PWRAP_DEW_RG_ADDR_MASK, + PWRAP_DEW_RG_WDATA_TARGET, + PWRAP_DEW_RG_WDATA_MASK, + PWRAP_DEW_RG_SPI_RECORD_CLR, + PWRAP_DEW_RG_CMD_ALERT_CLR, +}; + +static const u32 mt6357_regs[] = { + [PWRAP_DEW_DIO_EN] = 0x040A, + [PWRAP_DEW_READ_TEST] = 0x040C, + [PWRAP_DEW_WRITE_TEST] = 0x040E, + [PWRAP_DEW_CRC_EN] = 0x0412, + [PWRAP_DEW_CRC_VAL] = 0x0414, + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418, + [PWRAP_DEW_CIPHER_IV_SEL] = 0x041A, + [PWRAP_DEW_CIPHER_RDY] = 0x041E, + [PWRAP_DEW_CIPHER_MODE] = 0x0420, + [PWRAP_DEW_CIPHER_SWRST] = 0x0422, + [PWRAP_DEW_CIPHER_EN] = 0x041C, + [PWRAP_DEW_RDDMY_NO] = 0x0424, +}; + +static const u32 mt6359_regs[] = { + [PWRAP_DEW_RG_EN_RECORD] = 0x040a, + [PWRAP_DEW_DIO_EN] = 0x040c, + [PWRAP_DEW_READ_TEST] = 0x040e, + [PWRAP_DEW_WRITE_TEST] = 0x0410, + [PWRAP_DEW_CRC_SWRST] = 0x0412, + [PWRAP_DEW_CRC_EN] = 0x0414, + [PWRAP_DEW_CRC_VAL] = 0x0416, + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418, + [PWRAP_DEW_CIPHER_IV_SEL] = 0x041a, + [PWRAP_DEW_CIPHER_EN] = 0x041c, + [PWRAP_DEW_CIPHER_RDY] = 0x041e, + [PWRAP_DEW_CIPHER_MODE] = 0x0420, + [PWRAP_DEW_CIPHER_SWRST] = 0x0422, + [PWRAP_DEW_RDDMY_NO] = 0x0424, + [PWRAP_DEW_RECORD_CMD0] = 0x0428, + [PWRAP_DEW_RECORD_CMD1] = 0x042a, + [PWRAP_DEW_RECORD_CMD2] = 0x042c, + [PWRAP_DEW_RECORD_CMD3] = 0x042e, + [PWRAP_DEW_RECORD_CMD4] = 0x0430, + [PWRAP_DEW_RECORD_CMD5] = 0x0432, + [PWRAP_DEW_RECORD_WDATA0] = 0x0434, + [PWRAP_DEW_RECORD_WDATA1] = 0x0436, + [PWRAP_DEW_RECORD_WDATA2] = 0x0438, + [PWRAP_DEW_RECORD_WDATA3] = 0x043a, + [PWRAP_DEW_RECORD_WDATA4] = 0x043c, + [PWRAP_DEW_RECORD_WDATA5] = 0x043e, + [PWRAP_DEW_RG_ADDR_TARGET] = 0x0440, + [PWRAP_DEW_RG_ADDR_MASK] = 0x0442, + [PWRAP_DEW_RG_WDATA_TARGET] = 0x0444, + [PWRAP_DEW_RG_WDATA_MASK] = 0x0446, + [PWRAP_DEW_RG_SPI_RECORD_CLR] = 0x0448, + [PWRAP_DEW_RG_CMD_ALERT_CLR] = 0x0448, + [PWRAP_SPISLV_KEY] = 0x044a, +}; + +enum pwrap_regs { + PWRAP_MUX_SEL, + PWRAP_WRAP_EN, + PWRAP_DIO_EN, + PWRAP_SIDLY, + PWRAP_CSHEXT_WRITE, + PWRAP_CSHEXT_READ, + PWRAP_CSLEXT_START, + PWRAP_CSLEXT_END, + PWRAP_STAUPD_PRD, + PWRAP_STAUPD_GRPEN, + PWRAP_STAUPD_MAN_TRIG, + PWRAP_STAUPD_STA, + PWRAP_WRAP_STA, + PWRAP_HARB_INIT, + PWRAP_HARB_HPRIO, + PWRAP_HIPRIO_ARB_EN, + PWRAP_HARB_STA0, + PWRAP_HARB_STA1, + PWRAP_MAN_EN, + PWRAP_MAN_CMD, + PWRAP_MAN_RDATA, + PWRAP_MAN_VLDCLR, + PWRAP_WACS0_EN, + PWRAP_INIT_DONE0, + PWRAP_WACS0_CMD, + PWRAP_WACS0_RDATA, + PWRAP_WACS0_VLDCLR, + PWRAP_WACS1_EN, + PWRAP_INIT_DONE1, + PWRAP_WACS1_CMD, + PWRAP_WACS1_RDATA, + PWRAP_WACS1_VLDCLR, + PWRAP_WACS2_EN, + PWRAP_INIT_DONE2, + PWRAP_WACS2_CMD, + PWRAP_WACS2_RDATA, + PWRAP_WACS2_VLDCLR, + PWRAP_INT_EN, + PWRAP_INT_FLG_RAW, + PWRAP_INT_FLG, + PWRAP_INT_CLR, + PWRAP_SIG_ADR, + PWRAP_SIG_MODE, + PWRAP_SIG_VALUE, + PWRAP_SIG_ERRVAL, + PWRAP_CRC_EN, + PWRAP_TIMER_EN, + PWRAP_TIMER_STA, + PWRAP_WDT_UNIT, + PWRAP_WDT_SRC_EN, + PWRAP_WDT_FLG, + PWRAP_DEBUG_INT_SEL, + PWRAP_CIPHER_KEY_SEL, + PWRAP_CIPHER_IV_SEL, + PWRAP_CIPHER_RDY, + PWRAP_CIPHER_MODE, + PWRAP_CIPHER_SWRST, + PWRAP_DCM_EN, + PWRAP_DCM_DBC_PRD, + PWRAP_EINT_STA0_ADR, + PWRAP_EINT_STA1_ADR, + PWRAP_SWINF_2_WDATA_31_0, + PWRAP_SWINF_2_RDATA_31_0, + + /* MT8390 only regs */ + PWRAP_STAUPD_CTRL, + + /* MT8365 only regs */ + PWRAP_INT1_EN, + PWRAP_INT1_FLG, + PWRAP_INT1_CLR, + PWRAP_WDT_SRC_EN_1, +}; + +static int mt8188_regs[] = { + [PWRAP_INIT_DONE2] = 0x0, + [PWRAP_STAUPD_CTRL] = 0x4C, + [PWRAP_TIMER_EN] = 0x3E4, + [PWRAP_INT_EN] = 0x420, + [PWRAP_INT_FLG] = 0x428, + [PWRAP_INT_CLR] = 0x42C, + [PWRAP_INT1_EN] = 0x450, + [PWRAP_INT1_FLG] = 0x458, + [PWRAP_INT1_CLR] = 0x45C, + [PWRAP_WACS2_CMD] = 0x880, + [PWRAP_SWINF_2_WDATA_31_0] = 0x884, + [PWRAP_SWINF_2_RDATA_31_0] = 0x894, + [PWRAP_WACS2_VLDCLR] = 0x8A4, + [PWRAP_WACS2_RDATA] = 0x8A8, +}; + +static int mt8189_regs[] = { + [PWRAP_INIT_DONE2] = 0x0, + [PWRAP_TIMER_EN] = 0x3E4, + [PWRAP_INT_EN] = 0x450, + [PWRAP_WACS2_CMD] = 0x880, + [PWRAP_SWINF_2_WDATA_31_0] = 0x884, + [PWRAP_SWINF_2_RDATA_31_0] = 0x894, + [PWRAP_WACS2_VLDCLR] = 0x8A4, + [PWRAP_WACS2_RDATA] = 0x8A8, +}; + +static int mt8365_regs[] = { + [PWRAP_MUX_SEL] = 0x0, + [PWRAP_WRAP_EN] = 0x4, + [PWRAP_DIO_EN] = 0x8, + [PWRAP_CSHEXT_WRITE] = 0x24, + [PWRAP_CSHEXT_READ] = 0x28, + [PWRAP_STAUPD_PRD] = 0x3c, + [PWRAP_STAUPD_GRPEN] = 0x40, + [PWRAP_STAUPD_MAN_TRIG] = 0x58, + [PWRAP_STAUPD_STA] = 0x5c, + [PWRAP_WRAP_STA] = 0x60, + [PWRAP_HARB_INIT] = 0x64, + [PWRAP_HARB_HPRIO] = 0x68, + [PWRAP_HIPRIO_ARB_EN] = 0x6c, + [PWRAP_HARB_STA0] = 0x70, + [PWRAP_HARB_STA1] = 0x74, + [PWRAP_MAN_EN] = 0x7c, + [PWRAP_MAN_CMD] = 0x80, + [PWRAP_MAN_RDATA] = 0x84, + [PWRAP_MAN_VLDCLR] = 0x88, + [PWRAP_WACS0_EN] = 0x8c, + [PWRAP_INIT_DONE0] = 0x90, + [PWRAP_WACS0_CMD] = 0xc00, + [PWRAP_WACS0_RDATA] = 0xc04, + [PWRAP_WACS0_VLDCLR] = 0xc08, + [PWRAP_WACS1_EN] = 0x94, + [PWRAP_INIT_DONE1] = 0x98, + [PWRAP_WACS2_EN] = 0x9c, + [PWRAP_INIT_DONE2] = 0xa0, + [PWRAP_WACS2_CMD] = 0xc20, + [PWRAP_WACS2_RDATA] = 0xc24, + [PWRAP_WACS2_VLDCLR] = 0xc28, + [PWRAP_INT_EN] = 0xb4, + [PWRAP_INT_FLG_RAW] = 0xb8, + [PWRAP_INT_FLG] = 0xbc, + [PWRAP_INT_CLR] = 0xc0, + [PWRAP_SIG_ADR] = 0xd4, + [PWRAP_SIG_MODE] = 0xd8, + [PWRAP_SIG_VALUE] = 0xdc, + [PWRAP_SIG_ERRVAL] = 0xe0, + [PWRAP_CRC_EN] = 0xe4, + [PWRAP_TIMER_EN] = 0xe8, + [PWRAP_TIMER_STA] = 0xec, + [PWRAP_WDT_UNIT] = 0xf0, + [PWRAP_WDT_SRC_EN] = 0xf4, + [PWRAP_WDT_FLG] = 0xfc, + [PWRAP_DEBUG_INT_SEL] = 0x104, + [PWRAP_CIPHER_KEY_SEL] = 0x1c4, + [PWRAP_CIPHER_IV_SEL] = 0x1c8, + [PWRAP_CIPHER_RDY] = 0x1d0, + [PWRAP_CIPHER_MODE] = 0x1d4, + [PWRAP_CIPHER_SWRST] = 0x1d8, + [PWRAP_DCM_EN] = 0x1dc, + [PWRAP_DCM_DBC_PRD] = 0x1e0, + [PWRAP_EINT_STA0_ADR] = 0x44, + [PWRAP_EINT_STA1_ADR] = 0x48, + [PWRAP_INT1_EN] = 0xc4, + [PWRAP_INT1_FLG] = 0xcc, + [PWRAP_INT1_CLR] = 0xd0, + [PWRAP_WDT_SRC_EN_1] = 0xf8, +}; + +enum pwrap_type { + PWRAP_MT8188, + PWRAP_MT8189, + PWRAP_MT8365, +}; + +struct pwrap_slv_type { + const u32 *dew_regs; + u32 caps; +}; + +struct pmic_wrapper { + struct udevice *dev; + void __iomem *base; + const struct pmic_wrapper_type *master; + const struct pwrap_slv_type *slave; + struct clk *clk_spi; + struct clk *clk_wrap; + struct clk *clk_wrap_sys; + struct clk *clk_wrap_tmr; +}; + +struct pmic_wrapper_type { + int *regs; + enum pwrap_type type; + u32 arb_en_all; + u32 int_en_all; + u32 int1_en_all; + u32 spi_w; + u32 wdt_src; + /* Flags indicating the capability for the target pwrap */ + u32 caps; +}; + +static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg) +{ + return readl(wrp->base + wrp->master->regs[reg]); +} + +static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg) +{ + writel(val, wrp->base + wrp->master->regs[reg]); +} + +static u32 pwrap_get_fsm_state(struct pmic_wrapper *wrp) +{ + u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); + + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) + return FIELD_GET(PWRAP_GET_WACS_ARB_FSM, val); + + return FIELD_GET(PWRAP_GET_WACS_FSM, val); +} + +static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp) +{ + return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_IDLE; +} + +static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp) +{ + return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_WFVLDCLR; +} + +/* + * Timeout issue sometimes caused by the last read command + * failed because pmic wrap could not got the FSM_VLDCLR + * in time after finishing WACS2_CMD. It made state machine + * still on FSM_VLDCLR and timeout next time. + * Check the status of FSM and clear the vldclr to recovery the + * error. + */ +static inline void pwrap_leave_fsm_vldclr(struct pmic_wrapper *wrp) +{ + if (pwrap_is_fsm_vldclr(wrp)) + pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR); +} + +static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp) +{ + return FIELD_GET(PWRAP_STATE_SYNC_IDLE0, pwrap_readl(wrp, PWRAP_WACS2_RDATA)); +} + +static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp) +{ + u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); + + return FIELD_GET(PWRAP_GET_WACS_FSM, val) == PWRAP_WACS_FSM_IDLE && + FIELD_GET(PWRAP_STATE_SYNC_IDLE0, val); +} + +static int pwrap_wait_for_state(struct pmic_wrapper *wrp, bool (*fp)(struct pmic_wrapper *)) +{ + unsigned long timeout; + + timeout = timer_get_us() + 10000; + + do { + if (time_after(timer_get_us(), timeout)) + return fp(wrp) ? 0 : -ETIMEDOUT; + + if (fp(wrp)) + return 0; + } while (1); +} + +/* pwrap_read16 in linux kernel */ +static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) +{ + int ret; + u32 val; + + ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle); + if (ret) { + pwrap_leave_fsm_vldclr(wrp); + return ret; + } + + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) + val = adr; + else + val = (adr >> 1) << 16; + + pwrap_writel(wrp, val, PWRAP_WACS2_CMD); + + ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr); + if (ret) + return ret; + + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) + val = pwrap_readl(wrp, PWRAP_SWINF_2_RDATA_31_0); + else + val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); + + *rdata = FIELD_GET(PWRAP_GET_WACS_RDATA, val); + + pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR); + + return 0; +} + +/* pwrap_write16 in linux kernel */ +static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata) +{ + int ret; + + ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle); + if (ret) { + pwrap_leave_fsm_vldclr(wrp); + return ret; + } + + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) { + pwrap_writel(wrp, wdata, PWRAP_SWINF_2_WDATA_31_0); + pwrap_writel(wrp, BIT(29) | adr, PWRAP_WACS2_CMD); + } else { + pwrap_writel(wrp, BIT(31) | ((adr >> 1) << 16) | wdata, PWRAP_WACS2_CMD); + } + + return 0; +} + +static int pwrap_reset_spislave(struct pmic_wrapper *wrp) +{ + int ret, i; + + pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN); + pwrap_writel(wrp, 0, PWRAP_WRAP_EN); + pwrap_writel(wrp, 1, PWRAP_MUX_SEL); + pwrap_writel(wrp, 1, PWRAP_MAN_EN); + pwrap_writel(wrp, 0, PWRAP_DIO_EN); + + pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSL, PWRAP_MAN_CMD); + pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS, PWRAP_MAN_CMD); + pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSH, PWRAP_MAN_CMD); + + for (i = 0; i < 4; i++) + pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS, + PWRAP_MAN_CMD); + + ret = pwrap_wait_for_state(wrp, pwrap_is_sync_idle); + if (ret) { + dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret); + return ret; + } + + pwrap_writel(wrp, 0, PWRAP_MAN_EN); + pwrap_writel(wrp, 0, PWRAP_MUX_SEL); + + return 0; +} + +/* + * pwrap_init_sidly - configure serial input delay + * + * This configures the serial input delay. We can configure 0, 2, 4 or 6ns + * delay. Do a read test with all possible values and chose the best delay. + */ +static int pwrap_init_sidly(struct pmic_wrapper *wrp) +{ + u32 rdata; + u32 i; + u32 pass = 0; + signed char dly[16] = { + -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1 + }; + + for (i = 0; i < 4; i++) { + pwrap_writel(wrp, i, PWRAP_SIDLY); + pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata); + if (rdata == PWRAP_DEW_READ_TEST_VAL) { + dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i); + pass |= 1 << i; + } + } + + if (dly[pass] < 0) { + dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n", pass); + return -EIO; + } + + pwrap_writel(wrp, dly[pass], PWRAP_SIDLY); + + return 0; +} + +static int pwrap_init_dual_io(struct pmic_wrapper *wrp) +{ + int ret; + u32 rdata; + + /* Enable dual IO mode */ + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1); + + /* Check IDLE & INIT_DONE in advance */ + ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle); + if (ret) { + dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret); + return ret; + } + + pwrap_writel(wrp, 1, PWRAP_DIO_EN); + + /* Read Test */ + pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata); + if (rdata != PWRAP_DEW_READ_TEST_VAL) { + dev_err(wrp->dev, "Read failed on DIO mode: 0x%04x!=0x%04x\n", + PWRAP_DEW_READ_TEST_VAL, rdata); + return -EFAULT; + } + + return 0; +} + +static int pwrap_init(struct pmic_wrapper *wrp) +{ + int ret; + + /* Reset SPI slave */ + if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) { + ret = pwrap_reset_spislave(wrp); + if (ret) + return ret; + } + + pwrap_writel(wrp, 1, PWRAP_WRAP_EN); + + pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN); + + pwrap_writel(wrp, 1, PWRAP_WACS2_EN); + + /* Setup serial input delay */ + if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) { + ret = pwrap_init_sidly(wrp); + if (ret) + return ret; + } + + /* Enable dual I/O mode */ + if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) { + ret = pwrap_init_dual_io(wrp); + if (ret) + return ret; + } + + pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN); + pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN); + pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN); + pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD); + pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN); + + /* Setup the init done registers */ + pwrap_writel(wrp, 1, PWRAP_INIT_DONE2); + pwrap_writel(wrp, 1, PWRAP_INIT_DONE0); + pwrap_writel(wrp, 1, PWRAP_INIT_DONE1); + + return 0; +} + +static const struct pwrap_slv_type pmic_mt6357 = { + .dew_regs = mt6357_regs, + .caps = 0, +}; + +static const struct pwrap_slv_type pmic_mt6359 = { + .dew_regs = mt6359_regs, + .caps = PWRAP_SLV_CAP_DUALIO, +}; + +static const struct udevice_id mtk_pmic_ids[] = { + { .compatible = "mediatek,mt6357", .data = (ulong)&pmic_mt6357 }, + { .compatible = "mediatek,mt6359", .data = (ulong)&pmic_mt6359 }, + { } +}; + +static int mtk_pwrap_find_slave(const struct pwrap_slv_type **slave, ofnode pmic_node) +{ + const struct udevice_id *of_match = mtk_pmic_ids; + const char *pmic_name; + + pmic_name = ofnode_get_property(pmic_node, "compatible", NULL); + if (!pmic_name) { + log_err("%s: missing compatible property\n", __func__); + return -EINVAL; + } + + while (of_match->compatible) { + if (!strcmp(of_match->compatible, pmic_name)) { + *slave = (struct pwrap_slv_type *)of_match->data; + return 0; + } + of_match++; + } + + return -ENOENT; +} + +static int mtk_pwrap_probe(struct udevice *dev) +{ + struct pmic_wrapper *wrp = dev_get_priv(dev); + ofnode pmic_node; + u32 mask_done; + int ret; + + wrp->dev = dev; + + wrp->base = dev_remap_addr(dev); + if (IS_ERR(wrp->base)) + return PTR_ERR(wrp->base); + + wrp->master = (void *)dev_get_driver_data(dev); + + pmic_node = dev_read_first_subnode(dev); + if (!ofnode_valid(pmic_node)) { + dev_err(dev, "pmic subnode not found\n"); + return -ENXIO; + } + + ret = mtk_pwrap_find_slave(&wrp->slave, pmic_node); + if (ret) { + dev_err(dev, "pmic slave not found\n"); + return -EINVAL; + } + + wrp->clk_spi = devm_clk_get(dev, "spi"); + if (IS_ERR(wrp->clk_spi)) + return PTR_ERR(wrp->clk_spi); + + wrp->clk_wrap = devm_clk_get(dev, "wrap"); + if (IS_ERR(wrp->clk_wrap)) + return PTR_ERR(wrp->clk_wrap); + + wrp->clk_wrap_sys = devm_clk_get_optional(dev, "wrap_sys"); + wrp->clk_wrap_tmr = devm_clk_get_optional(dev, "wrap_tmr"); + + ret = clk_enable(wrp->clk_spi); + if (ret) + return ret; + + ret = clk_enable(wrp->clk_wrap); + if (ret) + return ret; + + ret = clk_enable(wrp->clk_wrap_sys); + if (ret) + return ret; + + ret = clk_enable(wrp->clk_wrap_tmr); + if (ret) + return ret; + + /* + * The PMIC could already be initialized by the bootloader. + * Skip initialization here in this case. + */ + if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) { + ret = pwrap_init(wrp); + if (ret) { + dev_err(dev, "init failed with %d\n", ret); + return ret; + } + } + + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) + mask_done = PWRAP_STATE_INIT_DONE1; + else + mask_done = PWRAP_STATE_INIT_DONE0; + + if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & mask_done)) { + dev_dbg(dev, "initialization isn't finished\n"); + return -ENODEV; + } + + /* + * Since STAUPD was not used on mt8173 platform, + * so STAUPD of WDT_SRC which should be turned off + */ + pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN); + + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_WDT_SRC1)) + pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN_1); + + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) + pwrap_writel(wrp, 0x3, PWRAP_TIMER_EN); + else + pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN); + + pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN); + + /* + * We add INT1 interrupt to handle starvation and request exception + * If we support it, we should enable it here. + */ + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) + pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN); + + return 0; +} + +static int mtk_pwrap_bind(struct udevice *dev) +{ + ofnode pmic_node, regulators_node; + int children; + const struct pmic_child_info *pmic_children_info; + struct pmic_wrapper_type *pw_type = (void *)dev_get_driver_data(dev); + + pmic_node = dev_read_first_subnode(dev); + if (!ofnode_valid(pmic_node)) { + dev_err(dev, "pmic subnode not found\n"); + return -ENXIO; + } + + switch (pw_type->type) { + case PWRAP_MT8365: + pmic_children_info = mt6357_pmic_children_info; + break; + case PWRAP_MT8188: + case PWRAP_MT8189: + pmic_children_info = mt6359_pmic_children_info; + break; + default: + dev_err(dev, "pwrap type %d not supported\n", pw_type->type); + return -ENXIO; + } + + regulators_node = ofnode_find_subnode(pmic_node, "regulators"); + if (ofnode_valid(regulators_node)) { + children = pmic_bind_children(dev, regulators_node, pmic_children_info); + if (!children) + dev_dbg(dev, "no children found\n"); + } else { + dev_dbg(dev, "regulators subnode not found\n"); + } + + return 0; +} + +static int mtk_pwrap_reg_count(struct udevice *dev) +{ + return 0x8000; +} + +static int mtk_pwrap_read(struct udevice *dev, uint reg, uint8_t *buf, int len) +{ + struct pmic_wrapper *wrp = dev_get_priv(dev); + + if ((len * sizeof(uint8_t)) > sizeof(u32)) + return -EINVAL; + + return pwrap_read(wrp, reg, (u32 *)buf); +} + +static int mtk_pwrap_write(struct udevice *dev, uint reg, const uint8_t *buf, int len) +{ + struct pmic_wrapper *wrp = dev_get_priv(dev); + + if ((len * sizeof(uint8_t)) > sizeof(u32)) + return -EINVAL; + + return pwrap_write(wrp, reg, *(u32 *)buf); +} + +static struct dm_pmic_ops mtk_pwrap_ops = { + .reg_count = mtk_pwrap_reg_count, + .read = mtk_pwrap_read, + .write = mtk_pwrap_write, +}; + +static struct pmic_wrapper_type pwrap_mt8188 = { + .regs = mt8188_regs, + .type = PWRAP_MT8188, + .arb_en_all = 0x777f, + .int_en_all = 0x180000, + .int1_en_all = 0x0, + .spi_w = PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src = PWRAP_WDT_SRC_MASK_ALL, + .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB, +}; + +static struct pmic_wrapper_type pwrap_mt8189 = { + .regs = mt8189_regs, + .type = PWRAP_MT8189, + .arb_en_all = 0x777f, + .int_en_all = 0x180000, + .spi_w = PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src = PWRAP_WDT_SRC_MASK_ALL, + .caps = PWRAP_CAP_ARB, +}; + +static const struct pmic_wrapper_type pwrap_mt8365 = { + .regs = mt8365_regs, + .type = PWRAP_MT8365, + .arb_en_all = 0x3ffff, + .int_en_all = 0x7f1fffff, + .int1_en_all = 0x0, + .spi_w = PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src = PWRAP_WDT_SRC_MASK_ALL, + .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1, +}; + +static const struct udevice_id mtk_pwrap_ids[] = { + { .compatible = "mediatek,mt8188-pwrap", .data = (ulong)&pwrap_mt8188 }, + { .compatible = "mediatek,mt8189-pwrap", .data = (ulong)&pwrap_mt8189 }, + { .compatible = "mediatek,mt8365-pwrap", .data = (ulong)&pwrap_mt8365 }, + { } +}; + +U_BOOT_DRIVER(mtk_pwrap) = { + .name = "mtk_pwrap", + .id = UCLASS_PMIC, + .of_match = mtk_pwrap_ids, + .bind = mtk_pwrap_bind, + .probe = mtk_pwrap_probe, + .ops = &mtk_pwrap_ops, + .priv_auto = sizeof(struct pmic_wrapper), +}; diff --git a/drivers/power/pmic/palmas.c b/drivers/power/pmic/palmas.c index 37d4190fabe..e5b497dfc39 100644 --- a/drivers/power/pmic/palmas.c +++ b/drivers/power/pmic/palmas.c @@ -48,7 +48,9 @@ static int palmas_bind(struct udevice *dev) ofnode subnode, gpio_node; int children, ret; - if (IS_ENABLED(CONFIG_SYSRESET_PALMAS)) { + if (IS_ENABLED(CONFIG_SYSRESET_PALMAS) && + (dev_read_bool(dev, "ti,system-power-controller") || + dev_read_bool(dev, "system-power-controller"))) { ret = device_bind_driver_to_node(dev, PALMAS_RST_DRIVER, "sysreset", dev_ofnode(dev), NULL); diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index e5c1f037b61..c95e6357ee8 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -10,7 +10,6 @@ #include <dm/lists.h> #include <i2c.h> #include <log.h> -#include <asm/global_data.h> #include <linux/delay.h> #include <linux/printk.h> #include <power/pmic.h> @@ -18,8 +17,6 @@ #include <power/pca9450.h> #include <sysreset.h> -DECLARE_GLOBAL_DATA_PTR; - static const struct pmic_child_info pmic_children_info[] = { /* buck */ { .prefix = "b", .driver = PCA9450_REGULATOR_DRIVER}, diff --git a/drivers/power/pmic/pmic_tps65910_dm.c b/drivers/power/pmic/pmic_tps65910_dm.c index de8d805566a..bce35603275 100644 --- a/drivers/power/pmic/pmic_tps65910_dm.c +++ b/drivers/power/pmic/pmic_tps65910_dm.c @@ -61,7 +61,9 @@ static int pmic_tps65910_bind(struct udevice *dev) ofnode regulators_node; int children, ret; - if (IS_ENABLED(CONFIG_SYSRESET_TPS65910)) { + if (IS_ENABLED(CONFIG_SYSRESET_TPS65910) && + (dev_read_bool(dev, "ti,system-power-controller") || + dev_read_bool(dev, "system-power-controller"))) { ret = device_bind_driver(dev, TPS65910_RST_DRIVER, "sysreset", NULL); if (ret) { diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c index d11f7a7886e..95b71d2fe49 100644 --- a/drivers/power/pmic/rk8xx.c +++ b/drivers/power/pmic/rk8xx.c @@ -220,7 +220,9 @@ static int rk8xx_bind(struct udevice *dev) debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); - if (CONFIG_IS_ENABLED(SYSRESET)) { + if (CONFIG_IS_ENABLED(SYSRESET) && + (dev_read_bool(dev, "rockchip,system-power-controller") || + dev_read_bool(dev, "system-power-controller"))) { ret = device_bind_driver_to_node(dev, "rk8xx_sysreset", "rk8xx_sysreset", dev_ofnode(dev), NULL); diff --git a/drivers/power/pmic/tps80031.c b/drivers/power/pmic/tps80031.c index a2f935b0c6d..6004a14cd6c 100644 --- a/drivers/power/pmic/tps80031.c +++ b/drivers/power/pmic/tps80031.c @@ -46,7 +46,9 @@ static int tps80031_bind(struct udevice *dev) ofnode regulators_node; int children, ret; - if (IS_ENABLED(CONFIG_SYSRESET_TPS80031)) { + if (IS_ENABLED(CONFIG_SYSRESET_TPS80031) && + (dev_read_bool(dev, "ti,system-power-controller") || + dev_read_bool(dev, "system-power-controller"))) { ret = device_bind_driver(dev, TPS80031_RST_DRIVER, "sysreset", NULL); if (ret) { diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index d8b3e0f62e6..a4ee5f1335a 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -191,6 +191,14 @@ config DM_REGULATOR_FAN53555 or switching the mode is not supported by this driver (at this time). +config SPL_DM_REGULATOR_FAN53555 + bool "Enable Driver Model for REGULATOR FAN53555 in SPL" + depends on SPL_DM_PMIC_FAN53555 + help + This configuration setting enables the implementation of the + driver-model regulator uclass features for the FAN53555 + regulator in SPL. + config DM_REGULATOR_COMMON bool depends on DM_REGULATOR @@ -521,3 +529,21 @@ config DM_REGULATOR_CPCAP REGULATOR CPCAP. The driver supports both DC-to-DC Step-Down Switching (SW) Regulators and Low-Dropout Linear (LDO) Regulators found in CPCAP PMIC and implements get/set api for voltage and state. + +config DM_REGULATOR_MT6357 + bool "Enable driver for MediaTek MT6357 PMIC regulators" + depends on DM_REGULATOR && DM_PMIC_MTK_PWRAP + help + Say y here to select this option to enable the power regulator of + MediaTek MT6357 PMIC. + This driver supports the control of different power rails of device + through regulator interface. + +config DM_REGULATOR_MT6359 + bool "Enable driver for MediaTek MT6359 PMIC regulators" + depends on DM_REGULATOR && DM_PMIC_MTK_PWRAP + help + Say y here to select this option to enable the power regulator of + MediaTek MT6359 PMIC. + This driver supports the control of different power rails of device + through regulator interface. diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index ee8f56ea3b9..9e303d4f7f8 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -47,3 +47,5 @@ obj-$(CONFIG_$(PHASE_)DM_REGULATOR_ANATOP) += anatop_regulator.o obj-$(CONFIG_DM_REGULATOR_TPS65219) += tps65219_regulator.o obj-$(CONFIG_REGULATOR_RZG2L_USBPHY) += rzg2l-usbphy-regulator.o obj-$(CONFIG_$(PHASE_)DM_REGULATOR_CPCAP) += cpcap_regulator.o +obj-$(CONFIG_DM_REGULATOR_MT6357) += mt6357_regulator.o +obj-$(CONFIG_DM_REGULATOR_MT6359) += mt6359_regulator.o diff --git a/drivers/power/regulator/cpcap_regulator.c b/drivers/power/regulator/cpcap_regulator.c index 04cd6651374..0fbce57048c 100644 --- a/drivers/power/regulator/cpcap_regulator.c +++ b/drivers/power/regulator/cpcap_regulator.c @@ -55,7 +55,7 @@ #define CPCAP_REG(_reg, _assignment_reg, _assignment_mask, _mode_mask, \ _volt_mask, _volt_shft, _mode_val, _off_mode_val, _val_tbl, \ - _mode_cntr, _volt_trans_time, _turn_on_time, _bit_offset) { \ + _mode_cntr, _volt_trans_time, _turn_on_time) { \ .reg = CPCAP_REG_##_reg, \ .assignment_reg = CPCAP_REG_##_assignment_reg, \ .assignment_mask = CPCAP_BIT_##_assignment_mask, \ @@ -69,60 +69,59 @@ .mode_cntr = _mode_cntr, \ .volt_trans_time = _volt_trans_time, \ .turn_on_time = _turn_on_time, \ - .bit_offset_from_cpcap_lowest_voltage = _bit_offset, \ } static const struct cpcap_regulator_data tegra20_regulators[CPCAP_REGULATORS_COUNT] = { /* BUCK */ [CPCAP_SW1] = CPCAP_REG(S1C1, ASSIGN2, SW1_SEL, 0x6f00, 0x007f, - 0, 0x6800, 0, sw1_val_tbl, 0, 0, 1500, 0x0c), + 0, 0x6800, 0, sw_val_tbl, 0, 0, 1500), [CPCAP_SW2] = CPCAP_REG(S2C1, ASSIGN2, SW2_SEL, 0x6f00, 0x007f, - 0, 0x4804, 0, sw2_sw4_val_tbl, 0, 0, 1500, 0x18), + 0, 0x4804, 0, sw_val_tbl, 0, 0, 1500), [CPCAP_SW3] = CPCAP_REG(S3C, ASSIGN2, SW3_SEL, 0x0578, 0x0003, - 0, 0x043c, 0, sw3_val_tbl, 0, 0, 0, 0), + 0, 0x043c, 0, sw3_val_tbl, 0, 0, 0), [CPCAP_SW4] = CPCAP_REG(S4C1, ASSIGN2, SW4_SEL, 0x6f00, 0x007f, - 0, 0x4909, 0, sw2_sw4_val_tbl, 0, 0, 1500, 0x18), + 0, 0x4909, 0, sw_val_tbl, 0, 0, 1500), [CPCAP_SW5] = CPCAP_REG(S5C, ASSIGN2, SW5_SEL, 0x0028, 0x0000, - 0, 0x0020, 0, sw5_val_tbl, 0, 0, 1500, 0), + 0, 0x0020, 0, sw5_val_tbl, 0, 0, 1500), [CPCAP_SW6] = CPCAP_REG(S6C, ASSIGN2, SW6_SEL, 0x0000, 0x0000, - 0, 0, 0, unknown_val_tbl, 0, 0, 0, 0), + 0, 0, 0, unknown_val_tbl, 0, 0, 0), /* LDO */ [CPCAP_VCAM] = CPCAP_REG(VCAMC, ASSIGN2, VCAM_SEL, 0x0087, 0x0030, - 4, 0x7, 0, vcam_val_tbl, 0, 420, 1000, 0), + 4, 0x7, 0, vcam_val_tbl, 0, 420, 1000), [CPCAP_VCSI] = CPCAP_REG(VCSIC, ASSIGN3, VCSI_SEL, 0x0047, 0x0010, - 4, 0x7, 0, vcsi_val_tbl, 0, 350, 1000, 0), + 4, 0x7, 0, vcsi_val_tbl, 0, 350, 1000), [CPCAP_VDAC] = CPCAP_REG(VDACC, ASSIGN3, VDAC_SEL, 0x0087, 0x0030, - 4, 0x0, 0, vdac_val_tbl, 0, 420, 1000, 0), + 4, 0x0, 0, vdac_val_tbl, 0, 420, 1000), [CPCAP_VDIG] = CPCAP_REG(VDIGC, ASSIGN2, VDIG_SEL, 0x0087, 0x0030, - 4, 0x0, 0, vdig_val_tbl, 0, 420, 1000, 0), + 4, 0x0, 0, vdig_val_tbl, 0, 420, 1000), [CPCAP_VFUSE] = CPCAP_REG(VFUSEC, ASSIGN3, VFUSE_SEL, 0x00a0, 0x000f, - 0, 0x0, 0, vfuse_val_tbl, 0, 420, 1000, 0), + 0, 0x0, 0, vfuse_val_tbl, 0, 420, 1000), [CPCAP_VHVIO] = CPCAP_REG(VHVIOC, ASSIGN3, VHVIO_SEL, 0x0017, 0x0000, - 0, 0x2, 0, vhvio_val_tbl, 0, 0, 1000, 0), + 0, 0x2, 0, vhvio_val_tbl, 0, 0, 1000), [CPCAP_VSDIO] = CPCAP_REG(VSDIOC, ASSIGN2, VSDIO_SEL, 0x0087, 0x0038, - 3, 0x2, 0, vsdio_val_tbl, 0, 420, 1000, 0), + 3, 0x2, 0, vsdio_val_tbl, 0, 420, 1000), [CPCAP_VPLL] = CPCAP_REG(VPLLC, ASSIGN3, VPLL_SEL, 0x0047, 0x0018, - 3, 0x1, 0, vpll_val_tbl, 0, 420, 100, 0), + 3, 0x1, 0, vpll_val_tbl, 0, 420, 100), [CPCAP_VRF1] = CPCAP_REG(VRF1C, ASSIGN3, VRF1_SEL, 0x00ac, 0x0002, - 1, 0x0, 0, vrf1_val_tbl, 0, 10, 1000, 0), + 1, 0x0, 0, vrf1_val_tbl, 0, 10, 1000), [CPCAP_VRF2] = CPCAP_REG(VRF2C, ASSIGN3, VRF2_SEL, 0x0023, 0x0008, - 3, 0x0, 0, vrf2_val_tbl, 0, 10, 1000, 0), + 3, 0x0, 0, vrf2_val_tbl, 0, 10, 1000), [CPCAP_VRFREF] = CPCAP_REG(VRFREFC, ASSIGN3, VRFREF_SEL, 0x0023, 0x0008, - 3, 0x0, 0, vrfref_val_tbl, 0, 420, 100, 0), + 3, 0x0, 0, vrfref_val_tbl, 0, 420, 100), [CPCAP_VWLAN1] = CPCAP_REG(VWLAN1C, ASSIGN3, VWLAN1_SEL, 0x0047, 0x0010, - 4, 0x0, 0, vwlan1_val_tbl, 0, 420, 1000, 0), + 4, 0x0, 0, vwlan1_val_tbl, 0, 420, 1000), [CPCAP_VWLAN2] = CPCAP_REG(VWLAN2C, ASSIGN3, VWLAN2_SEL, 0x020c, 0x00c0, - 6, 0xd, 0, vwlan2_val_tbl, 0, 420, 1000, 0), + 6, 0xd, 0, vwlan2_val_tbl, 0, 420, 1000), [CPCAP_VSIM] = CPCAP_REG(VSIMC, ASSIGN3, NONE, 0x0023, 0x0008, - 3, 0x0, 0, vsim_val_tbl, 0, 420, 1000, 0), + 3, 0x0, 0, vsim_val_tbl, 0, 420, 1000), [CPCAP_VSIMCARD] = CPCAP_REG(VSIMC, ASSIGN3, NONE, 0x1e80, 0x0008, - 3, 0x1E00, 0, vsimcard_val_tbl, 0, 420, 1000, 0), + 3, 0x1E00, 0, vsimcard_val_tbl, 0, 420, 1000), [CPCAP_VVIB] = CPCAP_REG(VVIBC, ASSIGN3, VVIB_SEL, 0x0001, 0x000c, - 2, 0x1, 0, vvib_val_tbl, 0, 500, 500, 0), + 2, 0x1, 0, vvib_val_tbl, 0, 500, 500), [CPCAP_VUSB] = CPCAP_REG(VUSBC, ASSIGN3, VUSB_SEL, 0x011c, 0x0040, - 6, 0xc, 0, vusb_val_tbl, 0, 0, 1000, 0), + 6, 0xc, 0, vusb_val_tbl, 0, 0, 1000), [CPCAP_VAUDIO] = CPCAP_REG(VAUDIOC, ASSIGN4, VAUDIO_SEL, 0x0016, 0x0001, - 0, 0x5, 0, vaudio_val_tbl, 0, 0, 1000, 0), + 0, 0x5, 0, vaudio_val_tbl, 0, 0, 1000), }; static int cpcap_regulator_get_value(struct udevice *dev) @@ -139,7 +138,6 @@ static int cpcap_regulator_get_value(struct udevice *dev) return 0; value &= regulator->volt_mask; - value -= regulator->bit_offset_from_cpcap_lowest_voltage; return regulator->val_tbl[value >> volt_shift]; } @@ -164,7 +162,6 @@ static int cpcap_regulator_set_value(struct udevice *dev, int uV) value = regulator->val_tbl_sz; value <<= volt_shift; - value += regulator->bit_offset_from_cpcap_lowest_voltage; } ret = pmic_clrsetbits(dev->parent, regulator->reg, regulator->volt_mask, @@ -232,7 +229,7 @@ static int cpcap_regulator_probe(struct udevice *dev) for (id = 0; id < CPCAP_REGULATORS_COUNT; id++) if (cpcap_regulator_to_name[id]) - if (!strcmp(dev->name, cpcap_regulator_to_name[id])) + if (!strcasecmp(dev->name, cpcap_regulator_to_name[id])) break; switch (id) { diff --git a/drivers/power/regulator/mt6357_regulator.c b/drivers/power/regulator/mt6357_regulator.c new file mode 100644 index 00000000000..533cc22b93a --- /dev/null +++ b/drivers/power/regulator/mt6357_regulator.c @@ -0,0 +1,512 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * MT6357 regulator driver + * + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Masson <[email protected]> + */ + +#include <dm.h> +#include <power/regulator.h> +#include <power/mt6357.h> +#include <power/pmic.h> + +enum mt6357_regulator_type { + MT6357_REG_TYPE_RANGE, + MT6357_REG_TYPE_TABLE, + MT6357_REG_TYPE_FIXED, +}; + +struct mt6357_linear_range { + unsigned int min; + unsigned int min_sel; + unsigned int max_sel; + unsigned int step; +}; + +struct mt6357_regulator_desc { + const char *name; + const char *of_match; + enum mt6357_regulator_type type; + int id; + unsigned int n_voltages; + const unsigned int *volt_table; + const struct mt6357_linear_range *linear_ranges; + int n_linear_ranges; + unsigned int min_uV; + unsigned int vsel_reg; + unsigned int vsel_mask; + unsigned int enable_reg; + unsigned int enable_mask; +}; + +struct mt6357_regulator_info { + struct mt6357_regulator_desc desc; + const u32 *index_table; + unsigned int n_table; + u32 vsel_shift; + u32 da_vsel_reg; + u32 da_vsel_mask; + u32 da_vsel_shift; +}; + +/* Initialize struct mt6357_linear_range for regulators */ +#define REGULATOR_LINEAR_RANGE(_min_uV, _min_sel, _max_sel, _step_uV) \ +{ \ + .min = _min_uV, \ + .min_sel = _min_sel, \ + .max_sel = _max_sel, \ + .step = _step_uV, \ +} + +#define MT6357_BUCK(match, vreg, min, max, step, \ + volt_ranges, vosel_reg, vosel_mask, _da_vsel_mask) \ + [MT6357_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .type = MT6357_REG_TYPE_RANGE, \ + .id = MT6357_ID_##vreg, \ + .n_voltages = ((max) - (min)) / (step) + 1, \ + .linear_ranges = volt_ranges, \ + .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ + .vsel_reg = vosel_reg, \ + .vsel_mask = vosel_mask, \ + .enable_reg = MT6357_BUCK_##vreg##_CON0, \ + .enable_mask = BIT(0), \ + }, \ + .da_vsel_reg = MT6357_BUCK_##vreg##_DBG0, \ + .da_vsel_mask = _da_vsel_mask, \ + .da_vsel_shift = 0, \ + } + +#define MT6357_LDO(match, vreg, ldo_volt_table, \ + ldo_index_table, enreg, vosel, \ + vosel_mask) \ + [MT6357_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .type = MT6357_REG_TYPE_TABLE, \ + .id = MT6357_ID_##vreg, \ + .n_voltages = ARRAY_SIZE(ldo_volt_table), \ + .volt_table = ldo_volt_table, \ + .vsel_reg = vosel, \ + .vsel_mask = vosel_mask << 8, \ + .enable_reg = enreg, \ + .enable_mask = BIT(0), \ + }, \ + .index_table = ldo_index_table, \ + .n_table = ARRAY_SIZE(ldo_index_table), \ + } + +#define MT6357_LDO1(match, vreg, min, max, step, volt_ranges, \ + enreg, vosel, vosel_mask) \ + [MT6357_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .type = MT6357_REG_TYPE_RANGE, \ + .id = MT6357_ID_##vreg, \ + .n_voltages = ((max) - (min)) / (step) + 1, \ + .linear_ranges = volt_ranges, \ + .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ + .vsel_reg = vosel, \ + .vsel_mask = vosel_mask, \ + .enable_reg = enreg, \ + .enable_mask = BIT(0), \ + }, \ + .da_vsel_reg = MT6357_LDO_##vreg##_DBG0, \ + .da_vsel_mask = 0x7f, \ + .da_vsel_shift = 8, \ + } + +#define MT6357_REG_FIXED(match, vreg, volt) \ + [MT6357_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .type = MT6357_REG_TYPE_FIXED, \ + .id = MT6357_ID_##vreg, \ + .n_voltages = 1, \ + .enable_reg = MT6357_LDO_##vreg##_CON0, \ + .enable_mask = BIT(0), \ + .min_uV = volt, \ + }, \ + } + +static int mt6357_range_find_value(const struct mt6357_linear_range *r, + unsigned int sel, + unsigned int *val) +{ + if (!val || sel < r->min_sel || sel > r->max_sel) + return -EINVAL; + + *val = r->min + r->step * (sel - r->min_sel); + + return 0; +} + +static int mt6357_range_find_selector(const struct mt6357_linear_range *r, + int val, unsigned int *sel) +{ + int num_vals = r->max_sel - r->min_sel + 1; + int ret = -EINVAL; + + if (val >= r->min && val <= r->min + r->step * (num_vals - 1)) { + if (r->step) { + *sel = r->min_sel + ((val - r->min) / r->step); + ret = 0; + } else { + *sel = r->min_sel; + ret = 0; + } + } + return ret; +} + +static int mt6357_get_enable(struct udevice *dev) +{ + struct mt6357_regulator_info *info = dev_get_priv(dev); + int ret; + + ret = pmic_reg_read(dev->parent, info->desc.enable_reg); + if (ret < 0) + return ret; + + return ret & info->desc.enable_mask ? true : false; +} + +static int mt6357_set_enable(struct udevice *dev, bool enable) +{ + struct mt6357_regulator_info *info = dev_get_priv(dev); + + return pmic_clrsetbits(dev->parent, info->desc.enable_reg, + info->desc.enable_mask, + enable ? info->desc.enable_mask : 0); +} + +static int mt6357_get_value(struct udevice *dev) +{ + struct mt6357_regulator_info *info = dev_get_priv(dev); + unsigned int val_uV; + int selector, idx, ret; + const u32 *pvol; + + switch (info->desc.type) { + case MT6357_REG_TYPE_RANGE: + selector = pmic_reg_read(dev->parent, info->da_vsel_reg); + if (selector < 0) + return selector; + + selector = (selector & info->da_vsel_mask) >> info->da_vsel_shift; + ret = mt6357_range_find_value(info->desc.linear_ranges, selector, &val_uV); + if (ret < 0) + return ret; + + return val_uV; + case MT6357_REG_TYPE_TABLE: + selector = pmic_reg_read(dev->parent, info->desc.vsel_reg); + if (selector < 0) + return selector; + + selector = (selector & info->desc.vsel_mask) >> 8; + pvol = info->index_table; + + for (idx = 0; idx < info->desc.n_voltages; idx++) { + if (pvol[idx] == selector) + return info->desc.volt_table[idx]; + } + + return -EINVAL; + case MT6357_REG_TYPE_FIXED: + return info->desc.min_uV; + default: + return -EINVAL; + } +} + +static int mt6357_set_value(struct udevice *dev, int uvolt) +{ + struct mt6357_regulator_info *info = dev_get_priv(dev); + int selector, idx, ret; + const u32 *pvol; + + switch (info->desc.type) { + case MT6357_REG_TYPE_RANGE: + ret = mt6357_range_find_selector(info->desc.linear_ranges, uvolt, + &selector); + if (ret < 0) + return ret; + + return pmic_clrsetbits(dev->parent, info->desc.vsel_reg, + info->desc.vsel_mask, selector); + case MT6357_REG_TYPE_TABLE: + pvol = info->desc.volt_table; + + for (idx = 0; idx < info->desc.n_voltages; idx++) { + if (pvol[idx] == uvolt) { + selector = info->index_table[idx]; + + return pmic_clrsetbits(dev->parent, info->desc.vsel_reg, + info->desc.vsel_mask, selector << 8); + } + } + + return -EINVAL; + default: + return -EINVAL; + } +} + +static const int vxo22_voltages[] = { + 2200000, + 2400000, +}; + +static const int vefuse_voltages[] = { + 1200000, + 1300000, + 1500000, + 1800000, + 2800000, + 2900000, + 3000000, + 3300000, +}; + +static const int vcn33_voltages[] = { + 3300000, + 3400000, + 3500000, +}; + +static const int vcama_voltages[] = { + 2500000, + 2800000, +}; + +static const int vcamd_voltages[] = { + 1000000, + 1100000, + 1200000, + 1300000, + 1500000, + 1800000, +}; + +static const int vldo28_voltages[] = { + 2800000, + 3000000, +}; + +static const int vdram_voltages[] = { + 1100000, + 1200000, +}; + +static const int vsim_voltages[] = { + 1700000, + 1800000, + 2700000, + 3000000, + 3100000, +}; + +static const int vibr_voltages[] = { + 1200000, + 1300000, + 1500000, + 1800000, + 2000000, + 2800000, + 3000000, + 3300000, +}; + +static const int vmc_voltages[] = { + 1800000, + 2900000, + 3000000, + 3300000, +}; + +static const int vmch_voltages[] = { + 2900000, + 3000000, + 3300000, +}; + +static const int vemc_voltages[] = { + 2900000, + 3000000, + 3300000, +}; + +static const int vusb_voltages[] = { + 3000000, + 3100000, +}; + +static const int vmc_idx[] = { + 4, 10, 11, 13, +}; + +static const int vmch_idx[] = { + 2, 3, 5, +}; + +static const int vemc_idx[] = { + 2, 3, 5, +}; + +static const int vusb_idx[] = { + 3, 4, +}; + +static const int vxo22_idx[] = { + 0, 2, +}; + +static const int vefuse_idx[] = { + 0, 1, 2, 4, 9, 10, 11, 13, +}; + +static const int vcn33_idx[] = { + 1, 2, 3, +}; + +static const int vcama_idx[] = { + 7, 10, +}; + +static const int vcamd_idx[] = { + 4, 5, 6, 7, 9, 12, +}; + +static const int vldo28_idx[] = { + 1, 3, +}; + +static const int vdram_idx[] = { + 1, 2, +}; + +static const int vsim_idx[] = { + 3, 4, 8, 11, 12, +}; + +static const int vibr_idx[] = { + 0, 1, 2, 4, 5, 9, 11, 13, +}; + +static const struct mt6357_linear_range buck_volt_range1[] = { + REGULATOR_LINEAR_RANGE(518750, 0, 0x7f, 6250), +}; + +static const struct mt6357_linear_range buck_volt_range2[] = { + REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250), +}; + +static const struct mt6357_linear_range buck_volt_range3[] = { + REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000), +}; + +static const struct mt6357_linear_range buck_volt_range4[] = { + REGULATOR_LINEAR_RANGE(1200000, 0, 0x7f, 12500), +}; + +/* The array is indexed by id(MT6357_ID_XXX) */ +static struct mt6357_regulator_info mt6357_regulators[] = { + /* Bucks */ + MT6357_BUCK("buck-vcore", VCORE, 518750, 1312500, 6250, + buck_volt_range1, MT6357_BUCK_VCORE_ELR0, 0x7f, 0x7f), + MT6357_BUCK("buck-vproc", VPROC, 518750, 1312500, 6250, + buck_volt_range1, MT6357_BUCK_VPROC_ELR0, 0x7f, 0x7f), + MT6357_BUCK("buck-vmodem", VMODEM, 500000, 1293750, 6250, + buck_volt_range2, MT6357_BUCK_VMODEM_ELR0, 0x7f, 0x7f), + MT6357_BUCK("buck-vpa", VPA, 500000, 3650000, 50000, + buck_volt_range3, MT6357_BUCK_VPA_CON1, 0x3f, 0x3f), + MT6357_BUCK("buck-vs1", VS1, 1200000, 2787500, 12500, + buck_volt_range4, MT6357_BUCK_VS1_ELR0, 0x7f, 0x7f), + + /* LDOs */ + MT6357_LDO("ldo-vcama", VCAMA, vcama_voltages, vcama_idx, + MT6357_LDO_VCAMA_CON0, MT6357_VCAMA_ANA_CON0, 0xf), + MT6357_LDO("ldo-vcamd", VCAMD, vcamd_voltages, vcamd_idx, + MT6357_LDO_VCAMD_CON0, MT6357_VCAMD_ANA_CON0, 0xf), + MT6357_LDO("ldo-vcn33-bt", VCN33_BT, vcn33_voltages, vcn33_idx, + MT6357_LDO_VCN33_CON0_0, MT6357_VCN33_ANA_CON0, 0x3), + MT6357_LDO("ldo-vcn33-wifi", VCN33_WIFI, vcn33_voltages, vcn33_idx, + MT6357_LDO_VCN33_CON0_1, MT6357_VCN33_ANA_CON0, 0x3), + MT6357_LDO("ldo-vdram", VDRAM, vdram_voltages, vdram_idx, + MT6357_LDO_VDRAM_CON0, MT6357_VDRAM_ELR_2, 0x3), + MT6357_LDO("ldo-vefuse", VEFUSE, vefuse_voltages, vefuse_idx, + MT6357_LDO_VEFUSE_CON0, MT6357_VEFUSE_ANA_CON0, 0xf), + MT6357_LDO("ldo-vemc", VEMC, vemc_voltages, vemc_idx, + MT6357_LDO_VEMC_CON0, MT6357_VEMC_ANA_CON0, 0x7), + MT6357_LDO("ldo-vibr", VIBR, vibr_voltages, vibr_idx, + MT6357_LDO_VIBR_CON0, MT6357_VIBR_ANA_CON0, 0xf), + MT6357_LDO("ldo-vldo28", VLDO28, vldo28_voltages, vldo28_idx, + MT6357_LDO_VLDO28_CON0_0, MT6357_VLDO28_ANA_CON0, 0x3), + MT6357_LDO("ldo-vmc", VMC, vmc_voltages, vmc_idx, + MT6357_LDO_VMC_CON0, MT6357_VMC_ANA_CON0, 0xf), + MT6357_LDO("ldo-vmch", VMCH, vmch_voltages, vmch_idx, + MT6357_LDO_VMCH_CON0, MT6357_VMCH_ANA_CON0, 0x7), + MT6357_LDO("ldo-vsim1", VSIM1, vsim_voltages, vsim_idx, + MT6357_LDO_VSIM1_CON0, MT6357_VSIM1_ANA_CON0, 0xf), + MT6357_LDO("ldo-vsim2", VSIM2, vsim_voltages, vsim_idx, + MT6357_LDO_VSIM2_CON0, MT6357_VSIM2_ANA_CON0, 0xf), + MT6357_LDO("ldo-vusb33", VUSB33, vusb_voltages, vusb_idx, + MT6357_LDO_VUSB33_CON0_0, MT6357_VUSB33_ANA_CON0, 0x7), + MT6357_LDO("ldo-vxo22", VXO22, vxo22_voltages, vxo22_idx, + MT6357_LDO_VXO22_CON0, MT6357_VXO22_ANA_CON0, 0x3), + + MT6357_LDO1("ldo-vsram-proc", VSRAM_PROC, 518750, 1312500, 6250, + buck_volt_range1, MT6357_LDO_VSRAM_PROC_CON0, + MT6357_LDO_VSRAM_CON0, 0x7f), + MT6357_LDO1("ldo-vsram-others", VSRAM_OTHERS, 518750, 1312500, 6250, + buck_volt_range1, MT6357_LDO_VSRAM_OTHERS_CON0, + MT6357_LDO_VSRAM_CON1, 0x7f), + + MT6357_REG_FIXED("ldo-vaud28", VAUD28, 2800000), + MT6357_REG_FIXED("ldo-vaux18", VAUX18, 1800000), + MT6357_REG_FIXED("ldo-vcamio18", VCAMIO, 1800000), + MT6357_REG_FIXED("ldo-vcn18", VCN18, 1800000), + MT6357_REG_FIXED("ldo-vcn28", VCN28, 2800000), + MT6357_REG_FIXED("ldo-vfe28", VFE28, 2800000), + MT6357_REG_FIXED("ldo-vio18", VIO18, 1800000), + MT6357_REG_FIXED("ldo-vio28", VIO28, 2800000), + MT6357_REG_FIXED("ldo-vrf12", VRF12, 1200000), + MT6357_REG_FIXED("ldo-vrf18", VRF18, 1800000), +}; + +static int mt6357_regulator_probe(struct udevice *dev) +{ + struct mt6357_regulator_info *priv = dev_get_priv(dev); + int i; + + for (i = 0; i < ARRAY_SIZE(mt6357_regulators); i++) { + if (!strcmp(dev->name, mt6357_regulators[i].desc.of_match)) { + *priv = mt6357_regulators[i]; + return 0; + } + } + + return -ENOENT; +} + +static const struct dm_regulator_ops mt6357_regulator_ops = { + .get_value = mt6357_get_value, + .set_value = mt6357_set_value, + .get_enable = mt6357_get_enable, + .set_enable = mt6357_set_enable, +}; + +U_BOOT_DRIVER(mt6357_regulator) = { + .name = MT6357_REGULATOR_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &mt6357_regulator_ops, + .probe = mt6357_regulator_probe, + .priv_auto = sizeof(struct mt6357_regulator_info), +}; diff --git a/drivers/power/regulator/mt6359_regulator.c b/drivers/power/regulator/mt6359_regulator.c new file mode 100644 index 00000000000..cdafcfcb25e --- /dev/null +++ b/drivers/power/regulator/mt6359_regulator.c @@ -0,0 +1,711 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 MediaTek Inc. All Rights Reserved. + * Author: Bo-Chen Chen <[email protected]> + */ + +#include <dm.h> +#include <linux/bitops.h> +#include <linux/kernel.h> +#include <power/mt6359.h> +#include <power/mt6359p.h> +#include <power/pmic.h> +#include <power/regulator.h> + +#include <dm/device.h> +#include <dm/device_compat.h> + +enum mt6359_regulator_type { + MT6359_REG_TYPE_LINEAR, + MT6359_REG_TYPE_TABLE, + MT6359_REG_TYPE_FIXED, + MT6359_REG_TYPE_VEMC, +}; + +struct regulator_desc { + const char *name; + const char *of_match; + enum mt6359_regulator_type type; + int id; + unsigned int uV_step; + unsigned int n_voltages; + const unsigned int *volt_table; + unsigned int min_uV; + unsigned int vsel_reg; + unsigned int vsel_mask; + unsigned int enable_reg; + unsigned int enable_mask; + unsigned int fixed_uV; +}; + +/* + * MT6359 regulators' information + * + * @desc: standard fields of regulator description. + * @status_reg: for query status of regulators. + * @qi: Mask for query enable signal status of regulators. + * @modeset_reg: for operating AUTO/PWM mode register. + * @modeset_mask: MASK for operating modeset register. + */ +struct mt6359_regulator_info { + struct regulator_desc desc; + u32 status_reg; + u32 qi; + u32 modeset_reg; + u32 modeset_mask; + u32 lp_mode_reg; + u32 lp_mode_mask; +}; + +#define MT6359_BUCK(match, _name, _min, _max, _step, \ + _enable_reg, _status_reg, \ + _vsel_reg, _vsel_mask, \ + _lp_mode_reg, _lp_mode_shift, \ + _modeset_reg, _modeset_shift) \ +[MT6359_ID_##_name] = { \ + .desc = { \ + .name = #_name, \ + .of_match = of_match_ptr(match), \ + .type = MT6359_REG_TYPE_LINEAR, \ + .id = MT6359_ID_##_name, \ + .uV_step = (_step), \ + .n_voltages = ((_max) - (_min)) / (_step) + 1, \ + .min_uV = (_min), \ + .vsel_reg = _vsel_reg, \ + .vsel_mask = _vsel_mask, \ + .enable_reg = _enable_reg, \ + .enable_mask = BIT(0), \ + }, \ + .status_reg = _status_reg, \ + .qi = BIT(0), \ + .lp_mode_reg = _lp_mode_reg, \ + .lp_mode_mask = BIT(_lp_mode_shift), \ + .modeset_reg = _modeset_reg, \ + .modeset_mask = BIT(_modeset_shift), \ +} + +#define MT6359_LDO_LINEAR(match, _name, _min, _max, _step, \ + _enable_reg, _status_reg, _vsel_reg, _vsel_mask) \ +[MT6359_ID_##_name] = { \ + .desc = { \ + .name = #_name, \ + .of_match = of_match_ptr(match), \ + .type = MT6359_REG_TYPE_LINEAR, \ + .id = MT6359_ID_##_name, \ + .uV_step = (_step), \ + .n_voltages = ((_max) - (_min)) / (_step) + 1, \ + .min_uV = (_min), \ + .vsel_reg = _vsel_reg, \ + .vsel_mask = _vsel_mask, \ + .enable_reg = _enable_reg, \ + .enable_mask = BIT(0), \ + }, \ + .status_reg = _status_reg, \ + .qi = BIT(0), \ +} + +#define MT6359_LDO(match, _name, _tmp_volt_table, \ + _enable_reg, _enable_mask, _status_reg, \ + _vsel_reg, _vsel_mask, _en_delay) \ +[MT6359_ID_##_name] = { \ + .desc = { \ + .name = #_name, \ + .of_match = of_match_ptr(match), \ + .type = MT6359_REG_TYPE_TABLE, \ + .id = MT6359_ID_##_name, \ + .n_voltages = ARRAY_SIZE(_tmp_volt_table), \ + .volt_table = _tmp_volt_table, \ + .vsel_reg = _vsel_reg, \ + .vsel_mask = _vsel_mask, \ + .enable_reg = _enable_reg, \ + .enable_mask = BIT(_enable_mask), \ + }, \ + .status_reg = _status_reg, \ + .qi = BIT(0), \ +} + +#define MT6359_REG_FIXED(match, _name, _enable_reg, \ + _status_reg, _fixed_volt) \ +[MT6359_ID_##_name] = { \ + .desc = { \ + .name = #_name, \ + .of_match = of_match_ptr(match), \ + .type = MT6359_REG_TYPE_FIXED, \ + .id = MT6359_ID_##_name, \ + .n_voltages = 1, \ + .enable_reg = _enable_reg, \ + .enable_mask = BIT(0), \ + .fixed_uV = (_fixed_volt), \ + }, \ + .status_reg = _status_reg, \ + .qi = BIT(0), \ +} + +#define MT6359P_LDO1(match, _name, _type, _tmp_volt_table, \ + _enable_reg, _enable_mask, _status_reg, \ + _vsel_reg, _vsel_mask) \ +[MT6359_ID_##_name] = { \ + .desc = { \ + .name = #_name, \ + .of_match = of_match_ptr(match), \ + .type = _type, \ + .id = MT6359_ID_##_name, \ + .n_voltages = ARRAY_SIZE(_tmp_volt_table), \ + .volt_table = _tmp_volt_table, \ + .vsel_reg = _vsel_reg, \ + .vsel_mask = _vsel_mask, \ + .enable_reg = _enable_reg, \ + .enable_mask = BIT(_enable_mask), \ + }, \ + .status_reg = _status_reg, \ + .qi = BIT(0), \ +} + +static const unsigned int vsim1_voltages[] = { + 0, 0, 0, 1700000, 1800000, 0, 0, 0, 2700000, 0, 0, 3000000, 3100000, +}; + +static const unsigned int vibr_voltages[] = { + 1200000, 1300000, 1500000, 0, 1800000, 2000000, 0, 0, 2700000, 2800000, + 0, 3000000, 0, 3300000, +}; + +static const unsigned int vrf12_voltages[] = { + 0, 0, 1100000, 1200000, 1300000, +}; + +static const unsigned int volt18_voltages[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1700000, 1800000, 1900000, +}; + +static const unsigned int vcn13_voltages[] = { + 900000, 1000000, 0, 1200000, 1300000, +}; + +static const unsigned int vcn33_voltages[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 2800000, 0, 0, 0, 3300000, 3400000, 3500000, +}; + +static const unsigned int vefuse_voltages[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1700000, 1800000, 1900000, 2000000, +}; + +static const unsigned int vxo22_voltages[] = { + 1800000, 0, 0, 0, 2200000, +}; + +static const unsigned int vrfck_voltages_1[] = { + 1240000, 1600000, +}; + +static const unsigned int vio28_voltages[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 2800000, 2900000, 3000000, 3100000, 3300000, +}; + +static const unsigned int vemc_voltages_1[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 2500000, 2800000, 2900000, 3000000, 3100000, + 3300000, +}; + +static const unsigned int va12_voltages[] = { + 0, 0, 0, 0, 0, 0, 1200000, 1300000, +}; + +static const unsigned int va09_voltages[] = { + 0, 0, 800000, 900000, 0, 0, 1200000, +}; + +static const unsigned int vrf18_voltages[] = { + 0, 0, 0, 0, 0, 1700000, 1800000, 1810000, +}; + +static const unsigned int vbbck_voltages[] = { + 0, 0, 0, 0, 1100000, 0, 0, 0, 1150000, 0, 0, 0, 1200000, +}; + +static const unsigned int vsim2_voltages[] = { + 0, 0, 0, 1700000, 1800000, 0, 0, 0, 2700000, 0, 0, 3000000, 3100000, +}; + +static int mt6359_set_voltage_sel_regmap(struct udevice *dev, + struct mt6359_regulator_info *info, + unsigned int sel) +{ + sel <<= ffs(info->desc.vsel_mask) - 1; + + return pmic_clrsetbits(dev->parent, info->desc.vsel_reg, + info->desc.vsel_mask, sel); +} + +static int mt6359p_vemc_set_voltage_sel(struct udevice *dev, + struct mt6359_regulator_info *info, unsigned int sel) +{ + int ret; + + sel <<= ffs(info->desc.vsel_mask) - 1; + ret = pmic_reg_write(dev->parent, MT6359P_TMA_KEY_ADDR, MT6359P_TMA_KEY); + if (ret) + return ret; + + ret = pmic_reg_read(dev->parent, MT6359P_VM_MODE_ADDR); + if (ret < 0) + return ret; + + switch (ret) { + case 0: + /* If HW trapping is 0, use VEMC_VOSEL_0 */ + ret = pmic_clrsetbits(dev->parent, info->desc.vsel_reg, + info->desc.vsel_mask, sel); + if (ret) + return ret; + + break; + case 1: + /* If HW trapping is 1, use VEMC_VOSEL_1 */ + ret = pmic_clrsetbits(dev->parent, info->desc.vsel_reg + 0x2, + info->desc.vsel_mask, sel); + if (ret) + return ret; + + break; + default: + return -EINVAL; + } + + return pmic_reg_write(dev->parent, MT6359P_TMA_KEY_ADDR, 0); +} + +static int mt6359_get_voltage_sel(struct udevice *dev, struct mt6359_regulator_info *info) +{ + int selector; + + selector = pmic_reg_read(dev->parent, info->desc.vsel_reg); + if (selector < 0) + return selector; + + selector &= info->desc.vsel_mask; + selector >>= ffs(info->desc.vsel_mask) - 1; + + return selector; +} + +static int mt6359p_vemc_get_voltage_sel(struct udevice *dev, struct mt6359_regulator_info *info) +{ + int selector; + + switch (pmic_reg_read(dev->parent, MT6359P_VM_MODE_ADDR)) { + case 0: + /* If HW trapping is 0, use VEMC_VOSEL_0 */ + selector = pmic_reg_read(dev->parent, info->desc.vsel_reg); + break; + case 1: + /* If HW trapping is 1, use VEMC_VOSEL_1 */ + selector = pmic_reg_read(dev->parent, info->desc.vsel_reg + 0x2); + break; + default: + return -EINVAL; + } + if (selector < 0) + return selector; + + selector &= info->desc.vsel_mask; + selector >>= ffs(info->desc.vsel_mask) - 1; + + return selector; +} + +static int mt6359_get_enable(struct udevice *dev) +{ + struct mt6359_regulator_info *info = dev_get_priv(dev); + int ret; + + ret = pmic_reg_read(dev->parent, info->desc.enable_reg); + if (ret < 0) + return ret; + + return ret & info->desc.enable_mask ? true : false; +} + +static int mt6359_set_enable(struct udevice *dev, bool enable) +{ + struct mt6359_regulator_info *info = dev_get_priv(dev); + + return pmic_clrsetbits(dev->parent, info->desc.enable_reg, + info->desc.enable_mask, + enable ? info->desc.enable_mask : 0); +} + +static int mt6359_get_value(struct udevice *dev) +{ + struct mt6359_regulator_info *info = dev_get_priv(dev); + int selector; + + switch (info->desc.type) { + case MT6359_REG_TYPE_LINEAR: + /* Get selection */ + selector = mt6359_get_voltage_sel(dev, info); + if (selector < 0) + return -EINVAL; + + /* Get voltage value */ + if (selector >= info->desc.n_voltages) + return -EINVAL; + + return info->desc.min_uV + (info->desc.uV_step * selector); + case MT6359_REG_TYPE_TABLE: + /* Get selection */ + selector = mt6359_get_voltage_sel(dev, info); + if (selector < 0) + return -EINVAL; + + /* Get voltage value */ + if (!info->desc.volt_table) { + dev_err(dev, "invalid voltage table for %s\n", info->desc.name); + return -EINVAL; + } + + if (selector >= info->desc.n_voltages) + return -EINVAL; + + return info->desc.volt_table[selector]; + case MT6359_REG_TYPE_FIXED: + return info->desc.fixed_uV; + case MT6359_REG_TYPE_VEMC: + /* Get selection */ + selector = mt6359p_vemc_get_voltage_sel(dev, info); + if (selector < 0) + return -EINVAL; + + /* Get voltage value */ + if (!info->desc.volt_table) { + dev_err(dev, "invalid voltage table for %s\n", info->desc.name); + return -EINVAL; + } + + if (selector >= info->desc.n_voltages) + return -EINVAL; + + return info->desc.volt_table[selector]; + default: + return -EINVAL; + } +} + +static int mt6359_set_value(struct udevice *dev, int uvolt) +{ + struct mt6359_regulator_info *info = dev_get_priv(dev); + int selector; + int i; + + switch (info->desc.type) { + case MT6359_REG_TYPE_LINEAR: + /* Find selection */ + if (uvolt < info->desc.min_uV) + return -EINVAL; + selector = DIV_ROUND_UP(uvolt - info->desc.min_uV, info->desc.uV_step); + if (selector < 0) + return -EINVAL; + + /* Set selection */ + return mt6359_set_voltage_sel_regmap(dev, info, selector); + case MT6359_REG_TYPE_TABLE: + /* Find selection */ + for (i = 0; i < info->desc.n_voltages; i++) { + if (info->desc.volt_table[i] == uvolt) + return mt6359_set_voltage_sel_regmap(dev, info, i); + } + + return -EINVAL; + case MT6359_REG_TYPE_VEMC: + /* Find selection */ + for (i = 0; i < info->desc.n_voltages; i++) { + if (info->desc.volt_table[i] == uvolt) + return mt6359p_vemc_set_voltage_sel(dev, info, i); + } + + return -EINVAL; + default: + return -EINVAL; + } +} + +static struct mt6359_regulator_info mt6359p_regulators[] = { + MT6359_BUCK("buck_vs1", VS1, 800000, 2200000, 12500, + MT6359_RG_BUCK_VS1_EN_ADDR, + MT6359_DA_VS1_EN_ADDR, MT6359_RG_BUCK_VS1_VOSEL_ADDR, + MT6359_RG_BUCK_VS1_VOSEL_MASK << + MT6359_RG_BUCK_VS1_VOSEL_SHIFT, + MT6359_RG_BUCK_VS1_LP_ADDR, MT6359_RG_BUCK_VS1_LP_SHIFT, + MT6359_RG_VS1_FPWM_ADDR, MT6359_RG_VS1_FPWM_SHIFT), + MT6359_BUCK("buck_vgpu11", VGPU11, 400000, 1193750, 6250, + MT6359_RG_BUCK_VGPU11_EN_ADDR, + MT6359_DA_VGPU11_EN_ADDR, MT6359P_RG_BUCK_VGPU11_VOSEL_ADDR, + MT6359_RG_BUCK_VGPU11_VOSEL_MASK << + MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT, + MT6359_RG_BUCK_VGPU11_LP_ADDR, + MT6359_RG_BUCK_VGPU11_LP_SHIFT, + MT6359_RG_VGPU11_FCCM_ADDR, MT6359_RG_VGPU11_FCCM_SHIFT), + MT6359_BUCK("buck_vmodem", VMODEM, 400000, 1100000, 6250, + MT6359_RG_BUCK_VMODEM_EN_ADDR, + MT6359_DA_VMODEM_EN_ADDR, MT6359_RG_BUCK_VMODEM_VOSEL_ADDR, + MT6359_RG_BUCK_VMODEM_VOSEL_MASK << + MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT, + MT6359_RG_BUCK_VMODEM_LP_ADDR, + MT6359_RG_BUCK_VMODEM_LP_SHIFT, + MT6359_RG_VMODEM_FCCM_ADDR, MT6359_RG_VMODEM_FCCM_SHIFT), + MT6359_BUCK("buck_vpu", VPU, 400000, 1193750, 6250, + MT6359_RG_BUCK_VPU_EN_ADDR, + MT6359_DA_VPU_EN_ADDR, MT6359_RG_BUCK_VPU_VOSEL_ADDR, + MT6359_RG_BUCK_VPU_VOSEL_MASK << + MT6359_RG_BUCK_VPU_VOSEL_SHIFT, + MT6359_RG_BUCK_VPU_LP_ADDR, MT6359_RG_BUCK_VPU_LP_SHIFT, + MT6359_RG_VPU_FCCM_ADDR, MT6359_RG_VPU_FCCM_SHIFT), + MT6359_BUCK("buck_vcore", VCORE, 506250, 1300000, 6250, + MT6359_RG_BUCK_VCORE_EN_ADDR, + MT6359_DA_VCORE_EN_ADDR, MT6359P_RG_BUCK_VCORE_VOSEL_ADDR, + MT6359_RG_BUCK_VCORE_VOSEL_MASK << + MT6359_RG_BUCK_VCORE_VOSEL_SHIFT, + MT6359_RG_BUCK_VCORE_LP_ADDR, MT6359_RG_BUCK_VCORE_LP_SHIFT, + MT6359_RG_VCORE_FCCM_ADDR, MT6359_RG_VCORE_FCCM_SHIFT), + MT6359_BUCK("buck_vs2", VS2, 800000, 1600000, 12500, + MT6359_RG_BUCK_VS2_EN_ADDR, + MT6359_DA_VS2_EN_ADDR, MT6359_RG_BUCK_VS2_VOSEL_ADDR, + MT6359_RG_BUCK_VS2_VOSEL_MASK << + MT6359_RG_BUCK_VS2_VOSEL_SHIFT, + MT6359_RG_BUCK_VS2_LP_ADDR, MT6359_RG_BUCK_VS2_LP_SHIFT, + MT6359_RG_VS2_FPWM_ADDR, MT6359_RG_VS2_FPWM_SHIFT), + MT6359_BUCK("buck_vpa", VPA, 500000, 3650000, 50000, + MT6359_RG_BUCK_VPA_EN_ADDR, + MT6359_DA_VPA_EN_ADDR, MT6359_RG_BUCK_VPA_VOSEL_ADDR, + MT6359_RG_BUCK_VPA_VOSEL_MASK << + MT6359_RG_BUCK_VPA_VOSEL_SHIFT, + MT6359_RG_BUCK_VPA_LP_ADDR, MT6359_RG_BUCK_VPA_LP_SHIFT, + MT6359_RG_VPA_MODESET_ADDR, MT6359_RG_VPA_MODESET_SHIFT), + MT6359_BUCK("buck_vproc2", VPROC2, 400000, 1193750, 6250, + MT6359_RG_BUCK_VPROC2_EN_ADDR, + MT6359_DA_VPROC2_EN_ADDR, MT6359_RG_BUCK_VPROC2_VOSEL_ADDR, + MT6359_RG_BUCK_VPROC2_VOSEL_MASK << + MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT, + MT6359_RG_BUCK_VPROC2_LP_ADDR, + MT6359_RG_BUCK_VPROC2_LP_SHIFT, + MT6359_RG_VPROC2_FCCM_ADDR, MT6359_RG_VPROC2_FCCM_SHIFT), + MT6359_BUCK("buck_vproc1", VPROC1, 400000, 1193750, 6250, + MT6359_RG_BUCK_VPROC1_EN_ADDR, + MT6359_DA_VPROC1_EN_ADDR, MT6359_RG_BUCK_VPROC1_VOSEL_ADDR, + MT6359_RG_BUCK_VPROC1_VOSEL_MASK << + MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT, + MT6359_RG_BUCK_VPROC1_LP_ADDR, + MT6359_RG_BUCK_VPROC1_LP_SHIFT, + MT6359_RG_VPROC1_FCCM_ADDR, MT6359_RG_VPROC1_FCCM_SHIFT), + MT6359_BUCK("buck_vgpu11_sshub", VGPU11_SSHUB, 400000, 1193750, 6250, + MT6359P_RG_BUCK_VGPU11_SSHUB_EN_ADDR, + MT6359_DA_VGPU11_EN_ADDR, + MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_ADDR, + MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_MASK << + MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_SHIFT, + MT6359_RG_BUCK_VGPU11_LP_ADDR, + MT6359_RG_BUCK_VGPU11_LP_SHIFT, + MT6359_RG_VGPU11_FCCM_ADDR, MT6359_RG_VGPU11_FCCM_SHIFT), + MT6359_REG_FIXED("ldo_vaud18", VAUD18, MT6359P_RG_LDO_VAUD18_EN_ADDR, + MT6359P_DA_VAUD18_B_EN_ADDR, 1800000), + MT6359_LDO("ldo_vsim1", VSIM1, vsim1_voltages, + MT6359P_RG_LDO_VSIM1_EN_ADDR, MT6359P_RG_LDO_VSIM1_EN_SHIFT, + MT6359P_DA_VSIM1_B_EN_ADDR, MT6359P_RG_VSIM1_VOSEL_ADDR, + MT6359_RG_VSIM1_VOSEL_MASK << MT6359_RG_VSIM1_VOSEL_SHIFT, + 480), + MT6359_LDO("ldo_vibr", VIBR, vibr_voltages, + MT6359P_RG_LDO_VIBR_EN_ADDR, MT6359P_RG_LDO_VIBR_EN_SHIFT, + MT6359P_DA_VIBR_B_EN_ADDR, MT6359P_RG_VIBR_VOSEL_ADDR, + MT6359_RG_VIBR_VOSEL_MASK << MT6359_RG_VIBR_VOSEL_SHIFT, + 240), + MT6359_LDO("ldo_vrf12", VRF12, vrf12_voltages, + MT6359P_RG_LDO_VRF12_EN_ADDR, MT6359P_RG_LDO_VRF12_EN_SHIFT, + MT6359P_DA_VRF12_B_EN_ADDR, MT6359P_RG_VRF12_VOSEL_ADDR, + MT6359_RG_VRF12_VOSEL_MASK << MT6359_RG_VRF12_VOSEL_SHIFT, + 480), + MT6359_REG_FIXED("ldo_vusb", VUSB, MT6359P_RG_LDO_VUSB_EN_0_ADDR, + MT6359P_DA_VUSB_B_EN_ADDR, 3000000), + MT6359_LDO_LINEAR("ldo_vsram_proc2", VSRAM_PROC2, 500000, 1293750, 6250, + MT6359P_RG_LDO_VSRAM_PROC2_EN_ADDR, + MT6359P_DA_VSRAM_PROC2_B_EN_ADDR, + MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_ADDR, + MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK << + MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT), + MT6359_LDO("ldo_vio18", VIO18, volt18_voltages, + MT6359P_RG_LDO_VIO18_EN_ADDR, MT6359P_RG_LDO_VIO18_EN_SHIFT, + MT6359P_DA_VIO18_B_EN_ADDR, MT6359P_RG_VIO18_VOSEL_ADDR, + MT6359_RG_VIO18_VOSEL_MASK << MT6359_RG_VIO18_VOSEL_SHIFT, + 960), + MT6359_LDO("ldo_vcamio", VCAMIO, volt18_voltages, + MT6359P_RG_LDO_VCAMIO_EN_ADDR, + MT6359P_RG_LDO_VCAMIO_EN_SHIFT, + MT6359P_DA_VCAMIO_B_EN_ADDR, MT6359P_RG_VCAMIO_VOSEL_ADDR, + MT6359_RG_VCAMIO_VOSEL_MASK << MT6359_RG_VCAMIO_VOSEL_SHIFT, + 1290), + MT6359_REG_FIXED("ldo_vcn18", VCN18, MT6359P_RG_LDO_VCN18_EN_ADDR, + MT6359P_DA_VCN18_B_EN_ADDR, 1800000), + MT6359_REG_FIXED("ldo_vfe28", VFE28, MT6359P_RG_LDO_VFE28_EN_ADDR, + MT6359P_DA_VFE28_B_EN_ADDR, 2800000), + MT6359_LDO("ldo_vcn13", VCN13, vcn13_voltages, + MT6359P_RG_LDO_VCN13_EN_ADDR, MT6359P_RG_LDO_VCN13_EN_SHIFT, + MT6359P_DA_VCN13_B_EN_ADDR, MT6359P_RG_VCN13_VOSEL_ADDR, + MT6359_RG_VCN13_VOSEL_MASK << MT6359_RG_VCN13_VOSEL_SHIFT, + 240), + MT6359_LDO("ldo_vcn33_1_bt", VCN33_1_BT, vcn33_voltages, + MT6359P_RG_LDO_VCN33_1_EN_0_ADDR, + MT6359_RG_LDO_VCN33_1_EN_0_SHIFT, + MT6359P_DA_VCN33_1_B_EN_ADDR, MT6359P_RG_VCN33_1_VOSEL_ADDR, + MT6359_RG_VCN33_1_VOSEL_MASK << + MT6359_RG_VCN33_1_VOSEL_SHIFT, 240), + MT6359_LDO("ldo_vcn33_1_wifi", VCN33_1_WIFI, vcn33_voltages, + MT6359P_RG_LDO_VCN33_1_EN_1_ADDR, + MT6359P_RG_LDO_VCN33_1_EN_1_SHIFT, + MT6359P_DA_VCN33_1_B_EN_ADDR, MT6359P_RG_VCN33_1_VOSEL_ADDR, + MT6359_RG_VCN33_1_VOSEL_MASK << + MT6359_RG_VCN33_1_VOSEL_SHIFT, 240), + MT6359_REG_FIXED("ldo_vaux18", VAUX18, MT6359P_RG_LDO_VAUX18_EN_ADDR, + MT6359P_DA_VAUX18_B_EN_ADDR, 1800000), + MT6359_LDO_LINEAR("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, 6250, + MT6359P_RG_LDO_VSRAM_OTHERS_EN_ADDR, + MT6359P_DA_VSRAM_OTHERS_B_EN_ADDR, + MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR, + MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK << + MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT), + MT6359_LDO("ldo_vefuse", VEFUSE, vefuse_voltages, + MT6359P_RG_LDO_VEFUSE_EN_ADDR, + MT6359P_RG_LDO_VEFUSE_EN_SHIFT, + MT6359P_DA_VEFUSE_B_EN_ADDR, MT6359P_RG_VEFUSE_VOSEL_ADDR, + MT6359_RG_VEFUSE_VOSEL_MASK << MT6359_RG_VEFUSE_VOSEL_SHIFT, + 240), + MT6359_LDO("ldo_vxo22", VXO22, vxo22_voltages, + MT6359P_RG_LDO_VXO22_EN_ADDR, MT6359P_RG_LDO_VXO22_EN_SHIFT, + MT6359P_DA_VXO22_B_EN_ADDR, MT6359P_RG_VXO22_VOSEL_ADDR, + MT6359_RG_VXO22_VOSEL_MASK << MT6359_RG_VXO22_VOSEL_SHIFT, + 480), + MT6359_LDO("ldo_vrfck", VRFCK, vrfck_voltages_1, + MT6359P_RG_LDO_VRFCK_EN_ADDR, MT6359P_RG_LDO_VRFCK_EN_SHIFT, + MT6359P_DA_VRFCK_B_EN_ADDR, MT6359P_RG_VRFCK_VOSEL_ADDR, + MT6359_RG_VRFCK_VOSEL_MASK << MT6359_RG_VRFCK_VOSEL_SHIFT, + 480), + MT6359_LDO("ldo_vrfck_1", VRFCK, vrfck_voltages_1, + MT6359P_RG_LDO_VRFCK_EN_ADDR, MT6359P_RG_LDO_VRFCK_EN_SHIFT, + MT6359P_DA_VRFCK_B_EN_ADDR, MT6359P_RG_VRFCK_VOSEL_ADDR, + MT6359_RG_VRFCK_VOSEL_MASK << MT6359_RG_VRFCK_VOSEL_SHIFT, + 480), + MT6359_REG_FIXED("ldo_vbif28", VBIF28, MT6359P_RG_LDO_VBIF28_EN_ADDR, + MT6359P_DA_VBIF28_B_EN_ADDR, 2800000), + MT6359_LDO("ldo_vio28", VIO28, vio28_voltages, + MT6359P_RG_LDO_VIO28_EN_ADDR, MT6359P_RG_LDO_VIO28_EN_SHIFT, + MT6359P_DA_VIO28_B_EN_ADDR, MT6359P_RG_VIO28_VOSEL_ADDR, + MT6359_RG_VIO28_VOSEL_MASK << MT6359_RG_VIO28_VOSEL_SHIFT, + 1920), + MT6359P_LDO1("ldo_vemc_1", VEMC, MT6359_REG_TYPE_VEMC, vemc_voltages_1, + MT6359P_RG_LDO_VEMC_EN_ADDR, MT6359P_RG_LDO_VEMC_EN_SHIFT, + MT6359P_DA_VEMC_B_EN_ADDR, + MT6359P_RG_LDO_VEMC_VOSEL_0_ADDR, + MT6359P_RG_LDO_VEMC_VOSEL_0_MASK << + MT6359P_RG_LDO_VEMC_VOSEL_0_SHIFT), + MT6359_LDO("ldo_vcn33_2_bt", VCN33_2_BT, vcn33_voltages, + MT6359P_RG_LDO_VCN33_2_EN_0_ADDR, + MT6359P_RG_LDO_VCN33_2_EN_0_SHIFT, + MT6359P_DA_VCN33_2_B_EN_ADDR, MT6359P_RG_VCN33_2_VOSEL_ADDR, + MT6359_RG_VCN33_2_VOSEL_MASK << + MT6359_RG_VCN33_2_VOSEL_SHIFT, 240), + MT6359_LDO("ldo_vcn33_2_wifi", VCN33_2_WIFI, vcn33_voltages, + MT6359P_RG_LDO_VCN33_2_EN_1_ADDR, + MT6359_RG_LDO_VCN33_2_EN_1_SHIFT, + MT6359P_DA_VCN33_2_B_EN_ADDR, MT6359P_RG_VCN33_2_VOSEL_ADDR, + MT6359_RG_VCN33_2_VOSEL_MASK << + MT6359_RG_VCN33_2_VOSEL_SHIFT, 240), + MT6359_LDO("ldo_va12", VA12, va12_voltages, + MT6359P_RG_LDO_VA12_EN_ADDR, MT6359P_RG_LDO_VA12_EN_SHIFT, + MT6359P_DA_VA12_B_EN_ADDR, MT6359P_RG_VA12_VOSEL_ADDR, + MT6359_RG_VA12_VOSEL_MASK << MT6359_RG_VA12_VOSEL_SHIFT, + 960), + MT6359_LDO("ldo_va09", VA09, va09_voltages, + MT6359P_RG_LDO_VA09_EN_ADDR, MT6359P_RG_LDO_VA09_EN_SHIFT, + MT6359P_DA_VA09_B_EN_ADDR, MT6359P_RG_VA09_VOSEL_ADDR, + MT6359_RG_VA09_VOSEL_MASK << MT6359_RG_VA09_VOSEL_SHIFT, + 960), + MT6359_LDO("ldo_vrf18", VRF18, vrf18_voltages, + MT6359P_RG_LDO_VRF18_EN_ADDR, MT6359P_RG_LDO_VRF18_EN_SHIFT, + MT6359P_DA_VRF18_B_EN_ADDR, MT6359P_RG_VRF18_VOSEL_ADDR, + MT6359_RG_VRF18_VOSEL_MASK << MT6359_RG_VRF18_VOSEL_SHIFT, + 240), + MT6359_LDO_LINEAR("ldo_vsram_md", VSRAM_MD, 500000, 1293750, 6250, + MT6359P_RG_LDO_VSRAM_MD_EN_ADDR, + MT6359P_DA_VSRAM_MD_B_EN_ADDR, + MT6359P_RG_LDO_VSRAM_MD_VOSEL_ADDR, + MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK << + MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT), + MT6359_LDO("ldo_vufs", VUFS, volt18_voltages, + MT6359P_RG_LDO_VUFS_EN_ADDR, MT6359P_RG_LDO_VUFS_EN_SHIFT, + MT6359P_DA_VUFS_B_EN_ADDR, MT6359P_RG_VUFS_VOSEL_ADDR, + MT6359_RG_VUFS_VOSEL_MASK << MT6359_RG_VUFS_VOSEL_SHIFT, + 1920), + MT6359_LDO("ldo_vm18", VM18, volt18_voltages, + MT6359P_RG_LDO_VM18_EN_ADDR, MT6359P_RG_LDO_VM18_EN_SHIFT, + MT6359P_DA_VM18_B_EN_ADDR, MT6359P_RG_VM18_VOSEL_ADDR, + MT6359_RG_VM18_VOSEL_MASK << MT6359_RG_VM18_VOSEL_SHIFT, + 1920), + MT6359_LDO("ldo_vbbck", VBBCK, vbbck_voltages, + MT6359P_RG_LDO_VBBCK_EN_ADDR, MT6359P_RG_LDO_VBBCK_EN_SHIFT, + MT6359P_DA_VBBCK_B_EN_ADDR, MT6359P_RG_VBBCK_VOSEL_ADDR, + MT6359P_RG_VBBCK_VOSEL_MASK << MT6359P_RG_VBBCK_VOSEL_SHIFT, + 480), + MT6359_LDO_LINEAR("ldo_vsram_proc1", VSRAM_PROC1, 500000, 1293750, 6250, + MT6359P_RG_LDO_VSRAM_PROC1_EN_ADDR, + MT6359P_DA_VSRAM_PROC1_B_EN_ADDR, + MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_ADDR, + MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK << + MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT), + MT6359_LDO("ldo_vsim2", VSIM2, vsim2_voltages, + MT6359P_RG_LDO_VSIM2_EN_ADDR, MT6359P_RG_LDO_VSIM2_EN_SHIFT, + MT6359P_DA_VSIM2_B_EN_ADDR, MT6359P_RG_VSIM2_VOSEL_ADDR, + MT6359_RG_VSIM2_VOSEL_MASK << MT6359_RG_VSIM2_VOSEL_SHIFT, + 480), + MT6359_LDO_LINEAR("ldo_vsram_others_sshub", VSRAM_OTHERS_SSHUB, + 500000, 1293750, 6250, + MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR, + MT6359P_DA_VSRAM_OTHERS_B_EN_ADDR, + MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR, + MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK << + MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT), +}; + +static int mt6359_regulator_probe(struct udevice *dev) +{ + struct mt6359_regulator_info *priv = dev_get_priv(dev); + int i, hw_ver; + + hw_ver = pmic_reg_read(dev->parent, MT6359P_HWCID); + if (hw_ver < MT6359P_CHIP_VER) { + dev_err(dev, "mt6359 is not supported. Only support mt6359p, hw_ver(%d)\n", + hw_ver); + return -EINVAL; + } + + for (i = 0; i < ARRAY_SIZE(mt6359p_regulators); i++) { + if (!strcmp(dev->name, mt6359p_regulators[i].desc.of_match)) { + *priv = mt6359p_regulators[i]; + return 0; + } + } + + return -ENOENT; +} + +static const struct dm_regulator_ops mt6359_regulator_ops = { + .get_value = mt6359_get_value, + .set_value = mt6359_set_value, + .get_enable = mt6359_get_enable, + .set_enable = mt6359_set_enable, +}; + +U_BOOT_DRIVER(mt6359_regulator) = { + .name = MT6359_REGULATOR_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &mt6359_regulator_ops, + .probe = mt6359_regulator_probe, + .priv_auto = sizeof(struct mt6359_regulator_info), +}; diff --git a/drivers/power/regulator/pwm_regulator.c b/drivers/power/regulator/pwm_regulator.c index ff738faadc5..adde5156c76 100644 --- a/drivers/power/regulator/pwm_regulator.c +++ b/drivers/power/regulator/pwm_regulator.c @@ -11,12 +11,9 @@ #include <errno.h> #include <log.h> #include <pwm.h> -#include <asm/global_data.h> #include <dm/device_compat.h> #include <power/regulator.h> -DECLARE_GLOBAL_DATA_PTR; - struct pwm_regulator_info { /* pwm id corresponding to the PWM driver */ int pwm_id; diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 94c52cf555b..1c7f75a9338 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -449,7 +449,7 @@ static int regulator_post_bind(struct udevice *dev) } if (!regulator_name_is_unique(dev, uc_pdata->name)) { - dev_err(dev, "'%s' has nonunique value: '%s\n", + dev_err(dev, "'%s' has nonunique value: '%s'\n", property, uc_pdata->name); return -EINVAL; } diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c index bb37b39fa0e..fc5d2a3e5e3 100644 --- a/drivers/pwm/pwm-imx.c +++ b/drivers/pwm/pwm-imx.c @@ -232,17 +232,19 @@ static int imx_pwm_of_to_plat(struct udevice *dev) priv->regs = dev_read_addr_ptr(dev); - ret = clk_get_by_name(dev, "per", &priv->per_clk); - if (ret) { - printf("Failed to get per_clk\n"); - return ret; - } - - ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk); - if (ret) { - printf("Failed to get ipg_clk\n"); - return ret; - } + if (CONFIG_IS_ENABLED(CLK)) { + ret = clk_get_by_name(dev, "per", &priv->per_clk); + if (ret) { + printf("Failed to get per_clk\n"); + return ret; + } + + ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk); + if (ret) { + printf("Failed to get ipg_clk\n"); + return ret; + } + } return 0; } @@ -252,17 +254,19 @@ static int imx_pwm_probe(struct udevice *dev) int ret; struct imx_pwm_priv *priv = dev_get_priv(dev); - ret = clk_enable(&priv->per_clk); - if (ret) { - printf("Failed to enable per_clk\n"); - return ret; - } - - ret = clk_enable(&priv->ipg_clk); - if (ret) { - printf("Failed to enable ipg_clk\n"); - return ret; - } + if (CONFIG_IS_ENABLED(CLK)) { + ret = clk_enable(&priv->per_clk); + if (ret) { + printf("Failed to enable per_clk\n"); + return ret; + } + + ret = clk_enable(&priv->ipg_clk); + if (ret) { + printf("Failed to enable ipg_clk\n"); + return ret; + } + } return 0; } diff --git a/drivers/pwm/pwm-sifive.c b/drivers/pwm/pwm-sifive.c index e9777c71f5e..dea7bc57495 100644 --- a/drivers/pwm/pwm-sifive.c +++ b/drivers/pwm/pwm-sifive.c @@ -17,7 +17,6 @@ #include <dm.h> #include <pwm.h> #include <regmap.h> -#include <asm/global_data.h> #include <linux/io.h> #include <linux/log2.h> #include <linux/bitfield.h> @@ -40,8 +39,6 @@ #define PWM_SIFIVE_CHANNEL_ENABLE_VAL 0 #define PWM_SIFIVE_CHANNEL_DISABLE_VAL 0xffff -DECLARE_GLOBAL_DATA_PTR; - struct pwm_sifive_regs { unsigned long cfg; unsigned long cnt; diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c index 0a64eb01dc2..b51dee31a98 100644 --- a/drivers/pwm/rk_pwm.c +++ b/drivers/pwm/rk_pwm.c @@ -11,14 +11,11 @@ #include <pwm.h> #include <regmap.h> #include <syscon.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/arch-rockchip/pwm.h> #include <linux/bitops.h> #include <power/regulator.h> -DECLARE_GLOBAL_DATA_PTR; - struct rockchip_pwm_data { struct rockchip_pwm_regs regs; unsigned int prescaler; diff --git a/drivers/pwm/sunxi_pwm.c b/drivers/pwm/sunxi_pwm.c index 2140a05b679..1dd2428da77 100644 --- a/drivers/pwm/sunxi_pwm.c +++ b/drivers/pwm/sunxi_pwm.c @@ -9,13 +9,10 @@ #include <pwm.h> #include <regmap.h> #include <syscon.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/arch/pwm.h> #include <power/regulator.h> -DECLARE_GLOBAL_DATA_PTR; - #define OSC_24MHZ 24000000 struct sunxi_pwm_priv { diff --git a/drivers/pwm/tegra_pwm.c b/drivers/pwm/tegra_pwm.c index e3f1417f2ad..3d8f9daa2b0 100644 --- a/drivers/pwm/tegra_pwm.c +++ b/drivers/pwm/tegra_pwm.c @@ -4,38 +4,94 @@ */ #include <dm.h> +#include <clk.h> +#include <div64.h> #include <log.h> #include <pwm.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/pwm.h> +#include <linux/time.h> + +#define PWM_PDIV_WIDTH 8 +#define PWM_PDIV_MAX BIT(PWM_PDIV_WIDTH) +#define PWM_FDIV_WIDTH 13 struct tegra_pwm_priv { struct pwm_ctlr *regs; + u64 clk_rate; + u32 min_period_ns; + u8 polarity; }; +static int tegra_pwm_set_invert(struct udevice *dev, uint channel, bool polarity) +{ + struct tegra_pwm_priv *priv = dev_get_priv(dev); + + if (channel >= 4) + return -EINVAL; + + clrsetbits_8(&priv->polarity, BIT(channel), (polarity << channel)); + + return 0; +} + static int tegra_pwm_set_config(struct udevice *dev, uint channel, uint period_ns, uint duty_ns) { struct tegra_pwm_priv *priv = dev_get_priv(dev); struct pwm_ctlr *regs = priv->regs; - const u32 pwm_max_freq = dev_get_driver_data(dev); - uint pulse_width; + u64 pulse_width; u32 reg; + s64 rate; if (channel >= 4) return -EINVAL; debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel); - clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_PERIPH, pwm_max_freq); + if (period_ns < priv->min_period_ns) { + debug("%s: Channel %u period too low, period_ns %u minimum %u\n", + __func__, channel, period_ns, priv->min_period_ns); + return -EINVAL; + } + + /* + * Convert from duty_ns / period_ns to a fixed number of duty ticks + * per (1 << PWM_PDIV_WIDTH) cycles and make sure to round to the + * nearest integer during division. + */ + pulse_width = duty_ns * PWM_PDIV_MAX; + pulse_width = DIV_ROUND_CLOSEST_ULL(pulse_width, period_ns); + + if (priv->polarity & BIT(channel)) + pulse_width = PWM_PDIV_MAX - pulse_width; + + if (pulse_width > PWM_PDIV_MAX) { + debug("%s: Channel %u pulse_width too high %llu\n", + __func__, channel, pulse_width); + return -EINVAL; + } + + /* + * Since the actual PWM divider is the register's frequency divider + * field plus 1, we need to decrement to get the correct value to + * write to the register. + */ + rate = (priv->clk_rate * period_ns) / ((u64)NSEC_PER_SEC << PWM_PDIV_WIDTH) - 1; + if (rate < 0) { + debug("%s: Channel %u rate is not positive\n", __func__, channel); + return -EINVAL; + } - pulse_width = duty_ns * 255 / period_ns; + if (rate >> PWM_FDIV_WIDTH) { + debug("%s: Channel %u rate too high %llu\n", __func__, channel, rate); + return -EINVAL; + } reg = pulse_width << PWM_WIDTH_SHIFT; - reg |= 1 << PWM_DIVIDER_SHIFT; + reg |= rate << PWM_DIVIDER_SHIFT; reg |= PWM_ENABLE_MASK; writel(reg, ®s[channel].control); - debug("%s: pulse_width=%u\n", __func__, pulse_width); return 0; } @@ -63,9 +119,32 @@ static int tegra_pwm_of_to_plat(struct udevice *dev) return 0; } +static int tegra_pwm_probe(struct udevice *dev) +{ + struct tegra_pwm_priv *priv = dev_get_priv(dev); + const u32 pwm_max_freq = dev_get_driver_data(dev); + struct clk *clk; + + clk = devm_clk_get(dev, NULL); + if (IS_ERR(clk)) { + debug("%s: Could not get PWM clock: %ld\n", __func__, PTR_ERR(clk)); + return PTR_ERR(clk); + } + + priv->clk_rate = clock_start_periph_pll(clk->id, CLOCK_ID_PERIPH, + pwm_max_freq); + priv->min_period_ns = (NSEC_PER_SEC / (pwm_max_freq >> PWM_PDIV_WIDTH)) + 1; + + debug("%s: clk_rate = %llu min_period_ns = %u\n", __func__, + priv->clk_rate, priv->min_period_ns); + + return 0; +} + static const struct pwm_ops tegra_pwm_ops = { .set_config = tegra_pwm_set_config, .set_enable = tegra_pwm_set_enable, + .set_invert = tegra_pwm_set_invert, }; static const struct udevice_id tegra_pwm_ids[] = { @@ -80,5 +159,6 @@ U_BOOT_DRIVER(tegra_pwm) = { .of_match = tegra_pwm_ids, .ops = &tegra_pwm_ops, .of_to_plat = tegra_pwm_of_to_plat, + .probe = tegra_pwm_probe, .priv_auto = sizeof(struct tegra_pwm_priv), }; diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile index fd94aad0cd4..27921ae4921 100644 --- a/drivers/ram/rockchip/Makefile +++ b/drivers/ram/rockchip/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o sdram_pctl_px30.o sdram_phy_px30.o obj-$(CONFIG_ROCKCHIP_RK3399) += sdram_rk3399.o +obj-$(CONFIG_ROCKCHIP_RK3506) += sdram_rk3506.o obj-$(CONFIG_ROCKCHIP_RK3528) += sdram_rk3528.o obj-$(CONFIG_ROCKCHIP_RK3568) += sdram_rk3568.o obj-$(CONFIG_ROCKCHIP_RK3576) += sdram_rk3576.o diff --git a/drivers/ram/rockchip/sdram_rk3506.c b/drivers/ram/rockchip/sdram_rk3506.c new file mode 100644 index 00000000000..a8396ea8888 --- /dev/null +++ b/drivers/ram/rockchip/sdram_rk3506.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright Contributors to the U-Boot project. + +#include <dm.h> +#include <ram.h> +#include <asm/arch-rockchip/sdram.h> + +#define PMUGRF_BASE 0xff910000 +#define OS_REG2_REG 0x208 + +static int rk3506_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + info->base = CFG_SYS_SDRAM_BASE; + info->size = rockchip_sdram_size(PMUGRF_BASE + OS_REG2_REG); + + return 0; +} + +static struct ram_ops rk3506_dmc_ops = { + .get_info = rk3506_dmc_get_info, +}; + +static const struct udevice_id rk3506_dmc_ids[] = { + { .compatible = "rockchip,rk3506-dmc" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3506_dmc) = { + .name = "rockchip_rk3506_dmc", + .id = UCLASS_RAM, + .of_match = rk3506_dmc_ids, + .ops = &rk3506_dmc_ops, +}; diff --git a/drivers/ram/stm32mp1/stm32mp1_tests.c b/drivers/ram/stm32mp1/stm32mp1_tests.c index 6108faa7073..3b41d6045ad 100644 --- a/drivers/ram/stm32mp1/stm32mp1_tests.c +++ b/drivers/ram/stm32mp1/stm32mp1_tests.c @@ -10,7 +10,6 @@ #include <log.h> #include <rand.h> #include <watchdog.h> -#include <asm/global_data.h> #include <asm/io.h> #include <linux/log2.h> #include "stm32mp1_tests.h" @@ -19,8 +18,6 @@ #define PATTERN_DEFAULT "-" -DECLARE_GLOBAL_DATA_PTR; - static int get_bufsize(char *string, int argc, char *argv[], int arg_nb, size_t *bufsize, size_t default_size, size_t min_size) { diff --git a/drivers/reboot-mode/reboot-mode-gpio.c b/drivers/reboot-mode/reboot-mode-gpio.c index 22ee40c3433..8d3e53d50ee 100644 --- a/drivers/reboot-mode/reboot-mode-gpio.c +++ b/drivers/reboot-mode/reboot-mode-gpio.c @@ -10,8 +10,6 @@ #include <reboot-mode/reboot-mode-gpio.h> #include <reboot-mode/reboot-mode.h> -DECLARE_GLOBAL_DATA_PTR; - static int reboot_mode_get(struct udevice *dev, u32 *buf) { int ret; diff --git a/drivers/reboot-mode/reboot-mode-rtc.c b/drivers/reboot-mode/reboot-mode-rtc.c index 4f4ad63febc..adca584d622 100644 --- a/drivers/reboot-mode/reboot-mode-rtc.c +++ b/drivers/reboot-mode/reboot-mode-rtc.c @@ -9,8 +9,6 @@ #include <reboot-mode/reboot-mode.h> #include <rtc.h> -DECLARE_GLOBAL_DATA_PTR; - static int reboot_mode_get(struct udevice *dev, u32 *buf) { if (!buf) diff --git a/drivers/remoteproc/rproc-uclass.c b/drivers/remoteproc/rproc-uclass.c index 2dbd3a21cea..47cb64fec77 100644 --- a/drivers/remoteproc/rproc-uclass.c +++ b/drivers/remoteproc/rproc-uclass.c @@ -22,8 +22,6 @@ #include <linux/compat.h> #include <linux/printk.h> -DECLARE_GLOBAL_DATA_PTR; - struct resource_table { u32 ver; u32 num; diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 2fd91d6299c..66911199c8b 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -208,7 +208,7 @@ config RESET_RASPBERRYPI config RESET_SCMI bool "Enable SCMI reset domain driver" - select SCMI_FIRMWARE + depends on SCMI_FIRMWARE help Enable this option if you want to support reset controller devices exposed by a SCMI agent based on SCMI reset domain diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index ee5b009d134..088545c6473 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o -obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3528.o rst-rk3576.o rst-rk3588.o +obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3506.o rst-rk3528.o rst-rk3576.o rst-rk3588.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index e57729f0ef9..36a205f9fca 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -115,7 +115,7 @@ static int socfpga_reset_remove(struct udevice *dev) if (socfpga_reset_keep_enabled()) { puts("Deasserting all peripheral resets\n"); writel(0, data->modrst_base + 4); - if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_ARRIA10)) + if (IS_ENABLED(CONFIG_ARCH_SOCFPGA_ARRIA10)) writel(0, data->modrst_base + 8); } diff --git a/drivers/reset/rst-rk3506.c b/drivers/reset/rst-rk3506.c new file mode 100644 index 00000000000..9c384db0589 --- /dev/null +++ b/drivers/reset/rst-rk3506.c @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * Author: Finley Xiao <[email protected]> + */ + +#include <dm.h> +#include <asm/arch-rockchip/clock.h> +#include <dt-bindings/reset/rockchip,rk3506-cru.h> + +/* 0xFF9A0000 + 0x0A00 */ +#define RK3506_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit) + +/* mapping table for reset ID to register offset */ +static const int rk3506_register_offset[] = { + /* CRU-->SOFTRST_CON00 */ + RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET0_AC, 0, 0), + RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET1_AC, 0, 1), + RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET2_AC, 0, 2), + RK3506_CRU_RESET_OFFSET(SRST_NCORESET0_AC, 0, 4), + RK3506_CRU_RESET_OFFSET(SRST_NCORESET1_AC, 0, 5), + RK3506_CRU_RESET_OFFSET(SRST_NCORESET2_AC, 0, 6), + RK3506_CRU_RESET_OFFSET(SRST_NL2RESET_AC, 0, 8), + RK3506_CRU_RESET_OFFSET(SRST_A_CORE_BIU_AC, 0, 9), + RK3506_CRU_RESET_OFFSET(SRST_H_M0_AC, 0, 10), + + /* CRU-->SOFTRST_CON02 */ + RK3506_CRU_RESET_OFFSET(SRST_NDBGRESET, 2, 10), + RK3506_CRU_RESET_OFFSET(SRST_P_CORE_BIU, 2, 14), + RK3506_CRU_RESET_OFFSET(SRST_PMU, 2, 15), + + /* CRU-->SOFTRST_CON03 */ + RK3506_CRU_RESET_OFFSET(SRST_P_DBG, 3, 1), + RK3506_CRU_RESET_OFFSET(SRST_POT_DBG, 3, 2), + RK3506_CRU_RESET_OFFSET(SRST_P_CORE_GRF, 3, 4), + RK3506_CRU_RESET_OFFSET(SRST_CORE_EMA_DETECT, 3, 6), + RK3506_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 3, 7), + RK3506_CRU_RESET_OFFSET(SRST_P_GPIO1, 3, 8), + RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO1, 3, 9), + + /* CRU-->SOFTRST_CON04 */ + RK3506_CRU_RESET_OFFSET(SRST_A_CORE_PERI_BIU, 4, 3), + RK3506_CRU_RESET_OFFSET(SRST_A_DSMC, 4, 5), + RK3506_CRU_RESET_OFFSET(SRST_P_DSMC, 4, 6), + RK3506_CRU_RESET_OFFSET(SRST_FLEXBUS, 4, 7), + RK3506_CRU_RESET_OFFSET(SRST_A_FLEXBUS, 4, 9), + RK3506_CRU_RESET_OFFSET(SRST_H_FLEXBUS, 4, 10), + RK3506_CRU_RESET_OFFSET(SRST_A_DSMC_SLV, 4, 11), + RK3506_CRU_RESET_OFFSET(SRST_H_DSMC_SLV, 4, 12), + RK3506_CRU_RESET_OFFSET(SRST_DSMC_SLV, 4, 13), + + /* CRU-->SOFTRST_CON05 */ + RK3506_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 5, 3), + RK3506_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 5, 4), + RK3506_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 5, 5), + RK3506_CRU_RESET_OFFSET(SRST_A_SYSRAM, 5, 6), + RK3506_CRU_RESET_OFFSET(SRST_H_SYSRAM, 5, 7), + RK3506_CRU_RESET_OFFSET(SRST_A_DMAC0, 5, 8), + RK3506_CRU_RESET_OFFSET(SRST_A_DMAC1, 5, 9), + RK3506_CRU_RESET_OFFSET(SRST_H_M0, 5, 10), + RK3506_CRU_RESET_OFFSET(SRST_M0_JTAG, 5, 11), + RK3506_CRU_RESET_OFFSET(SRST_H_CRYPTO, 5, 15), + + /* CRU-->SOFTRST_CON06 */ + RK3506_CRU_RESET_OFFSET(SRST_H_RNG, 6, 0), + RK3506_CRU_RESET_OFFSET(SRST_P_BUS_GRF, 6, 1), + RK3506_CRU_RESET_OFFSET(SRST_P_TIMER0, 6, 2), + RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH0, 6, 3), + RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH1, 6, 4), + RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH2, 6, 5), + RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH3, 6, 6), + RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH4, 6, 7), + RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH5, 6, 8), + RK3506_CRU_RESET_OFFSET(SRST_P_WDT0, 6, 9), + RK3506_CRU_RESET_OFFSET(SRST_T_WDT0, 6, 10), + RK3506_CRU_RESET_OFFSET(SRST_P_WDT1, 6, 11), + RK3506_CRU_RESET_OFFSET(SRST_T_WDT1, 6, 12), + RK3506_CRU_RESET_OFFSET(SRST_P_MAILBOX, 6, 13), + RK3506_CRU_RESET_OFFSET(SRST_P_INTMUX, 6, 14), + RK3506_CRU_RESET_OFFSET(SRST_P_SPINLOCK, 6, 15), + + /* CRU-->SOFTRST_CON07 */ + RK3506_CRU_RESET_OFFSET(SRST_P_DDRC, 7, 0), + RK3506_CRU_RESET_OFFSET(SRST_H_DDRPHY, 7, 1), + RK3506_CRU_RESET_OFFSET(SRST_P_DDRMON, 7, 2), + RK3506_CRU_RESET_OFFSET(SRST_DDRMON_OSC, 7, 3), + RK3506_CRU_RESET_OFFSET(SRST_P_DDR_LPC, 7, 4), + RK3506_CRU_RESET_OFFSET(SRST_H_USBOTG0, 7, 5), + RK3506_CRU_RESET_OFFSET(SRST_USBOTG0_ADP, 7, 7), + RK3506_CRU_RESET_OFFSET(SRST_H_USBOTG1, 7, 8), + RK3506_CRU_RESET_OFFSET(SRST_USBOTG1_ADP, 7, 10), + RK3506_CRU_RESET_OFFSET(SRST_P_USBPHY, 7, 11), + RK3506_CRU_RESET_OFFSET(SRST_USBPHY_POR, 7, 12), + RK3506_CRU_RESET_OFFSET(SRST_USBPHY_OTG0, 7, 13), + RK3506_CRU_RESET_OFFSET(SRST_USBPHY_OTG1, 7, 14), + + /* CRU-->SOFTRST_CON08 */ + RK3506_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 8, 0), + RK3506_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 8, 1), + + /* CRU-->SOFTRST_CON09 */ + RK3506_CRU_RESET_OFFSET(SRST_USBOTG0_UTMI, 9, 0), + RK3506_CRU_RESET_OFFSET(SRST_USBOTG1_UTMI, 9, 1), + + /* CRU-->SOFTRST_CON10 */ + RK3506_CRU_RESET_OFFSET(SRST_A_DDRC_0, 10, 0), + RK3506_CRU_RESET_OFFSET(SRST_A_DDRC_1, 10, 1), + RK3506_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 10, 2), + RK3506_CRU_RESET_OFFSET(SRST_DDRC, 10, 3), + RK3506_CRU_RESET_OFFSET(SRST_DDRMON, 10, 4), + + /* CRU-->SOFTRST_CON11 */ + RK3506_CRU_RESET_OFFSET(SRST_H_LSPERI_BIU, 11, 2), + RK3506_CRU_RESET_OFFSET(SRST_P_UART0, 11, 4), + RK3506_CRU_RESET_OFFSET(SRST_P_UART1, 11, 5), + RK3506_CRU_RESET_OFFSET(SRST_P_UART2, 11, 6), + RK3506_CRU_RESET_OFFSET(SRST_P_UART3, 11, 7), + RK3506_CRU_RESET_OFFSET(SRST_P_UART4, 11, 8), + RK3506_CRU_RESET_OFFSET(SRST_UART0, 11, 9), + RK3506_CRU_RESET_OFFSET(SRST_UART1, 11, 10), + RK3506_CRU_RESET_OFFSET(SRST_UART2, 11, 11), + RK3506_CRU_RESET_OFFSET(SRST_UART3, 11, 12), + RK3506_CRU_RESET_OFFSET(SRST_UART4, 11, 13), + RK3506_CRU_RESET_OFFSET(SRST_P_I2C0, 11, 14), + RK3506_CRU_RESET_OFFSET(SRST_I2C0, 11, 15), + + /* CRU-->SOFTRST_CON12 */ + RK3506_CRU_RESET_OFFSET(SRST_P_I2C1, 12, 0), + RK3506_CRU_RESET_OFFSET(SRST_I2C1, 12, 1), + RK3506_CRU_RESET_OFFSET(SRST_P_I2C2, 12, 2), + RK3506_CRU_RESET_OFFSET(SRST_I2C2, 12, 3), + RK3506_CRU_RESET_OFFSET(SRST_P_PWM1, 12, 4), + RK3506_CRU_RESET_OFFSET(SRST_PWM1, 12, 5), + RK3506_CRU_RESET_OFFSET(SRST_P_SPI0, 12, 10), + RK3506_CRU_RESET_OFFSET(SRST_SPI0, 12, 11), + RK3506_CRU_RESET_OFFSET(SRST_P_SPI1, 12, 12), + RK3506_CRU_RESET_OFFSET(SRST_SPI1, 12, 13), + RK3506_CRU_RESET_OFFSET(SRST_P_GPIO2, 12, 14), + RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO2, 12, 15), + + /* CRU-->SOFTRST_CON13 */ + RK3506_CRU_RESET_OFFSET(SRST_P_GPIO3, 13, 0), + RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO3, 13, 1), + RK3506_CRU_RESET_OFFSET(SRST_P_GPIO4, 13, 2), + RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO4, 13, 3), + RK3506_CRU_RESET_OFFSET(SRST_H_CAN0, 13, 4), + RK3506_CRU_RESET_OFFSET(SRST_CAN0, 13, 5), + RK3506_CRU_RESET_OFFSET(SRST_H_CAN1, 13, 6), + RK3506_CRU_RESET_OFFSET(SRST_CAN1, 13, 7), + RK3506_CRU_RESET_OFFSET(SRST_H_PDM, 13, 8), + RK3506_CRU_RESET_OFFSET(SRST_M_PDM, 13, 9), + RK3506_CRU_RESET_OFFSET(SRST_PDM, 13, 10), + RK3506_CRU_RESET_OFFSET(SRST_SPDIFTX, 13, 11), + RK3506_CRU_RESET_OFFSET(SRST_H_SPDIFTX, 13, 12), + RK3506_CRU_RESET_OFFSET(SRST_H_SPDIFRX, 13, 13), + RK3506_CRU_RESET_OFFSET(SRST_SPDIFRX, 13, 14), + RK3506_CRU_RESET_OFFSET(SRST_M_SAI0, 13, 15), + + /* CRU-->SOFTRST_CON14 */ + RK3506_CRU_RESET_OFFSET(SRST_H_SAI0, 14, 0), + RK3506_CRU_RESET_OFFSET(SRST_M_SAI1, 14, 2), + RK3506_CRU_RESET_OFFSET(SRST_H_SAI1, 14, 3), + RK3506_CRU_RESET_OFFSET(SRST_H_ASRC0, 14, 5), + RK3506_CRU_RESET_OFFSET(SRST_ASRC0, 14, 6), + RK3506_CRU_RESET_OFFSET(SRST_H_ASRC1, 14, 7), + RK3506_CRU_RESET_OFFSET(SRST_ASRC1, 14, 8), + + /* CRU-->SOFTRST_CON17 */ + RK3506_CRU_RESET_OFFSET(SRST_H_HSPERI_BIU, 17, 4), + RK3506_CRU_RESET_OFFSET(SRST_H_SDMMC, 17, 7), + RK3506_CRU_RESET_OFFSET(SRST_H_FSPI, 17, 8), + RK3506_CRU_RESET_OFFSET(SRST_S_FSPI, 17, 9), + RK3506_CRU_RESET_OFFSET(SRST_P_SPI2, 17, 10), + RK3506_CRU_RESET_OFFSET(SRST_A_MAC0, 17, 11), + RK3506_CRU_RESET_OFFSET(SRST_A_MAC1, 17, 12), + + /* CRU-->SOFTRST_CON18 */ + RK3506_CRU_RESET_OFFSET(SRST_M_SAI2, 18, 2), + RK3506_CRU_RESET_OFFSET(SRST_H_SAI2, 18, 3), + RK3506_CRU_RESET_OFFSET(SRST_H_SAI3, 18, 6), + RK3506_CRU_RESET_OFFSET(SRST_M_SAI3, 18, 7), + RK3506_CRU_RESET_OFFSET(SRST_H_SAI4, 18, 10), + RK3506_CRU_RESET_OFFSET(SRST_M_SAI4, 18, 11), + RK3506_CRU_RESET_OFFSET(SRST_H_DSM, 18, 12), + RK3506_CRU_RESET_OFFSET(SRST_M_DSM, 18, 13), + RK3506_CRU_RESET_OFFSET(SRST_P_AUDIO_ADC, 18, 14), + RK3506_CRU_RESET_OFFSET(SRST_M_AUDIO_ADC, 18, 15), + + /* CRU-->SOFTRST_CON19 */ + RK3506_CRU_RESET_OFFSET(SRST_P_SARADC, 19, 0), + RK3506_CRU_RESET_OFFSET(SRST_SARADC, 19, 1), + RK3506_CRU_RESET_OFFSET(SRST_SARADC_PHY, 19, 2), + RK3506_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 19, 3), + RK3506_CRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 19, 4), + RK3506_CRU_RESET_OFFSET(SRST_USER_OTPC_NS, 19, 5), + RK3506_CRU_RESET_OFFSET(SRST_P_UART5, 19, 6), + RK3506_CRU_RESET_OFFSET(SRST_UART5, 19, 7), + RK3506_CRU_RESET_OFFSET(SRST_P_GPIO234_IOC, 19, 8), + + /* CRU-->SOFTRST_CON21 */ + RK3506_CRU_RESET_OFFSET(SRST_A_VIO_BIU, 21, 3), + RK3506_CRU_RESET_OFFSET(SRST_H_VIO_BIU, 21, 4), + RK3506_CRU_RESET_OFFSET(SRST_H_RGA, 21, 6), + RK3506_CRU_RESET_OFFSET(SRST_A_RGA, 21, 7), + RK3506_CRU_RESET_OFFSET(SRST_CORE_RGA, 21, 8), + RK3506_CRU_RESET_OFFSET(SRST_A_VOP, 21, 9), + RK3506_CRU_RESET_OFFSET(SRST_H_VOP, 21, 10), + RK3506_CRU_RESET_OFFSET(SRST_VOP, 21, 11), + RK3506_CRU_RESET_OFFSET(SRST_P_DPHY, 21, 12), + RK3506_CRU_RESET_OFFSET(SRST_P_DSI_HOST, 21, 13), + RK3506_CRU_RESET_OFFSET(SRST_P_TSADC, 21, 14), + RK3506_CRU_RESET_OFFSET(SRST_TSADC, 21, 15), + + /* CRU-->SOFTRST_CON22 */ + RK3506_CRU_RESET_OFFSET(SRST_P_GPIO1_IOC, 22, 1), +}; + +int rk3506_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number) +{ + return rockchip_reset_bind_lut(pdev, rk3506_register_offset, + reg_offset, reg_number); +} diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index ef1663f3450..65d9bf533cb 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -73,6 +73,7 @@ config RTC_DS1307 config RTC_DS1337 bool "Enable DS1337 driver" + depends on DM_RTC help Support for Dallas Semiconductor (now Maxim) DS1337/8/9 compatible Real Time Clock devices. @@ -81,15 +82,9 @@ config RTC_DS1337_NOOSC bool "Enable support for no oscillator output in DS1337 driver" depends on RTC_DS1337 -config RTC_DS1338 - bool "Enable DS1338 driver" - help - Support for Dallas Semiconductor (now Maxim) DS1338 and compatible - Real Time Clock devices. - config RTC_DS1374 bool "Enable DS1374 driver" - depends on !DM_RTC + depends on !DM_RTC && !DM_I2C help Support for Dallas Semiconductor (now Maxim) DS1374 and compatible Real Time Clock devices. @@ -171,12 +166,14 @@ config RTC_PCF85063 config RTC_PCF8563 bool "Philips PCF8563" + depends on DM_RTC help If you say yes here you get support for the Philips PCF8563 RTC and compatible chips. config RTC_PT7C4338 bool "Enable Pericom Technology PT7C4338 RTC driver" + depends on DM_RTC config RTC_RV3028 bool "Enable RV3028 driver" @@ -240,13 +237,14 @@ config RTC_MV config RTC_S35392A bool "Enable S35392A driver" + depends on DM_RTC select BITREVERSE help Enable s35392a driver which provides rtc get and set function. config RTC_MC13XXX bool "Enable MC13XXX RTC driver" - depends on !DM_RTC + depends on !DM_RTC && POWER_LEGACY config RTC_MC146818 bool "Enable MC146818 driver" @@ -258,6 +256,7 @@ config RTC_MC146818 config MCFRTC bool "Use common CF RTC driver" + depends on DM_RTC depends on M68K config SYS_MCFRTC_BASE @@ -267,9 +266,11 @@ config SYS_MCFRTC_BASE config RTC_MXS bool "Enable i.MXS RTC driver" depends on ARCH_MX23 || ARCH_MX28 + depends on !DM_RTC config RTC_M41T62 bool "Enable M41T62 driver" + depends on DM_RTC help Enable driver for ST's M41T62 compatible RTC devices (like RV-4162). It is a serial (I2C) real-time clock (RTC) with alarm. @@ -310,6 +311,7 @@ config RTC_ABX80X config RTC_DAVINCI bool "Enable TI OMAP RTC driver" depends on ARCH_DAVINCI || ARCH_OMAP2PLUS + depends on DM_RTC help Say "yes" here to support the on chip real time clock present on TI OMAP1, AM33xx, DA8xx/OMAP-L13x, AM43xx and DRA7xx. diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 9df373d5148..782f5a3bc3d 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -9,7 +9,6 @@ obj-$(CONFIG_$(PHASE_)DM_RTC) += rtc-uclass.o obj-$(CONFIG_RTC_ARMADA38X) += armada38x.o obj-$(CONFIG_RTC_DAVINCI) += davinci.o obj-$(CONFIG_RTC_DS1307) += ds1307.o -obj-$(CONFIG_RTC_DS1338) += ds1307.o obj-$(CONFIG_RTC_DS1337) += ds1337.o obj-$(CONFIG_RTC_DS1374) += ds1374.o obj-$(CONFIG_RTC_DS1672) += ds1672.o diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c index 77544298d8a..e9db6220c55 100644 --- a/drivers/rtc/ds1337.c +++ b/drivers/rtc/ds1337.c @@ -21,7 +21,6 @@ /* * RTC register addresses */ -#if defined CONFIG_RTC_DS1337 #define RTC_SEC_REG_ADDR 0x0 #define RTC_MIN_REG_ADDR 0x1 #define RTC_HR_REG_ADDR 0x2 @@ -32,18 +31,6 @@ #define RTC_CTL_REG_ADDR 0x0e #define RTC_STAT_REG_ADDR 0x0f #define RTC_TC_REG_ADDR 0x10 -#elif defined CONFIG_RTC_DS1388 -#define RTC_SEC_REG_ADDR 0x1 -#define RTC_MIN_REG_ADDR 0x2 -#define RTC_HR_REG_ADDR 0x3 -#define RTC_DAY_REG_ADDR 0x4 -#define RTC_DATE_REG_ADDR 0x5 -#define RTC_MON_REG_ADDR 0x6 -#define RTC_YR_REG_ADDR 0x7 -#define RTC_CTL_REG_ADDR 0x0c -#define RTC_STAT_REG_ADDR 0x0b -#define RTC_TC_REG_ADDR 0x0a -#endif /* * RTC control register bits @@ -62,132 +49,6 @@ #define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */ #define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */ -#if !CONFIG_IS_ENABLED(DM_RTC) -static uchar rtc_read (uchar reg); -static void rtc_write (uchar reg, uchar val); - -/* - * Get the current time from the RTC - */ -int rtc_get (struct rtc_time *tmp) -{ - int rel = 0; - uchar sec, min, hour, mday, wday, mon_cent, year, control, status; - - control = rtc_read (RTC_CTL_REG_ADDR); - status = rtc_read (RTC_STAT_REG_ADDR); - sec = rtc_read (RTC_SEC_REG_ADDR); - min = rtc_read (RTC_MIN_REG_ADDR); - hour = rtc_read (RTC_HR_REG_ADDR); - wday = rtc_read (RTC_DAY_REG_ADDR); - mday = rtc_read (RTC_DATE_REG_ADDR); - mon_cent = rtc_read (RTC_MON_REG_ADDR); - year = rtc_read (RTC_YR_REG_ADDR); - - /* No century bit, assume year 2000 */ -#ifdef CONFIG_RTC_DS1388 - mon_cent |= 0x80; -#endif - - debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " - "hr: %02x min: %02x sec: %02x control: %02x status: %02x\n", - year, mon_cent, mday, wday, hour, min, sec, control, status); - - if (status & RTC_STAT_BIT_OSF) { - printf ("### Warning: RTC oscillator has stopped\n"); - /* clear the OSF flag */ - rtc_write (RTC_STAT_REG_ADDR, - rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF); - rel = -1; - } - - tmp->tm_sec = bcd2bin (sec & 0x7F); - tmp->tm_min = bcd2bin (min & 0x7F); - tmp->tm_hour = bcd2bin (hour & 0x3F); - tmp->tm_mday = bcd2bin (mday & 0x3F); - tmp->tm_mon = bcd2bin (mon_cent & 0x1F); - tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900); - tmp->tm_wday = bcd2bin ((wday - 1) & 0x07); - tmp->tm_yday = 0; - tmp->tm_isdst= 0; - - debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - return rel; -} - -/* - * Set the RTC - */ -int rtc_set (struct rtc_time *tmp) -{ - uchar century; - - debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100)); - - century = (tmp->tm_year >= 2000) ? 0x80 : 0; - rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century); - - rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1)); - rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday)); - rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour)); - rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min)); - rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec)); - - return 0; -} - -/* - * Reset the RTC. We also enable the oscillator output on the - * SQW/INTB* pin and program it for 32,768 Hz output. Note that - * according to the datasheet, turning on the square wave output - * increases the current drain on the backup battery from about - * 600 nA to 2uA. Define CONFIG_RTC_DS1337_NOOSC if you wish to turn - * off the OSC output. - */ - -#ifdef CONFIG_RTC_DS1337_NOOSC - #define RTC_DS1337_RESET_VAL \ - (RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) -#else - #define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) -#endif -void rtc_reset (void) -{ -#ifdef CONFIG_RTC_DS1337 - rtc_write (RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL); -#elif defined CONFIG_RTC_DS1388 - rtc_write(RTC_CTL_REG_ADDR, 0x0); /* hw default */ -#endif -#ifdef CONFIG_RTC_DS1339_TCR_VAL - rtc_write (RTC_TC_REG_ADDR, CONFIG_RTC_DS1339_TCR_VAL); -#endif -#ifdef CONFIG_RTC_DS1388_TCR_VAL - rtc_write(RTC_TC_REG_ADDR, CONFIG_RTC_DS1388_TCR_VAL); -#endif -} - -/* - * Helper functions - */ - -static -uchar rtc_read (uchar reg) -{ - return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg)); -} - -static void rtc_write (uchar reg, uchar val) -{ - i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); -} -#else static uchar rtc_read(struct udevice *dev, uchar reg) { return dm_i2c_reg_read(dev, reg); @@ -213,11 +74,6 @@ static int ds1337_rtc_get(struct udevice *dev, struct rtc_time *tmp) mon_cent = rtc_read(dev, RTC_MON_REG_ADDR); year = rtc_read(dev, RTC_YR_REG_ADDR); - /* No century bit, assume year 2000 */ -#ifdef CONFIG_RTC_DS1388 - mon_cent |= 0x80; -#endif - debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x\n", year, mon_cent, mday, wday); debug("hr: %02x min: %02x sec: %02x control: %02x status: %02x\n", @@ -278,17 +134,8 @@ static int ds1337_rtc_set(struct udevice *dev, const struct rtc_time *tmp) #endif static int ds1337_rtc_reset(struct udevice *dev) { -#ifdef CONFIG_RTC_DS1337 rtc_write(dev, RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL); -#elif defined CONFIG_RTC_DS1388 - rtc_write(dev, RTC_CTL_REG_ADDR, 0x0); /* hw default */ -#endif -#ifdef CONFIG_RTC_DS1339_TCR_VAL - rtc_write(dev, RTC_TC_REG_ADDR, CONFIG_RTC_DS1339_TCR_VAL); -#endif -#ifdef CONFIG_RTC_DS1388_TCR_VAL - rtc_write(dev, RTC_TC_REG_ADDR, CONFIG_RTC_DS1388_TCR_VAL); -#endif + return 0; } @@ -311,4 +158,3 @@ U_BOOT_DRIVER(rtc_ds1337) = { .of_match = ds1337_rtc_ids, .ops = &ds1337_rtc_ops, }; -#endif diff --git a/drivers/rtc/zynqmp_rtc.c b/drivers/rtc/zynqmp_rtc.c index 15122a04838..4fee75bf9cf 100644 --- a/drivers/rtc/zynqmp_rtc.c +++ b/drivers/rtc/zynqmp_rtc.c @@ -5,26 +5,30 @@ #define LOG_CATEGORY UCLASS_RTC +#include <clk.h> #include <dm.h> #include <rtc.h> #include <asm/io.h> +#include <dm/device_compat.h> /* RTC Registers */ #define RTC_SET_TM_WR 0x00 #define RTC_SET_TM_RD 0x04 #define RTC_CALIB_WR 0x08 +#define RTC_CALIB_RD 0x0C #define RTC_CUR_TM 0x10 #define RTC_INT_STS 0x20 #define RTC_CTRL 0x40 #define RTC_INT_SEC BIT(0) #define RTC_BATT_EN BIT(31) -#define RTC_CALIB_DEF 0x198233 +#define RTC_CALIB_DEF 0x7FFF +#define RTC_FREQ_MAX 0x10000 #define RTC_CALIB_MASK 0x1FFFFF struct zynqmp_rtc_priv { fdt_addr_t base; - unsigned int calibval; + unsigned long calibval; }; static int zynqmp_rtc_get(struct udevice *dev, struct rtc_time *tm) @@ -70,13 +74,6 @@ static int zynqmp_rtc_set(struct udevice *dev, const struct rtc_time *tm) */ new_time = rtc_mktime(tm) + 1; - /* - * Writing into calibration register will clear the Tick Counter and - * force the next second to be signaled exactly in 1 second period - */ - priv->calibval &= RTC_CALIB_MASK; - writel(priv->calibval, (priv->base + RTC_CALIB_WR)); - writel(new_time, priv->base + RTC_SET_TM_WR); /* @@ -107,15 +104,6 @@ static int zynqmp_rtc_init(struct udevice *dev) rtc_ctrl |= RTC_BATT_EN; writel(rtc_ctrl, priv->base + RTC_CTRL); - /* - * Based on crystal freq of 33.330 KHz - * set the seconds counter and enable, set fractions counter - * to default value suggested as per design spec - * to correct RTC delay in frequency over period of time. - */ - priv->calibval &= RTC_CALIB_MASK; - writel(priv->calibval, (priv->base + RTC_CALIB_WR)); - return 0; } @@ -128,8 +116,44 @@ static int zynqmp_rtc_probe(struct udevice *dev) if (priv->base == FDT_ADDR_T_NONE) return -EINVAL; - priv->calibval = dev_read_u32_default(dev, "calibration", - RTC_CALIB_DEF); + ret = readl(priv->base + RTC_CALIB_RD); + if (!ret) { + struct clk rtc_clk; + unsigned long clk_rate; + + /* Get the RTC clock rate */ + ret = clk_get_by_name_optional(dev, "rtc", &rtc_clk); + if (!ret) { + clk_rate = clk_get_rate(&rtc_clk); + /* Use clock frequency if valid, fallback to calibration value */ + if (clk_rate > 0 && clk_rate <= RTC_FREQ_MAX) { + /* Valid clock frequency */ + priv->calibval = clk_rate - 1; + } else if (clk_rate == 0) { + priv->calibval = dev_read_u32_default(dev, "calibration", + RTC_CALIB_DEF); + } else { + dev_err(dev, "Invalid clock frequency 0x%lx\n", + clk_rate); + return -EINVAL; + } + } else { + /* Clock framework unavailable, use DT calibration */ + priv->calibval = dev_read_u32_default(dev, "calibration", + RTC_CALIB_DEF); + } + + /* Validate final calibration value */ + if (priv->calibval > RTC_FREQ_MAX) { + dev_err(dev, "Invalid calibration 0x%lx\n", + priv->calibval); + return -EINVAL; + } + + writel(priv->calibval, (priv->base + RTC_CALIB_WR)); + } else { + priv->calibval = ret & RTC_CALIB_MASK; + } ret = zynqmp_rtc_init(dev); diff --git a/drivers/scsi/Makefile b/drivers/scsi/Makefile index b76de1b22a8..c9af60d5d03 100644 --- a/drivers/scsi/Makefile +++ b/drivers/scsi/Makefile @@ -16,4 +16,7 @@ ifdef CONFIG_XPL_BUILD ifdef CONFIG_SPL_SATA obj-$(CONFIG_SCSI) += scsi.o scsi-uclass.o endif +ifdef CONFIG_SPL_UFS_SUPPORT +obj-$(CONFIG_SCSI) += scsi.o scsi-uclass.o +endif endif diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c index 8fe6b38a8c7..116b696b08d 100644 --- a/drivers/scsi/scsi.c +++ b/drivers/scsi/scsi.c @@ -513,7 +513,7 @@ static int scsi_detect_dev(struct udevice *dev, int target, int lun, pccb->target = target; pccb->lun = lun; pccb->pdata = tempbuff; - pccb->datalen = 512; + pccb->datalen = 36; pccb->dma_dir = DMA_FROM_DEVICE; scsi_setup_inquiry(pccb); if (scsi_exec(dev, pccb)) { diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index b84cb9ec781..c86c883e0cb 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -398,7 +398,7 @@ config DEBUG_UART_PL010 config DEBUG_UART_PL011 bool "pl011" - depends on PL01X_SERIAL || PL011_SERIAL + depends on PL01X_SERIAL help Select this to enable a debug UART using the pl01x driver with the PL011 UART type. You will need to provide parameters to make this @@ -862,12 +862,6 @@ config INTEL_MID_SERIAL Select this to enable a UART for Intel MID platforms. This uses the ns16550 driver as a library. -config PL011_SERIAL - bool "ARM PL011 driver" - depends on !DM_SERIAL - help - Select this to enable a UART for platforms using PL011. - config PL01X_SERIAL bool "ARM PL010 and PL011 driver" depends on DM_SERIAL diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index fe8d23be512..66088b44eb6 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -10,7 +10,6 @@ obj-y += serial.o endif obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o -obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o obj-$(CONFIG_$(PHASE_)SYS_NS16550_SERIAL) += serial_ns16550.o obj-$(CONFIG_ALTERA_UART) += altera_uart.o diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 4f7de3ea215..2f24f47badf 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -14,13 +14,10 @@ #include <reset.h> #include <spl.h> #include <watchdog.h> -#include <asm/global_data.h> #include <linux/err.h> #include <linux/types.h> #include <asm/io.h> -DECLARE_GLOBAL_DATA_PTR; - #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ #define UART_MCRVAL (UART_MCR_DTR | \ UART_MCR_RTS) /* RTS/DTR */ @@ -140,9 +137,9 @@ static int serial_in_dynamic(struct ns16550_plat *plat, u8 *addr) } } else if (plat->flags & NS16550_FLAG_BE) { return readb(addr + (1 << plat->reg_shift) - 1); - } else { - return readb(addr); } + + return readb(addr); } #else static inline void serial_out_dynamic(struct ns16550_plat *plat, u8 *addr, diff --git a/drivers/serial/sandbox.c b/drivers/serial/sandbox.c index cc0491bc3c8..658cbd2bbc9 100644 --- a/drivers/serial/sandbox.c +++ b/drivers/serial/sandbox.c @@ -14,13 +14,10 @@ #include <os.h> #include <serial.h> #include <video.h> -#include <asm/global_data.h> #include <linux/compiler.h> #include <asm/serial.h> #include <asm/state.h> -DECLARE_GLOBAL_DATA_PTR; - static size_t _sandbox_serial_written = 1; static bool sandbox_serial_enabled = true; diff --git a/drivers/serial/serial_adi_uart4.c b/drivers/serial/serial_adi_uart4.c index 24b2071d705..8039ee4d1d8 100644 --- a/drivers/serial/serial_adi_uart4.c +++ b/drivers/serial/serial_adi_uart4.c @@ -78,8 +78,6 @@ #define ERXS BIT(8) #define ETXS BIT(9) -DECLARE_GLOBAL_DATA_PTR; - struct uart4_reg { u32 revid; u32 control; diff --git a/drivers/serial/serial_htif.c b/drivers/serial/serial_htif.c index 2a93bbbcc9f..690de3fc085 100644 --- a/drivers/serial/serial_htif.c +++ b/drivers/serial/serial_htif.c @@ -8,14 +8,11 @@ #include <fdtdec.h> #include <log.h> #include <watchdog.h> -#include <asm/global_data.h> #include <asm/io.h> #include <linux/compiler.h> #include <serial.h> #include <linux/err.h> -DECLARE_GLOBAL_DATA_PTR; - #define HTIF_DATA_BITS 48 #define HTIF_DATA_MASK ((1ULL << HTIF_DATA_BITS) - 1) #define HTIF_DATA_SHIFT 0 diff --git a/drivers/serial/serial_pl01x_internal.h b/drivers/serial/serial_pl01x_internal.h index 7ae3ae50908..3c481b1e3d1 100644 --- a/drivers/serial/serial_pl01x_internal.h +++ b/drivers/serial/serial_pl01x_internal.h @@ -26,11 +26,7 @@ struct pl01x_regs { u32 pl010_lcrl; /* 0x10 Line control register, low byte */ u32 pl010_cr; /* 0x14 Control register */ u32 fr; /* 0x18 Flag register (Read only) */ -#ifdef CONFIG_PL011_SERIAL_RLCR - u32 pl011_rlcr; /* 0x1c Receive line control register */ -#else u32 reserved; -#endif u32 ilpr; /* 0x20 IrDA low-power counter register */ u32 pl011_ibrd; /* 0x24 Integer baud rate register */ u32 pl011_fbrd; /* 0x28 Fractional baud rate register */ diff --git a/drivers/serial/serial_xen.c b/drivers/serial/serial_xen.c index e05805f6372..4ba8d3ee641 100644 --- a/drivers/serial/serial_xen.c +++ b/drivers/serial/serial_xen.c @@ -7,7 +7,6 @@ #include <dm.h> #include <serial.h> #include <watchdog.h> -#include <asm/global_data.h> #include <linux/bug.h> @@ -20,8 +19,6 @@ #include <xen/interface/io/console.h> #include <xen/interface/io/ring.h> -DECLARE_GLOBAL_DATA_PTR; - u32 console_evtchn; /* diff --git a/drivers/smem/msm_smem.c b/drivers/smem/msm_smem.c index b6b92d3530d..7a50d5a5792 100644 --- a/drivers/smem/msm_smem.c +++ b/drivers/smem/msm_smem.c @@ -7,7 +7,6 @@ #include <errno.h> #include <dm.h> -#include <asm/global_data.h> #include <dm/device_compat.h> #include <dm/devres.h> #include <dm/of_access.h> @@ -20,8 +19,6 @@ #include <linux/sizes.h> #include <smem.h> -DECLARE_GLOBAL_DATA_PTR; - /* * The Qualcomm shared memory system is an allocate-only heap structure that * consists of one of more memory areas that can be accessed by the processors diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 8c6c095a8cf..4ff17617d99 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -34,7 +34,7 @@ config DM_SPI spi_slave structure. config SPI_MEM - bool "SPI memory extension" + bool select DEVRES help Enable this option if you want to enable the SPI memory extension. @@ -43,7 +43,7 @@ config SPI_MEM config SPI_DIRMAP bool "SPI direct mapping" - depends on SPI_MEM + select SPI_MEM help Enable the SPI direct mapping API. Most modern SPI controllers can directly map a SPI memory (or a portion of the SPI memory) in the CPU @@ -62,7 +62,8 @@ config ADI_SPI3 config AIROHA_SNFI_SPI bool "Airoha SPI memory controller driver" - depends on SPI_MEM && ARCH_AIROHA + depends on ARCH_AIROHA + select SPI_MEM help Enable the Airoha SPI memory controller driver. This driver is originally based on the Airoha SNFI IP core. It can only be @@ -102,7 +103,8 @@ config ATH79_SPI config ATMEL_QSPI bool "Atmel Quad SPI Controller" - depends on ARCH_AT91 && SPI_MEM + depends on ARCH_AT91 + select SPI_MEM help Enable the Atmel Quad SPI controller in master mode. This driver does not support generic SPI. The implementation supports only the @@ -152,7 +154,7 @@ config BCMSTB_SPI config CORTINA_SFLASH bool "Cortina-Access Serial Flash controller driver" - depends on SPI_MEM + select SPI_MEM help Enable the Cortina-Access Serial Flash controller driver. This driver can be used to access the SPI NOR/NAND flash on platforms embedding this @@ -160,6 +162,7 @@ config CORTINA_SFLASH config CADENCE_QSPI bool "Cadence QSPI driver" + select SPI_MEM help Enable the Cadence Quad-SPI (QSPI) driver. This driver can be used to access the SPI NOR flash on platforms embedding this @@ -205,7 +208,7 @@ config CF_SPI config CV1800B_SPIF bool "Sophgo cv1800b SPI Flash Controller driver" - depends on SPI_MEM + select SPI_MEM help Enable the Sophgo cv1800b SPI Flash Controller driver. This driver can be used to access the SPI NOR flash on platforms embedding this @@ -243,6 +246,7 @@ config FSL_DSPI config FSL_QSPI bool "Freescale QSPI driver" + select SPI_MEM imply SPI_FLASH_BAR help Enable the Freescale Quad-SPI (QSPI) driver. This driver can be @@ -294,6 +298,7 @@ config MESON_SPIFC config MICROCHIP_COREQSPI bool "Microchip FPGA QSPI Controller driver" + select SPI_MEM help Enable the QSPI driver for Microchip FPGA QSPI controllers. This driver can be used on Polarfire SoC. @@ -343,7 +348,7 @@ config MT7621_SPI config MTK_SNOR bool "Mediatek SPI-NOR controller driver" - depends on SPI_MEM + select SPI_MEM select DEVRES help Enable the Mediatek SPINOR controller driver. This driver has @@ -351,7 +356,7 @@ config MTK_SNOR config MTK_SNFI_SPI bool "Mediatek SPI memory controller driver" - depends on SPI_MEM + select SPI_MEM help Enable the Mediatek SPI memory controller driver. This driver is originally based on the MediaTek SNFI IP core. It can only be @@ -360,7 +365,7 @@ config MTK_SNFI_SPI config MTK_SPIM bool "Mediatek SPI-MEM master controller driver" - depends on SPI_MEM + select SPI_MEM help Enable MediaTek SPI-MEM master controller driver. This driver mainly supports SPI flashes. You can use single, dual or quad mode @@ -385,6 +390,7 @@ config MXS_SPI config SPI_MXIC bool "Macronix MX25F0A SPI controller" + select SPI_MEM help Enable the Macronix MX25F0A SPI controller driver. This driver can be used to access the SPI flash on platforms embedding @@ -403,11 +409,19 @@ config NPCM_PSPI config NXP_FSPI bool "NXP FlexSPI driver" - depends on SPI_MEM + select SPI_MEM help Enable the NXP FlexSPI (FSPI) driver. This driver can be used to access the SPI NOR flash on platforms embedding this NXP IP core. +config NXP_XSPI + bool "NXP XSPI driver" + depends on ARCH_IMX9 + select SPI_MEM + help + Enable the NXP External SPI (XSPI) driver. This driver can be used to + access the SPI NOR/NAND flash on platforms embedding this NXP IP core. + config OCTEON_SPI bool "Octeon SPI driver" depends on ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2 @@ -513,7 +527,8 @@ config SANDBOX_SPI_MAX_CS config SPI_ASPEED_SMC bool "ASPEED SPI flash controller driver" - depends on DM_SPI && SPI_MEM && ARCH_ASPEED + depends on DM_SPI && ARCH_ASPEED + select SPI_MEM help Enable ASPEED SPI flash controller driver for AST2500 and AST2600 SoCs. @@ -534,7 +549,7 @@ config SOFT_SPI config SPI_SN_F_OSPI tristate "Socionext F_OSPI SPI flash controller" - depends on SPI_MEM + select SPI_MEM help This enables support for the Socionext F_OSPI controller for connecting an SPI flash memory over up to 8-bit wide bus. diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 0dc2d23e172..13d9c5dce80 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_MXS_SPI) += mxs_spi.o obj-$(CONFIG_NPCM_FIU_SPI) += npcm_fiu_spi.o obj-$(CONFIG_NPCM_PSPI) += npcm_pspi.o obj-$(CONFIG_NXP_FSPI) += nxp_fspi.o +obj-$(CONFIG_NXP_XSPI) += nxp_xspi.o obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o obj-$(CONFIG_OCTEON_SPI) += octeon_spi.o obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o diff --git a/drivers/spi/ca_sflash.c b/drivers/spi/ca_sflash.c index db32e39add2..f00df93a5f5 100644 --- a/drivers/spi/ca_sflash.c +++ b/drivers/spi/ca_sflash.c @@ -21,9 +21,6 @@ #include <spi.h> #include <spi-mem.h> #include <reset.h> -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; struct ca_sflash_regs { u32 idr; /* 0x00:Flash word ID Register */ diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index a00642d09d3..e6f4ba49e77 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -35,6 +35,10 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, bytes_to_dma = n_rx - rx_rem; if (bytes_to_dma) { + if (priv->use_dac_mode) + clrbits_le32(priv->regbase + CQSPI_REG_CONFIG, + CQSPI_REG_CONFIG_DIRECT); + cadence_qspi_apb_enable_linear_mode(false); reg = readl(priv->regbase + CQSPI_REG_CONFIG); reg |= CQSPI_REG_CONFIG_ENBL_DMA; @@ -125,6 +129,9 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, memcpy(rxbuf, rxbuf + 1, n_rx - 1); } + if (priv->use_dac_mode) + cadence_qspi_apb_dac_mode_enable(priv->regbase); + return 0; } diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index d1404e13810..2a4a49c5f1c 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -13,6 +13,7 @@ #include <spi.h> #include <spi-mem.h> #include <dm/device_compat.h> +#include <linux/delay.h> #include <linux/err.h> #include <linux/errno.h> #include <linux/io.h> @@ -254,8 +255,23 @@ static int cadence_spi_probe(struct udevice *bus) } priv->resets = devm_reset_bulk_get_optional(bus); - if (priv->resets) - reset_deassert_bulk(priv->resets); + if (priv->resets) { + /* Assert all OSPI reset lines */ + ret = reset_assert_bulk(priv->resets); + if (ret) { + dev_err(bus, "Failed to assert OSPI reset: %d\n", ret); + return ret; + } + + udelay(10); + + /* Deassert all OSPI reset lines */ + ret = reset_deassert_bulk(priv->resets); + if (ret) { + dev_err(bus, "Failed to deassert OSPI reset: %d\n", ret); + return ret; + } + } if (!priv->qspi_is_init) { cadence_qspi_apb_controller_init(priv); diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index 7ed35aa3e66..117e36376b7 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -275,7 +275,7 @@ int espi_xfer(struct fsl_spi_slave *fsl, uint cs, unsigned int bitlen, } } if (data_in) { - memcpy(data_in, buffer + 2 * cmd_len, tran_len); + memcpy(data_in, buffer + rx_offset, tran_len); if (*buffer == 0x0b) { data_in += tran_len; data_len -= tran_len; diff --git a/drivers/spi/microchip_coreqspi.c b/drivers/spi/microchip_coreqspi.c index a84b257fb1a..b3ff611e8f7 100644 --- a/drivers/spi/microchip_coreqspi.c +++ b/drivers/spi/microchip_coreqspi.c @@ -18,8 +18,6 @@ #include <linux/sizes.h> #include <asm/gpio.h> -DECLARE_GLOBAL_DATA_PTR; - /* * QSPI Control register mask defines */ diff --git a/drivers/spi/mvebu_a3700_spi.c b/drivers/spi/mvebu_a3700_spi.c index fde9b142fb8..79836d7e271 100644 --- a/drivers/spi/mvebu_a3700_spi.c +++ b/drivers/spi/mvebu_a3700_spi.c @@ -11,14 +11,11 @@ #include <spi.h> #include <clk.h> #include <wait_bit.h> -#include <asm/global_data.h> #include <asm/io.h> #include <dm/device_compat.h> #include <linux/bitops.h> #include <asm/gpio.h> -DECLARE_GLOBAL_DATA_PTR; - #define MVEBU_SPI_A3700_XFER_RDY BIT(1) #define MVEBU_SPI_A3700_FIFO_FLUSH BIT(9) #define MVEBU_SPI_A3700_BYTE_LEN BIT(5) diff --git a/drivers/spi/nxp_xspi.c b/drivers/spi/nxp_xspi.c new file mode 100644 index 00000000000..200138f5adf --- /dev/null +++ b/drivers/spi/nxp_xspi.c @@ -0,0 +1,914 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include <asm/arch/clock.h> +#include <asm/io.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <linux/bitops.h> +#include <linux/bug.h> +#include <linux/err.h> +#include <linux/iopoll.h> +#include <linux/kernel.h> +#include <linux/sizes.h> +#include <log.h> +#include <malloc.h> +#include <spi.h> +#include <spi-mem.h> + +#include "nxp_xspi.h" + +static inline void xspi_writel(u32 val, u32 addr) +{ + void __iomem *_addr = (void __iomem *)(uintptr_t)addr; + + out_le32(_addr, val); +}; + +static inline u32 xspi_readl(u32 addr) +{ + return in_le32((uintptr_t)addr); +}; + +#define xspi_config_sfp_tg(x, env, sfar, ipcr) \ + do { \ + xspi_writel_offset(x, env, (sfar), SFP_TG_SFAR); \ + xspi_writel_offset(x, env, (ipcr), SFP_TG_IPCR); \ + } while (0) + +static int xspi_readl_poll_tout(struct nxp_xspi *x, int env, u32 offset, + u32 mask, u32 delay_us, u32 timeout_us, bool wait_mask_set) +{ + u32 reg; + void __iomem *addr = (void __iomem *)(uintptr_t)x->iobase + (env * ENV_ADDR_SIZE) + offset; + + if (wait_mask_set) + return readl_poll_sleep_timeout(addr, reg, (reg & mask), + delay_us, timeout_us); + else + return readl_poll_sleep_timeout(addr, reg, !(reg & mask), + delay_us, timeout_us); +}; + +static struct nxp_xspi_devtype_data imx94_data = { + .rxfifo = SZ_512, /* RX fifo Size*/ + .rx_buf_size = 64 * 4, /* RBDR buffer size */ + .txfifo = SZ_1K, + .ahb_buf_size = SZ_4K, + .quirks = 0, +}; + +static const struct udevice_id nxp_xspi_ids[] = { + { .compatible = "nxp,imx94-xspi", .data = (ulong)&imx94_data, }, + { } +}; + +static int nxp_xspi_claim_bus(struct udevice *dev) +{ + return 0; +} + +#if CONFIG_IS_ENABLED(CLK) +static int nxp_xspi_clk_prep_enable(struct nxp_xspi *x) +{ + return clk_enable(&x->clk); +}; + +static void nxp_xspi_clk_disable_unprep(struct nxp_xspi *x) +{ + clk_disable(&x->clk); +}; +#endif + +static int xspi_swreset(struct nxp_xspi *x) +{ + u32 reg; + + reg = xspi_readl_offset(x, 0, MCR); + reg |= (XSPI_MCR_SWRSTHD_MASK | XSPI_MCR_SWRSTSD_MASK); + xspi_writel_offset(x, 0, reg, MCR); + udelay(2); + reg &= ~(XSPI_MCR_SWRSTHD_MASK | XSPI_MCR_SWRSTSD_MASK); + xspi_writel_offset(x, 0, reg, MCR); + + return 0; +}; + +static void nxp_xspi_dll_bypass(struct nxp_xspi *x) +{ + u32 reg; + int ret; + + xspi_swreset(x); + + xspi_writel_offset(x, 0, 0, DLLCRA); + + reg = XSPI_DLLCRA_SLV_EN_MASK; + xspi_writel_offset(x, 0, reg, DLLCRA); + + reg = XSPI_DLLCRA_FREQEN_MASK | XSPI_DLLCRA_SLV_EN_MASK | + XSPI_DLLCRA_SLV_DLL_BYPASS_MASK | XSPI_DLLCRA_SLV_DLY_COARSE(7); + xspi_writel_offset(x, 0, reg, DLLCRA); + + reg |= XSPI_DLLCRA_SLV_UPD_MASK; + xspi_writel_offset(x, 0, reg, DLLCRA); + + ret = xspi_readl_poll_tout(x, 0, XSPI_DLLSR, XSPI_DLLSR_SLVA_LOCK_MASK, 1, POLL_TOUT, true); + if (ret) + dev_err(x->dev, "DLL SLVA unlock, the DLL status is %x, need to check!\n", + xspi_readl(x->iobase + XSPI_DLLSR)); + + reg &= ~XSPI_DLLCRA_SLV_UPD_MASK; + xspi_writel_offset(x, 0, reg, DLLCRA); +} + +static void nxp_xspi_dll_auto(struct nxp_xspi *x, unsigned long rate) +{ + u32 reg; + int ret; + + xspi_swreset(x); + + xspi_writel_offset(x, 0, 0, DLLCRA); + + reg = XSPI_DLLCRA_SLV_EN_MASK; + xspi_writel_offset(x, 0, reg, DLLCRA); + + reg = XSPI_DLLCRA_DLL_REFCNTR(2) | XSPI_DLLCRA_DLLRES(8) | + XSPI_DLLCRA_SLAVE_AUTO_UPDT_MASK | XSPI_DLLCRA_SLV_EN_MASK; + if (rate > MHZ(133)) + reg |= XSPI_DLLCRA_FREQEN_MASK; + + xspi_writel_offset(x, 0, reg, DLLCRA); + + reg |= XSPI_DLLCRA_SLV_UPD_MASK; + xspi_writel_offset(x, 0, reg, DLLCRA); + + reg |= XSPI_DLLCRA_DLLEN_MASK; + xspi_writel_offset(x, 0, reg, DLLCRA); + + ret = xspi_readl_poll_tout(x, 0, XSPI_DLLSR, + XSPI_DLLSR_DLLA_LOCK_MASK | XSPI_DLLSR_SLVA_LOCK_MASK, + 1, POLL_TOUT, true); + if (ret) + dev_err(x->dev, "the DLL status is %x, need to check!\n", + xspi_readl(x->iobase + XSPI_DLLSR)); +} + +static void nxp_xspi_disable_ddr(struct nxp_xspi *x) +{ + u32 reg; + + reg = xspi_readl_offset(x, 0, MCR); + reg |= XSPI_MCR_MDIS_MASK; + xspi_writel_offset(x, 0, reg, MCR); + + reg &= ~(XSPI_MCR_DQS_EN_MASK | XSPI_MCR_DDR_EN_MASK); + reg &= ~XSPI_MCR_DQS_FA_SEL_MASK; + reg |= XSPI_MCR_DQS_FA_SEL(1); + xspi_writel_offset(x, 0, reg, MCR); + + reg = xspi_readl_offset(x, 0, FLSHCR); + reg &= ~XSPI_FLSHCR_TDH_MASK; + xspi_writel_offset(x, 0, reg, FLSHCR); + + xspi_writel_offset(x, 0, XSPI_SMPR_DLLFSMPFA(7), SMPR); + + reg = xspi_readl_offset(x, 0, MCR); + reg &= ~XSPI_MCR_MDIS_MASK; + xspi_writel_offset(x, 0, reg, MCR); + + x->support_max_rate = MHZ(133); +} + +static void nxp_xspi_enable_ddr(struct nxp_xspi *x) +{ + u32 reg; + + reg = xspi_readl_offset(x, 0, MCR); + reg |= XSPI_MCR_MDIS_MASK; + xspi_writel_offset(x, 0, reg, MCR); + + reg |= XSPI_MCR_DQS_EN_MASK | XSPI_MCR_DDR_EN_MASK; + reg &= ~XSPI_MCR_DQS_FA_SEL_MASK; + reg |= XSPI_MCR_DQS_FA_SEL(3); + xspi_writel_offset(x, 0, reg, MCR); + + reg = xspi_readl_offset(x, 0, FLSHCR); + reg |= XSPI_FLSHCR_TDH(1); + xspi_writel_offset(x, 0, reg, FLSHCR); + + xspi_writel_offset(x, 0, XSPI_SMPR_DLLFSMPFA(4), SMPR); + + reg = xspi_readl_offset(x, 0, MCR); + reg &= ~XSPI_MCR_MDIS_MASK; + xspi_writel_offset(x, 0, reg, MCR); + + x->support_max_rate = MHZ(200); +} + +static int nxp_xspi_set_speed(struct udevice *bus, uint speed) +{ + debug("%s: %u\n", __func__, speed); +#if CONFIG_IS_ENABLED(CLK) + struct nxp_xspi *x = dev_get_priv(bus); + int ret; + + nxp_xspi_clk_disable_unprep(x); + + ret = clk_set_rate(&x->clk, speed); + if (ret < 0) + return ret; + + ret = nxp_xspi_clk_prep_enable(x); + if (ret) + return ret; + + xspi_swreset(x); +#endif + return 0; +} + +static int nxp_xspi_set_mode(struct udevice *bus, uint mode) +{ + return 0; +} + +static int nxp_xspi_adjust_op_size(struct spi_slave *slave, + struct spi_mem_op *op) +{ + struct nxp_xspi *x; + struct udevice *bus; + + bus = slave->dev->parent; + x = dev_get_priv(bus); + + if (op->data.dir == SPI_MEM_DATA_OUT) { + if (op->data.nbytes > x->devtype_data->txfifo) + op->data.nbytes = x->devtype_data->txfifo; + } else { + if (op->data.nbytes > x->devtype_data->ahb_buf_size) + op->data.nbytes = x->devtype_data->ahb_buf_size; + else if (op->data.nbytes > x->devtype_data->rxfifo) + op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8); + } + + return 0; +} + +static int nxp_xspi_check_buswidth(struct nxp_xspi *x, u8 width) +{ + switch (width) { + case 1: + case 2: + case 4: + case 8: + return 0; + } + + return -ENOTSUPP; +} + +static bool nxp_xspi_supports_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + struct nxp_xspi *x; + struct udevice *bus; + int ret; + + bus = slave->dev->parent; + x = dev_get_priv(bus); + + ret = nxp_xspi_check_buswidth(x, op->cmd.buswidth); + + if (op->addr.nbytes) + ret |= nxp_xspi_check_buswidth(x, op->addr.buswidth); + + if (op->dummy.nbytes) + ret |= nxp_xspi_check_buswidth(x, op->dummy.buswidth); + + if (op->data.nbytes) + ret |= nxp_xspi_check_buswidth(x, op->data.buswidth); + + if (ret) + return false; + + /* + * The number of address bytes should be equal to or less than 4 bytes. + */ + if (op->addr.nbytes > 4) + return false; + + /* + * If requested address value is greater than controller assigned + * memory mapped space, return error as it didn't fit in the range + * of assigned address space. + */ + if (op->addr.val >= x->a1_size + x->a2_size) + return false; + + /* Max 64 dummy clock cycles supported */ + if (op->dummy.buswidth && + (op->dummy.nbytes * 8 / op->dummy.buswidth > 64)) + return false; + + /* Max data length, check controller limits and alignment */ + if (op->data.dir == SPI_MEM_DATA_IN && + (op->data.nbytes > x->devtype_data->ahb_buf_size || + (op->data.nbytes > x->devtype_data->rxfifo && + !IS_ALIGNED(op->data.nbytes, 8)))) + return false; + + if (op->data.dir == SPI_MEM_DATA_OUT && + op->data.nbytes > x->devtype_data->txfifo) + return false; + + if (op->cmd.dtr) + return spi_mem_dtr_supports_op(slave, op); + else + return spi_mem_default_supports_op(slave, op); +} + +static int xspi_update_lut(struct nxp_xspi *x, u32 seq_index, const u32 *lut_base, u32 num_of_seq) +{ + int ret; + + ret = xspi_readl_poll_tout(x, 0, XSPI_SR, XSPI_SR_BUSY_MASK, 1, POLL_TOUT, false); + if (ret) { + dev_err(x->dev, "%s: Timeout while waiting for busy flag to clear.\n", __func__); + return ret; + } + + xspi_writel_offset(x, 0, XSPI_LUT_KEY_VAL, LUTKEY); + xspi_writel_offset(x, 0, 0x2, LCKCR); + + for (int i = 0; i < num_of_seq; i++) + xspi_writel(*(lut_base + i), x->iobase + XSPI_LUT + (seq_index * 5 + i) * 4); + + xspi_writel_offset(x, 0, XSPI_LUT_KEY_VAL, LUTKEY); + xspi_writel_offset(x, 0, 0x1, LCKCR); + + return 0; +} + +static int nxp_xspi_prepare_lut(struct nxp_xspi *x, + const struct spi_mem_op *op) +{ + u32 lutval[5] = {0}; + int lutidx = 1; + int ret; + + /* cmd */ + if (op->cmd.dtr) { + lutval[0] |= LUT_DEF(0, CMD_DDR, LUT_PAD(op->cmd.buswidth), + op->cmd.opcode >> 8); + lutval[lutidx / 2] |= LUT_DEF(lutidx, CMD_DDR, + LUT_PAD(op->cmd.buswidth), + op->cmd.opcode & 0x00ff); + lutidx++; + } else { + lutval[0] |= LUT_DEF(0, CMD_SDR, LUT_PAD(op->cmd.buswidth), + op->cmd.opcode); + } + + /* addr bytes */ + if (op->addr.nbytes) { + lutval[lutidx / 2] |= LUT_DEF(lutidx, op->addr.dtr ? RADDR_DDR : RADDR_SDR, + LUT_PAD(op->addr.buswidth), + op->addr.nbytes * 8); + lutidx++; + } + + /* dummy bytes, if needed */ + if (op->dummy.nbytes) { + lutval[lutidx / 2] |= LUT_DEF(lutidx, DUMMY_CYCLE, + LUT_PAD(op->data.buswidth), + op->dummy.nbytes * 8 / + op->dummy.buswidth / (op->dummy.dtr ? 2 : 1)); + lutidx++; + } + + /* read/write data bytes */ + if (op->data.nbytes) { + lutval[lutidx / 2] |= LUT_DEF(lutidx, + op->data.dir == SPI_MEM_DATA_IN ? + (op->data.dtr ? READ_DDR : READ_SDR) : + (op->data.dtr ? WRITE_DDR : WRITE_SDR), + LUT_PAD(op->data.buswidth), + 0); + lutidx++; + } + + /* stop condition. */ + lutval[lutidx / 2] |= LUT_DEF(lutidx, CMD_STOP, 0, 0); +#ifdef DEBUG + print_buffer(0, lutval, 4, lutidx / 2 + 1, 4); +#endif + ret = xspi_update_lut(x, CMD_LUT_FOR_IP_CMD, lutval, ARRAY_SIZE(lutval)); + if (ret) + return ret; + + if (op->data.nbytes && + (op->data.dir == SPI_MEM_DATA_IN || op->data.dir == SPI_MEM_DATA_OUT) && + op->addr.nbytes) { + ret = xspi_update_lut(x, CMD_LUT_FOR_AHB_CMD, lutval, ARRAY_SIZE(lutval)); + if (ret) + return ret; + } + + return 0; +} + +static void nxp_xspi_read_ahb(struct nxp_xspi *x, const struct spi_mem_op *op) +{ + u32 len = op->data.nbytes; + + /* Read out the data directly from the AHB buffer. */ + memcpy_fromio(op->data.buf.in, (void *)(uintptr_t)(x->ahb_addr + op->addr.val), len); +} + +static int nxp_xspi_fill_txfifo(struct nxp_xspi *x, + const struct spi_mem_op *op) +{ + const u8 *buf = (u8 *)op->data.buf.out; + int xfer_remaining_size = op->data.nbytes; + u32 reg, val = 0; + int ret; + + /* clear the TX FIFO. */ + xspi_set_reg_field(x, x->config.env, 1, MCR, CLR_TXF); + ret = xspi_readl_poll_tout(x, x->config.env, XSPI_MCR, + XSPI_MCR_CLR_TXF_MASK, 1, POLL_TOUT, false); + if (ret) { + dev_err(x->dev, "%s: Timeout while waiting for TX FIFO clear\n", __func__); + return ret; + } + + reg = XSPI_TBCT_WMRK((x->devtype_data->txfifo - ALIGN_DOWN(op->data.nbytes, 4)) / 4 + 1); + xspi_writel_offset(x, x->config.env, reg, TBCT); + + reg = x->ahb_addr + op->addr.val; + xspi_writel_offset(x, x->config.env, reg, SFP_TG_SFAR); + + udelay(2); + reg = XSPI_SFP_TG_IPCR_SEQID(CMD_LUT_FOR_IP_CMD) | XSPI_SFP_TG_IPCR_IDATSZ(op->data.nbytes); + u64 start = timer_get_us(); + + xspi_writel_offset(x, x->config.env, reg, SFP_TG_IPCR); + + while (xfer_remaining_size > 0) { + if (xspi_get_reg_field(x, x->config.env, SR, TXFULL)) + continue; + + if (xfer_remaining_size > 4) { + memcpy(&val, buf, 4); + buf += 4; + } else { + val = 0; + memcpy(&val, buf, xfer_remaining_size); + buf += xfer_remaining_size; + } + + xspi_writel_offset(x, x->config.env, val, TBDR); + xfer_remaining_size -= 4; + + if (xspi_get_reg_field(x, x->config.env, FR, ILLINE)) + break; + } + + /* Wait for controller being ready. */ + ret = xspi_readl_poll_tout(x, x->config.env, XSPI_SR, + XSPI_SR_BUSY_MASK, 1, POLL_TOUT, false); + if (ret) { + dev_err(x->dev, "%s: Timeout while waiting for busy flag to clear\n", __func__); + return ret; + } + + u32 trctr = xspi_get_reg_field(x, x->config.env, TBSR, TRCTR); + + if ((ALIGN(op->data.nbytes, 4) / 4) != trctr) + dev_dbg(x->dev, "Fail to write data. tx_size = %u, trctr = %u.\n", + op->data.nbytes, trctr * 4); + + dev_dbg(x->dev, "tx data size: %u bytes, spend: %llu us\r\n", + op->data.nbytes, timer_get_us() - start); + + return 0; +} + +static int nxp_xspi_read_rxfifo(struct nxp_xspi *x, + const struct spi_mem_op *op) +{ + u32 reg; + int ret, i; + u32 val; + + u8 *buf = op->data.buf.in; + + reg = XSPI_RBCT_WMRK(x->devtype_data->rx_buf_size / 4 - 1); + xspi_writel_offset(x, x->config.env, reg, RBCT); + + /* clear the TX FIFO. */ + xspi_set_reg_field(x, x->config.env, 1, MCR, CLR_RXF); + ret = xspi_readl_poll_tout(x, x->config.env, XSPI_MCR, + XSPI_MCR_CLR_RXF_MASK, 1, POLL_TOUT, false); + if (ret) { + dev_err(x->dev, "%s: Timeout while waiting for RX FIFO clear\n", __func__); + return ret; + } + + xspi_writel_offset(x, x->config.env, x->ahb_addr + op->addr.val, SFP_TG_SFAR); + reg = XSPI_SFP_TG_IPCR_SEQID(CMD_LUT_FOR_IP_CMD) | XSPI_SFP_TG_IPCR_IDATSZ(op->data.nbytes); + u64 start = timer_get_us(); + + xspi_writel_offset(x, x->config.env, reg, SFP_TG_IPCR); + + ret = xspi_readl_poll_tout(x, x->config.env, XSPI_SR, XSPI_SR_BUSY_MASK, 1, + POLL_TOUT, false); + if (ret) { + dev_err(x->dev, "%s: Timeout while waiting for busy flag to clear\n", __func__); + return ret; + } + + for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) { + if (i == x->devtype_data->rx_buf_size) { + reg = xspi_readl_offset(x, x->config.env, FR); + reg |= XSPI_FR_RBDF_MASK; + xspi_writel_offset(x, x->config.env, reg, FR); + } + val = xspi_readl(x->iobase + (x->config.env * ENV_ADDR_SIZE) + + XSPI_RBDR + (i % x->devtype_data->rx_buf_size)); + memcpy(buf + i, &val, 4); + } + + if (i < op->data.nbytes) { + val = xspi_readl(x->iobase + (x->config.env * ENV_ADDR_SIZE) + + XSPI_RBDR + (i % x->devtype_data->rx_buf_size)); + memcpy(buf + i, &val, op->data.nbytes - i); + } + + /* clear the RX FIFO. */ + xspi_set_reg_field(x, x->config.env, 1, MCR, CLR_RXF); + ret = xspi_readl_poll_tout(x, x->config.env, XSPI_MCR, + XSPI_MCR_CLR_RXF_MASK, 1, POLL_TOUT, false); + if (ret) { + dev_err(x->dev, "%s: Timeout while waiting for RX FIFO clear\n", __func__); + return ret; + } + + dev_dbg(x->dev, "rx data size: %u bytes, spend: %llu us\r\n", + op->data.nbytes, timer_get_us() - start); + + return 0; +} + +static int nxp_xspi_xfer_cmd(struct nxp_xspi *x, const struct spi_mem_op *op) +{ + u32 reg; + int ret; + + xspi_writel_offset(x, x->config.env, x->ahb_addr + op->addr.val, SFP_TG_SFAR); + reg = XSPI_SFP_TG_IPCR_SEQID(CMD_LUT_FOR_IP_CMD) | XSPI_SFP_TG_IPCR_IDATSZ(op->data.nbytes); + xspi_writel_offset(x, x->config.env, reg, SFP_TG_IPCR); + + /* Wait for controller being ready. */ + ret = xspi_readl_poll_tout(x, x->config.env, XSPI_SR, XSPI_SR_BUSY_MASK, 1, + POLL_TOUT, false); + if (ret) { + dev_err(x->dev, "%s: Timeout while waiting for busy flag to clear\n", __func__); + return ret; + } + + return 0; +} + +static void nxp_xspi_select_mem(struct nxp_xspi *xspi, struct spi_slave *slave, + const struct spi_mem_op *op) +{ + unsigned long rate = slave->max_hz; + + if (xspi->selected == spi_chip_select(slave->dev) && + xspi->dtr == op->cmd.dtr) + return; + + if (!op->cmd.dtr) { + nxp_xspi_disable_ddr(xspi); + rate = min(xspi->support_max_rate, rate); + xspi->dtr = false; + } else { + nxp_xspi_enable_ddr(xspi); + rate = min(xspi->support_max_rate, rate); + rate *= 2; + xspi->dtr = true; + } + +#if CONFIG_IS_ENABLED(CLK) + int ret; + + nxp_xspi_clk_disable_unprep(xspi); + + ret = clk_set_rate(&xspi->clk, rate); + if (ret < 0) + return; + + ret = nxp_xspi_clk_prep_enable(xspi); + if (ret) + return; +#endif + + xspi->selected = spi_chip_select(slave->dev); + + if (!op->cmd.dtr || rate < MHZ(60)) + nxp_xspi_dll_bypass(xspi); + else + nxp_xspi_dll_auto(xspi, rate); +} + +static int nxp_xspi_exec_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + struct nxp_xspi *x; + struct udevice *bus; + int err = 0; + + bus = slave->dev->parent; + x = dev_get_priv(bus); + + dev_dbg(bus, "%s:%s:%d\n", __FILE__, __func__, __LINE__); + dev_dbg(bus, "buswidth = %u, nbytes = %u, dtr = %u, opcode = 0x%x\n", + op->cmd.buswidth, op->cmd.nbytes, op->cmd.dtr, op->cmd.opcode); + dev_dbg(bus, "buswidth = %u, nbytes = %u, dtr = %u, val = 0x%llx\n", + op->addr.buswidth, op->addr.nbytes, op->addr.dtr, op->addr.val); + dev_dbg(bus, "buswidth = %u, nbytes = %u, dtr = %u\n", + op->dummy.buswidth, op->dummy.nbytes, op->dummy.dtr); + dev_dbg(bus, "buswidth = %u, nbytes = %u, dtr = %u, dir = %u, buf = 0x%llx\n", + op->data.buswidth, op->data.nbytes, op->data.dtr, op->data.dir, + (u64)op->data.buf.in); + + nxp_xspi_select_mem(x, slave, op); + + nxp_xspi_prepare_lut(x, op); + /* + * If we have large chunks of data, we read them through the AHB bus by + * accessing the mapped memory. In all other cases we use IP commands + * to access the flash. Read via AHB bus may be corrupted due to + * existence of an errata and therefore discard AHB read in such cases. + */ + if (op->data.nbytes > (x->config.gmid ? x->devtype_data->rxfifo : DEFAULT_XMIT_SIZE) && + op->data.dir == SPI_MEM_DATA_IN) { + dev_dbg(bus, "ahb read\n"); + nxp_xspi_read_ahb(x, op); + } else { + dev_dbg(bus, "ip command\n"); + /* Wait for controller being ready. */ + err = xspi_readl_poll_tout(x, x->config.env, XSPI_SR, XSPI_SR_BUSY_MASK, + 1, POLL_TOUT, false); + if (err) { + dev_err(x->dev, "Timeout while waiting for XSPI busy flag to clear.\n"); + return err; + } + + xspi_writel_offset(x, x->config.env, GENMASK(31, 0), FR); + + if (op->data.nbytes) { + if (op->data.dir == SPI_MEM_DATA_OUT) + nxp_xspi_fill_txfifo(x, op); + else if (op->data.dir == SPI_MEM_DATA_IN) + nxp_xspi_read_rxfifo(x, op); + else + dev_dbg(x->dev, "%d: never should happen\r\n", __LINE__); + } else { + nxp_xspi_xfer_cmd(x, op); + } + } + +#ifdef DEBUG + if (op->data.nbytes <= 10) + if (op->data.dir != SPI_MEM_NO_DATA) + print_buffer(0, op->data.buf.out, 1, op->data.nbytes, 16); +#endif + + return err; +} + +static const struct spi_controller_mem_ops nxp_xspi_mem_ops = { + .adjust_op_size = nxp_xspi_adjust_op_size, + .supports_op = nxp_xspi_supports_op, + .exec_op = nxp_xspi_exec_op, +}; + +static const struct dm_spi_ops nxp_xspi_ops = { + .claim_bus = nxp_xspi_claim_bus, + .set_speed = nxp_xspi_set_speed, + .set_mode = nxp_xspi_set_mode, + .mem_ops = &nxp_xspi_mem_ops, +}; + +static int nxp_xspi_of_to_plat(struct udevice *bus) +{ + struct nxp_xspi *x = dev_get_priv(bus); + fdt_addr_t iobase; + fdt_addr_t iobase_size; + fdt_addr_t ahb_addr; + fdt_addr_t ahb_size; + +#if CONFIG_IS_ENABLED(CLK) + int ret; +#endif + + x->dev = bus; + + iobase = devfdt_get_addr_size_name(bus, "xspi_base", &iobase_size); + if (iobase == FDT_ADDR_T_NONE) { + dev_err(bus, "xspi_base regs missing\n"); + return -ENODEV; + } + x->iobase = iobase; + + ahb_addr = devfdt_get_addr_size_name(bus, "xspi_mmap", &ahb_size); + if (ahb_addr == FDT_ADDR_T_NONE) { + dev_err(bus, "xspi_mmap regs missing\n"); + return -ENODEV; + } + x->ahb_addr = ahb_addr; + x->a1_size = ahb_size; + x->a2_size = 0; + x->config.gmid = true; + x->config.env = 0; + +#if CONFIG_IS_ENABLED(CLK) + ret = clk_get_by_name(bus, "xspi", &x->clk); + if (ret) { + dev_err(bus, "failed to get xspi clock\n"); + return ret; + } +#endif + + dev_dbg(bus, "iobase=<0x%x>, ahb_addr=<0x%x>, a1_size=<0x%x>, a2_size=<0x%x>, env=<0x%x>, gmid=<0x%x>\n", + x->iobase, x->ahb_addr, x->a1_size, x->a2_size, x->config.env, x->config.gmid); + + return 0; +} + +static int nxp_xspi_config_ahb_buffers(struct nxp_xspi *x) +{ + u32 reg; + + reg = XSPI_BUF3CR_MSTRID(0xa); + xspi_writel_offset(x, 0, reg, BUF0CR); + reg = XSPI_BUF3CR_MSTRID(0x2); + xspi_writel_offset(x, 0, reg, BUF1CR); + reg = XSPI_BUF3CR_MSTRID(0xd); + xspi_writel_offset(x, 0, reg, BUF2CR); + + reg = XSPI_BUF3CR_MSTRID(0x6) | XSPI_BUF3CR_ALLMST_MASK; + reg |= XSPI_BUF3CR_ADATSZ(x->devtype_data->ahb_buf_size / 8U); + xspi_writel_offset(x, 0, reg, BUF3CR); + + /* Only the buffer3 is used */ + xspi_writel_offset(x, 0, 0, BUF0IND); + xspi_writel_offset(x, 0, 0, BUF1IND); + xspi_writel_offset(x, 0, 0, BUF2IND); + + /* Program the Sequence ID for read/write operation. */ + reg = XSPI_BFGENCR_SEQID_WR_EN_MASK | XSPI_BFGENCR_SEQID(CMD_LUT_FOR_AHB_CMD); + xspi_writel_offset(x, 0, reg, BFGENCR); + + /* AHB access towards flash is broken if this AHB alignment boundary is crossed */ + /* 0-No limit 1-256B 10-512B 11b-limit */ + xspi_set_reg_field(x, 0, 0, BFGENCR, ALIGN); + + return 0; +}; + +static void nxp_xspi_config_mdad(struct nxp_xspi *x) +{ + xspi_writel_offset(x, 0, XSPI_TG2MDAD_EXT_VLD_MASK, TG0MDAD); + xspi_writel_offset(x, 0, XSPI_TG2MDAD_EXT_VLD_MASK, TG1MDAD); + xspi_writel_offset(x, 0, XSPI_TG2MDAD_EXT_VLD_MASK, TG2MDAD_EXT); + xspi_writel_offset(x, 0, XSPI_TG2MDAD_EXT_VLD_MASK, TG3MDAD_EXT); + xspi_writel_offset(x, 0, XSPI_TG2MDAD_EXT_VLD_MASK, TG4MDAD_EXT); +} + +static void nxp_xspi_config_frad(struct nxp_xspi *x) +{ + /* Enable Read/Write Access permissions & Valid */ + for (int i = 0; i < 8; i++) { + xspi_writel(XSPI_FRAD0_WORD2_MD0ACP_MASK | XSPI_FRAD0_WORD2_MD1ACP_MASK, + x->iobase + XSPI_FRAD0_WORD2 + (i * 0x20U)); + xspi_writel(XSPI_FRAD0_WORD3_VLD_MASK, + x->iobase + XSPI_FRAD0_WORD3 + (i * 0x20U)); + } + for (int i = 0; i < 8; i++) { + xspi_writel(XSPI_FRAD0_WORD2_MD0ACP_MASK | XSPI_FRAD0_WORD2_MD1ACP_MASK, + x->iobase + XSPI_FRAD8_WORD2 + (i * 0x20U)); + xspi_writel(XSPI_FRAD0_WORD3_VLD_MASK, + x->iobase + XSPI_FRAD8_WORD3 + (i * 0x20U)); + } +} + +static int nxp_xspi_default_setup(struct nxp_xspi *x) +{ + int ret = 0; + u32 reg; + +#if CONFIG_IS_ENABLED(CLK) + ret = clk_set_rate(&x->clk, 20UL * 1000000UL); + if (ret < 0) { + dev_err(x->dev, "clk_set_rate fail\n"); + return ret; + } + dev_dbg(x->dev, "clk rate = %lu\n", clk_get_rate(&x->clk)); + + ret = nxp_xspi_clk_prep_enable(x); + if (ret) { + dev_err(x->dev, "nxp_xspi_clk_prep_enable fail\n"); + return ret; + } +#endif + + if (x->config.gmid) { + reg = xspi_readl_offset(x, 0, MGC); + reg &= ~(XSPI_MGC_GVLD_MASK | XSPI_MGC_GVLDMDAD_MASK | XSPI_MGC_GVLDFRAD_MASK); + xspi_writel_offset(x, 0, reg, MGC); + + xspi_writel_offset(x, 0, GENMASK(31, 0), MTO); + } + + nxp_xspi_config_mdad(x); + nxp_xspi_config_frad(x); + + xspi_set_reg_field(x, 0, 0, MCR, MDIS); + + xspi_swreset(x); + + xspi_set_reg_field(x, 0, 1, MCR, MDIS); + + reg = xspi_readl_offset(x, 0, MCR); + reg &= ~(XSPI_MCR_END_CFG_MASK | XSPI_MCR_DQS_FA_SEL_MASK | + XSPI_MCR_DDR_EN_MASK | XSPI_MCR_DQS_EN_MASK | XSPI_MCR_CKN_FA_EN_MASK | + XSPI_MCR_DQS_OUT_EN_MASK | XSPI_MCR_ISD2FA_MASK | XSPI_MCR_ISD3FA_MASK); + + reg |= XSPI_MCR_ISD2FA_MASK; + reg |= XSPI_MCR_ISD3FA_MASK; + + reg |= XSPI_MCR_END_CFG(3); + + xspi_writel_offset(x, 0, reg, MCR); + + reg = xspi_readl_offset(x, 0, SFACR); + + reg &= ~(uint32_t)(XSPI_SFACR_CAS_MASK | XSPI_SFACR_WA_MASK | + XSPI_SFACR_BYTE_SWAP_MASK | XSPI_SFACR_WA_4B_EN_MASK | + XSPI_SFACR_FORCE_A10_MASK); + + xspi_writel_offset(x, 0, reg, SFACR); + + nxp_xspi_config_ahb_buffers(x); + + reg = XSPI_FLSHCR_TCSH(3) | XSPI_FLSHCR_TCSS(3); + xspi_writel_offset(x, 0, reg, FLSHCR); + + xspi_writel_offset(x, 0, x->ahb_addr + x->a1_size, SFA1AD); + xspi_writel_offset(x, 0, x->ahb_addr + x->a1_size + x->a2_size, SFA2AD); + + reg = XSPI_SMPR_DLLFSMPFA(7); + xspi_writel_offset(x, 0, reg, SMPR); + + xspi_set_reg_field(x, 0, 0, MCR, MDIS); + + xspi_swreset(x); + + x->selected = -1; + + return ret; +}; + +static int nxp_xspi_probe(struct udevice *bus) +{ + int ret; + struct nxp_xspi *x = dev_get_priv(bus); + + x->devtype_data = + (struct nxp_xspi_devtype_data *)dev_get_driver_data(bus); + + ret = nxp_xspi_default_setup(x); + if (ret) + dev_err(x->dev, "nxp_xspi_default_setup fail %d\n", ret); + + return ret; +}; + +U_BOOT_DRIVER(nxp_xspi) = { + .name = "nxp_xspi", + .id = UCLASS_SPI, + .of_match = nxp_xspi_ids, + .ops = &nxp_xspi_ops, + .of_to_plat = nxp_xspi_of_to_plat, + .priv_auto = sizeof(struct nxp_xspi), + .probe = nxp_xspi_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/spi/nxp_xspi.h b/drivers/spi/nxp_xspi.h new file mode 100644 index 00000000000..31c4147ebe1 --- /dev/null +++ b/drivers/spi/nxp_xspi.h @@ -0,0 +1,703 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2025 NXP + */ + +#ifndef __NXP_XSPI_H +#define __NXP_XSPI_H + +/* XSPI Register defination */ + +#define XSPI_MCR 0x0 + +#define XSPI_MCR_CKN_FA_EN_MASK BIT(26) +#define XSPI_MCR_CKN_FA_EN_SHIFT 26 +#define XSPI_MCR_DQS_FA_SEL_MASK GENMASK(25, 24) +#define XSPI_MCR_DQS_FA_SEL_SHIFT 24 +#define XSPI_MCR_DQS_FA_SEL(x) ((x) << 24) +#define XSPI_MCR_ISD3FA_MASK BIT(17) +#define XSPI_MCR_ISD3FA_SHIFT 17 +#define XSPI_MCR_ISD3FA_MASK BIT(17) +#define XSPI_MCR_ISD3FA_SHIFT 17 +#define XSPI_MCR_ISD2FA_MASK BIT(16) +#define XSPI_MCR_ISD2FA_SHIFT 16 +#define XSPI_MCR_DOZE_MASK BIT(15) +#define XSPI_MCR_DOZE_SHIFT 15 +#define XSPI_MCR_MDIS_MASK BIT(14) +#define XSPI_MCR_MDIS_SHIFT 14 +#define XSPI_MCR_DLPEN_MASK BIT(12) +#define XSPI_MCR_DLPEN_SHIFT 12 +#define XSPI_MCR_CLR_TXF_MASK BIT(11) +#define XSPI_MCR_CLR_TXF_SHIFT 11 +#define XSPI_MCR_CLR_RXF_MASK BIT(10) +#define XSPI_MCR_CLR_RXF_SHIFT 10 +#define XSPI_MCR_IPS_TG_RST_MASK BIT(9) +#define XSPI_MCR_IPS_TG_RST_SHIFT 9 +#define XSPI_MCR_VAR_LAT_EN_MASK BIT(8) +#define XSPI_MCR_VAR_LAT_EN_SHIFT 8 +#define XSPI_MCR_DDR_EN_MASK BIT(7) +#define XSPI_MCR_DDR_EN_SHIFT 7 +#define XSPI_MCR_DQS_EN_MASK BIT(6) +#define XSPI_MCR_DQS_EN_SHIFT 6 +#define XSPI_MCR_DQS_LAT_EN_MASK BIT(5) +#define XSPI_MCR_DQS_LAT_EN_SHIFT 5 +#define XSPI_MCR_DQS_OUT_EN_MASK BIT(4) +#define XSPI_MCR_DQS_OUT_EN_SHIFT 4 +#define XSPI_MCR_END_CFG_MASK GENMASK(3, 2) +#define XSPI_MCR_END_CFG_SHIFT 2 +#define XSPI_MCR_END_CFG(x) ((x) << 2) +#define XSPI_MCR_SWRSTHD_MASK BIT(1) +#define XSPI_MCR_SWRSTHD_SHIFT 1 +#define XSPI_MCR_SWRSTSD_MASK BIT(0) +#define XSPI_MCR_SWRSTSD_SHIFT 0 + +#define XSPI_IPCR 0x8U + +#define XSPI_IPCR_SEQID_MASK GENMASK(27, 24) +#define XSPI_IPCR_SEQID_SHIFT 24 +#define XSPI_IPCR_SEQID(x) ((x) << 24) +#define XSPI_IPCR_IDATSZ_MASK GENMASK(14, 0) +#define XSPI_IPCR_IDATSZ_SHIFT 0 +#define XSPI_IPCR_IDATSZ(x) ((x) << 0) + +#define XSPI_FLSHCR 0xCU + +#define XSPI_FLSHCR_TDH_MASK GENMASK(17, 16) +#define XSPI_FLSHCR_TDH_SHIFT 16 +#define XSPI_FLSHCR_TDH(x) ((x) << 16) +#define XSPI_FLSHCR_TCSH_MASK GENMASK(11, 8) +#define XSPI_FLSHCR_TCSH_SHIFT 8 +#define XSPI_FLSHCR_TCSH(x) ((x) << 8) +#define XSPI_FLSHCR_TCSS_MASK GENMASK(3, 0) +#define XSPI_FLSHCR_TCSS_SHIFT 0 +#define XSPI_FLSHCR_TCSS(x) ((x) << 0) + +#define XSPI_BUF0CR 0x010U + +#define XSPI_BUF0CR_HP_EN_MASK BIT(31) +#define XSPI_BUF0CR_HP_EN_SHIFT 31 +#define XSPI_BUF0CR_SUB_DIV_EN_MASK BIT(30) +#define XSPI_BUF0CR_SUB_DIV_EN_SHIFT 30 +#define XSPI_BUF0CR_SUBBUF2_DIV_MASK GENMASK(29, 27) +#define XSPI_BUF0CR_SUBBUF2_DIV_SHIFT 27 +#define XSPI_BUF0CR_SUBBUF2_DIV(x) ((x) << 27) +#define XSPI_BUF0CR_SUBBUF1_DIV_MASK GENMASK(26, 24) +#define XSPI_BUF0CR_SUBBUF1_DIV_SHIFT 24 +#define XSPI_BUF0CR_SUBBUF1_DIV(x) ((x) << 24) +#define XSPI_BUF0CR_SUBBUF0_DIV_MASK GENMASK(23, 21) +#define XSPI_BUF0CR_SUBBUF0_DIV_SHIFT 21 +#define XSPI_BUF0CR_SUBBUF0_DIV(x) ((x) << 21) +#define XSPI_BUF0CR_ADATSZ_MASK GENMASK(17, 8) +#define XSPI_BUF0CR_ADATSZ_SHIFT 8 +#define XSPI_BUF0CR_ADATSZ(x) ((x) << 8) +#define XSPI_BUF0CR_MSTRID_MASK GENMASK(3, 0) +#define XSPI_BUF0CR_MSTRID_SHIFT 0 +#define XSPI_BUF0CR_MSTRID(x) ((x) << 0) + +#define XSPI_BUF1CR 0x014U +#define XSPI_BUF2CR 0x018U +#define XSPI_BUF3CR 0x1CU + +#define XSPI_BUF3CR_ALLMST_MASK BIT(31) +#define XSPI_BUF3CR_ALLMST_SHIFT 31 +#define XSPI_BUF3CR_SUB_DIV_EN_MASK BIT(30) +#define XSPI_BUF3CR_SUB_DIV_EN_SHIFT 30 +#define XSPI_BUF3CR_SUBBUF2_DIV_MASK GENMASK(29, 27) +#define XSPI_BUF3CR_SUBBUF2_DIV_SHIFT 27 +#define XSPI_BUF3CR_SUBBUF2_DIV(x) ((x) << 27) +#define XSPI_BUF3CR_SUBBUF1_DIV_MASK GENMASK(26, 24) +#define XSPI_BUF3CR_SUBBUF1_DIV_SHIFT 24 +#define XSPI_BUF3CR_SUBBUF1_DIV(x) ((x) << 24) +#define XSPI_BUF3CR_SUBBUF0_DIV_MASK GENMASK(23, 21) +#define XSPI_BUF3CR_SUBBUF0_DIV_SHIFT 21 +#define XSPI_BUF3CR_SUBBUF0_DIV(x) ((x) << 21) +#define XSPI_BUF3CR_ADATSZ_MASK GENMASK(17, 8) +#define XSPI_BUF3CR_ADATSZ_SHIFT 8 +#define XSPI_BUF3CR_ADATSZ(x) ((x) << 8) +#define XSPI_BUF3CR_MSTRID_MASK GENMASK(3, 0) +#define XSPI_BUF3CR_MSTRID_SHIFT 0 +#define XSPI_BUF3CR_MSTRID(x) ((x) << 0) + +#define XSPI_BUF0IND 0x030U + +#define XSPI_BUF0IND_TPINDX_MASK GENMASK(12, 3) +#define XSPI_BUF0IND_TPINDX_SHIFT 3 +#define XSPI_BUF0IND_TPINDX(x) ((x) << 3) + +#define XSPI_BUF1IND 0x034U + +#define XSPI_BUF2IND 0x038U + +#define XSPI_AWRCR 0x50 + +#define XSPI_AWRCR_PPW_WR_DIS_MASK BIT(15) +#define XSPI_AWRCR_PPW_WR_DIS_SHIFT 15 +#define XSPI_AWRCR_PPW_RD_DIS_MASK BIT(14) +#define XSPI_AWRCR_PPW_RD_DIS_SHIFT 14 + +#define XSPI_DLLCRA 0x60U + +#define XSPI_DLLCRA_DLLEN_MASK BIT(31) +#define XSPI_DLLCRA_DLLEN_SHIFT 31 +#define XSPI_DLLCRA_FREQEN_MASK BIT(30) +#define XSPI_DLLCRA_FREQEN_SHIFT 30 +#define XSPI_DLLCRA_DLL_REFCNTR_MASK GENMASK(27, 24) +#define XSPI_DLLCRA_DLL_REFCNTR_SHIFT 24 +#define XSPI_DLLCRA_DLL_REFCNTR(x) ((x) << 24) +#define XSPI_DLLCRA_DLLRES_MASK GENMASK(23, 20) +#define XSPI_DLLCRA_DLLRES_SHIFT 20 +#define XSPI_DLLCRA_DLLRES(x) ((x) << 20) +#define XSPI_DLLCRA_SLV_FINE_OFFSET_MASK GENMASK(19, 16) +#define XSPI_DLLCRA_SLV_FINE_OFFSET_SHIFT 16 +#define XSPI_DLLCRA_SLV_FINE_OFFSET(x) ((x) << 16) +#define XSPI_DLLCRA_SLV_DLY_OFFSET_MASK GENMASK(14, 12) +#define XSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT 12 +#define XSPI_DLLCRA_SLV_DLY_OFFSET(x) ((x) << 12) +#define XSPI_DLLCRA_SLV_DLY_COARSE_MASK GENMASK(11, 8) +#define XSPI_DLLCRA_SLV_DLY_COARSE_SHIFT 8 +#define XSPI_DLLCRA_SLV_DLY_COARSE(x) ((x) << 8) +#define XSPI_DLLCRA_SLV_DLY_FINE_MASK GENMASK(7, 5) +#define XSPI_DLLCRA_SLV_DLY_FINE_SHIFT 5 +#define XSPI_DLLCRA_SLV_DLY_FINE(x) ((x) << 5) +#define XSPI_DLLCRA_DLL_CDL8_MASK BIT(4) +#define XSPI_DLLCRA_DLL_CDL8_SHIFT 4 +#define XSPI_DLLCRA_SLAVE_AUTO_UPDT_MASK BIT(3) +#define XSPI_DLLCRA_SLAVE_AUTO_UPDT_SHIFT 3 +#define XSPI_DLLCRA_SLV_EN_MASK BIT(2) +#define XSPI_DLLCRA_SLV_EN_SHIFT 2 +#define XSPI_DLLCRA_SLV_DLL_BYPASS_MASK BIT(1) +#define XSPI_DLLCRA_SLV_DLL_BYPASS_SHIFT 1 +#define XSPI_DLLCRA_SLV_UPD_MASK BIT(0) +#define XSPI_DLLCRA_SLV_UPD_SHIFT 0 + +#define XSPI_SFACR 0x104U + +#define XSPI_SFACR_FORCE_A10_MASK BIT(22) +#define XSPI_SFACR_FORCE_A10_SHIFT 22 +#define XSPI_SFACR_WA_4B_EN_MASK BIT(21) +#define XSPI_SFACR_WA_4B_EN_SHIFT 21 +#define XSPI_SFACR_CAS_INTRLVD_MASK BIT(20) +#define XSPI_SFACR_CAS_INTRLVD_SHIFT 20 +#define XSPI_SFACR_RX_BP_EN_MASK BIT(18) +#define XSPI_SFACR_RX_BP_EN_SHIFT 18 +#define XSPI_SFACR_BYTE_SWAP_MASK BIT(17) +#define XSPI_SFACR_BYTE_SWAP_SHIFT 17 +#define XSPI_SFACR_WA_MASK BIT(16) +#define XSPI_SFACR_WA_SHIFT 16 +#define XSPI_SFACR_PPWB_MASK GENMASK(12, 8) +#define XSPI_SFACR_PPWB_SHIFT 8 +#define XSPI_SFACR_PPWB(x) ((x) << 8) +#define XSPI_SFACR_CAS_MASK GENMASK(3, 0) +#define XSPI_SFACR_CAS_SHIFT 0 +#define XSPI_SFACR_CAS(x) ((x) << 0) + +#define XSPI_SFAR 0x100U + +#define XSPI_SFAR_SFADR_MASK GENMASK(31, 0) +#define XSPI_SFAR_SFADR_SHIFT 0 +#define XSPI_SFAR_SFADR(x) ((x) << 0) + +#define XSPI_SMPR 0x108U + +#define XSPI_SMPR_DLLFSMPFA_MASK GENMASK(26, 24) +#define XSPI_SMPR_DLLFSMPFA_SHIFT 24 +#define XSPI_SMPR_DLLFSMPFA(x) ((x) << 24) +#define XSPI_SMPR_FSDLY_MASK BIT(6) +#define XSPI_SMPR_FSDLY_SHIFT 6 +#define XSPI_SMPR_FSPHS_MASK BIT(5) +#define XSPI_SMPR_FSPHS_SHIFT 5 + +#define XSPI_RBSR 0x10CU + +#define XSPI_RBSR_RDCTR_MASK GENMASK(31, 16) +#define XSPI_RBSR_RDCTR_SHIFT 16 +#define XSPI_RBSR_RDCTR(x) ((x) << 16) +#define XSPI_RBSR_RDBFL_MASK GENMASK(8, 0) +#define XSPI_RBSR_RDBFL_SHIFT 0 +#define XSPI_RBSR_RDBFL(x) ((x) << 0) + +#define XSPI_RBCT 0x110U + +#define XSPI_RBCT_WMRK_MASK GENMASK(8, 0) +#define XSPI_RBCT_WMRK_SHIFT 0 +#define XSPI_RBCT_WMRK(x) ((x) << 0) + +#define XSPI_DLLSR 0x12CU + +#define XSPI_DLLSR_DLLA_LOCK_MASK BIT(15) +#define XSPI_DLLSR_DLLA_LOCK_SHIFT 15 +#define XSPI_DLLSR_SLVA_LOCK_MASK BIT(14) +#define XSPI_DLLSR_SLVA_LOCK_SHIFT 14 +#define XSPI_DLLSR_DLLA_RANGE_ERR_MASK BIT(13) +#define XSPI_DLLSR_DLLA_RANGE_ERR_SHIFT 13 +#define XSPI_DLLSR_DLLA_FINE_UNDERFLOW_MASK BIT(12) +#define XSPI_DLLSR_DLLA_FINE_UNDERFLOW_SHIFT 12 +#define XSPI_DLLSR_DLLA_SLV_FINE_VAL_MASK GENMASK(7, 4) +#define XSPI_DLLSR_DLLA_SLV_FINE_VAL_SHIFT 4 +#define XSPI_DLLSR_DLLA_SLV_FINE_VAL(x) ((x) << 4) +#define XSPI_DLLSR_DLLA_SLV_COARSE_VAL_MASK GENMASK(3, 0) +#define XSPI_DLLSR_DLLA_SLV_COARSE_VAL_SHIFT 0 +#define XSPI_DLLSR_DLLA_SLV_COARSE_VAL(x) ((x) << 0) + +#define XSPI_DLCR 0x130U + +#define XSPI_DLCR_DL_NONDLP_FLSH_MASK BIT(24) +#define XSPI_DLCR_DL_NONDLP_FLSH_SHIFT 24 +#define XSPI_DLCR_DLP_SEL_FA_MASK GENMASK(15, 14) +#define XSPI_DLCR_DLP_SEL_FA_SHIFT 14 +#define XSPI_DLCR_DLP_SEL_FA(x) ((x) << 14) + +#define XSPI_TBSR 0x150U + +#define XSPI_TBSR_TRCTR_MASK GENMASK(31, 16) +#define XSPI_TBSR_TRCTR_SHIFT 16 +#define XSPI_TBSR_TRCTR(x) ((x) << 16) +#define XSPI_TBSR_TRBFL_MASK GENMASK(8, 0) +#define XSPI_TBSR_TRBFL_SHIFT 0 +#define XSPI_TBSR_TRBFL(x) ((x) << 0) + +#define XSPI_TBDR 0x154U + +#define XSPI_TBDR_TXDATA_MASK GENMASK(31, 0) +#define XSPI_TBDR_TXDATA_SHIFT 0 +#define XSPI_TBDR_TXDATA(x) ((x) << 0) + +#define XSPI_TBCT 0x158U + +#define XSPI_TBCT_WMRK_MASK GENMASK(7, 0) +#define XSPI_TBCT_WMRK_SHIFT 0 +#define XSPI_TBCT_WMRK(x) ((x) << 0) + +#define XSPI_SR 0x15CU + +#define XSPI_SR_TXFULL_MASK BIT(27) +#define XSPI_SR_TXFULL_SHIFT 27 +#define XSPI_SR_TXDMA_MASK BIT(26) +#define XSPI_SR_TXDMA_SHIFT 26 +#define XSPI_SR_TXWA_MASK BIT(25) +#define XSPI_SR_TXWA_SHIFT 25 +#define XSPI_SR_TXNE_MASK BIT(24) +#define XSPI_SR_TXNE_SHIFT 24 +#define XSPI_SR_RXDMA_MASK BIT(23) +#define XSPI_SR_RXDMA_SHIFT 23 +#define XSPI_SR_ARB_STATE_MASK GENMASK(22, 20) +#define XSPI_SR_ARB_STATE_SHIFT 20 +#define XSPI_SR_ARB_STATE(x) ((x) << 20) +#define XSPI_SR_RXFULL_MASK BIT(19) +#define XSPI_SR_RXFULL_SHIFT 19 +#define XSPI_SR_RXWE_MASK BIT(16) +#define XSPI_SR_RXWE_SHIFT 16 +#define XSPI_SR_ARB_LCK_MASK BIT(15) +#define XSPI_SR_ARB_LCK_SHIFT 15 +#define XSPI_SR_AHBnFUL_MASK GENMASK(14, 11) +#define XSPI_SR_AHBnFUL_SHIFT 11 +#define XSPI_SR_AHBnFUL(x) ((x) << 11) +#define XSPI_SR_AHBnNE_MASK GENMASK(10, 7) +#define XSPI_SR_AHBnNE_SHIFT 7 +#define XSPI_SR_AHBnNE(x) ((x) << 7) +#define XSPI_SR_AHBTRN_MASK BIT(6) +#define XSPI_SR_AHBTRN_SHIFT 6 +#define XSPI_SR_AWRACC_MASK BIT(4) +#define XSPI_SR_AWRACC_SHIFT 4 +#define XSPI_SR_AHB_ACC_MASK BIT(2) +#define XSPI_SR_AHB_ACC_SHIFT 2 +#define XSPI_SR_IP_ACC_MASK BIT(1) +#define XSPI_SR_IP_ACC_SHIFT 1 +#define XSPI_SR_BUSY_MASK BIT(0) +#define XSPI_SR_BUSY_SHIFT 0 + +#define XSPI_FR 0x160U + +#define XSPI_FR_DLPFF_MASK BIT(31) +#define XSPI_FR_DLPFF_SHIFT 31 +#define XSPI_FR_DLLABRT_MASK BIT(28) +#define XSPI_FR_DLLABRT_SHIFT 28 +#define XSPI_FR_TBFF_MASK BIT(27) +#define XSPI_FR_TBFF_SHIFT 27 +#define XSPI_FR_TBUF_MASK BIT(26) +#define XSPI_FR_TBUF_SHIFT 26 +#define XSPI_FR_DLLUNLCK_MASK BIT(24) +#define XSPI_FR_DLLUNLCK_SHIFT 24 +#define XSPI_FR_ILLINE_MASK BIT(23) +#define XSPI_FR_ILLINE_SHIFT 23 +#define XSPI_FR_RBOF_MASK BIT(17) +#define XSPI_FR_RBOF_SHIFT 17 +#define XSPI_FR_RBDF_MASK BIT(16) +#define XSPI_FR_RBDF_SHIFT 16 +#define XSPI_FR_AAEF_MASK BIT(15) +#define XSPI_FR_AAEF_SHIFT 15 +#define XSPI_FR_AITEF_MASK BIT(14) +#define XSPI_FR_AITEF_SHIFT 14 +#define XSPI_FR_AIBSEF_MASK BIT(13) +#define XSPI_FR_AIBSEF_SHIFT 13 +#define XSPI_FR_ABOF_MASK BIT(12) +#define XSPI_FR_ABOF_SHIFT 12 +#define XSPI_FR_CRCAEF_MASK BIT(10) +#define XSPI_FR_CRCAEF_SHIFT 10 +#define XSPI_FR_PPWF_MASK BIT(8) +#define XSPI_FR_PPWF_SHIFT 8 +#define XSPI_FR_IPIEF_MASK BIT(6) +#define XSPI_FR_IPIEF_SHIFT 6 +#define XSPI_FR_IPEDERR_MASK BIT(5) +#define XSPI_FR_IPEDERR_SHIFT 5 +#define XSPI_FR_PERFOVF_MASK BIT(2) +#define XSPI_FR_PERFOVF_SHIFT 2 +#define XSPI_FR_RDADDR_MASK BIT(1) +#define XSPI_FR_RDADDR_SHIFT 1 +#define XSPI_FR_TFF_MASK BIT(0) +#define XSPI_FR_TFF_SHIFT 0 + +#define XSPI_SFA1AD 0x180U + +#define XSPI_SFA1AD_TPAD_MASK GENMASK(31, 10) +#define XSPI_SFA1AD_TPAD_SHIFT 10 +#define XSPI_SFA1AD_TPAD(x) ((x) << 10) + +#define XSPI_SFA2AD 0x184U + +#define XSPI_DLPR 0x190U + +#define XSPI_DLPR_DLPV_MASK GENMASK(31, 0) +#define XSPI_DLPR_DLPV_SHIFT 0 +#define XSPI_DLPR_DLPV(x) ((x) << 0) + +#define XSPI_RBDR 0x200U + +#define XSPI_LUTKEY 0x300U + +#define XSPI_LCKCR 0x304U + +#define XSPI_LCKCR_UNLOCK_MASK BIT(1) +#define XSPI_LCKCR_UNLOCK_SHIFT 1 +#define XSPI_LCKCR_LOCK_MASK BIT(0) +#define XSPI_LCKCR_LOCK_SHIFT 0 + +#define XSPI_LUT 0x310 + +#define XSPI_BFGENCR 0x20 + +#define XSPI_BFGENCR_SEQID_WR_MASK GENMASK(31, 28) +#define XSPI_BFGENCR_SEQID_WR_SHIFT 28 +#define XSPI_BFGENCR_SEQID_WR(x) ((x) << 28) +#define XSPI_BFGENCR_ALIGN_MASK GENMASK(23, 22) +#define XSPI_BFGENCR_ALIGN_SHIFT 22 +#define XSPI_BFGENCR_ALIGN(x) ((x) << 22) +#define XSPI_BFGENCR_WR_FLUSH_EN_MASK BIT(21) +#define XSPI_BFGENCR_WR_FLUSH_EN_SHIFT 21 +#define XSPI_BFGENCR_PPWF_CLR_MASK BIT(20) +#define XSPI_BFGENCR_PPWF_CLR_SHIFT 20 +#define XSPI_BFGENCR_SEQID_WR_EN_MASK BIT(17) +#define XSPI_BFGENCR_SEQID_WR_EN_SHIFT 17 +#define XSPI_BFGENCR_SEQID_MASK GENMASK(15, 12) +#define XSPI_BFGENCR_SEQID_SHIFT 12 +#define XSPI_BFGENCR_SEQID(x) ((x) << 12) +#define XSPI_BFGENCR_AHBSSIZE_MASK GENMASK(10, 9) +#define XSPI_BFGENCR_AHBSSIZE_SHIFT 9 +#define XSPI_BFGENCR_AHBSSIZE(x) ((x) << 9) +#define XSPI_BFGENCR_SPLITEN_MASK BIT(8) +#define XSPI_BFGENCR_SPLITEN_SHIFT 8 +#define XSPI_BFGENCR_SEQID_RDSR_MASK GENMASK(3, 0) +#define XSPI_BFGENCR_SEQID_RDSR_SHIFT 0 +#define XSPI_BFGENCR_SEQID_RDSR(x) ((x) << 0) + +#define XSPI_FRAD0_WORD2 0x808U + +#define XSPI_FRAD0_WORD2_EALO_MASK GENMASK(29, 24) +#define XSPI_FRAD0_WORD2_EALO_SHIFT 24 +#define XSPI_FRAD0_WORD2_EALO(x) ((x) << 24) +#define XSPI_FRAD0_WORD2_MD4ACP_MASK GENMASK(14, 12) +#define XSPI_FRAD0_WORD2_MD4ACP_SHIFT 12 +#define XSPI_FRAD0_WORD2_MD4ACP(x) ((x) << 12) +#define XSPI_FRAD0_WORD2_MD3ACP_MASK GENMASK(11, 9) +#define XSPI_FRAD0_WORD2_MD3ACP_SHIFT 9 +#define XSPI_FRAD0_WORD2_MD3ACP(x) ((x) << 9) +#define XSPI_FRAD0_WORD2_MD2ACP_MASK GENMASK(8, 6) +#define XSPI_FRAD0_WORD2_MD2ACP_SHIFT 6 +#define XSPI_FRAD0_WORD2_MD2ACP(x) ((x) << 6) +#define XSPI_FRAD0_WORD2_MD1ACP_MASK GENMASK(5, 3) +#define XSPI_FRAD0_WORD2_MD1ACP_SHIFT 3 +#define XSPI_FRAD0_WORD2_MD1ACP(x) ((x) << 3) +#define XSPI_FRAD0_WORD2_MD0ACP_MASK GENMASK(2, 0) +#define XSPI_FRAD0_WORD2_MD0ACP_SHIFT 0 +#define XSPI_FRAD0_WORD2_MD0ACP(x) ((x) << 0) + +#define XSPI_FRAD1_WORD2 0x828U + +#define XSPI_FRAD2_WORD2 0x848U + +#define XSPI_FRAD3_WORD2 0x868U + +#define XSPI_FRAD4_WORD2 0x888U + +#define XSPI_FRAD5_WORD2 0x8A8U + +#define XSPI_FRAD6_WORD2 0x8C8U + +#define XSPI_FRAD7_WORD2 0x8E8U + +#define XSPI_FRAD8_WORD2 0x988U + +#define XSPI_FRAD9_WORD2 0x9A8U + +#define XSPI_FRAD10_WORD2 0x9C8U + +#define XSPI_FRAD11_WORD2 0x9E8U + +#define XSPI_FRAD12_WORD2 0xA08U + +#define XSPI_FRAD13_WORD2 0xA28U + +#define XSPI_FRAD14_WORD2 0xA48U + +#define XSPI_FRAD15_WORD2 0xA68U + +#define XSPI_FRAD0_WORD3 0x80CU + +#define XSPI_FRAD0_WORD3_VLD_MASK BIT(31) +#define XSPI_FRAD0_WORD3_VLD_SHIFT 31 +#define XSPI_FRAD0_WORD3_LOCK_MASK GENMASK(30, 29) +#define XSPI_FRAD0_WORD3_LOCK_SHIFT 29 +#define XSPI_FRAD0_WORD3_LOCK(x) ((x) << 29) +#define XSPI_FRAD0_WORD3_EAL_MASK GENMASK(25, 24) +#define XSPI_FRAD0_WORD3_EAL_SHIFT 24 +#define XSPI_FRAD0_WORD3_EAL(x) ((x) << 24) + +#define XSPI_FRAD1_WORD3 0x82CU + +#define XSPI_FRAD2_WORD3 0x84CU + +#define XSPI_FRAD3_WORD3 0x86CU + +#define XSPI_FRAD4_WORD3 0x88CU + +#define XSPI_FRAD5_WORD3 0x8ACU + +#define XSPI_FRAD6_WORD3 0x8CCU + +#define XSPI_FRAD7_WORD3 0x8ECU + +#define XSPI_FRAD8_WORD3 0x98CU + +#define XSPI_FRAD9_WORD3 0x9ACU + +#define XSPI_FRAD10_WORD3 0x9CCU + +#define XSPI_FRAD11_WORD3 0x9ECU + +#define XSPI_FRAD12_WORD3 0xA0CU + +#define XSPI_FRAD13_WORD3 0xA2CU + +#define XSPI_FRAD14_WORD3 0xA4CU + +#define XSPI_FRAD15_WORD3 0xA6CU + +#define XSPI_TG0MDAD 0x900U + +#define XSPI_TG0MDAD_VLD_MASK BIT(31) +#define XSPI_TG0MDAD_VLD_SHIFT 31 +#define XSPI_TG0MDAD_LCK_MASK BIT(29) +#define XSPI_TG0MDAD_LCK_SHIFT 29 +#define XSPI_TG0MDAD_SA_MASK GENMASK(15, 14) +#define XSPI_TG0MDAD_SA_SHIFT 14 +#define XSPI_TG0MDAD_SA(x) ((x) << 14) +#define XSPI_TG0MDAD_MASKTYPE_MASK BIT(12) +#define XSPI_TG0MDAD_MASKTYPE_SHIFT 12 +#define XSPI_TG0MDAD_MASK_MASK GENMASK(11, 6) +#define XSPI_TG0MDAD_MASK_SHIFT 6 +#define XSPI_TG0MDAD_MASK(x) ((x) << 6) +#define XSPI_TG0MDAD_MIDMATCH_MASK GENMASK(5, 0) +#define XSPI_TG0MDAD_MIDMATCH_SHIFT 0 +#define XSPI_TG0MDAD_MIDMATCH(x) ((x) << 0) + +#define XSPI_TG1MDAD 0x910U + +#define XSPI_MGC 0x920 + +#define XSPI_MGC_GVLD_MASK BIT(31) +#define XSPI_MGC_GVLD_SHIFT 31 +#define XSPI_MGC_GVLDMDAD_MASK BIT(29) +#define XSPI_MGC_GVLDMDAD_SHIFT 29 +#define XSPI_MGC_GVLDFRAD_MASK BIT(27) +#define XSPI_MGC_GVLDFRAD_SHIFT 27 +#define XSPI_MGC_TG1_FIX_PRIO_MASK BIT(16) +#define XSPI_MGC_TG1_FIX_PRIO_SHIFT 16 +#define XSPI_MGC_GCLCK_MASK GENMASK(11, 10) +#define XSPI_MGC_GCLCK_SHIFT 10 +#define XSPI_MGC_GCLCK(x) ((x) << 10) +#define XSPI_MGC_GCLCKMID_MASK GENMASK(5, 0) +#define XSPI_MGC_GCLCKMID_SHIFT 0 +#define XSPI_MGC_GCLCKMID(x) ((x) << 0) + +#define XSPI_MTO 0x928 + +#define XSPI_MTO_SFP_ACC_TO_MASK GENMASK(31, 0) +#define XSPI_MTO_SFP_ACC_TO_SHIFT 0 +#define XSPI_MTO_SFP_ACC_TO(x) ((x) << 0) + +#define XSPI_TG2MDAD_EXT 0x940U + +#define XSPI_TG2MDAD_EXT_VLD_MASK BIT(31) +#define XSPI_TG2MDAD_EXT_VLD_SHIFT 31 +#define XSPI_TG2MDAD_EXT_LCK_MASK BIT(29) +#define XSPI_TG2MDAD_EXT_LCK_SHIFT 29 +#define XSPI_TG2MDAD_EXT_SA_MASK GENMASK(15, 14) +#define XSPI_TG2MDAD_EXT_SA_SHIFT 14 +#define XSPI_TG2MDAD_EXT_SA(x) ((x) << 14) +#define XSPI_TG2MDAD_EXT_MASKTYPE_MASK BIT(12) +#define XSPI_TG2MDAD_EXT_MASKTYPE_SHIFT 12 +#define XSPI_TG2MDAD_EXT_MASK_MASK GENMASK(11, 6) +#define XSPI_TG2MDAD_EXT_MASK_SHIFT 6 +#define XSPI_TG2MDAD_EXT_MASK(x) ((x) << 6) +#define XSPI_TG2MDAD_EXT_MIDMATCH_MASK GENMASK(5, 0) +#define XSPI_TG2MDAD_EXT_MIDMATCH_SHIFT 0 +#define XSPI_TG2MDAD_EXT_MIDMATCH(x) ((x) << 0) + +#define XSPI_TG3MDAD_EXT 0x944U + +#define XSPI_TG4MDAD_EXT 0x948U + +#define XSPI_SFP_TG_IPCR 0x958U + +#define XSPI_SFP_TG_IPCR_SEQID_MASK GENMASK(27, 24) +#define XSPI_SFP_TG_IPCR_SEQID_SHIFT 24 +#define XSPI_SFP_TG_IPCR_SEQID(x) ((x) << 24) +#define XSPI_SFP_TG_IPCR_ARB_UNLOCK_MASK BIT(23) +#define XSPI_SFP_TG_IPCR_ARB_UNLOCK_SHIFT 23 +#define XSPI_SFP_TG_IPCR_ARB_LOCK_MASK BIT(22) +#define XSPI_SFP_TG_IPCR_ARB_LOCK_SHIFT 22 +#define XSPI_SFP_TG_IPCR_IDATSZ_MASK GENMASK(15, 0) +#define XSPI_SFP_TG_IPCR_IDATSZ_SHIFT 0 +#define XSPI_SFP_TG_IPCR_IDATSZ(x) ((x) << 0) + +#define XSPI_SFP_TG_SFAR 0x95CU + +/* XSPI Register defination end */ + +/* xspi data structure */ +struct nxp_xspi_devtype_data { + unsigned int rxfifo; + unsigned int rx_buf_size; + unsigned int txfifo; + unsigned int ahb_buf_size; + unsigned int quirks; +}; + +struct nxp_xspi { + struct udevice *dev; + u32 iobase; + u32 ahb_addr; + u32 a1_size; + u32 a2_size; + struct { + bool gmid; + u8 env; + } config; + struct clk clk; + struct nxp_xspi_devtype_data *devtype_data; + unsigned long support_max_rate; + int selected; + bool dtr; +}; + +/* xspi data structure end */ + +/********* XSPI CMD definitions ***************************/ +#define CMD_SDR 0x01U +#define CMD_DDR 0x11U +#define RADDR_SDR 0x02U +#define RADDR_DDR 0x0AU +#define CADDR_SDR 0x12U +#define CADDR_DDR 0x13U +#define MODE2_SDR 0x05U +#define MODE2_DDR 0x0CU +#define MODE4_SDR 0x06U +#define MODE4_DDR 0x0DU +#define MODE8_SDR 0x04U +#define MODE8_DDR 0x0BU +#define WRITE_SDR 0x08U +#define WRITE_DDR 0x0FU +#define READ_SDR 0x07U +#define READ_DDR 0x0EU +#define DATA_LEARN 0x10U +#define DUMMY_CYCLE 0x03U +#define JMP_ON_CS 0x09U +#define JMP_TO_SEQ 0x14U +#define CMD_STOP 0U + +/********* XSPI PAD definitions ************/ +#define XSPI_1PAD 0U +#define XSPI_2PAD 1U +#define XSPI_4PAD 2U +#define XSPI_8PAD 3U + +#define DEFAULT_XMIT_SIZE 0x40U + +#define ENV_ADDR_SIZE SZ_64K + +#define XSPI_LUT_KEY_VAL 0x5AF05AF0UL + +#define xspi_get_reg_field(x, env, reg_name, field_name) \ + ({ \ + u32 reg; \ + reg = xspi_readl_offset(x, env, reg_name); \ + reg &= XSPI_##reg_name##_##field_name##_MASK; \ + reg = reg >> XSPI_##reg_name##_##field_name##_SHIFT; \ + reg; \ + }) + +#define xspi_set_reg_field(x, env, val, reg_name, field_name) \ + do { \ + u32 reg; \ + reg = xspi_readl_offset(x, env, reg_name); \ + reg &= ~XSPI_##reg_name##_##field_name##_MASK; \ + reg |= (val << XSPI_##reg_name##_##field_name##_SHIFT); \ + xspi_writel_offset(x, env, reg, reg_name); \ + } while (0) + +#define xspi_writel_offset(x, env, val, offset) \ + do { \ + out_le32((void __iomem *)(uintptr_t)x->iobase + \ + (env * ENV_ADDR_SIZE) + XSPI_##offset, val); \ + } while (0) + +#define xspi_readl_offset(x, env, offset) ({ \ + u32 reg; \ + reg = in_le32((void __iomem *)(uintptr_t)x->iobase + \ + (env * ENV_ADDR_SIZE) + XSPI_##offset); \ + reg; \ +}) + +#define POLL_TOUT 5000 + +#define CMD_LUT_FOR_IP_CMD 1 +#define CMD_LUT_FOR_AHB_CMD 0 + +/* + * Calculate number of required PAD bits for LUT register. + * + * The pad stands for the number of IO lines [0:7]. + * For example, the octal read needs eight IO lines, + * so you should use LUT_PAD(8). This macro + * returns 3 i.e. use eight (2^3) IP lines for read. + */ +#define LUT_PAD(x) (fls(x) - 1) + +/* + * Macro for constructing the LUT entries with the following + * register layout: + * + * --------------------------------------------------- + * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | + * --------------------------------------------------- + */ +#define PAD_SHIFT 8 +#define INSTR_SHIFT 10 +#define OPRND_SHIFT 16 + +/* Macros for constructing the LUT register. */ +#define LUT_DEF(idx, ins, pad, opr) \ + ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \ + (opr)) << (((idx) % 2) * OPRND_SHIFT)) + +#endif diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index 35bd8766097..b2d115aded4 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -20,13 +20,10 @@ #include <spi.h> #include <time.h> #include <malloc.h> -#include <asm/global_data.h> #include <asm/io.h> #include <linux/bitops.h> #include <omap3_spi.h> -DECLARE_GLOBAL_DATA_PTR; - struct omap2_mcspi_platform_config { unsigned int regs_offset; }; diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c index 50bd7be5640..e97352000f8 100644 --- a/drivers/spi/soft_spi.c +++ b/drivers/spi/soft_spi.c @@ -173,7 +173,8 @@ static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen, soft_spi_scl(dev, !cidle); if ((txrx & SPI_MASTER_NO_TX) == 0) soft_spi_sda(dev, !!(tmpdout & 0x80)); - udelay(plat->spi_delay_us); + if (plat->spi_delay_us) + udelay(plat->spi_delay_us); /* * sample bit @@ -190,7 +191,8 @@ static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen, &plat->mosi : &plat->miso); tmpdout <<= 1; - udelay(plat->spi_delay_us); + if (plat->spi_delay_us) + udelay(plat->spi_delay_us); /* * drive bit diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c index e00532a371b..0bdc112d249 100644 --- a/drivers/spi/spi-sunxi.c +++ b/drivers/spi/spi-sunxi.c @@ -26,7 +26,6 @@ #include <fdt_support.h> #include <reset.h> #include <wait_bit.h> -#include <asm/global_data.h> #include <dm/device_compat.h> #include <linux/bitops.h> @@ -35,8 +34,6 @@ #include <linux/iopoll.h> -DECLARE_GLOBAL_DATA_PTR; - /* sun4i spi registers */ #define SUN4I_RXDATA_REG 0x00 #define SUN4I_TXDATA_REG 0x04 diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c index a3c0ad17121..66c97da610b 100644 --- a/drivers/spi/spi-synquacer.c +++ b/drivers/spi/spi-synquacer.c @@ -99,8 +99,6 @@ #define TXBIT 1 #define RXBIT 2 -DECLARE_GLOBAL_DATA_PTR; - struct synquacer_spi_plat { void __iomem *base; bool aces, rtm; diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 49b584c648d..6b7ad47c22d 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -12,14 +12,11 @@ #include <spi.h> #include <spi-mem.h> #include <dm/device_compat.h> -#include <asm/global_data.h> #include <dm/device-internal.h> #include <dm/uclass-internal.h> #include <dm/lists.h> #include <dm/util.h> -DECLARE_GLOBAL_DATA_PTR; - #define SPI_DEFAULT_SPEED_HZ 100000 static int spi_set_speed_mode(struct udevice *bus, int speed, int mode) @@ -180,11 +177,76 @@ int spi_write_then_read(struct spi_slave *slave, const u8 *opcode, static int spi_child_post_bind(struct udevice *dev) { struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev); + int mode = 0; + int value; + int ret; if (!dev_has_ofnode(dev)) return 0; - return spi_slave_of_to_plat(dev, plat); + if (CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)) { + ret = dev_read_u32_array(dev, "reg", plat->cs, SPI_CS_CNT_MAX); + if (ret && ret != -EOVERFLOW && ret != -FDT_ERR_BADLAYOUT) { + dev_err(dev, "has no valid 'reg' property (%d)\n", ret); + return ret; + } + } + + plat->cs[0] = dev_read_u32_default(dev, "reg", -1); + + plat->max_hz = dev_read_u32_default(dev, "spi-max-frequency", + SPI_DEFAULT_SPEED_HZ); + if (dev_read_bool(dev, "spi-cpol")) + mode |= SPI_CPOL; + if (dev_read_bool(dev, "spi-cpha")) + mode |= SPI_CPHA; + if (dev_read_bool(dev, "spi-cs-high")) + mode |= SPI_CS_HIGH; + if (dev_read_bool(dev, "spi-3wire")) + mode |= SPI_3WIRE; + if (dev_read_bool(dev, "spi-half-duplex")) + mode |= SPI_PREAMBLE; + + /* Device DUAL/QUAD mode */ + value = dev_read_u32_default(dev, "spi-tx-bus-width", 1); + switch (value) { + case 1: + break; + case 2: + mode |= SPI_TX_DUAL; + break; + case 4: + mode |= SPI_TX_QUAD; + break; + case 8: + mode |= SPI_TX_OCTAL; + break; + default: + warn_non_xpl("spi-tx-bus-width %d not supported\n", value); + break; + } + + value = dev_read_u32_default(dev, "spi-rx-bus-width", 1); + switch (value) { + case 1: + break; + case 2: + mode |= SPI_RX_DUAL; + break; + case 4: + mode |= SPI_RX_QUAD; + break; + case 8: + mode |= SPI_RX_OCTAL; + break; + default: + warn_non_xpl("spi-rx-bus-width %d not supported\n", value); + break; + } + + plat->mode = mode; + + return 0; } #endif @@ -511,81 +573,6 @@ void spi_free_slave(struct spi_slave *slave) device_remove(slave->dev, DM_REMOVE_NORMAL); } -int spi_slave_of_to_plat(struct udevice *dev, struct dm_spi_slave_plat *plat) -{ - int mode = 0; - int value; - -#if CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL) - int ret; - - ret = dev_read_u32_array(dev, "reg", plat->cs, SPI_CS_CNT_MAX); - - if (ret == -EOVERFLOW || ret == -FDT_ERR_BADLAYOUT) { - dev_read_u32(dev, "reg", &plat->cs[0]); - } else { - dev_err(dev, "has no valid 'reg' property (%d)\n", ret); - return ret; - } -#else - plat->cs[0] = dev_read_u32_default(dev, "reg", -1); -#endif - - plat->max_hz = dev_read_u32_default(dev, "spi-max-frequency", - SPI_DEFAULT_SPEED_HZ); - if (dev_read_bool(dev, "spi-cpol")) - mode |= SPI_CPOL; - if (dev_read_bool(dev, "spi-cpha")) - mode |= SPI_CPHA; - if (dev_read_bool(dev, "spi-cs-high")) - mode |= SPI_CS_HIGH; - if (dev_read_bool(dev, "spi-3wire")) - mode |= SPI_3WIRE; - if (dev_read_bool(dev, "spi-half-duplex")) - mode |= SPI_PREAMBLE; - - /* Device DUAL/QUAD mode */ - value = dev_read_u32_default(dev, "spi-tx-bus-width", 1); - switch (value) { - case 1: - break; - case 2: - mode |= SPI_TX_DUAL; - break; - case 4: - mode |= SPI_TX_QUAD; - break; - case 8: - mode |= SPI_TX_OCTAL; - break; - default: - warn_non_xpl("spi-tx-bus-width %d not supported\n", value); - break; - } - - value = dev_read_u32_default(dev, "spi-rx-bus-width", 1); - switch (value) { - case 1: - break; - case 2: - mode |= SPI_RX_DUAL; - break; - case 4: - mode |= SPI_RX_QUAD; - break; - case 8: - mode |= SPI_RX_OCTAL; - break; - default: - warn_non_xpl("spi-rx-bus-width %d not supported\n", value); - break; - } - - plat->mode = mode; - - return 0; -} - UCLASS_DRIVER(spi) = { .id = UCLASS_SPI, .name = "spi", diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c index b969a7993d4..0f77fbc8d41 100644 --- a/drivers/spi/tegra210_qspi.c +++ b/drivers/spi/tegra210_qspi.c @@ -9,7 +9,6 @@ #include <dm.h> #include <log.h> #include <time.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch-tegra/clk_rst.h> @@ -19,8 +18,6 @@ #include <linux/delay.h> #include "tegra_spi.h" -DECLARE_GLOBAL_DATA_PTR; - /* COMMAND1 */ #define QSPI_CMD1_GO BIT(31) #define QSPI_CMD1_M_S BIT(30) diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c index f3cd98c3db8..b89dd0b406b 100644 --- a/drivers/spmi/spmi-msm.c +++ b/drivers/spmi/spmi-msm.c @@ -10,13 +10,10 @@ #include <dm.h> #include <errno.h> #include <fdtdec.h> -#include <asm/global_data.h> #include <asm/io.h> #include <dm/device_compat.h> #include <spmi/spmi.h> -DECLARE_GLOBAL_DATA_PTR; - /* PMIC Arbiter configuration registers */ #define PMIC_ARB_VERSION 0x0000 #define PMIC_ARB_VERSION_V2_MIN 0x20010000 diff --git a/drivers/sysinfo/smbios.c b/drivers/sysinfo/smbios.c index 99104274f72..ff5873c940e 100644 --- a/drivers/sysinfo/smbios.c +++ b/drivers/sysinfo/smbios.c @@ -24,6 +24,7 @@ struct sysinfo_plat_priv { struct smbios_type7 t7[SYSINFO_CACHE_LVL_MAX]; u16 cache_handles[SYSINFO_CACHE_LVL_MAX]; u8 cache_level; + u16 marray_handles[SYSINFO_MEM_HANDLE_MAX]; }; static void smbios_cache_info_dump(struct smbios_type7 *cache_info) @@ -165,6 +166,10 @@ static int sysinfo_plat_get_data(struct udevice *dev, int id, void **buf, *buf = &priv->cache_handles[0]; *size = sizeof(priv->cache_handles); break; + case SYSID_SM_MEMARRAY_HANDLE: + *buf = &priv->marray_handles[0]; + *size = sizeof(priv->marray_handles); + break; default: return -EOPNOTSUPP; } diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 120e7510f15..16ef434a8d9 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -196,14 +196,14 @@ config SYSRESET_SBI config SYSRESET_SOCFPGA bool "Enable support for Intel SOCFPGA family" - depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10) + depends on ARCH_SOCFPGA && (ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10) help This enables the system reset driver support for Intel SOCFPGA SoCs (Cyclone 5, Arria 5 and Arria 10). config SYSRESET_SOCFPGA_SOC64 bool "Enable support for Intel SOCFPGA SoC64 family (Stratix10/Agilex)" - depends on ARCH_SOCFPGA && TARGET_SOCFPGA_SOC64 + depends on ARCH_SOCFPGA && ARCH_SOCFPGA_SOC64 help This enables the system reset driver support for Intel SOCFPGA SoC64 SoCs. diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c index c8389d507ee..1bde4d07f52 100644 --- a/drivers/thermal/imx_tmu.c +++ b/drivers/thermal/imx_tmu.c @@ -5,7 +5,6 @@ */ #include <config.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> @@ -19,8 +18,6 @@ #include <malloc.h> #include <thermal.h> -DECLARE_GLOBAL_DATA_PTR; - #define SITES_MAX 16 #define FLAGS_VER2 0x1 #define FLAGS_VER3 0x2 diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index a84a0dc0539..500a25638a9 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -11,7 +11,7 @@ config TIMER config SPL_TIMER bool "Enable driver model for timer drivers in SPL" - depends on TIMER && SPL + depends on TIMER && SPL && SPL_DM help Enable support for timer drivers in SPL. These can be used to get a timer value when in SPL, or perhaps for implementing a delay @@ -328,7 +328,7 @@ config XILINX_TIMER bool "Xilinx timer support" depends on TIMER select REGMAP - select SPL_REGMAP if SPL + select SPL_REGMAP if SPL_TIMER help Select this to enable support for the timer found on any Xilinx boards (axi timer). diff --git a/drivers/timer/ostm_timer.c b/drivers/timer/ostm_timer.c index 314f956cdfb..3841d3c90d0 100644 --- a/drivers/timer/ostm_timer.c +++ b/drivers/timer/ostm_timer.c @@ -7,7 +7,6 @@ #include <clock_legacy.h> #include <malloc.h> -#include <asm/global_data.h> #include <asm/io.h> #include <dm.h> #include <clk.h> @@ -22,8 +21,6 @@ #define OSTM_CTL 0x20 #define OSTM_CTL_D BIT(1) -DECLARE_GLOBAL_DATA_PTR; - struct ostm_priv { fdt_addr_t regs; }; diff --git a/drivers/timer/sp804_timer.c b/drivers/timer/sp804_timer.c index 3e57f4b98ba..05532e3330c 100644 --- a/drivers/timer/sp804_timer.c +++ b/drivers/timer/sp804_timer.c @@ -8,15 +8,12 @@ #include <dm.h> #include <init.h> #include <log.h> -#include <asm/global_data.h> #include <dm/ofnode.h> #include <mapmem.h> #include <dt-structs.h> #include <timer.h> #include <asm/io.h> -DECLARE_GLOBAL_DATA_PTR; - #define SP804_TIMERX_LOAD 0x00 #define SP804_TIMERX_VALUE 0x04 #define SP804_TIMERX_CONTROL 0x08 diff --git a/drivers/ufs/Kconfig b/drivers/ufs/Kconfig index 6c75bb2a079..49472933de3 100644 --- a/drivers/ufs/Kconfig +++ b/drivers/ufs/Kconfig @@ -76,6 +76,10 @@ config UFS_RENESAS_GEN5 config UFS_ROCKCHIP bool "Rockchip specific hooks to UFS controller platform driver" depends on UFS + depends on DM_GPIO + depends on RESET_ROCKCHIP + depends on SPL_DM_GPIO || !SPL_UFS_SUPPORT + depends on SPL_RESET_ROCKCHIP || !SPL_UFS_SUPPORT help This selects the Rockchip specific additions to UFSHCD platform driver. diff --git a/drivers/ufs/ufs-rockchip.c b/drivers/ufs/ufs-rockchip.c index 643a6ffb9bc..a13236c7f76 100644 --- a/drivers/ufs/ufs-rockchip.c +++ b/drivers/ufs/ufs-rockchip.c @@ -5,6 +5,7 @@ * Copyright (C) 2025 Rockchip Electronics Co.Ltd. */ +#include <asm/gpio.h> #include <asm/io.h> #include <clk.h> #include <dm.h> @@ -29,12 +30,9 @@ static int ufs_rockchip_hce_enable_notify(struct ufs_hba *hba, ufshcd_dme_reset(hba); ufshcd_dme_enable(hba); - if (hba->ops->phy_initialization) { - err = hba->ops->phy_initialization(hba); - if (err) - dev_err(hba->dev, - "Phy init failed (%d)\n", err); - } + err = ufshcd_ops_phy_initialization(hba); + if (err) + dev_err(hba->dev, "Phy init failed (%d)\n", err); return err; } @@ -152,11 +150,31 @@ static int ufs_rockchip_common_init(struct ufs_hba *hba) return err; } + err = gpio_request_by_name(dev, "reset-gpios", 0, &host->device_reset, + GPIOD_IS_OUT | GPIOD_ACTIVE_LOW); + if (err) { + dev_err(dev, "Cannot get reset GPIO\n"); + return err; + } + host->hba = hba; return 0; } +static int ufs_rockchip_device_reset(struct ufs_hba *hba) +{ + struct ufs_rockchip_host *host = dev_get_priv(hba->dev); + + dm_gpio_set_value(&host->device_reset, true); + udelay(20); + + dm_gpio_set_value(&host->device_reset, false); + udelay(20); + + return 0; +} + static int ufs_rockchip_rk3576_init(struct ufs_hba *hba) { int ret = 0; @@ -174,6 +192,7 @@ static struct ufs_hba_ops ufs_hba_rk3576_vops = { .init = ufs_rockchip_rk3576_init, .phy_initialization = ufs_rockchip_rk3576_phy_init, .hce_enable_notify = ufs_rockchip_hce_enable_notify, + .device_reset = ufs_rockchip_device_reset, }; static const struct udevice_id ufs_rockchip_of_match[] = { diff --git a/drivers/ufs/ufs-rockchip.h b/drivers/ufs/ufs-rockchip.h index 3dcb80f5702..50c2539da78 100644 --- a/drivers/ufs/ufs-rockchip.h +++ b/drivers/ufs/ufs-rockchip.h @@ -72,6 +72,7 @@ struct ufs_rockchip_host { void __iomem *ufs_sys_ctrl; void __iomem *mphy_base; struct reset_ctl_bulk rsts; + struct gpio_desc device_reset; struct clk ref_out_clk; uint64_t caps; uint32_t phy_config_mode; diff --git a/drivers/ufs/ufs-uclass.c b/drivers/ufs/ufs-uclass.c index 7a80a9d5664..bb997aace8f 100644 --- a/drivers/ufs/ufs-uclass.c +++ b/drivers/ufs/ufs-uclass.c @@ -127,11 +127,6 @@ static void ufshcd_print_pwr_info(struct ufs_hba *hba) hba->pwr_info.hs_rate); } -static void ufshcd_device_reset(struct ufs_hba *hba) -{ - ufshcd_vops_device_reset(hba); -} - /** * ufshcd_ready_for_uic_cmd - Check if controller is ready * to accept UIC commands @@ -512,7 +507,9 @@ static int ufshcd_link_startup(struct ufs_hba *hba) int retries = DME_LINKSTARTUP_RETRIES; do { - ufshcd_ops_link_startup_notify(hba, PRE_CHANGE); + ret = ufshcd_ops_link_startup_notify(hba, PRE_CHANGE); + if (ret) + goto out; ret = ufshcd_dme_link_startup(hba); @@ -598,12 +595,18 @@ static inline void ufshcd_hba_start(struct ufs_hba *hba) static int ufshcd_hba_enable(struct ufs_hba *hba) { int retry; + int ret; if (!ufshcd_is_hba_active(hba)) /* change controller state to "reset state" */ ufshcd_hba_stop(hba); - ufshcd_ops_hce_enable_notify(hba, PRE_CHANGE); + ret = ufshcd_ops_hce_enable_notify(hba, PRE_CHANGE); + if (ret) { + dev_err(hba->dev, "Controller enable notify PRE_CHANGE failed: %i\n", + ret); + return ret; + } /* start controller initialization sequence */ ufshcd_hba_start(hba); @@ -635,7 +638,12 @@ static int ufshcd_hba_enable(struct ufs_hba *hba) /* enable UIC related interrupts */ ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); - ufshcd_ops_hce_enable_notify(hba, POST_CHANGE); + ret = ufshcd_ops_hce_enable_notify(hba, POST_CHANGE); + if (ret) { + dev_err(hba->dev, "Controller enable notify POST_CHANGE failed: %i\n", + ret); + return ret; + } return 0; } @@ -2184,7 +2192,11 @@ int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops) /* Set descriptor lengths to specification defaults */ ufshcd_def_desc_sizes(hba); - ufshcd_ops_init(hba); + err = ufshcd_ops_init(hba); + if (err) { + dev_err(hba->dev, "Host controller init failed: %i\n", err); + return err; + } /* Read capabilities registers */ hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); @@ -2228,7 +2240,11 @@ int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops) mb(); /* flush previous writes */ /* Reset the attached device */ - ufshcd_device_reset(hba); + err = ufshcd_vops_device_reset(hba); + if (err) { + dev_err(hba->dev, "Failed to reset attached device: %i\n", err); + return err; + } err = ufshcd_hba_enable(hba); if (err) { diff --git a/drivers/ufs/ufs.h b/drivers/ufs/ufs.h index bc839a43704..0f6c93fbce7 100644 --- a/drivers/ufs/ufs.h +++ b/drivers/ufs/ufs.h @@ -509,7 +509,7 @@ struct ufs_query { }; /** - * struct ufs_dev_cmd - all assosiated fields with device management commands + * struct ufs_dev_cmd - all associated fields with device management commands * @type: device management command type - Query, NOP OUT * @tag_wq: wait queue until free command slot is available */ @@ -756,6 +756,14 @@ static inline int ufshcd_ops_link_startup_notify(struct ufs_hba *hba, return 0; } +static inline int ufshcd_ops_phy_initialization(struct ufs_hba *hba) +{ + if (hba->ops && hba->ops->phy_initialization) + return hba->ops->phy_initialization(hba); + + return 0; +} + static inline int ufshcd_vops_device_reset(struct ufs_hba *hba) { if (hba->ops && hba->ops->device_reset) diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c index 13e9a61072a..22aa6525c96 100644 --- a/drivers/usb/common/common.c +++ b/drivers/usb/common/common.c @@ -7,14 +7,11 @@ */ #include <dm.h> -#include <asm/global_data.h> #include <linux/printk.h> #include <linux/usb/otg.h> #include <linux/usb/ch9.h> #include <linux/usb/phy.h> -DECLARE_GLOBAL_DATA_PTR; - static const char *const usb_dr_modes[] = { [USB_DR_MODE_UNKNOWN] = "", [USB_DR_MODE_HOST] = "host", diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index ebb306852a6..baa2eb61ea3 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -89,6 +89,7 @@ config USB_GADGET_PRODUCT_NUM default 0x350b if ROCKCHIP_RK3588 default 0x350c if ROCKCHIP_RK3528 default 0x350e if ROCKCHIP_RK3576 + default 0x350f if ROCKCHIP_RK3506 default 0x4ee0 if ARCH_SNAPDRAGON default 0x0 help diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 046bb335ecb..4729570c525 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -990,7 +990,7 @@ int dm_usb_gadget_handle_interrupts(struct udevice *dev) return value; } -void udc_disconnect(void) +static void udc_disconnect(void) { struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; /* disable pullup */ diff --git a/drivers/usb/isp1760/Kconfig b/drivers/usb/isp1760/Kconfig index 993d71e74cd..d1c5a687d9e 100644 --- a/drivers/usb/isp1760/Kconfig +++ b/drivers/usb/isp1760/Kconfig @@ -1,11 +1,13 @@ # SPDX-License-Identifier: GPL-2.0 config USB_ISP1760 - tristate "NXP ISP 1760/1761/1763 support" + bool "NXP ISP 1760/1761/1763 support" + depends on DM && OF_CONTROL select DM_USB + select REGMAP select USB_HOST help - Say Y or M here if your system as an ISP1760/1761/1763 USB host + Say Y here if your system as an ISP1760/1761/1763 USB host controller. This USB controller is usually attached to a non-DMA-Master diff --git a/drivers/usb/musb-new/ti-musb.c b/drivers/usb/musb-new/ti-musb.c index bcd31adba52..cc6c3b94a65 100644 --- a/drivers/usb/musb-new/ti-musb.c +++ b/drivers/usb/musb-new/ti-musb.c @@ -83,17 +83,17 @@ static int ti_musb_of_to_plat(struct udevice *dev) struct ti_musb_plat *plat = dev_get_plat(dev); const void *fdt = gd->fdt_blob; int node = dev_of_offset(dev); - int phys; - int ctrl_mod; + ofnode phys_node; + ofnode ctrl_mod_node; int usb_index; int ret; struct musb_hdrc_config *musb_config; plat->base = devfdt_get_addr_index_ptr(dev, 1); - phys = fdtdec_lookup_phandle(fdt, node, "phys"); - ctrl_mod = fdtdec_lookup_phandle(fdt, phys, "ti,ctrl_mod"); - plat->ctrl_mod_base = (void *)fdtdec_get_addr(fdt, ctrl_mod, "reg"); + phys_node = ofnode_get_by_phandle(dev_read_u32_default(dev, "phys", 0)); + ctrl_mod_node = ofnode_get_by_phandle(ofnode_read_u32_default(phys_node, "ti,ctrl_mod", 0)); + plat->ctrl_mod_base = (void *)ofnode_get_addr(ctrl_mod_node); usb_index = ti_musb_get_usb_index(node); switch (usb_index) { case 1: @@ -183,6 +183,21 @@ static int ti_musb_host_remove(struct udevice *dev) } #if CONFIG_IS_ENABLED(OF_CONTROL) +static const struct udevice_id ti_musb_host_periph_ids[] = { + { .compatible = "ti,musb-am33xx" }, + { } +}; + +static int ti_musb_host_bind(struct udevice *dev) +{ + enum usb_dr_mode dr_mode = usb_get_dr_mode(dev_ofnode(dev)); + + if (dr_mode != USB_DR_MODE_HOST && dr_mode != USB_DR_MODE_OTG) + return -ENODEV; + + return 0; +} + static int ti_musb_host_of_to_plat(struct udevice *dev) { struct ti_musb_plat *plat = dev_get_plat(dev); @@ -206,6 +221,8 @@ U_BOOT_DRIVER(ti_musb_host) = { .name = "ti-musb-host", .id = UCLASS_USB, #if CONFIG_IS_ENABLED(OF_CONTROL) + .of_match = ti_musb_host_periph_ids, + .bind = ti_musb_host_bind, .of_to_plat = ti_musb_host_of_to_plat, #endif .probe = ti_musb_host_probe, @@ -221,6 +238,16 @@ struct ti_musb_peripheral { }; #if CONFIG_IS_ENABLED(OF_CONTROL) +static int ti_musb_peripheral_bind(struct udevice *dev) +{ + enum usb_dr_mode dr_mode = usb_get_dr_mode(dev_ofnode(dev)); + + if (dr_mode != USB_DR_MODE_PERIPHERAL) + return -ENODEV; + + return 0; +} + static int ti_musb_peripheral_of_to_plat(struct udevice *dev) { struct ti_musb_plat *plat = dev_get_plat(dev); @@ -283,6 +310,8 @@ U_BOOT_DRIVER(ti_musb_peripheral) = { .name = "ti-musb-peripheral", .id = UCLASS_USB_GADGET_GENERIC, #if CONFIG_IS_ENABLED(OF_CONTROL) + .of_match = ti_musb_host_periph_ids, + .bind = ti_musb_peripheral_bind, .of_to_plat = ti_musb_peripheral_of_to_plat, #endif .ops = &ti_musb_gadget_ops, diff --git a/drivers/usb/phy/rockchip_usb2_phy.c b/drivers/usb/phy/rockchip_usb2_phy.c index ce9a7b5b819..bdbd0d44813 100644 --- a/drivers/usb/phy/rockchip_usb2_phy.c +++ b/drivers/usb/phy/rockchip_usb2_phy.c @@ -5,15 +5,12 @@ #include <hang.h> #include <log.h> -#include <asm/global_data.h> #include <asm/io.h> #include <linux/bitops.h> #include <linux/delay.h> #include "../gadget/dwc2_udc_otg_priv.h" -DECLARE_GLOBAL_DATA_PTR; - #define BIT_WRITEABLE_SHIFT 16 struct usb2phy_reg { diff --git a/drivers/usb/tcpm/tcpm.c b/drivers/usb/tcpm/tcpm.c index 0aee57cb2f4..3061b466d7c 100644 --- a/drivers/usb/tcpm/tcpm.c +++ b/drivers/usb/tcpm/tcpm.c @@ -19,8 +19,6 @@ #include <usb/tcpm.h> #include "tcpm-internal.h" -DECLARE_GLOBAL_DATA_PTR; - const char * const tcpm_states[] = { FOREACH_TCPM_STATE(GENERATE_TCPM_STRING) }; diff --git a/drivers/video/hx8238d.c b/drivers/video/hx8238d.c index f0220e4cc07..b6980b1aec1 100644 --- a/drivers/video/hx8238d.c +++ b/drivers/video/hx8238d.c @@ -16,8 +16,6 @@ #include <panel.h> #include <spi.h> -DECLARE_GLOBAL_DATA_PTR; - /* Register Address */ #define HX8238D_OUTPUT_CTRL_ADDR 0x01 #define HX8238D_LCD_AC_CTRL_ADDR 0x02 diff --git a/drivers/video/imx/Kconfig b/drivers/video/imx/Kconfig index b35ba965efc..c25f209629e 100644 --- a/drivers/video/imx/Kconfig +++ b/drivers/video/imx/Kconfig @@ -15,6 +15,13 @@ config IMX_HDMI bool "Enable HDMI support in IPUv3" depends on VIDEO_IPUV3 +config IPU_CLK_LEGACY + bool "Use legacy clock management for IPU" + depends on VIDEO_IPUV3 && !CLK + default y + help + Use legacy clock management instead of Common Clock Framework. + config IMX_LDB bool "Freescale i.MX8MP LDB bridge" depends on VIDEO_BRIDGE diff --git a/drivers/video/imx/Makefile b/drivers/video/imx/Makefile index 1edf5a6bdf0..0e7f71a9f93 100644 --- a/drivers/video/imx/Makefile +++ b/drivers/video/imx/Makefile @@ -4,5 +4,6 @@ # Wolfgang Denk, DENX Software Engineering, [email protected]. obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o +obj-$(CONFIG_IPU_CLK_LEGACY) += ipu_clk_legacy.o obj-$(CONFIG_IMX_LDB) += ldb.o obj-$(CONFIG_IMX_LCDIF) += lcdif.o diff --git a/drivers/video/imx/ipu.h b/drivers/video/imx/ipu.h index 62827dc480d..ae40e20bc28 100644 --- a/drivers/video/imx/ipu.h +++ b/drivers/video/imx/ipu.h @@ -18,14 +18,23 @@ #ifndef __ASM_ARCH_IPU_H__ #define __ASM_ARCH_IPU_H__ +#if !CONFIG_IS_ENABLED(IPU_CLK_LEGACY) +#include <clk.h> +#endif #include <ipu_pixfmt.h> #include <linux/types.h> +#define IPUV3_CLK_MX51 133000000 +#define IPUV3_CLK_MX53 200000000 +#define IPUV3_CLK_MX6Q 264000000 +#define IPUV3_CLK_MX6DL 198000000 + #define IDMA_CHAN_INVALID 0xFF #define HIGH_RESOLUTION_WIDTH 1024 struct ipu_ctx; -struct ipu_di_config; + +#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) struct clk { const char *name; @@ -75,6 +84,46 @@ struct clk { int (*set_parent)(struct clk *clk, struct clk *parent); }; +/* Legacy clock API functions */ +void clk_enable(struct clk *clk); +void clk_disable(struct clk *clk); +int clk_get_usecount(struct clk *clk); +u32 clk_get_rate(struct clk *clk); +struct clk *clk_get_parent(struct clk *clk); +int clk_set_rate(struct clk *clk, unsigned long rate); +long clk_round_rate(struct clk *clk, unsigned long rate); +int clk_set_parent(struct clk *clk, struct clk *parent); + +/* IPU clock initialization */ +int ipu_clk_init_legacy(struct ipu_ctx *ctx); +int ipu_ldb_clk_init_legacy(struct ipu_ctx *ctx); +int ipu_pixel_clk_init_legacy(struct ipu_ctx *ctx, int id); + +#else + +static inline int clk_get_usecount(struct clk *clk) +{ + return clk->enable_count; +} + +/* Stub functions for non-legacy builds */ +static inline int ipu_clk_init_legacy(struct ipu_ctx *ctx) +{ + return -ENOSYS; +} + +static inline int ipu_ldb_clk_init_legacy(struct ipu_ctx *ctx) +{ + return -ENOSYS; +} + +static inline int ipu_pixel_clk_init_legacy(struct ipu_ctx *ctx, int id) +{ + return -ENOSYS; +} + +#endif /* CONFIG_IS_ENABLED(IPU_CLK_LEGACY) */ + struct udevice; /* @@ -298,15 +347,6 @@ int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable, u32 bytes_per_pixel(u32 fmt); -void clk_enable(struct clk *clk); -void clk_disable(struct clk *clk); -u32 clk_get_rate(struct clk *clk); -int clk_set_rate(struct clk *clk, unsigned long rate); -long clk_round_rate(struct clk *clk, unsigned long rate); -int clk_set_parent(struct clk *clk, struct clk *parent); -int clk_get_usecount(struct clk *clk); -struct clk *clk_get_parent(struct clk *clk); - void ipu_dump_registers(void); struct ipu_ctx *ipu_probe(struct udevice *dev); bool ipu_clk_enabled(struct ipu_ctx *ctx); diff --git a/drivers/video/imx/ipu_clk_legacy.c b/drivers/video/imx/ipu_clk_legacy.c new file mode 100644 index 00000000000..8aaafa2a080 --- /dev/null +++ b/drivers/video/imx/ipu_clk_legacy.c @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Legacy IPU clock management for i.MX5/6 without Common Clock Framework + * + * (C) Copyright 2026 + * Brian Ruley, GE HealthCare, [email protected] + */ + +#include "ipu.h" +#include "ipu_regs.h" +#include <asm/arch/crm_regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> +#include <div64.h> +#include <dm/devres.h> +#include <linux/err.h> +#include <log.h> + +extern struct mxc_ccm_reg *mxc_ccm; + +void clk_enable(struct clk *clk) +{ + if (clk) { + if (clk->usecount++ == 0) + clk->enable(clk); + } +} + +void clk_disable(struct clk *clk) +{ + if (clk) { + if (!(--clk->usecount)) { + if (clk->disable) + clk->disable(clk); + } + } +} + +int clk_get_usecount(struct clk *clk) +{ + if (clk == NULL) + return 0; + + return clk->usecount; +} + +u32 clk_get_rate(struct clk *clk) +{ + if (!clk) + return 0; + + return clk->rate; +} + +struct clk *clk_get_parent(struct clk *clk) +{ + if (!clk) + return 0; + + return clk->parent; +} + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + if (!clk) + return 0; + + if (clk->set_rate) + clk->set_rate(clk, rate); + + return clk->rate; +} + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + if (clk == NULL || !clk->round_rate) + return 0; + + return clk->round_rate(clk, rate); +} + +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + clk->parent = parent; + if (clk->set_parent) + return clk->set_parent(clk, parent); + return 0; +} + +static int clk_ipu_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + +#if CONFIG_IS_ENABLED(MX51) || CONFIG_IS_ENABLED(MX53) + reg = __raw_readl(&mxc_ccm->ccdr); + reg &= ~MXC_CCM_CCDR_IPU_HS_MASK; + __raw_writel(reg, &mxc_ccm->ccdr); + + reg = __raw_readl(&mxc_ccm->clpcr); + reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; + __raw_writel(reg, &mxc_ccm->clpcr); +#endif + return 0; +} + +static void clk_ipu_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); + +#if CONFIG_IS_ENABLED(MX51) || CONFIG_IS_ENABLED(MX53) + reg = __raw_readl(&mxc_ccm->ccdr); + reg |= MXC_CCM_CCDR_IPU_HS_MASK; + __raw_writel(reg, &mxc_ccm->ccdr); + + reg = __raw_readl(&mxc_ccm->clpcr); + reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; + __raw_writel(reg, &mxc_ccm->clpcr); +#endif +} + +static void ipu_pixel_clk_recalc(struct clk *clk) +{ + u32 div; + u64 final_rate = (unsigned long long)clk->parent->rate * 16; + + div = __raw_readl(DI_BS_CLKGEN0(clk->id)); + debug("read BS_CLKGEN0 div:%d, final_rate:%lld, prate:%ld\n", div, + final_rate, clk->parent->rate); + + clk->rate = 0; + if (div != 0) { + do_div(final_rate, div); + clk->rate = final_rate; + } +} + +static unsigned long ipu_pixel_clk_round_rate(struct clk *clk, + unsigned long rate) +{ + u64 div, final_rate; + u32 remainder; + u64 parent_rate = (unsigned long long)clk->parent->rate * 16; + + div = parent_rate; + remainder = do_div(div, rate); + if (remainder > (rate / 2)) + div++; + if (div < 0x10) + div = 0x10; + if (div & ~0xFEF) + div &= 0xFF8; + else { + if ((div & 0xC) == 0xC) { + div += 0x10; + div &= ~0xF; + } + } + final_rate = parent_rate; + do_div(final_rate, div); + + return final_rate; +} + +static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate) +{ + u64 div, parent_rate; + u32 remainder; + + parent_rate = (unsigned long long)clk->parent->rate * 16; + div = parent_rate; + remainder = do_div(div, rate); + if (remainder > (rate / 2)) + div++; + + if ((div & 0xC) == 0xC) { + div += 0x10; + div &= ~0xF; + } + if (div > 0x1000) + debug("Overflow, DI_BS_CLKGEN0 div:0x%x\n", (u32)div); + + __raw_writel(div, DI_BS_CLKGEN0(clk->id)); + __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id)); + + do_div(parent_rate, div); + clk->rate = parent_rate; + + return 0; +} + +static int ipu_pixel_clk_enable(struct clk *clk) +{ + u32 disp_gen = __raw_readl(IPU_DISP_GEN); + disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE; + __raw_writel(disp_gen, IPU_DISP_GEN); + + return 0; +} + +static void ipu_pixel_clk_disable(struct clk *clk) +{ + u32 disp_gen = __raw_readl(IPU_DISP_GEN); + disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE; + __raw_writel(disp_gen, IPU_DISP_GEN); +} + +static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent) +{ + u32 di_gen = __raw_readl(DI_GENERAL(clk->id)); + struct ipu_ctx *ctx = clk->ctx; + + if (parent == ctx->ipu_clk) + di_gen &= ~DI_GEN_DI_CLK_EXT; + else if (!IS_ERR(ctx->di_clk[clk->id]) && parent == ctx->ldb_clk) + di_gen |= DI_GEN_DI_CLK_EXT; + else + return -EINVAL; + + __raw_writel(di_gen, DI_GENERAL(clk->id)); + ipu_pixel_clk_recalc(clk); + return 0; +} + +int ipu_pixel_clk_init_legacy(struct ipu_ctx *ctx, int id) +{ + struct clk *pixel_clk; + + pixel_clk = devm_kzalloc(ctx->dev, sizeof(*pixel_clk), GFP_KERNEL); + if (!pixel_clk) + return -ENOMEM; + + pixel_clk->name = "pixel_clk"; + pixel_clk->id = id; + pixel_clk->ctx = ctx; + pixel_clk->recalc = ipu_pixel_clk_recalc; + pixel_clk->set_rate = ipu_pixel_clk_set_rate; + pixel_clk->round_rate = ipu_pixel_clk_round_rate; + pixel_clk->set_parent = ipu_pixel_clk_set_parent; + pixel_clk->enable = ipu_pixel_clk_enable; + pixel_clk->disable = ipu_pixel_clk_disable; + pixel_clk->usecount = 0; + + ctx->pixel_clk[id] = pixel_clk; + return 0; +} + +int ipu_clk_init_legacy(struct ipu_ctx *ctx) +{ + struct clk *ipu_clk; + + ipu_clk = devm_kzalloc(ctx->dev, sizeof(*ipu_clk), GFP_KERNEL); + if (!ipu_clk) + return -ENOMEM; + + ipu_clk->name = "ipu_clk"; + ipu_clk->ctx = ctx; +#if CONFIG_IS_ENABLED(MX51) || CONFIG_IS_ENABLED(MX53) + ipu_clk->enable_reg = + (u32 *)(CCM_BASE_ADDR + offsetof(struct mxc_ccm_reg, CCGR5)); + ipu_clk->enable_shift = MXC_CCM_CCGR5_IPU_OFFSET; +#else + ipu_clk->enable_reg = + (u32 *)(CCM_BASE_ADDR + offsetof(struct mxc_ccm_reg, CCGR3)); + ipu_clk->enable_shift = MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET; +#endif + + ipu_clk->enable = clk_ipu_enable; + ipu_clk->disable = clk_ipu_disable; + ipu_clk->usecount = 0; + +#if CONFIG_IS_ENABLED(MX51) + ipu_clk->rate = IPUV3_CLK_MX51; +#elif CONFIG_IS_ENABLED(MX53) + ipu_clk->rate = IPUV3_CLK_MX53; +#else + ipu_clk->rate = is_mx6sdl() ? IPUV3_CLK_MX6DL : IPUV3_CLK_MX6Q; +#endif + + ctx->ipu_clk = ipu_clk; + return 0; +} + +#if !defined CFG_SYS_LDB_CLOCK +#define CFG_SYS_LDB_CLOCK 65000000 +#endif + +int ipu_ldb_clk_init_legacy(struct ipu_ctx *ctx) +{ + struct clk *ldb_clk; + + ldb_clk = devm_kzalloc(ctx->dev, sizeof(*ldb_clk), GFP_KERNEL); + if (!ldb_clk) + return -ENOMEM; + + ldb_clk->name = "ldb_clk"; + ldb_clk->ctx = ctx; + ldb_clk->rate = CFG_SYS_LDB_CLOCK; + ldb_clk->usecount = 0; + + ctx->ldb_clk = ldb_clk; + return 0; +} diff --git a/drivers/video/imx/ipu_common.c b/drivers/video/imx/ipu_common.c index e9897ee79d2..8630374a055 100644 --- a/drivers/video/imx/ipu_common.c +++ b/drivers/video/imx/ipu_common.c @@ -31,8 +31,8 @@ #include <linux/types.h> #include <log.h> -extern struct mxc_ccm_reg *mxc_ccm; -extern u32 *ipu_cpmem_base; +u32 *ipu_cpmem_base; +u32 *ipu_dc_tmpl_reg; struct ipu_ch_param_word { u32 data[5]; @@ -92,126 +92,6 @@ struct ipu_ch_param { #define IPU_SW_RST_TOUT_USEC (10000) -#define IPUV3_CLK_MX51 133000000 -#define IPUV3_CLK_MX53 200000000 -#define IPUV3_CLK_MX6Q 264000000 -#define IPUV3_CLK_MX6DL 198000000 - -void clk_enable(struct clk *clk) -{ - if (clk) { - if (clk->usecount++ == 0) - clk->enable(clk); - } -} - -void clk_disable(struct clk *clk) -{ - if (clk) { - if (!(--clk->usecount)) { - if (clk->disable) - clk->disable(clk); - } - } -} - -int clk_get_usecount(struct clk *clk) -{ - if (clk == NULL) - return 0; - - return clk->usecount; -} - -u32 clk_get_rate(struct clk *clk) -{ - if (!clk) - return 0; - - return clk->rate; -} - -struct clk *clk_get_parent(struct clk *clk) -{ - if (!clk) - return 0; - - return clk->parent; -} - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - if (!clk) - return 0; - - if (clk->set_rate) - clk->set_rate(clk, rate); - - return clk->rate; -} - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - if (clk == NULL || !clk->round_rate) - return 0; - - return clk->round_rate(clk, rate); -} - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - clk->parent = parent; - if (clk->set_parent) - return clk->set_parent(clk, parent); - return 0; -} - -static int clk_ipu_enable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(clk->enable_reg); - reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift; - __raw_writel(reg, clk->enable_reg); - -#if CONFIG_IS_ENABLED(MX51) || CONFIG_IS_ENABLED(MX53) - /* Handshake with IPU when certain clock rates are changed. */ - reg = __raw_readl(&mxc_ccm->ccdr); - reg &= ~MXC_CCM_CCDR_IPU_HS_MASK; - __raw_writel(reg, &mxc_ccm->ccdr); - - /* Handshake with IPU when LPM is entered as its enabled. */ - reg = __raw_readl(&mxc_ccm->clpcr); - reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; - __raw_writel(reg, &mxc_ccm->clpcr); -#endif - return 0; -} - -static void clk_ipu_disable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(clk->enable_reg); - reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift); - __raw_writel(reg, clk->enable_reg); - -#if CONFIG_IS_ENABLED(MX51) || CONFIG_IS_ENABLED(MX53) - /* - * No handshake with IPU whe dividers are changed - * as its not enabled. - */ - reg = __raw_readl(&mxc_ccm->ccdr); - reg |= MXC_CCM_CCDR_IPU_HS_MASK; - __raw_writel(reg, &mxc_ccm->ccdr); - - /* No handshake with IPU when LPM is entered as its not enabled. */ - reg = __raw_readl(&mxc_ccm->clpcr); - reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; - __raw_writel(reg, &mxc_ccm->clpcr); -#endif -} - /* * Function to initialize the ipu clock * @@ -221,43 +101,19 @@ static void clk_ipu_disable(struct clk *clk) */ static int ipu_clk_init(struct ipu_ctx *ctx) { - struct clk *ipu_clk; - - ipu_clk = devm_kzalloc(ctx->dev, sizeof(*ipu_clk), GFP_KERNEL); - if (!ipu_clk) - return -ENOMEM; - - ipu_clk->name = "ipu_clk"; - ipu_clk->ctx = ctx; -#if CONFIG_IS_ENABLED(MX51) || CONFIG_IS_ENABLED(MX53) - ipu_clk->enable_reg = - (u32 *)(CCM_BASE_ADDR + offsetof(struct mxc_ccm_reg, CCGR5)); - ipu_clk->enable_shift = MXC_CCM_CCGR5_IPU_OFFSET; +#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) + return ipu_clk_init_legacy(ctx); #else - ipu_clk->enable_reg = - (u32 *)(CCM_BASE_ADDR + offsetof(struct mxc_ccm_reg, CCGR3)); - ipu_clk->enable_shift = MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET; -#endif + struct clk *clk; - ipu_clk->enable = clk_ipu_enable; - ipu_clk->disable = clk_ipu_disable; - ipu_clk->usecount = 0; + clk = devm_clk_get(ctx->dev, "bus"); + if (IS_ERR(clk)) + return PTR_ERR(clk); -#if CONFIG_IS_ENABLED(MX51) - ipu_clk->rate = IPUV3_CLK_MX51; -#elif CONFIG_IS_ENABLED(MX53) - ipu_clk->rate = IPUV3_CLK_MX53; -#else - ipu_clk->rate = is_mx6sdl() ? IPUV3_CLK_MX6DL : IPUV3_CLK_MX6Q; -#endif - - ctx->ipu_clk = ipu_clk; + ctx->ipu_clk = clk; return 0; -}; - -#if !defined CFG_SYS_LDB_CLOCK -#define CFG_SYS_LDB_CLOCK 65000000 #endif +} /* * Function to initialize the ldb dummy clock @@ -268,23 +124,14 @@ static int ipu_clk_init(struct ipu_ctx *ctx) */ static int ipu_ldb_clk_init(struct ipu_ctx *ctx) { - struct clk *ldb_clk; - - ldb_clk = devm_kzalloc(ctx->dev, sizeof(*ldb_clk), GFP_KERNEL); - if (!ldb_clk) - return -ENOMEM; - - ldb_clk->name = "ldb_clk"; - ldb_clk->ctx = ctx; - ldb_clk->rate = CFG_SYS_LDB_CLOCK; - ldb_clk->usecount = 0; - - ctx->ldb_clk = ldb_clk; +#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) + return ipu_ldb_clk_init_legacy(ctx); +#else + /* Set this in the FB driver where we know the display id */ + ctx->ldb_clk = NULL; return 0; -}; - -u32 *ipu_cpmem_base; -u32 *ipu_dc_tmpl_reg; +#endif +} /* Static functions */ @@ -320,124 +167,29 @@ static inline void ipu_ch_param_set_buffer(u32 ch, int buf_num, #define idma_mask(ch) (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0) #define idma_is_set(reg, dma) (__raw_readl(reg(dma)) & idma_mask(dma)) -static void ipu_pixel_clk_recalc(struct clk *clk) -{ - u32 div; - u64 final_rate = (unsigned long long)clk->parent->rate * 16; - - div = __raw_readl(DI_BS_CLKGEN0(clk->id)); - debug("read BS_CLKGEN0 div:%d, final_rate:%lld, prate:%ld\n", div, - final_rate, clk->parent->rate); - - clk->rate = 0; - if (div != 0) { - do_div(final_rate, div); - clk->rate = final_rate; - } -} - -static unsigned long ipu_pixel_clk_round_rate(struct clk *clk, - unsigned long rate) -{ - u64 div, final_rate; - u32 remainder; - u64 parent_rate = (unsigned long long)clk->parent->rate * 16; - - /* - * Calculate divider - * Fractional part is 4 bits, - * so simply multiply by 2^4 to get fractional part. - */ - div = parent_rate; - remainder = do_div(div, rate); - /* Round the divider value */ - if (remainder > (rate / 2)) - div++; - if (div < 0x10) /* Min DI disp clock divider is 1 */ - div = 0x10; - if (div & ~0xFEF) - div &= 0xFF8; - else { - /* Round up divider if it gets us closer to desired pix clk */ - if ((div & 0xC) == 0xC) { - div += 0x10; - div &= ~0xF; - } - } - final_rate = parent_rate; - do_div(final_rate, div); - - return final_rate; -} - -static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate) -{ - u64 div, parent_rate; - u32 remainder; - - parent_rate = (unsigned long long)clk->parent->rate * 16; - div = parent_rate; - remainder = do_div(div, rate); - /* Round the divider value */ - if (remainder > (rate / 2)) - div++; - - /* Round up divider if it gets us closer to desired pix clk */ - if ((div & 0xC) == 0xC) { - div += 0x10; - div &= ~0xF; - } - if (div > 0x1000) - debug("Overflow, DI_BS_CLKGEN0 div:0x%x\n", (u32)div); - - __raw_writel(div, DI_BS_CLKGEN0(clk->id)); - - /* - * Setup pixel clock timing - * Down time is half of period - */ - __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id)); - - do_div(parent_rate, div); - - clk->rate = parent_rate; - - return 0; -} - -static int ipu_pixel_clk_enable(struct clk *clk) +/* + * Function to initialize the display clocks + * + * @param ctx The ipu context for which the function is called + * + * Return: Returns 0 on success or negative error code on error + */ +static int ipu_di_clk_init(struct ipu_ctx *ctx, int id) { - u32 disp_gen = __raw_readl(IPU_DISP_GEN); - disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE; - __raw_writel(disp_gen, IPU_DISP_GEN); - +#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) + ctx->di_clk[id] = NULL; return 0; -} - -static void ipu_pixel_clk_disable(struct clk *clk) -{ - u32 disp_gen = __raw_readl(IPU_DISP_GEN); - disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE; - __raw_writel(disp_gen, IPU_DISP_GEN); -} - -static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent) -{ - u32 di_gen = __raw_readl(DI_GENERAL(clk->id)); - struct ipu_ctx *ctx = clk->ctx; +#else + struct clk *clk; - if (parent == ctx->ipu_clk) - di_gen &= ~DI_GEN_DI_CLK_EXT; - else if (!IS_ERR(ctx->di_clk[clk->id]) && parent == ctx->ldb_clk) - di_gen |= DI_GEN_DI_CLK_EXT; - else - return -EINVAL; + clk = devm_clk_get(ctx->dev, id ? "di1" : "di0"); + if (IS_ERR(clk)) + return PTR_ERR(clk); - __raw_writel(di_gen, DI_GENERAL(clk->id)); - ipu_pixel_clk_recalc(clk); + ctx->di_clk[id] = clk; return 0; +#endif } - /* * Function to initialize the pixel clock * @@ -447,26 +199,13 @@ static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent) */ static int ipu_pixel_clk_init(struct ipu_ctx *ctx, int id) { - struct clk *pixel_clk; - - pixel_clk = devm_kzalloc(ctx->dev, sizeof(*pixel_clk), GFP_KERNEL); - if (!pixel_clk) - return -ENOMEM; - - pixel_clk->name = "pixel_clk"; - pixel_clk->id = id; - pixel_clk->ctx = ctx; - pixel_clk->recalc = ipu_pixel_clk_recalc; - pixel_clk->set_rate = ipu_pixel_clk_set_rate; - pixel_clk->round_rate = ipu_pixel_clk_round_rate; - pixel_clk->set_parent = ipu_pixel_clk_set_parent; - pixel_clk->enable = ipu_pixel_clk_enable; - pixel_clk->disable = ipu_pixel_clk_disable; - pixel_clk->usecount = 0; - - ctx->pixel_clk[id] = pixel_clk; +#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) + return ipu_pixel_clk_init_legacy(ctx, id); +#else + ctx->pixel_clk[id] = ctx->ipu_clk; return 0; -}; +#endif +} /* * This function resets IPU @@ -536,33 +275,39 @@ struct ipu_ctx *ipu_probe(struct udevice *dev) ipu_cpmem_base = (u32 *)(ipu_base + IPU_CPMEM_REG_BASE); ipu_dc_tmpl_reg = (u32 *)(ipu_base + IPU_DC_TMPL_REG_BASE); - ret = ipu_pixel_clk_init(ctx, 0); - if (ret) - goto err; - - ret = ipu_pixel_clk_init(ctx, 1); - if (ret) - goto err; + for (int i = 0; i <= 1; i++) { + ret = ipu_pixel_clk_init(ctx, i); + if (ret) + goto err; + } ret = ipu_clk_init(ctx); if (ret) goto err; - debug("ipu_clk = %u\n", clk_get_rate(ctx->ipu_clk)); + debug("ipu_clk = %lu\n", (ulong)clk_get_rate(ctx->ipu_clk)); ret = ipu_ldb_clk_init(ctx); if (ret) goto err; - debug("ldb_clk = %u\n", clk_get_rate(ctx->ldb_clk)); + if (ctx->ldb_clk) + debug("ldb_clk = %lu\n", (ulong)clk_get_rate(ctx->ldb_clk)); + ipu_reset(); +#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) clk_set_parent(ctx->pixel_clk[0], ctx->ipu_clk); clk_set_parent(ctx->pixel_clk[1], ctx->ipu_clk); + clk_enable(ctx->ipu_clk); +#endif - ctx->di_clk[0] = NULL; - ctx->di_clk[1] = NULL; + for (int i = 0; i <= 1; i++) { + ret = ipu_di_clk_init(ctx, i); + if (ret) + goto err; + } __raw_writel(0x807FFFFF, IPU_MEM_RST); while (__raw_readl(IPU_MEM_RST) & 0x80000000) @@ -584,7 +329,9 @@ struct ipu_ctx *ipu_probe(struct udevice *dev) /* Set MCU_T to divide MCU access window into 2 */ __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN); +#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) clk_disable(ctx->ipu_clk); +#endif return ctx; err: diff --git a/drivers/video/imx/ipu_disp.c b/drivers/video/imx/ipu_disp.c index 6a337b13af6..5e78574da9b 100644 --- a/drivers/video/imx/ipu_disp.c +++ b/drivers/video/imx/ipu_disp.c @@ -612,6 +612,11 @@ void ipu_dp_dc_enable(struct ipu_ctx *ctx, ipu_channel_t channel) __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); clk_enable(ctx->pixel_clk[di]); +#if !CONFIG_IS_ENABLED(IPU_CLK_LEGACY) + reg = __raw_readl(IPU_DISP_GEN); + reg |= di ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE; + __raw_writel(reg, IPU_DISP_GEN); +#endif } static unsigned char dc_swap; @@ -702,6 +707,12 @@ void ipu_dp_dc_disable(struct ipu_ctx *ctx, ipu_channel_t channel, /* Clock is already off because it must be done quickly, but we need to fix the ref count */ +#if !CONFIG_IS_ENABLED(IPU_CLK_LEGACY) + reg = __raw_readl(IPU_DISP_GEN); + reg &= ctx->dc_di_assignment[dc_chan] ? ~DI1_COUNTER_RELEASE : + ~DI0_COUNTER_RELEASE; + __raw_writel(reg, IPU_DISP_GEN); +#endif clk_disable(ctx->pixel_clk[ctx->dc_di_assignment[dc_chan]]); } } @@ -765,40 +776,21 @@ static int ipu_pixfmt_to_map(u32 fmt) * * @param sig Bitfield of signal polarities for LCD interface. * - * Return: This function returns 0 on success or negative error code on - * fail. + * Return: The integer portion of the divider set for the pixel clock. */ - -int32_t ipu_init_sync_panel(struct ipu_di_config *di, ipu_di_signal_cfg_t sig) +static u32 ipu_di_clk_config(struct ipu_di_config *di, ipu_di_signal_cfg_t sig) { struct ipu_ctx *ctx = di->ctx; int disp = di->disp; - u32 reg; - u32 di_gen, vsync_cnt; - u32 div, rounded_pixel_clk; - u32 h_total, v_total; - int map; - struct clk *di_parent; - - debug("panel size = %d x %d\n", di->width, di->height); - - if ((di->v_sync_width == 0) || (di->h_sync_width == 0)) - return -EINVAL; - - /* adapt panel to ipu restricitions */ - if (di->v_end_width < 2) { - di->v_end_width = 2; - puts("WARNING: v_end_width (lower_margin) must be >= 2, adjusted\n"); - } - - h_total = di->width + di->h_sync_width + di->h_start_width + - di->h_end_width; - v_total = di->height + di->v_sync_width + di->v_start_width + - di->v_end_width; + u32 div; /* Init clocking */ debug("pixel clk = %dHz\n", di->pixel_clk_rate); +#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) + u32 rounded_pixel_clk; + struct clk *di_parent; + if (sig.ext_clk) { if (!(g_di1_tvout && (disp == 1))) { /*not round div for tvout*/ /* @@ -830,13 +822,109 @@ int32_t ipu_init_sync_panel(struct ipu_di_config *di, ipu_di_signal_cfg_t sig) if (clk_get_usecount(ctx->pixel_clk[disp]) != 0) clk_set_parent(ctx->pixel_clk[disp], ctx->ipu_clk); } + rounded_pixel_clk = clk_round_rate(ctx->pixel_clk[disp], di->pixel_clk_rate); clk_set_rate(ctx->pixel_clk[disp], rounded_pixel_clk); - udelay(5000); + /* Get integer portion of divider */ div = clk_get_rate(clk_get_parent(ctx->pixel_clk[disp])) / rounded_pixel_clk; +#else + struct clk *clk; + u32 clkgen0, di_gen; + ulong id; + + if (sig.ext_clk) { + /* + * Bypass the divider, assuming synchronous mode + */ + clk = ctx->di_clk[disp]; + div = 1; + } else { + + ulong clk_rate = clk_get_rate(ctx->ipu_clk); + u32 error; + + div = DIV_ROUND_CLOSEST(clk_rate, di->pixel_clk_rate); + div = clamp(div, 1U, 255U); + + error = (clk_rate / div) / (di->pixel_clk_rate / 1000); + + /* + * Select IPU if the rate is within 1% of requested pixel + * clock, otherwise, use the DI clock + */ + if (990 <= error && error < 1010) { + clk = ctx->ipu_clk; + } else { + clk = ctx->di_clk[disp]; + + clk_set_rate(clk, di->pixel_clk_rate); + div = DIV_ROUND_CLOSEST(clk_get_rate(clk), + di->pixel_clk_rate); + div = clamp(div, 1U, 255U); + } + } + + clkgen0 = div << 4; + + ctx->pixel_clk[disp] = clk; + debug("new pixel rate: %lu Hz\n", clk_get_rate(clk)); + + id = clk_get_id(clk); + __raw_writel(clkgen0, DI_BS_CLKGEN0(id)); + __raw_writel((clkgen0 & 0xFFF0) << 12, DI_BS_CLKGEN1(id)); + + di_gen = __raw_readl(DI_GENERAL(id)) & ~DI_GEN_DI_CLK_EXT; + if (clk == ctx->di_clk[disp]) + di_gen |= DI_GEN_DI_CLK_EXT; + + __raw_writel(di_gen, DI_GENERAL(id)); +#endif + + udelay(5000); + return div; +} + +/* + * This function is called to initialize a synchronous LCD panel. + * + * @param di Pointer to display data. + * + * @param sig Bitfield of signal polarities for LCD interface. + * + * Return: This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_init_sync_panel(struct ipu_di_config *di, ipu_di_signal_cfg_t sig) +{ + int disp = di->disp; + u32 reg; + u32 di_gen, vsync_cnt; + u32 div; + u32 h_total, v_total; + int map; + + debug("panel size = %d x %d\n", di->width, di->height); + + if ((di->v_sync_width == 0) || (di->h_sync_width == 0)) + return -EINVAL; + + /* adapt panel to ipu restricitions */ + if (di->v_end_width < 2) { + di->v_end_width = 2; + puts("WARNING: v_end_width (lower_margin) must be >= 2, adjusted\n"); + } + + h_total = di->width + di->h_sync_width + di->h_start_width + + di->h_end_width; + v_total = di->height + di->v_sync_width + di->v_start_width + + di->v_end_width; + + div = ipu_di_clk_config(di, sig); + if (div < 0) + return div; ipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1); ipu_di_data_pin_config(disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2); diff --git a/drivers/video/imx/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c index ab416fdd33c..3a327b9e97d 100644 --- a/drivers/video/imx/mxc_ipuv3_fb.c +++ b/drivers/video/imx/mxc_ipuv3_fb.c @@ -21,7 +21,6 @@ #include "ipu_regs.h" #include "mxcfb.h" #include <asm/cache.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/mach-imx/video.h> #include <linux/err.h> @@ -36,8 +35,7 @@ #include <dm.h> #include <dm/devres.h> #include <video.h> - -DECLARE_GLOBAL_DATA_PTR; +#include <dt-bindings/clock/imx6qdl-clock.h> static int mxcfb_map_video_memory(struct fb_info *fbi); static int mxcfb_unmap_video_memory(struct fb_info *fbi); @@ -602,6 +600,22 @@ static int ipuv3_video_probe(struct udevice *dev) if (ret < 0) return ret; +#if !CONFIG_IS_ENABLED(IPU_CLK_LEGACY) + if (of_machine_is_compatible("fsl,imx6qp")) + ret = clk_get_by_id(gdisp ? IMX6QDL_CLK_LDB_DI1_PODF : + IMX6QDL_CLK_LDB_DI0_PODF, + &ctx->ldb_clk); + else + ret = clk_get_by_id(gdisp ? IMX6QDL_CLK_LDB_DI1 : + IMX6QDL_CLK_LDB_DI0, + &ctx->ldb_clk); + + if (ret < 0) + return ret; + + debug("ldb_clk = %lu\n", clk_get_rate(ctx->ldb_clk)); +#endif + ret = mxcfb_probe(dev, gpixfmt, gdisp, gmode); if (ret < 0) return ret; diff --git a/drivers/video/nexell_display.c b/drivers/video/nexell_display.c index ea3776258a0..e0416b70ec0 100644 --- a/drivers/video/nexell_display.c +++ b/drivers/video/nexell_display.c @@ -16,14 +16,11 @@ #include <linux/compat.h> #include <linux/err.h> #include <video.h> /* For struct video_uc_plat */ -#include <asm/global_data.h> #include <asm/io.h> #include <asm/arch/display.h> #include <asm/arch/display_dev.h> #include "videomodes.h" -DECLARE_GLOBAL_DATA_PTR; - #if !defined(CONFIG_DM) && !defined(CONFIG_OF_CONTROL) static struct nx_display_dev *dp_dev; #endif diff --git a/drivers/video/renesas-r61307.c b/drivers/video/renesas-r61307.c index ef6fab1e953..b643fd1db89 100644 --- a/drivers/video/renesas-r61307.c +++ b/drivers/video/renesas-r61307.c @@ -228,7 +228,7 @@ static int renesas_r61307_of_to_plat(struct udevice *dev) } priv->dig_cont_adj = dev_read_bool(dev, "renesas,contrast"); - priv->inversion = dev_read_bool(dev, "renesas,inversion"); + priv->inversion = dev_read_bool(dev, "renesas,column-inversion"); priv->gamma = dev_read_u32_default(dev, "renesas,gamma", 0); return 0; diff --git a/drivers/video/rockchip/rk_lvds.c b/drivers/video/rockchip/rk_lvds.c index c969dae30b6..97c8619a6d8 100644 --- a/drivers/video/rockchip/rk_lvds.c +++ b/drivers/video/rockchip/rk_lvds.c @@ -10,7 +10,6 @@ #include <panel.h> #include <regmap.h> #include <syscon.h> -#include <asm/global_data.h> #include <asm/gpio.h> #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/grf_rk3288.h> @@ -19,8 +18,6 @@ #include <dt-bindings/clock/rk3288-cru.h> #include <dt-bindings/video/rk3288.h> -DECLARE_GLOBAL_DATA_PTR; - /** * struct rk_lvds_priv - private rockchip lvds display driver info * diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c index 0a603083ba9..e7b5973ca58 100644 --- a/drivers/video/rockchip/rk_mipi.c +++ b/drivers/video/rockchip/rk_mipi.c @@ -10,7 +10,6 @@ #include <log.h> #include <panel.h> #include <regmap.h> -#include <asm/global_data.h> #include "rk_mipi.h" #include <syscon.h> #include <asm/gpio.h> @@ -22,8 +21,6 @@ #include <asm/arch-rockchip/grf_rk3399.h> #include <asm/arch-rockchip/rockchip_mipi_dsi.h> -DECLARE_GLOBAL_DATA_PTR; - int rk_mipi_read_timing(struct udevice *dev, struct display_timing *timing) { diff --git a/drivers/video/samsung-ltl106hl02.c b/drivers/video/samsung-ltl106hl02.c index 1efc9fca610..97881a1524e 100644 --- a/drivers/video/samsung-ltl106hl02.c +++ b/drivers/video/samsung-ltl106hl02.c @@ -93,9 +93,9 @@ static int samsung_ltl106hl02_of_to_plat(struct udevice *dev) } ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev, - "vdd-supply", &priv->vdd); + "power-supply", &priv->vdd); if (ret) - log_debug("%s: cannot get vdd-supply: error %d\n", + log_debug("%s: cannot get power-supply: error %d\n", __func__, ret); ret = gpio_request_by_name(dev, "reset-gpios", 0, diff --git a/drivers/video/sandbox_sdl.c b/drivers/video/sandbox_sdl.c index 69dfa930273..48da350080a 100644 --- a/drivers/video/sandbox_sdl.c +++ b/drivers/video/sandbox_sdl.c @@ -7,15 +7,12 @@ #include <fdtdec.h> #include <log.h> #include <video.h> -#include <asm/global_data.h> #include <asm/sdl.h> #include <asm/state.h> #include <asm/u-boot-sandbox.h> #include <dm/device-internal.h> #include <dm/test.h> -DECLARE_GLOBAL_DATA_PTR; - enum { /* Default LCD size we support */ LCD_MAX_WIDTH = 1366, diff --git a/drivers/video/tidss/tidss_drv.c b/drivers/video/tidss/tidss_drv.c index 790ff6e591c..c231fd0341e 100644 --- a/drivers/video/tidss/tidss_drv.c +++ b/drivers/video/tidss/tidss_drv.c @@ -42,8 +42,6 @@ #include "tidss_regs.h" #include "tidss_oldi.h" -DECLARE_GLOBAL_DATA_PTR; - /* Panel parameters */ enum { LCD_MAX_WIDTH = 1920, diff --git a/drivers/video/zynqmp/zynqmp_dpsub.c b/drivers/video/zynqmp/zynqmp_dpsub.c index a0efd3393f5..fba65bb3d5b 100644 --- a/drivers/video/zynqmp/zynqmp_dpsub.c +++ b/drivers/video/zynqmp/zynqmp_dpsub.c @@ -20,12 +20,9 @@ #include <linux/delay.h> #include <linux/ioport.h> #include <dm/device_compat.h> -#include <asm/global_data.h> #include "zynqmp_dpsub.h" -DECLARE_GLOBAL_DATA_PTR; - /* Maximum supported resolution */ #define WIDTH 1024 #define HEIGHT 768 diff --git a/drivers/virtio/virtio-uclass.c b/drivers/virtio/virtio-uclass.c index ac563991b90..c36e9e9b3a7 100644 --- a/drivers/virtio/virtio-uclass.c +++ b/drivers/virtio/virtio-uclass.c @@ -292,6 +292,9 @@ static int virtio_uclass_child_pre_probe(struct udevice *vdev) if (ret) goto err; + /* After a reset we always need to start the init sequence again */ + virtio_add_status(vdev, VIRTIO_CONFIG_S_ACKNOWLEDGE); + /* We have a driver! */ virtio_add_status(vdev, VIRTIO_CONFIG_S_DRIVER); diff --git a/drivers/virtio/virtio_rng.c b/drivers/virtio/virtio_rng.c index 90a371a59cc..c6de62142bb 100644 --- a/drivers/virtio/virtio_rng.c +++ b/drivers/virtio/virtio_rng.c @@ -46,7 +46,7 @@ static int virtio_rng_read(struct udevice *dev, void *data, size_t len) ; if (rsize > sg.length) - return -EIO; + rsize = sg.length; memcpy(ptr, buf, rsize); len -= rsize; diff --git a/drivers/watchdog/armada-37xx-wdt.c b/drivers/watchdog/armada-37xx-wdt.c index 4b51178e1b8..d7a6b8de492 100644 --- a/drivers/watchdog/armada-37xx-wdt.c +++ b/drivers/watchdog/armada-37xx-wdt.c @@ -7,14 +7,11 @@ #include <dm.h> #include <wdt.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/soc.h> #include <dm/device_compat.h> -DECLARE_GLOBAL_DATA_PTR; - struct a37xx_wdt { void __iomem *sel_reg; void __iomem *reg; diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c index 72e13787448..2fb25126b8c 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -15,7 +15,6 @@ */ #include <log.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/arch/at91_wdt.h> #include <div64.h> @@ -23,8 +22,6 @@ #include <errno.h> #include <wdt.h> -DECLARE_GLOBAL_DATA_PTR; - /* * AT91SAM9 watchdog runs a 12bit counter @ 256Hz, * use this to convert a watchdog diff --git a/drivers/watchdog/mt7621_wdt.c b/drivers/watchdog/mt7621_wdt.c index 6308d9632a8..08ef3d84e26 100644 --- a/drivers/watchdog/mt7621_wdt.c +++ b/drivers/watchdog/mt7621_wdt.c @@ -11,12 +11,9 @@ #include <dm.h> #include <wdt.h> -#include <asm/global_data.h> #include <linux/bitops.h> #include <linux/io.h> -DECLARE_GLOBAL_DATA_PTR; - struct mt762x_wdt { void __iomem *regs; }; diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index 4d4ab4cbe90..3c7e043c08e 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -146,6 +146,7 @@ static const struct udevice_id mtk_wdt_ids[] = { { .compatible = "mediatek,mt6589-wdt"}, { .compatible = "mediatek,mt7986-wdt" }, { .compatible = "mediatek,mt8188-wdt" }, + { .compatible = "mediatek,mt8195-wdt" }, {} }; diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c index 4562b2a37e3..a2000b968c9 100644 --- a/drivers/watchdog/orion_wdt.c +++ b/drivers/watchdog/orion_wdt.c @@ -16,15 +16,12 @@ #include <clk.h> #include <log.h> #include <wdt.h> -#include <asm/global_data.h> #include <linux/bitops.h> #include <linux/kernel.h> #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/soc.h> -DECLARE_GLOBAL_DATA_PTR; - struct orion_wdt_priv { void __iomem *reg; int wdt_counter_offset; diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c index 03585529bb6..807884c5bc7 100644 --- a/drivers/watchdog/sbsa_gwdt.c +++ b/drivers/watchdog/sbsa_gwdt.c @@ -5,7 +5,6 @@ * Copyright 2020 NXP */ -#include <asm/global_data.h> #include <asm/io.h> #include <dm/device.h> #include <dm/fdtaddr.h> @@ -15,8 +14,6 @@ #include <watchdog.h> #include <wdt.h> -DECLARE_GLOBAL_DATA_PTR; - /* SBSA Generic Watchdog register definitions */ /* refresh frame */ #define SBSA_GWDT_WRR 0x000 diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c index b32590069d9..438833b2245 100644 --- a/drivers/watchdog/wdt-uclass.c +++ b/drivers/watchdog/wdt-uclass.c @@ -14,13 +14,10 @@ #include <sysreset.h> #include <time.h> #include <wdt.h> -#include <asm/global_data.h> #include <dm/device-internal.h> #include <dm/lists.h> #include <linux/kernel.h> -DECLARE_GLOBAL_DATA_PTR; - #define WATCHDOG_TIMEOUT_SECS (CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000) struct wdt_priv { |