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authorDavid Lechner <[email protected]>2026-03-10 10:32:22 -0500
committerDavid Lechner <[email protected]>2026-03-24 11:04:01 -0500
commit999c169c354399639d4e10d36c0ab464beeaced5 (patch)
treeea2c60343ec74229974989c35c8055c412aa76b4 /drivers
parente60c459757aad646bcf2f0a9c208dff222ab24f5 (diff)
clk: mediatek: mt8183: convert CLK_XTAL to CLK_PAD_CLK26M
Replace all uses of CLK_XTAL with CLK_PAD_CLK26M. This avoids declaring the same parent clock two different ways and will eventually let us remove CLK_PARENT_XTAL completely. Reviewed-by: Julien Stephan <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: David Lechner <[email protected]>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/mediatek/clk-mt8183.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index 6158441fb95..7b2d796bc6c 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -76,7 +76,7 @@ static const struct mtk_pll_data apmixed_plls[] = {
};
#define FIXED_CLK0(_id, _rate) \
- FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)
+ FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate)
#define FIXED_CLK1(_id, _rate) \
FIXED_CLK(_id, CLK_TOP_UNIVPLL, CLK_PARENT_TOPCKGEN, _rate)
@@ -605,7 +605,6 @@ static const struct mtk_composite top_muxes[] = {
};
static const struct mtk_clk_tree mt8183_clk_tree = {
- .xtal_rate = 26 * MHZ,
.pll_parent = EXT_PARENT(CLK_PAD_CLK26M),
.ext_clk_rates = ext_clock_rates,
.num_ext_clks = ARRAY_SIZE(ext_clock_rates),