diff options
| author | Marek Vasut <[email protected]> | 2018-06-13 08:02:55 +0200 |
|---|---|---|
| committer | Marek Vasut <[email protected]> | 2018-11-02 16:07:04 +0100 |
| commit | a376dde1deb9cc42e3804b9c654f873c936cc8d4 (patch) | |
| tree | 41619b83454a6492735e574910035257e2cb070d /drivers | |
| parent | 2fc10754d1902ddc2aa3ecd2f0e976a1714a6780 (diff) | |
mmc: tmio: sdhi: Merge DTCNTL access into single register write
It is perfectly fine to write th DTCNTL TAP count and enable the
SCC sampling clock operation in the same write.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Masahiro Yamada <[email protected]>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mmc/renesas-sdhi.c | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index 63561e19c82..e7f96f8bf22 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -51,12 +51,9 @@ static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv) tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL); /* Set sampling clock selection range */ - tmio_sd_writel(priv, 0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT, - RENESAS_SDHI_SCC_DTCNTL); - - reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL); - reg |= RENESAS_SDHI_SCC_DTCNTL_TAPEN; - tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_DTCNTL); + tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) | + RENESAS_SDHI_SCC_DTCNTL_TAPEN, + RENESAS_SDHI_SCC_DTCNTL); reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL); reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL; |