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authorVenkatesh Yadav Abbarapu <[email protected]>2025-11-26 19:21:49 +0100
committerMichal Simek <[email protected]>2025-12-19 08:25:27 +0100
commitb6391d1d9b3d04c1986b3ce7951528f8fde76bbd (patch)
tree39b71a551074f9f3d97f1685bff4d47f71fceb4e /drivers
parent857a3b49c36e3fc53c4a5e1280216359ab2b92bf (diff)
cadence_qspi: Update the delays for flash reset
Updating the delays for flash reset in the mini u-boot case. These experimental delay values by looking at different flash device vendors datasheets. Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/3fd0641a164a4d628fdf28a94771829f3bf9cb0c.1764181308.git.michal.simek@amd.com
Diffstat (limited to 'drivers')
-rw-r--r--drivers/spi/cadence_ospi_versal.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c
index 0efbbf56a5e..e3ddf127e5a 100644
--- a/drivers/spi/cadence_ospi_versal.c
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -178,15 +178,15 @@ int cadence_qspi_flash_reset(struct udevice *dev)
/* Disable Tri-state */
writel((readl(BANK0_TRI) & ~BIT(FLASH_RESET_GPIO)), BANK0_TRI);
- udelay(1);
+ udelay(5);
/* Set value 0 to pin */
writel((readl(BANK0_OUTPUT) & ~BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT);
- udelay(10);
+ udelay(150);
/* Set value 1 to pin */
writel((readl(BANK0_OUTPUT) | BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT);
- udelay(10);
+ udelay(1200);
return 0;
}