Merge branch '2023-08-30-assorted-code-improvements' into next

- pcie-bcmstb improvements, nvmxip improvements, fix a corner case in
  the serial uclass, send error messages to stderr in host tools, fwu
  library CI state fixup, turn some setexpr diagnostic messages to debug

5 files changed, 46 insertions, 48 deletions

diff --git a/drivers/mtd/nvmxip/nvmxip-uclass.c b/drivers/mtd/nvmxip/nvmxip-uclass.c
index 6d8eb177b50..9a316d1de39 100644
--- a/drivers/mtd/nvmxip/nvmxip-uclass.c
+++ b/drivers/mtd/nvmxip/nvmxip-uclass.c
@@ -22,27 +22,13 @@
 
 #define DEFAULT_LBA_SZ BIT(DEFAULT_LBA_SHIFT)
 
-/**
- * nvmxip_post_bind() - post binding treatments
- * @dev:	the NVMXIP device
- *
- * Create and probe a child block device.
- *
- * Return:
- *
- * 0 on success. Otherwise, failure
- */
-static int nvmxip_post_bind(struct udevice *udev)
+int nvmxip_probe(struct udevice *udev)
 {
 	int ret;
 	struct udevice *bdev = NULL;
 	char bdev_name[NVMXIP_BLKDEV_NAME_SZ + 1];
 	int devnum;
 
-#if CONFIG_IS_ENABLED(SANDBOX64)
-	sandbox_set_enable_memio(true);
-#endif
-
 	devnum = uclass_id_count(UCLASS_NVMXIP);
 	snprintf(bdev_name, NVMXIP_BLKDEV_NAME_SZ, "blk#%d", devnum);
 
@@ -67,6 +53,12 @@ static int nvmxip_post_bind(struct udevice *udev)
 	return 0;
 }
 
+static int nvmxip_post_bind(struct udevice *udev)
+{
+	dev_or_flags(udev, DM_FLAG_PROBE_AFTER_BIND);
+	return 0;
+}
+
 UCLASS_DRIVER(nvmxip) = {
 	.name	   = "nvmxip",
 	.id	   = UCLASS_NVMXIP,
diff --git a/drivers/mtd/nvmxip/nvmxip.c b/drivers/mtd/nvmxip/nvmxip.c
index a359e3b4822..0bd98d64275 100644
--- a/drivers/mtd/nvmxip/nvmxip.c
+++ b/drivers/mtd/nvmxip/nvmxip.c
@@ -16,23 +16,6 @@
 #include "nvmxip.h"
 
 /**
- * nvmxip_mmio_rawread() - read from the XIP flash
- * @address:	address of the data
- * @value:	pointer to where storing the value read
- *
- * Read raw data from the XIP flash.
- *
- * Return:
- *
- * Always return 0.
- */
-static int nvmxip_mmio_rawread(const phys_addr_t address, u64 *value)
-{
-	*value = readq(address);
-	return 0;
-}
-
-/**
  * nvmxip_blk_read() - block device read operation
  * @dev:	the block device
  * @blknr:	first block number to read from
@@ -49,15 +32,14 @@ static ulong nvmxip_blk_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcn
 {
 	struct nvmxip_plat *plat = dev_get_plat(dev->parent);
 	struct blk_desc *desc = dev_get_uclass_plat(dev);
-	/* number of the u64 words to read */
-	u32 qwords = (blkcnt * desc->blksz) / sizeof(u64);
+	/* number of bytes to read */
+	u32 size = blkcnt * desc->blksz;
 	/* physical address of the first block to read */
 	phys_addr_t blkaddr = plat->phys_base + blknr * desc->blksz;
-	u64 *virt_blkaddr;
-	u64 *pdst = buffer;
+	void *virt_blkaddr;
 	uint qdata_idx;
 
-	if (!pdst)
+	if (!buffer)
 		return -EINVAL;
 
 	log_debug("[%s]: reading from blknr: %lu , blkcnt: %lu\n", dev->name, blknr, blkcnt);
@@ -66,12 +48,16 @@ static ulong nvmxip_blk_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcn
 
 	/* assumption: the data is virtually contiguous */
 
-	for (qdata_idx = 0 ; qdata_idx < qwords ; qdata_idx++)
-		nvmxip_mmio_rawread((phys_addr_t)(virt_blkaddr + qdata_idx), pdst++);
-
+#if IS_ENABLED(CONFIG_PHYS_64BIT)
+	for (qdata_idx = 0 ; qdata_idx < size; qdata_idx += sizeof(u64))
+		*(u64 *)(buffer + qdata_idx) = readq(virt_blkaddr + qdata_idx);
+#else
+	for (qdata_idx = 0 ; qdata_idx < size; qdata_idx += sizeof(u32))
+		*(u32 *)(buffer + qdata_idx) = readl(virt_blkaddr + qdata_idx);
+#endif
 	log_debug("[%s]:     src[0]: 0x%llx , dst[0]: 0x%llx , src[-1]: 0x%llx , dst[-1]: 0x%llx\n",
 		  dev->name,
-		  *virt_blkaddr,
+		  *(u64 *)virt_blkaddr,
 		  *(u64 *)buffer,
 		  *(u64 *)((u8 *)virt_blkaddr + desc->blksz * blkcnt - sizeof(u64)),
 		  *(u64 *)((u8 *)buffer + desc->blksz * blkcnt - sizeof(u64)));
diff --git a/drivers/mtd/nvmxip/nvmxip_qspi.c b/drivers/mtd/nvmxip/nvmxip_qspi.c
index 7221fd1cb46..4d7471118a4 100644
--- a/drivers/mtd/nvmxip/nvmxip_qspi.c
+++ b/drivers/mtd/nvmxip/nvmxip_qspi.c
@@ -50,8 +50,8 @@ static int nvmxip_qspi_of_to_plat(struct udevice *dev)
 		return -EINVAL;
 	}
 
-	log_debug("[%s]: XIP device base addr: 0x%llx , lba_shift: %d , lbas: %lu\n",
-		  dev->name, plat->phys_base, plat->lba_shift, plat->lba);
+	log_debug("[%s]: XIP device base addr: 0x%p , lba_shift: %d , lbas: %lu\n",
+		  dev->name, (void *)(uintptr_t)plat->phys_base, plat->lba_shift, plat->lba);
 
 	return 0;
 }
@@ -66,5 +66,6 @@ U_BOOT_DRIVER(nvmxip_qspi) = {
 	.id = UCLASS_NVMXIP,
 	.of_match = nvmxip_qspi_ids,
 	.of_to_plat = nvmxip_qspi_of_to_plat,
+	.probe = nvmxip_probe,
 	.plat_auto = sizeof(struct nvmxip_plat),
 };
diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c
index 1de28021138..cd45f0bee9b 100644
--- a/drivers/pci/pcie_brcmstb.c
+++ b/drivers/pci/pcie_brcmstb.c
@@ -33,6 +33,9 @@
 #define PCIE_RC_CFG_PRIV1_ID_VAL3			0x043c
 #define  CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK		0xffffff
 
+#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY			0x04dc
+#define  PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK	0xc00
+
 #define PCIE_RC_DL_MDIO_ADDR				0x1100
 #define PCIE_RC_DL_MDIO_WR_DATA				0x1104
 #define PCIE_RC_DL_MDIO_RD_DATA				0x1108
@@ -88,7 +91,6 @@
 	 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
 
 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG			0x4204
-#define  PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK	0x2
 #define  PCIE_HARD_DEBUG_SERDES_IDDQ_MASK		0x08000000
 
 #define PCIE_MSI_INTR2_CLR				0x4508
@@ -223,6 +225,10 @@ static int brcm_pcie_config_address(const struct udevice *dev, pci_dev_t bdf,
 		return 0;
 	}
 
+	/* An access to our HW w/o link-up will cause a CPU Abort */
+	if (!brcm_pcie_link_up(pcie))
+		return -EINVAL;
+
 	/* For devices, write to the config space index register */
 	idx = PCIE_ECAM_OFFSET(pci_bus, pci_dev, pci_func, 0);
 
@@ -505,6 +511,12 @@ static int brcm_pcie_probe(struct udevice *dev)
 	clrbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1,
 		     RGR1_SW_INIT_1_PERST_MASK);
 
+	/*
+	 * Wait for 100ms after PERST# deassertion; see PCIe CEM specification
+	 * sections 2.2, PCIe r5.0, 6.6.1.
+	 */
+	mdelay(100);
+
 	/* Give the RC/EP time to wake up, before trying to configure RC.
 	 * Intermittently check status for link-up, up to a total of 100ms.
 	 */
@@ -562,12 +574,18 @@ static int brcm_pcie_probe(struct udevice *dev)
 	clrsetbits_le32(base + PCIE_RC_CFG_VENDOR_SPECIFIC_REG1,
 			VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK,
 			VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN);
+
 	/*
-	 * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
-	 * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
+	 * We used to enable the CLKREQ# input here, but a few PCIe cards don't
+	 * attach anything to the CLKREQ# line, so we shouldn't assume that
+	 * it's connected and working. The controller does allow detecting
+	 * whether the port on the other side of our link is/was driving this
+	 * signal, so we could check before we assume. But because this signal
+	 * is for power management, which doesn't make sense in a bootloader,
+	 * let's instead just unadvertise ASPM support.
 	 */
-	setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
-		     PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK);
+	clrbits_le32(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY,
+		     PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
 
 	return 0;
 }
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 067fae26145..e954f0189bb 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -151,6 +151,7 @@ static void serial_find_console_or_panic(void)
 #ifdef CONFIG_REQUIRE_SERIAL_CONSOLE
 	panic_str("No serial driver found");
 #endif
+	gd->cur_serial_dev = NULL;
 }
 #endif /* CONFIG_SERIAL_PRESENT */