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authorPeng Fan <[email protected]>2024-10-01 21:07:57 +0800
committerFabio Estevam <[email protected]>2024-10-04 09:15:15 -0300
commitc24dcfa0c55076d91268dffed66f9b9cbd75fe8d (patch)
tree2fc0f4354d97c5b2f393860e7a4be5981cb799a0 /drivers
parent876f6de20aead2de6c55f58b2ecc45375238426c (diff)
mmc: fsl_esdhc_imx: Reset tuning logic
When supporting partition reset for SoC such as i.MX95 , the Linux Kernel may have configured the tuning, while after force reset by wdog or else, uboot CMD0 will never pass unless config RSTT to reset tuning logic. Since RSTA and RSTT are independent, so need both to be reseted in the controller. Acked-by: Haibo Chen <[email protected]> Signed-off-by: Peng Fan <[email protected]>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/mmc/fsl_esdhc_imx.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index debfc78b7f0..fb410104c1f 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -987,11 +987,11 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
ulong start;
/* Reset the entire host controller */
- esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
+ esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA | SYSCTL_RSTT);
/* Wait until the controller is available */
start = get_timer(0);
- while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
+ while ((esdhc_read32(&regs->sysctl) & (SYSCTL_RSTA | SYSCTL_RSTT))) {
if (get_timer(start) > 1000)
return -ETIMEDOUT;
}
@@ -1095,11 +1095,11 @@ static int esdhc_reset(struct fsl_esdhc *regs)
ulong start;
/* reset the controller */
- esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
+ esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA | SYSCTL_RSTT);
/* hardware clears the bit when it is done */
start = get_timer(0);
- while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
+ while ((esdhc_read32(&regs->sysctl) & (SYSCTL_RSTA | SYSCTL_RSTT))) {
if (get_timer(start) > 100) {
printf("MMC/SD: Reset never completed.\n");
return -ETIMEDOUT;