Merge tag 'xilinx-for-v2025.04-rc2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

AMD/Xilinx changes for v2025.04-rc2

fpga:
- Cleanup help
- Show xilinx only options on Xilinx devices

ospi-versal:
- Fix alignment issue
- Fix cadence_qspi_flash_reset() prototype

zynqmp:
- Define usb_pgood_delay
- Fix bootseq number

versal:
- Fix mini_ospi configuration

versal2:
- Enable OPTEE

xilinx:
- Enable some flashes
- Clean up SYS_MALLOC_F_LEN Kconfig
- Some binman fixes
- DT updates
- Enable mkfwumdata compilation
- Enable meminfo command
- Switch to LWIP and enable HTTPS

3 files changed, 20 insertions, 8 deletions

diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index 1f6782537de..f88267e01b6 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -33,9 +33,9 @@ static void fpga_no_sup(char *fn, char *msg)
 /* fpga_get_desc
  *	map a device number to a descriptor
  */
-const fpga_desc *const fpga_get_desc(int devnum)
+const fpga_desc *fpga_get_desc(int devnum)
 {
-	fpga_desc *desc = (fpga_desc *)NULL;
+	const fpga_desc *desc = NULL;
 
 	if ((devnum >= 0) && (devnum < next_desc)) {
 		desc = &desc_table[devnum];
@@ -50,8 +50,8 @@ const fpga_desc *const fpga_get_desc(int devnum)
  * fpga_validate
  *	generic parameter checking code
  */
-const fpga_desc *const fpga_validate(int devnum, const void *buf,
-				     size_t bsize, char *fn)
+const fpga_desc *fpga_validate(int devnum, const void *buf,
+			       size_t bsize, char *fn)
 {
 	const fpga_desc *desc = fpga_get_desc(devnum);
 
@@ -60,7 +60,7 @@ const fpga_desc *const fpga_validate(int devnum, const void *buf,
 
 	if (!buf) {
 		printf("%s: Null buffer.\n", fn);
-		return (fpga_desc * const)NULL;
+		return NULL;
 	}
 	return desc;
 }
@@ -72,7 +72,7 @@ const fpga_desc *const fpga_validate(int devnum, const void *buf,
 static int fpga_dev_info(int devnum)
 {
 	int ret_val = FPGA_FAIL; /* assume failure */
-	const fpga_desc * const desc = fpga_get_desc(devnum);
+	const fpga_desc *desc = fpga_get_desc(devnum);
 
 	if (desc) {
 		debug("%s: Device Descriptor @ 0x%p\n",
@@ -374,7 +374,7 @@ int fpga_info(int devnum)
 #if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)
 int fpga_compatible2flag(int devnum, const char *compatible)
 {
-	const fpga_desc * const desc = fpga_get_desc(devnum);
+	const fpga_desc *desc = fpga_get_desc(devnum);
 
 	if (!desc)
 		return 0;
diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c
index dcf28c75596..816916de16d 100644
--- a/drivers/spi/cadence_ospi_versal.c
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -24,6 +24,13 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
 	u8 opcode, addr_bytes, *rxbuf, dummy_cycles;
 
 	n_rx = op->data.nbytes;
+
+	if (op->addr.dtr && (op->addr.val % 2)) {
+		n_rx += 1;
+		writel(op->addr.val & ~0x1,
+		       priv->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
+	}
+
 	rxbuf = op->data.buf.in;
 	rx_rem = n_rx % 4;
 	bytes_to_dma = n_rx - rx_rem;
@@ -104,6 +111,11 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
 		memcpy(rxbuf, &data, rx_rem);
 	}
 
+	if (op->addr.dtr && (op->addr.val % 2)) {
+		rxbuf -= bytes_to_dma;
+		memcpy(rxbuf, rxbuf + 1, n_rx - 1);
+	}
+
 	return 0;
 }
 
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 693474a2871..1f9125cd239 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -307,7 +307,7 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
 			      const struct spi_mem_op *op);
 int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv);
 int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg);
-int cadence_qspi_versal_flash_reset(struct udevice *dev);
+int cadence_qspi_flash_reset(struct udevice *dev);
 ofnode cadence_qspi_get_subnode(struct udevice *dev);
 void cadence_qspi_apb_enable_linear_mode(bool enable);