Merge branch '2022-07-06-platform-updates' into next

- Assorted updates for Toradex, TI, Aspeed and Nuvoton platforms

15 files changed, 475 insertions, 62 deletions

diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index a1b4496ca2c..623c6915b81 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -12,6 +12,7 @@
 #include <asm/arch/scu_ast2500.h>
 #include <dm/lists.h>
 #include <dt-bindings/clock/aspeed-clock.h>
+#include <dt-bindings/reset/ast2500-reset.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 
@@ -173,6 +174,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
 		rate = ast2500_get_uart_clk_rate(priv->scu, 5);
 		break;
 	default:
+		debug("%s: unknown clk %ld\n", __func__, clk->id);
 		return -ENOENT;
 	}
 
@@ -425,6 +427,25 @@ static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate)
 	return new_rate;
 }
 
+#define SCU_CLKSTOP_SDIO 27
+static ulong ast2500_enable_sdclk(struct ast2500_scu *scu)
+{
+	u32 reset_bit;
+	u32 clkstop_bit;
+
+	reset_bit = BIT(ASPEED_RESET_SDIO);
+	clkstop_bit = BIT(SCU_CLKSTOP_SDIO);
+
+	setbits_le32(&scu->sysreset_ctrl1, reset_bit);
+	udelay(100);
+	//enable clk
+	clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit);
+	mdelay(10);
+	clrbits_le32(&scu->sysreset_ctrl1, reset_bit);
+
+	return 0;
+}
+
 static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate)
 {
 	struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
@@ -438,6 +459,7 @@ static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate)
 		new_rate = ast2500_configure_d2pll(priv->scu, rate);
 		break;
 	default:
+		debug("%s: unknown clk %ld\n", __func__, clk->id);
 		return -ENOENT;
 	}
 
@@ -479,7 +501,11 @@ static int ast2500_clk_enable(struct clk *clk)
 	case ASPEED_CLK_D2PLL:
 		ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
 		break;
+	case ASPEED_CLK_GATE_SDCLK:
+		ast2500_enable_sdclk(priv->scu);
+		break;
 	default:
+		debug("%s: unknown clk %ld\n", __func__, clk->id);
 		return -ENOENT;
 	}
 
diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c
index f191b0f3170..0df1dc3718d 100644
--- a/drivers/clk/aspeed/clk_ast2600.c
+++ b/drivers/clk/aspeed/clk_ast2600.c
@@ -471,7 +471,7 @@ static ulong ast2600_clk_get_rate(struct clk *clk)
 		rate = ast2600_get_uart_huxclk_rate(priv->scu);
 		break;
 	default:
-		debug("can't get clk rate\n");
+		debug("%s: unknown clk %ld\n", __func__, clk->id);
 		return -ENOENT;
 	}
 
@@ -1073,13 +1073,13 @@ static int ast2600_clk_enable(struct clk *clk)
 	case ASPEED_CLK_GATE_SDCLK:
 		ast2600_enable_sdclk(priv->scu);
 		break;
-	case ASPEED_CLK_GATE_SDEXTCLK:
+	case ASPEED_CLK_SDIO:
 		ast2600_enable_extsdclk(priv->scu);
 		break;
 	case ASPEED_CLK_GATE_EMMCCLK:
 		ast2600_enable_emmcclk(priv->scu);
 		break;
-	case ASPEED_CLK_GATE_EMMCEXTCLK:
+	case ASPEED_CLK_EMMC:
 		ast2600_enable_extemmcclk(priv->scu);
 		break;
 	case ASPEED_CLK_GATE_FSICLK:
@@ -1098,7 +1098,7 @@ static int ast2600_clk_enable(struct clk *clk)
 		ast2600_enable_rsaclk(priv->scu);
 		break;
 	default:
-		pr_err("can't enable clk\n");
+		debug("%s: unknown clk %ld\n", __func__, clk->id);
 		return -ENOENT;
 	}
 
diff --git a/drivers/firmware/ti_sci_static_data.h b/drivers/firmware/ti_sci_static_data.h
index 8529ef29007..5ae0556a9a4 100644
--- a/drivers/firmware/ti_sci_static_data.h
+++ b/drivers/firmware/ti_sci_static_data.h
@@ -16,7 +16,7 @@ struct ti_sci_resource_static_data {
 
 #if IS_ENABLED(CONFIG_K3_DM_FW)
 
-#if IS_ENABLED(CONFIG_TARGET_J721E_R5_EVM)
+#if IS_ENABLED(CONFIG_SOC_K3_J721E)
 static struct ti_sci_resource_static_data rm_static_data[] = {
 	/* Free rings */
 	{
@@ -48,43 +48,9 @@ static struct ti_sci_resource_static_data rm_static_data[] = {
 	},
 	{ },
 };
-#endif /* CONFIG_TARGET_J721E_R5_EVM */
+#endif /* CONFIG_SOC_K3_J721E */
 
-#if IS_ENABLED(CONFIG_TARGET_J7200_R5_EVM)
-static struct ti_sci_resource_static_data rm_static_data[] = {
-	/* Free rings */
-	{
-		.dev_id = 235,
-		.subtype = 1,
-		.range_start = 124,
-		.range_num = 32,
-	},
-	/* TX channels */
-	{
-		.dev_id = 236,
-		.subtype = 13,
-		.range_start = 6,
-		.range_num = 2,
-	},
-	/* RX channels */
-	{
-		.dev_id = 236,
-		.subtype = 10,
-		.range_start = 6,
-		.range_num = 2,
-	},
-	/* RX Free flows */
-	{
-		.dev_id = 236,
-		.subtype = 0,
-		.range_start = 60,
-		.range_num = 8,
-	},
-	{ },
-};
-#endif /* CONFIG_TARGET_J7200_R5_EVM */
-
-#if IS_ENABLED(CONFIG_TARGET_J721S2_R5_EVM)
+#if IS_ENABLED(CONFIG_SOC_K3_J721S2)
 static struct ti_sci_resource_static_data rm_static_data[] = {
 	/* Free rings */
 	{
@@ -116,7 +82,7 @@ static struct ti_sci_resource_static_data rm_static_data[] = {
 	},
 	{ },
 };
-#endif /* CONFIG_TARGET_J721S2_R5_EVM */
+#endif /* CONFIG_SOC_K3_J721S2 */
 
 #if IS_ENABLED(CONFIG_SOC_K3_AM625)
 static struct ti_sci_resource_static_data rm_static_data[] = {
diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c
index 2d3fecaa14e..c9ffe2d6282 100644
--- a/drivers/i2c/ast_i2c.c
+++ b/drivers/i2c/ast_i2c.c
@@ -16,6 +16,7 @@
 #include <asm/arch/scu_ast2500.h>
 #include <linux/delay.h>
 #include <linux/err.h>
+#include <reset.h>
 
 #include "ast_i2c.h"
 
@@ -108,19 +109,26 @@ static int ast_i2c_of_to_plat(struct udevice *dev)
 
 static int ast_i2c_probe(struct udevice *dev)
 {
-	struct ast2500_scu *scu;
+	struct reset_ctl reset_ctl;
+	int rc;
 
 	debug("Enabling I2C%u\n", dev_seq(dev));
 
 	/*
 	 * Get all I2C devices out of Reset.
-	 * Only needs to be done once, but doing it for every
-	 * device does not hurt.
+	 *
+	 * Only needs to be done once so test before performing reset.
 	 */
-	scu = ast_get_scu();
-	ast_scu_unlock(scu);
-	clrbits_le32(&scu->sysreset_ctrl1, SCU_SYSRESET_I2C);
-	ast_scu_lock(scu);
+	rc = reset_get_by_index(dev, 0, &reset_ctl);
+	if (rc) {
+		printf("%s: Failed to get reset signal\n", __func__);
+		return rc;
+	}
+
+	if (reset_status(&reset_ctl) > 0) {
+		reset_assert(&reset_ctl);
+		reset_deassert(&reset_ctl);
+	}
 
 	ast_i2c_init_bus(dev);
 
@@ -343,6 +351,7 @@ static const struct dm_i2c_ops ast_i2c_ops = {
 static const struct udevice_id ast_i2c_ids[] = {
 	{ .compatible = "aspeed,ast2400-i2c-bus" },
 	{ .compatible = "aspeed,ast2500-i2c-bus" },
+	{ .compatible = "aspeed,ast2600-i2c-bus" },
 	{ },
 };
 
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 92264e5935b..e839c08c191 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -326,6 +326,12 @@ config MXC_OCOTP
 	  Programmable memory pages that are stored on the some
 	  Freescale i.MX processors.
 
+config NPCM_HOST
+	bool "Enable support espi or LPC for Host"
+	depends on REGMAP && SYSCON
+	help
+	  Enable NPCM BMC espi or LPC support for Host reading and writing.
+
 config SPL_MXC_OCOTP
 	bool "Enable MXC OCOTP driver in SPL"
 	depends on SPL_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 0bf05ca05ef..022e54e0650 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_$(SPL_TPL_)LS2_SFP) += ls2_sfp.o
 obj-$(CONFIG_$(SPL_)MXC_OCOTP) += mxc_ocotp.o
 obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
 obj-$(CONFIG_NPCM_OTP) += npcm_otp.o
+obj-$(CONFIG_NPCM_HOST) += npcm_host_intf.o
 obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
 obj-$(CONFIG_P2SB) += p2sb-uclass.o
 obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
diff --git a/drivers/misc/npcm_host_intf.c b/drivers/misc/npcm_host_intf.c
new file mode 100644
index 00000000000..0244e404570
--- /dev/null
+++ b/drivers/misc/npcm_host_intf.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Host interface (LPC or eSPI) configuration on Nuvoton BMC
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <linux/bitfield.h>
+
+#define SMC_CTL_REG_ADDR	0xc0001001
+#define SMC_CTL_HOSTWAIT	0x80
+
+/* GCR Register Offsets */
+#define HIFCR			0x50
+#define MFSEL1			0x260
+#define MFSEL4			0x26c
+
+/* ESPI Register offsets */
+#define ESPICFG			0x4
+#define ESPIHINDP		0x80
+
+/* MFSEL bit fileds */
+#define MFSEL1_LPCSEL		BIT(26)
+#define MFSEL4_ESPISEL		BIT(8)
+
+/* ESPICFG bit fileds */
+#define CHSUPP_MASK		GENMASK(27, 24)
+#define IOMODE_MASK		GENMASK(9, 8)
+#define IOMODE_SDQ		FIELD_PREP(IOMODE_MASK, 3)
+#define MAXFREQ_MASK		GENMASK(12, 10)
+#define MAXFREQ_33MHZ		FIELD_PREP(MAXFREQ_MASK, 2)
+
+/* ESPIHINDP bit fileds */
+#define AUTO_SBLD		BIT(4)
+#define AUTO_HS1		BIT(8)
+#define AUTO_HS2		BIT(12)
+#define AUTO_HS3		BIT(16)
+
+static int npcm_host_intf_bind(struct udevice *dev)
+{
+	struct regmap *syscon;
+	void __iomem *base;
+	u32 ch_supp, val;
+	u32 ioaddr;
+	const char *type;
+	int ret;
+
+	/* Release host wait */
+	setbits_8(SMC_CTL_REG_ADDR, SMC_CTL_HOSTWAIT);
+
+	syscon = syscon_regmap_lookup_by_phandle(dev, "syscon");
+	if (IS_ERR(syscon)) {
+		dev_err(dev, "%s: unable to get syscon, dev %s\n", __func__, dev->name);
+		return PTR_ERR(syscon);
+	}
+
+	ioaddr  = dev_read_u32_default(dev, "ioaddr", 0);
+	if (ioaddr)
+		regmap_write(syscon, HIFCR, ioaddr);
+
+	type = dev_read_string(dev, "type");
+	if (!type)
+		return -EINVAL;
+
+	if (!strcmp(type, "espi")) {
+		base = dev_read_addr_ptr(dev);
+		if (!base)
+			return -EINVAL;
+
+		ret = dev_read_u32(dev, "channel-support", &ch_supp);
+		if (ret)
+			return ret;
+
+		/* Select eSPI pins function */
+		regmap_update_bits(syscon, MFSEL1, MFSEL1_LPCSEL, 0);
+		regmap_update_bits(syscon, MFSEL4, MFSEL4_ESPISEL, MFSEL4_ESPISEL);
+
+		val = AUTO_SBLD | AUTO_HS1 | AUTO_HS2 | AUTO_HS3 | ch_supp;
+		writel(val, base + ESPIHINDP);
+
+		val = readl(base + ESPICFG);
+		val &= ~(CHSUPP_MASK | IOMODE_MASK | MAXFREQ_MASK);
+		val |= IOMODE_SDQ | MAXFREQ_33MHZ | FIELD_PREP(CHSUPP_MASK, ch_supp);
+		writel(val, base + ESPICFG);
+	} else if (!strcmp(type, "lpc")) {
+		/* Select LPC pin function */
+		regmap_update_bits(syscon, MFSEL4, MFSEL4_ESPISEL, 0);
+		regmap_update_bits(syscon, MFSEL1, MFSEL1_LPCSEL, MFSEL1_LPCSEL);
+	}
+
+	return 0;
+}
+
+static const struct udevice_id npcm_hostintf_ids[] = {
+	{ .compatible = "nuvoton,npcm750-host-intf" },
+	{ .compatible = "nuvoton,npcm845-host-intf" },
+	{ }
+};
+
+U_BOOT_DRIVER(npcm_host_intf) = {
+	.name	= "npcm_host_intf",
+	.id	= UCLASS_MISC,
+	.of_match = npcm_hostintf_ids,
+	.bind = npcm_host_intf_bind,
+};
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 53a6b0093d1..b44cd98150f 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -502,6 +502,7 @@ config MMC_SDHCI_ASPEED
 	depends on ARCH_ASPEED
 	depends on DM_MMC
 	depends on MMC_SDHCI
+	select MISC
 	help
 	  Enables support for the Aspeed SDHCI 2.0 controller present on Aspeed
 	  SoCs. This device is compatible with SD 3.0 and/or MMC 4.3
diff --git a/drivers/mmc/aspeed_sdhci.c b/drivers/mmc/aspeed_sdhci.c
index 45373157198..9d79bf58cc7 100644
--- a/drivers/mmc/aspeed_sdhci.c
+++ b/drivers/mmc/aspeed_sdhci.c
@@ -10,6 +10,7 @@
 #include <malloc.h>
 #include <sdhci.h>
 #include <linux/err.h>
+#include <dm/lists.h>
 
 struct aspeed_sdhci_plat {
 	struct mmc_config cfg;
@@ -26,12 +27,16 @@ static int aspeed_sdhci_probe(struct udevice *dev)
 	int ret;
 
 	ret = clk_get_by_index(dev, 0, &clk);
-	if (ret)
+	if (ret) {
+		debug("%s: clock get failed %d\n", __func__, ret);
 		return ret;
+	}
 
 	ret = clk_enable(&clk);
-	if (ret)
+	if (ret) {
+		debug("%s: clock enable failed %d\n", __func__, ret);
 		goto free;
+	}
 
 	host->name = dev->name;
 	host->ioaddr = dev_read_addr_ptr(dev);
@@ -39,6 +44,7 @@ static int aspeed_sdhci_probe(struct udevice *dev)
 	max_clk = clk_get_rate(&clk);
 	if (IS_ERR_VALUE(max_clk)) {
 		ret = max_clk;
+		debug("%s: clock rate get failed %d\n", __func__, ret);
 		goto err;
 	}
 
@@ -89,3 +95,38 @@ U_BOOT_DRIVER(aspeed_sdhci_drv) = {
 	.priv_auto	= sizeof(struct sdhci_host),
 	.plat_auto	= sizeof(struct aspeed_sdhci_plat),
 };
+
+
+static int aspeed_sdc_probe(struct udevice *parent)
+{
+	struct clk clk;
+	int ret;
+
+	ret = clk_get_by_index(parent, 0, &clk);
+	if (ret) {
+		debug("%s: clock get failed %d\n", __func__, ret);
+		return ret;
+	}
+
+	ret = clk_enable(&clk);
+	if (ret) {
+		debug("%s: clock enable failed %d\n", __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct udevice_id aspeed_sdc_ids[] = {
+	{ .compatible = "aspeed,ast2400-sd-controller" },
+	{ .compatible = "aspeed,ast2500-sd-controller" },
+	{ .compatible = "aspeed,ast2600-sd-controller" },
+	{ }
+};
+
+U_BOOT_DRIVER(aspeed_sdc_drv) = {
+	.name		= "aspeed_sdc",
+	.id		= UCLASS_MISC,
+	.of_match	= aspeed_sdc_ids,
+	.probe		= aspeed_sdc_probe,
+};
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index c01d9e09b90..4a3856d3c2f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -274,6 +274,13 @@ config PHY_MTK_TPHY
 	  multi-ports is first version, otherwise is second veriosn,
 	  so you can easily distinguish them by banks layout.
 
+config PHY_NPCM_USB
+	bool "Nuvoton NPCM USB PHY support"
+	depends on PHY
+	depends on ARCH_NPCM
+	help
+	  Support the USB PHY in NPCM SoCs
+
 config PHY_IMX8MQ_USB
 	bool "NXP i.MX8MQ/i.MX8MP USB PHY Driver"
 	depends on PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index bf9b40932fe..d95439c4257 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_MT7620_USB_PHY) += mt7620-usb-phy.o
 obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o
 obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o
 obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
+obj-$(CONFIG_PHY_NPCM_USB) += phy-npcm-usb.o
 obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o
 obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o
 obj-y += cadence/
diff --git a/drivers/phy/phy-npcm-usb.c b/drivers/phy/phy-npcm-usb.c
new file mode 100644
index 00000000000..24eba665543
--- /dev/null
+++ b/drivers/phy/phy-npcm-usb.c
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corp.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <reset.h>
+#include <syscon.h>
+#include <dm/device_compat.h>
+#include <linux/bitfield.h>
+#include <linux/delay.h>
+
+/* GCR Register Offsets */
+#define GCR_INTCR3	0x9C
+#define GCR_USB1PHYCTL	0x140
+#define GCR_USB2PHYCTL	0x144
+#define GCR_USB3PHYCTL	0x148
+
+/* USBnPHYCTL bit fields */
+#define PHYCTL_RS	BIT(28)
+
+#define USBPHY2SW	GENMASK(13, 12)
+#define USBPHY3SW	GENMASK(15, 14)
+
+#define USBPHY2SW_DEV9_PHY1	FIELD_PREP(USBPHY2SW, 0)
+#define USBPHY2SW_HOST1		FIELD_PREP(USBPHY2SW, 1)
+#define USBPHY2SW_DEV9_PHY2	FIELD_PREP(USBPHY2SW, 3)
+#define USBPHY3SW_DEV8_PHY1	FIELD_PREP(USBPHY3SW, 0)
+#define USBPHY3SW_HOST2		FIELD_PREP(USBPHY3SW, 1)
+#define USBPHY3SW_DEV8_PHY3	FIELD_PREP(USBPHY3SW, 3)
+
+enum controller_id {
+	UDC0_7,
+	UDC8,
+	UDC9,
+	USBH1,
+	USBH2,
+};
+
+enum phy_id {
+	PHY1 = 1,
+	PHY2,
+	PHY3,
+};
+
+/* Phy Switch Settings */
+#define USBDPHY1	((PHY1 << 8) | UDC0_7)	/* Connect UDC0~7 to PHY1 */
+#define USBD8PHY1	((PHY1 << 8) | UDC8)	/* Connect UDC8 to PHY1 */
+#define USBD9PHY1	((PHY1 << 8) | UDC9)	/* Connect UDC9 to PHY1 */
+#define USBD9PHY2	((PHY2 << 8) | UDC9)	/* Connect UDC9 to PHY2 */
+#define USBH1PHY2	((PHY2 << 8) | USBH1)	/* Connect USBH1 to PHY2 */
+#define USBD8PHY3	((PHY3 << 8) | UDC8)	/* Connect UDC8 to PHY3 */
+#define USBH2PHY3	((PHY3 << 8) | USBH2)	/* Connect USBH2 to PHY3 */
+
+struct npcm_usbphy {
+	struct regmap *syscon;
+	u8 id;
+	u16 phy_switch;	/* (phy_id << 8) | controller_id */
+};
+
+static int npcm_usb_phy_init(struct phy *phy)
+{
+	struct npcm_usbphy *priv = dev_get_priv(phy->dev);
+	struct reset_ctl reset;
+	int ret;
+
+	ret = reset_get_by_index(phy->dev, 0, &reset);
+	if (ret && ret != -ENOENT && ret != -ENOTSUPP) {
+		dev_err(phy->dev, "can't get phy reset ctrl (err %d)", ret);
+		return ret;
+	}
+
+	/* setup PHY switch */
+	switch (priv->phy_switch) {
+	case USBD8PHY1:
+		regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY3SW,
+				   USBPHY3SW_DEV8_PHY1);
+		break;
+	case USBD8PHY3:
+		regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY3SW,
+				   USBPHY3SW_DEV8_PHY3);
+		break;
+	case USBD9PHY1:
+		regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY2SW,
+				   USBPHY2SW_DEV9_PHY1);
+		break;
+	case USBD9PHY2:
+		regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY2SW,
+				   USBPHY2SW_DEV9_PHY2);
+		break;
+	case USBH1PHY2:
+		regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY2SW,
+				   USBPHY2SW_HOST1);
+		break;
+	case USBH2PHY3:
+		regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY3SW,
+				   USBPHY3SW_HOST2);
+		break;
+	default:
+		break;
+	}
+	/* reset phy */
+	if (reset_valid(&reset))
+		reset_assert(&reset);
+
+	/* Wait for PHY clocks to stablize for 50us or more */
+	udelay(100);
+
+	/* release phy from reset */
+	if (reset_valid(&reset))
+		reset_deassert(&reset);
+
+	/* PHY RS bit should be set after reset */
+	switch (priv->id) {
+	case PHY1:
+		regmap_update_bits(priv->syscon, GCR_USB1PHYCTL, PHYCTL_RS, PHYCTL_RS);
+		break;
+	case PHY2:
+		regmap_update_bits(priv->syscon, GCR_USB2PHYCTL, PHYCTL_RS, PHYCTL_RS);
+		break;
+	case PHY3:
+		regmap_update_bits(priv->syscon, GCR_USB3PHYCTL, PHYCTL_RS, PHYCTL_RS);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int npcm_usb_phy_exit(struct phy *phy)
+{
+	struct npcm_usbphy *priv = dev_get_priv(phy->dev);
+
+	/* set PHY switch to default state */
+	switch (priv->phy_switch) {
+	case USBD8PHY1:
+	case USBD8PHY3:
+		regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY3SW,
+				   USBPHY3SW_HOST2);
+		break;
+	case USBD9PHY1:
+	case USBD9PHY2:
+		regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY2SW,
+				   USBPHY2SW_HOST1);
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+static int  npcm_usb_phy_xlate(struct phy *phy, struct ofnode_phandle_args *args)
+{
+	struct npcm_usbphy *priv = dev_get_priv(phy->dev);
+	u16 phy_switch;
+
+	if (args->args_count < 1 || args->args[0] > USBH2)
+		return -EINVAL;
+
+	phy_switch = (priv->id << 8) | args->args[0];
+	switch (phy_switch) {
+	case USBD9PHY1:
+	case USBH2PHY3:
+	case USBD8PHY3:
+		if (!IS_ENABLED(CONFIG_ARCH_NPCM8XX))
+			return -EINVAL;
+	case USBDPHY1:
+	case USBD8PHY1:
+	case USBD9PHY2:
+	case USBH1PHY2:
+		priv->phy_switch = phy_switch;
+		return 0;
+	default:
+		return -EINVAL;
+	}
+}
+
+static int npcm_usb_phy_probe(struct udevice *dev)
+{
+	struct npcm_usbphy *priv = dev_get_priv(dev);
+
+	priv->syscon = syscon_regmap_lookup_by_phandle(dev->parent, "syscon");
+	if (IS_ERR(priv->syscon)) {
+		dev_err(dev, "%s: unable to get syscon\n", __func__);
+		return PTR_ERR(priv->syscon);
+	}
+	priv->id = dev_read_u32_default(dev, "reg", -1);
+
+	return 0;
+}
+
+static const struct udevice_id npcm_phy_ids[] = {
+	{ .compatible = "nuvoton,npcm845-usb-phy",},
+	{ .compatible = "nuvoton,npcm750-usb-phy",},
+	{ }
+};
+
+static struct phy_ops npcm_phy_ops = {
+	.init = npcm_usb_phy_init,
+	.exit = npcm_usb_phy_exit,
+	.of_xlate = npcm_usb_phy_xlate,
+};
+
+U_BOOT_DRIVER(npcm_phy) = {
+	.name	= "npcm-usb-phy",
+	.id	= UCLASS_PHY,
+	.of_match = npcm_phy_ids,
+	.ops = &npcm_phy_ops,
+	.probe		= npcm_usb_phy_probe,
+	.priv_auto	= sizeof(struct npcm_usbphy),
+};
diff --git a/drivers/reset/reset-ast2500.c b/drivers/reset/reset-ast2500.c
index 0a1dd236aff..d9cecf3a72e 100644
--- a/drivers/reset/reset-ast2500.c
+++ b/drivers/reset/reset-ast2500.c
@@ -48,6 +48,24 @@ static int ast2500_reset_deassert(struct reset_ctl *reset_ctl)
 	return 0;
 }
 
+static int ast2500_reset_status(struct reset_ctl *reset_ctl)
+{
+	struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	struct ast2500_scu *scu = priv->scu;
+	int status;
+
+	debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
+
+	if (reset_ctl->id < 32)
+		status = BIT(reset_ctl->id) & readl(&scu->sysreset_ctrl1);
+	else
+		status = BIT(reset_ctl->id - 32) & readl(&scu->sysreset_ctrl2);
+
+	return !!status;
+}
+
+
+
 static int ast2500_reset_probe(struct udevice *dev)
 {
 	int rc;
@@ -79,6 +97,7 @@ static const struct udevice_id ast2500_reset_ids[] = {
 struct reset_ops ast2500_reset_ops = {
 	.rst_assert = ast2500_reset_assert,
 	.rst_deassert = ast2500_reset_deassert,
+	.rst_status = ast2500_reset_status,
 };
 
 U_BOOT_DRIVER(ast2500_reset) = {
diff --git a/drivers/reset/reset-ast2600.c b/drivers/reset/reset-ast2600.c
index 985235a3ac4..1732a450efc 100644
--- a/drivers/reset/reset-ast2600.c
+++ b/drivers/reset/reset-ast2600.c
@@ -47,6 +47,22 @@ static int ast2600_reset_deassert(struct reset_ctl *reset_ctl)
 	return 0;
 }
 
+static int ast2600_reset_status(struct reset_ctl *reset_ctl)
+{
+	struct ast2600_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	struct ast2600_scu *scu = priv->scu;
+	int status;
+
+	debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
+
+	if (reset_ctl->id < 32)
+		status = BIT(reset_ctl->id) & readl(&scu->modrst_ctrl1);
+	else
+		status = BIT(reset_ctl->id - 32) & readl(&scu->modrst_ctrl2);
+
+	return !!status;
+}
+
 static int ast2600_reset_probe(struct udevice *dev)
 {
 	int rc;
@@ -78,6 +94,7 @@ static const struct udevice_id ast2600_reset_ids[] = {
 struct reset_ops ast2600_reset_ops = {
 	.rst_assert = ast2600_reset_assert,
 	.rst_deassert = ast2600_reset_deassert,
+	.rst_status = ast2600_reset_status,
 };
 
 U_BOOT_DRIVER(ast2600_reset) = {
diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
index 42344145f9f..b1e7c4ae5f6 100644
--- a/drivers/soc/soc_ti_k3.c
+++ b/drivers/soc/soc_ti_k3.c
@@ -64,8 +64,8 @@ static char *j721e_rev_string_map[] = {
 	"1.0", "1.1",
 };
 
-static char *am65x_rev_string_map[] = {
-	"1.0", "2.0",
+static char *typical_rev_string_map[] = {
+	"1.0", "2.0", "3.0",
 };
 
 static const char *get_rev_string(u32 idreg)
@@ -82,16 +82,10 @@ static const char *get_rev_string(u32 idreg)
 			goto bail;
 		return j721e_rev_string_map[rev];
 
-	case AM65X:
-		if (rev > ARRAY_SIZE(am65x_rev_string_map))
-			goto bail;
-		return am65x_rev_string_map[rev];
-
-	case AM64X:
-	case J7200:
 	default:
-		if (!rev)
-			return "1.0";
+		if (rev > ARRAY_SIZE(typical_rev_string_map))
+			goto bail;
+		return typical_rev_string_map[rev];
 	};
 
 bail: