dt-bindings: clock: sifive: sync FU740 PRCI clock binding header

This commit sychronizes the header file for FU740 PRCI clocks with the
one from Linux 5.19.

The constant values are the same, but all constant names are changed
(most are just prefixed with FU740_).

Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>

2 files changed, 11 insertions, 11 deletions

diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c
index b025050e224..5edc864e4bd 100644
--- a/drivers/clk/sifive/fu740-prci.c
+++ b/drivers/clk/sifive/fu740-prci.c
@@ -103,53 +103,53 @@ static const struct __prci_clock_ops sifive_fu740_prci_pcieaux_clk_ops = {
 
 /* List of clock controls provided by the PRCI */
 struct __prci_clock __prci_init_clocks_fu740[] = {
-	[PRCI_CLK_COREPLL] = {
+	[FU740_PRCI_CLK_COREPLL] = {
 		.name = "corepll",
 		.parent_name = "hfclk",
 		.ops = &sifive_fu740_prci_wrpll_clk_ops,
 		.pwd = &__prci_corepll_data,
 	},
-	[PRCI_CLK_DDRPLL] = {
+	[FU740_PRCI_CLK_DDRPLL] = {
 		.name = "ddrpll",
 		.parent_name = "hfclk",
 		.ops = &sifive_fu740_prci_wrpll_clk_ops,
 		.pwd = &__prci_ddrpll_data,
 	},
-	[PRCI_CLK_GEMGXLPLL] = {
+	[FU740_PRCI_CLK_GEMGXLPLL] = {
 		.name = "gemgxlpll",
 		.parent_name = "hfclk",
 		.ops = &sifive_fu740_prci_wrpll_clk_ops,
 		.pwd = &__prci_gemgxlpll_data,
 	},
-	[PRCI_CLK_DVFSCOREPLL] = {
+	[FU740_PRCI_CLK_DVFSCOREPLL] = {
 		.name = "dvfscorepll",
 		.parent_name = "hfclk",
 		.ops = &sifive_fu740_prci_wrpll_clk_ops,
 		.pwd = &__prci_dvfscorepll_data,
 	},
-	[PRCI_CLK_HFPCLKPLL] = {
+	[FU740_PRCI_CLK_HFPCLKPLL] = {
 		.name = "hfpclkpll",
 		.parent_name = "hfclk",
 		.ops = &sifive_fu740_prci_wrpll_clk_ops,
 		.pwd = &__prci_hfpclkpll_data,
 	},
-	[PRCI_CLK_CLTXPLL] = {
+	[FU740_PRCI_CLK_CLTXPLL] = {
 		.name = "cltxpll",
 		.parent_name = "hfclk",
 		.ops = &sifive_fu740_prci_wrpll_clk_ops,
 		.pwd = &__prci_cltxpll_data,
 	},
-	[PRCI_CLK_TLCLK] = {
+	[FU740_PRCI_CLK_TLCLK] = {
 		.name = "tlclk",
 		.parent_name = "corepll",
 		.ops = &sifive_fu740_prci_tlclksel_clk_ops,
 	},
-	[PRCI_CLK_PCLK] = {
+	[FU740_PRCI_CLK_PCLK] = {
 		.name = "pclk",
 		.parent_name = "hfpclkpll",
 		.ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
 	},
-	[PRCI_CLK_PCIEAUX] {
+	[FU740_PRCI_CLK_PCIE_AUX] {
 		.name = "pcieaux",
 		.parent_name = "",
 		.ops = &sifive_fu740_prci_pcieaux_clk_ops,
diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c
index 52ae268e0c8..c8fb6002907 100644
--- a/drivers/clk/sifive/sifive-prci.c
+++ b/drivers/clk/sifive/sifive-prci.c
@@ -685,14 +685,14 @@ static int sifive_prci_probe(struct udevice *dev)
 				 * case the design uses hfpclk to drive
 				 * Chiplink
 				 */
-				pc = &data->clks[PRCI_CLK_HFPCLKPLL];
+				pc = &data->clks[FU740_PRCI_CLK_HFPCLKPLL];
 				parent_rate = sifive_prci_parent_rate(pc, data);
 				sifive_prci_wrpll_set_rate(pc, 260000000,
 							   parent_rate);
 				pc->ops->enable_clk(pc, 1);
 			} else if (prci_pll_reg & PRCI_PRCIPLL_CLTXPLL) {
 				/* CLTX pll init */
-				pc = &data->clks[PRCI_CLK_CLTXPLL];
+				pc = &data->clks[FU740_PRCI_CLK_CLTXPLL];
 				parent_rate = sifive_prci_parent_rate(pc, data);
 				sifive_prci_wrpll_set_rate(pc, 260000000,
 							   parent_rate);