dm: pcie_fsl: Fix the Class Code fixup function

The Class Code fixup method was changed from PCIe block
revision 3.0, the current fixup is only valid for the
revision 3.0 and the later ones.

So add the Class Code fixup for the block revision < 3.0.

Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>

2 files changed, 16 insertions, 4 deletions

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 1879d8104c2..1be50634674 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -503,14 +503,23 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie)
 static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
 {
 	ccsr_fsl_pci_t *regs = pcie->regs;
+	u32 classcode_reg;
 	u32 val;
 
-	setbits_be32(&regs->dbi_ro_wr_en, 0x01);
-	fsl_pcie_hose_read_config_dword(pcie, PCI_CLASS_REVISION, &val);
+	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
+		classcode_reg = PCI_CLASS_REVISION;
+		setbits_be32(&regs->dbi_ro_wr_en, 0x01);
+	} else {
+		classcode_reg = CSR_CLASSCODE;
+	}
+
+	fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val);
 	val &= 0xff;
 	val |= PCI_CLASS_BRIDGE_PCI << 16;
-	fsl_pcie_hose_write_config_dword(pcie, PCI_CLASS_REVISION, val);
-	clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
+	fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val);
+
+	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0)
+		clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
 
 	return 0;
 }
diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h
index 5eefc31fa9a..032775ca05d 100644
--- a/drivers/pci/pcie_fsl.h
+++ b/drivers/pci/pcie_fsl.h
@@ -9,6 +9,9 @@
 #ifndef _PCIE_FSL_H_
 #define _PCIE_FSL_H_
 
+/* GPEX CSR */
+#define CSR_CLASSCODE			0x474
+
 #ifdef CONFIG_SYS_FSL_PCI_VER_3_X
 #define FSL_PCIE_CAP_ID			0x70
 #else