Merge git://git.denx.de/u-boot-sh

4 files changed, 164 insertions, 27 deletions

diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c
index 260bb892d60..4ba18b18bea 100644
--- a/drivers/clk/renesas/r8a7792-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c
@@ -39,7 +39,7 @@ enum clk_ids {
 	MOD_CLK_BASE
 };
 
-static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
+static const struct cpg_core_clk r8a7792_core_clks[] = {
 	/* External Clock Inputs */
 	DEF_INPUT("extal",     CLK_EXTAL),
 
@@ -78,7 +78,7 @@ static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
 	DEF_FIXED("osc",    R8A7792_CLK_OSC,   CLK_PLL1,      12288, 1),
 };
 
-static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = {
+static const struct mssr_mod_clk r8a7792_mod_clks[] = {
 	DEF_MOD("msiof0",		   0,	R8A7792_CLK_MP),
 	DEF_MOD("jpu",			 106,	R8A7792_CLK_M2),
 	DEF_MOD("tmu1",			 111,	R8A7792_CLK_P),
@@ -152,10 +152,6 @@ static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = {
 	DEF_MOD("ssi3",			1012,	MOD_CLK_ID(1005)),
 };
 
-static const unsigned int r8a7792_crit_mod_clks[] __initconst = {
-	MOD_CLK_ID(408),	/* INTC-SYS (GIC) */
-};
-
 /*
  * CPG Clock Data
  */
@@ -179,7 +175,7 @@ static const unsigned int r8a7792_crit_mod_clks[] __initconst = {
 #define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 12) | \
 					 (((md) & BIT(13)) >> 12) | \
 					 (((md) & BIT(19)) >> 19))
-static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
 	{ 1, 208, 106, 200 },
 	{ 1, 208,  88, 200 },
 	{ 1, 156,  80, 150 },
diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c b/drivers/clk/renesas/r8a7794-cpg-mssr.c
index 90bac3deedb..e8f57c3d015 100644
--- a/drivers/clk/renesas/r8a7794-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c
@@ -40,7 +40,7 @@ enum clk_ids {
 	MOD_CLK_BASE
 };
 
-static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
+static const struct cpg_core_clk r8a7794_core_clks[] = {
 	/* External Clock Inputs */
 	DEF_INPUT("extal",     CLK_EXTAL),
 	DEF_INPUT("usb_extal", CLK_USB_EXTAL),
@@ -85,7 +85,7 @@ static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
 	DEF_DIV6P1("mmc0",  R8A7794_CLK_MMC0,  CLK_PLL1_DIV2, 0x240),
 };
 
-static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = {
+static const struct mssr_mod_clk r8a7794_mod_clks[] = {
 	DEF_MOD("msiof0",		   0,	R8A7794_CLK_MP),
 	DEF_MOD("vcp0",			 101,	R8A7794_CLK_ZS),
 	DEF_MOD("vpc0",			 103,	R8A7794_CLK_ZS),
@@ -188,10 +188,6 @@ static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = {
 	DEF_MOD("scifa5",		1108,	R8A7794_CLK_MP),
 };
 
-static const unsigned int r8a7794_crit_mod_clks[] __initconst = {
-	MOD_CLK_ID(408),	/* INTC-SYS (GIC) */
-};
-
 /*
  * CPG Clock Data
  */
@@ -210,7 +206,7 @@ static const unsigned int r8a7794_crit_mod_clks[] __initconst = {
  */
 #define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 13) | \
 					 (((md) & BIT(13)) >> 13))
-static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] __initconst = {
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] = {
 	{ 1, 208,  88, 200 },
 	{ 1, 156,  66, 150 },
 	{ 2, 240, 102, 230 },
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 6935da2177d..4fa8dd83bb7 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -266,6 +266,12 @@ config SH_SDHI
 	help
 	  Support for the on-chip SDHI host controller on SuperH/Renesas ARM SoCs platform
 
+config SH_MMCIF
+	bool "SuperH/Renesas ARM SoCs on-chip MMCIF host controller support"
+	depends on ARCH_RMOBILE || SH
+	help
+	  Support for the on-chip MMCIF host controller on SuperH/Renesas ARM SoCs platform
+
 config MMC_UNIPHIER
 	bool "UniPhier SD/MMC Host Controller support"
 	depends on ARCH_UNIPHIER
diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c
index 1ff59f06d57..26fe125cea7 100644
--- a/drivers/mmc/sh_mmcif.c
+++ b/drivers/mmc/sh_mmcif.c
@@ -11,9 +11,13 @@
 #include <watchdog.h>
 #include <command.h>
 #include <mmc.h>
+#include <clk.h>
+#include <dm.h>
 #include <malloc.h>
 #include <linux/errno.h>
-#include <asm/io.h>
+#include <linux/compat.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
 #include "sh_mmcif.h"
 
 #define DRIVER_NAME	"sh_mmcif"
@@ -510,10 +514,9 @@ static int sh_mmcif_start_cmd(struct sh_mmcif_host *host,
 	return ret;
 }
 
-static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd,
-			    struct mmc_data *data)
+static int sh_mmcif_send_cmd_common(struct sh_mmcif_host *host,
+				    struct mmc_cmd *cmd, struct mmc_data *data)
 {
-	struct sh_mmcif_host *host = mmc->priv;
 	int ret;
 
 	WATCHDOG_RESET();
@@ -539,10 +542,8 @@ static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd,
 	return ret;
 }
 
-static int sh_mmcif_set_ios(struct mmc *mmc)
+static int sh_mmcif_set_ios_common(struct sh_mmcif_host *host, struct mmc *mmc)
 {
-	struct sh_mmcif_host *host = mmc->priv;
-
 	if (mmc->clock)
 		sh_mmcif_clock_control(host, mmc->clock);
 
@@ -558,19 +559,45 @@ static int sh_mmcif_set_ios(struct mmc *mmc)
 	return 0;
 }
 
-static int sh_mmcif_init(struct mmc *mmc)
+static int sh_mmcif_initialize_common(struct sh_mmcif_host *host)
 {
-	struct sh_mmcif_host *host = mmc->priv;
-
 	sh_mmcif_sync_reset(host);
 	sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask);
 	return 0;
 }
 
+#ifndef CONFIG_DM_MMC
+static void *mmc_priv(struct mmc *mmc)
+{
+	return (void *)mmc->priv;
+}
+
+static int sh_mmcif_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+			    struct mmc_data *data)
+{
+	struct sh_mmcif_host *host = mmc_priv(mmc);
+
+	return sh_mmcif_send_cmd_common(host, cmd, data);
+}
+
+static int sh_mmcif_set_ios(struct mmc *mmc)
+{
+	struct sh_mmcif_host *host = mmc_priv(mmc);
+
+	return sh_mmcif_set_ios_common(host, mmc);
+}
+
+static int sh_mmcif_initialize(struct mmc *mmc)
+{
+	struct sh_mmcif_host *host = mmc_priv(mmc);
+
+	return sh_mmcif_initialize_common(host);
+}
+
 static const struct mmc_ops sh_mmcif_ops = {
-	.send_cmd	= sh_mmcif_request,
-	.set_ios	= sh_mmcif_set_ios,
-	.init		= sh_mmcif_init,
+	.send_cmd       = sh_mmcif_send_cmd,
+	.set_ios        = sh_mmcif_set_ios,
+	.init           = sh_mmcif_initialize,
 };
 
 static struct mmc_config sh_mmcif_cfg = {
@@ -606,3 +633,115 @@ int mmcif_mmc_init(void)
 
 	return 0;
 }
+
+#else
+struct sh_mmcif_plat {
+	struct mmc_config cfg;
+	struct mmc mmc;
+};
+
+int sh_mmcif_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+			struct mmc_data *data)
+{
+	struct sh_mmcif_host *host = dev_get_priv(dev);
+
+	return sh_mmcif_send_cmd_common(host, cmd, data);
+}
+
+int sh_mmcif_dm_set_ios(struct udevice *dev)
+{
+	struct sh_mmcif_host *host = dev_get_priv(dev);
+	struct mmc *mmc = mmc_get_mmc_dev(dev);
+
+	return sh_mmcif_set_ios_common(host, mmc);
+}
+
+static const struct dm_mmc_ops sh_mmcif_dm_ops = {
+	.send_cmd	= sh_mmcif_dm_send_cmd,
+	.set_ios	= sh_mmcif_dm_set_ios,
+};
+
+static int sh_mmcif_dm_bind(struct udevice *dev)
+{
+	struct sh_mmcif_plat *plat = dev_get_platdata(dev);
+
+	return mmc_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static int sh_mmcif_dm_probe(struct udevice *dev)
+{
+	struct sh_mmcif_plat *plat = dev_get_platdata(dev);
+	struct sh_mmcif_host *host = dev_get_priv(dev);
+	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+	struct clk sh_mmcif_clk;
+	fdt_addr_t base;
+	int ret;
+
+	base = devfdt_get_addr(dev);
+	if (base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	host->regs = (struct sh_mmcif_regs *)devm_ioremap(dev, base, SZ_2K);
+	if (!host->regs)
+		return -ENOMEM;
+
+	ret = clk_get_by_index(dev, 0, &sh_mmcif_clk);
+	if (ret) {
+		debug("failed to get clock, ret=%d\n", ret);
+		return ret;
+	}
+
+	ret = clk_enable(&sh_mmcif_clk);
+	if (ret) {
+		debug("failed to enable clock, ret=%d\n", ret);
+		return ret;
+	}
+
+	host->clk = clk_get_rate(&sh_mmcif_clk);
+
+	plat->cfg.name = dev->name;
+	plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
+
+	switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
+			       1)) {
+	case 8:
+		plat->cfg.host_caps |= MMC_MODE_8BIT;
+		break;
+	case 4:
+		plat->cfg.host_caps |= MMC_MODE_4BIT;
+		break;
+	case 1:
+		break;
+	default:
+		dev_err(dev, "Invalid \"bus-width\" value\n");
+		return -EINVAL;
+	}
+
+	sh_mmcif_initialize_common(host);
+
+	plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
+	plat->cfg.f_min = MMC_CLK_DIV_MIN(host->clk);
+	plat->cfg.f_max = MMC_CLK_DIV_MAX(host->clk);
+	plat->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+
+	upriv->mmc = &plat->mmc;
+
+	return 0;
+}
+
+static const struct udevice_id sh_mmcif_sd_match[] = {
+	{ .compatible = "renesas,sh-mmcif" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(sh_mmcif_mmc) = {
+	.name			= "sh-mmcif",
+	.id			= UCLASS_MMC,
+	.of_match		= sh_mmcif_sd_match,
+	.bind			= sh_mmcif_dm_bind,
+	.probe			= sh_mmcif_dm_probe,
+	.priv_auto_alloc_size	= sizeof(struct sh_mmcif_host),
+	.platdata_auto_alloc_size = sizeof(struct sh_mmcif_plat),
+	.ops			= &sh_mmcif_dm_ops,
+};
+#endif