Merge tag 'v2025.10-rc4' into next

Prepare v2025.10-rc4

26 files changed, 453 insertions, 217 deletions

diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c
index a5186f885f0..0542b066788 100644
--- a/drivers/clk/at91/clk-main.c
+++ b/drivers/clk/at91/clk-main.c
@@ -315,7 +315,8 @@ static int clk_sam9x5_main_set_parent(struct clk *clk, struct clk *parent)
 {
 	struct clk_main *main = to_clk_main(clk);
 	void __iomem *reg = main->reg;
-	unsigned int tmp, index;
+	unsigned int tmp;
+	int index;
 
 	index = at91_clk_mux_val_to_index(main->clk_mux_table,
 			main->num_parents, AT91_CLK_ID_TO_DID(parent->id));
diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
index cdc5271fa83..530205b8c6b 100644
--- a/drivers/clk/at91/clk-master.c
+++ b/drivers/clk/at91/clk-master.c
@@ -335,8 +335,8 @@ struct clk *at91_clk_sama7g5_register_master(void __iomem *base,
 {
 	struct clk_master *master;
 	struct clk *clk;
-	u32 val, index;
-	int ret;
+	u32 val;
+	int ret, index;
 
 	if (!base || !name || !num_parents || !parent_names ||
 	    !mux_table || !clk_mux_table || id > MASTER_MAX_ID)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index 6d6f12578db..3fde8ea7138 100644
--- a/drivers/clk/at91/sckc.c
+++ b/drivers/clk/at91/sckc.c
@@ -74,8 +74,8 @@ static struct clk *at91_sam9x60_clk_register_td_slck(struct sam9x60_sckc *sckc,
 		int num_parents)
 {
 	struct clk *clk;
-	int ret = -ENOMEM;
-	u32 val, i;
+	int ret = -ENOMEM, i;
+	u32 val;
 
 	if (!sckc || !name || !parent_names || num_parents != 2)
 		return ERR_PTR(-EINVAL);
@@ -99,8 +99,10 @@ static struct clk *at91_sam9x60_clk_register_td_slck(struct sam9x60_sckc *sckc,
 	clk = &sckc->clk;
 	ret = clk_register(clk, UBOOT_DM_CLK_AT91_SAM9X60_TD_SLCK, name,
 			   parent_names[val]);
-	if (ret)
+	if (ret) {
+		i--;
 		goto free;
+	}
 
 	return clk;
 
diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c
index 3aa751bf4e4..7de4e688f03 100644
--- a/drivers/clk/exynos/clk-exynos7420.c
+++ b/drivers/clk/exynos/clk-exynos7420.c
@@ -192,7 +192,7 @@ static int exynos7420_clk_top0_probe(struct udevice *dev)
 static ulong exynos7420_peric1_get_rate(struct clk *clk)
 {
 	struct clk in_clk;
-	unsigned int ret;
+	int ret;
 	unsigned long freq = 0;
 
 	switch (clk->id) {
diff --git a/drivers/clk/rockchip/clk_rk3528.c b/drivers/clk/rockchip/clk_rk3528.c
index 06f20895acc..d58557ff56d 100644
--- a/drivers/clk/rockchip/clk_rk3528.c
+++ b/drivers/clk/rockchip/clk_rk3528.c
@@ -1535,6 +1535,7 @@ static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate)
 	/* Might occur in cru assigned-clocks, can be ignored here */
 	case ACLK_BUS_VOPGL_ROOT:
 	case BCLK_EMMC:
+	case CLK_REF_PCIE_INNER_PHY:
 	case XIN_OSC0_DIV:
 		ret = 0;
 		break;
diff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c
index e84a0943a94..125b08ee832 100644
--- a/drivers/clk/rockchip/clk_rk3576.c
+++ b/drivers/clk/rockchip/clk_rk3576.c
@@ -2168,6 +2168,8 @@ static ulong rk3576_clk_set_rate(struct clk *clk, ulong rate)
 	case CLK_CPLL_DIV10:
 	case FCLK_DDR_CM0_CORE:
 	case ACLK_PHP_ROOT:
+	case CLK_REF_PCIE0_PHY:
+	case CLK_REF_PCIE1_PHY:
 		ret = 0;
 		break;
 #ifndef CONFIG_SPL_BUILD
diff --git a/drivers/mfd/atmel-smc.c b/drivers/mfd/atmel-smc.c
index 15296f71a16..94e5e7b67a0 100644
--- a/drivers/mfd/atmel-smc.c
+++ b/drivers/mfd/atmel-smc.c
@@ -347,7 +347,7 @@ const struct atmel_hsmc_reg_layout *
 atmel_hsmc_get_reg_layout(ofnode np)
 {
 	int i;
-	const struct udevice_id *match;
+	const struct udevice_id *match = NULL;
 	const char *name;
 	int len;
 
diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c
index 6a531fa0961..838b4f4a65a 100644
--- a/drivers/mmc/gen_atmel_mci.c
+++ b/drivers/mmc/gen_atmel_mci.c
@@ -206,10 +206,9 @@ static u32 mci_data_read(atmel_mci_t *mci, u32* data, u32 error_flags)
 			goto io_fail;
 	} while (!(status & MMCI_BIT(RXRDY)));
 
-	if (status & MMCI_BIT(RXRDY)) {
-		*data = readl(&mci->rdr);
-		status = 0;
-	}
+	*data = readl(&mci->rdr);
+	status = 0;
+
 io_fail:
 	return status;
 }
@@ -225,10 +224,9 @@ static u32 mci_data_write(atmel_mci_t *mci, u32* data, u32 error_flags)
 			goto io_fail;
 	} while (!(status & MMCI_BIT(TXRDY)));
 
-	if (status & MMCI_BIT(TXRDY)) {
-		writel(*data, &mci->tdr);
-		status = 0;
-	}
+	writel(*data, &mci->tdr);
+	status = 0;
+
 io_fail:
 	return status;
 }
@@ -265,13 +263,15 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 	/* Figure out the transfer arguments */
 	cmdr = mci_encode_cmd(cmd, data, &error_flags);
 
-	mci_set_blklen(mci, data->blocksize);
+	if (data) {
+		mci_set_blklen(mci, data->blocksize);
 
-	/* For multi blocks read/write, set the block register */
-	if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK)
-			|| (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK))
-		writel(data->blocks | MMCI_BF(BLKLEN, data->blocksize),
-		       &mci->blkr);
+		/* For multi blocks read/write, set the block register */
+		if (cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK ||
+		    cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)
+			writel(data->blocks | MMCI_BF(BLKLEN, data->blocksize),
+			       &mci->blkr);
+	}
 
 	/* Send the command */
 	writel(cmd->cmdarg, &mci->argr);
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index 761e3619329..5e025d76a82 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -500,7 +500,7 @@ static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
 {
 	struct rockchip_sdhc *priv = dev_get_priv(mmc->dev);
 	struct sdhci_host *host = &priv->host;
-	char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
+	s8 tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
 	struct mmc_cmd cmd;
 	u32 ctrl, blk_size;
 	int ret;
diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c
index 9483fb57daf..122690aef3e 100644
--- a/drivers/mmc/stm32_sdmmc2.c
+++ b/drivers/mmc/stm32_sdmmc2.c
@@ -385,15 +385,29 @@ static int stm32_sdmmc2_end_data(struct udevice *dev,
 	u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT |
 		   SDMMC_STA_IDMATE | SDMMC_STA_DATAEND;
 	u32 status;
+	unsigned long timeout_msecs = ctx->data_length >> 8;
+	unsigned long start_timeout;
+
+	/* At least, a timeout of 2 seconds is set */
+	if (timeout_msecs < 2000)
+		timeout_msecs = 2000;
 
 	if (data->flags & MMC_DATA_READ)
 		mask |= SDMMC_STA_RXOVERR;
 	else
 		mask |= SDMMC_STA_TXUNDERR;
 
+	start_timeout = get_timer(0);
 	status = readl(plat->base + SDMMC_STA);
-	while (!(status & mask))
+	while (!(status & mask)) {
+		if (get_timer(start_timeout) > timeout_msecs) {
+			ctx->dpsm_abort = true;
+			return -ETIMEDOUT;
+		}
+
+		schedule();
 		status = readl(plat->base + SDMMC_STA);
+	}
 
 	/*
 	 * Need invalidate the dcache again to avoid any
diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
index d1c88643c98..21e3c88a55a 100644
--- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c
+++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
@@ -1034,6 +1034,7 @@ static int stm32_fmc2_nfc_probe(struct udevice *dev)
 		ecclayout->eccpos[i] = oob_index;
 	ecclayout->oobfree->offset = oob_index;
 	ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
+	ecclayout->oobavail = ecclayout->oobfree->length;
 	chip->ecc.layout = ecclayout;
 
 	if (chip->options & NAND_BUSWIDTH_16)
diff --git a/drivers/net/MAINTAINERS b/drivers/net/MAINTAINERS
new file mode 100644
index 00000000000..fd002295d0c
--- /dev/null
+++ b/drivers/net/MAINTAINERS
@@ -0,0 +1,6 @@
+NETWORK DW XGMAC
+M:	Boon Khai Ng <[email protected]>
+S:	Supported
+F:	drivers/net/dwc_eth_xgmac.c
+F:	drivers/net/dwc_eth_xgmac.h
+F:	drivers/net/dwc_eth_xgmac_socfpga.c
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 88b33de1b2a..4ea6600ce7f 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -167,20 +167,27 @@ static struct phy_ops rockchip_usb2phy_ops = {
 	.of_xlate = rockchip_usb2phy_of_xlate,
 };
 
-static void rockchip_usb2phy_clkout_ctl(struct clk *clk, struct regmap **base,
-					const struct usb2phy_reg **clkout_ctl)
+static int rockchip_usb2phy_clkout_ctl(struct clk *clk, struct regmap **base,
+				       const struct usb2phy_reg **clkout_ctl)
 {
 	struct udevice *parent = dev_get_parent(clk->dev);
 	struct rockchip_usb2phy *priv = dev_get_priv(parent);
 	const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg;
 
-	if (priv->phy_cfg->clkout_ctl_phy.enable) {
+	// phy_cfg can be NULL if this function called before probe (when parent
+	// clocks are enabled)
+	if (!phy_cfg)
+		return -EINVAL;
+
+	if (phy_cfg->clkout_ctl_phy.enable) {
 		*base = priv->phy_base;
 		*clkout_ctl = &phy_cfg->clkout_ctl_phy;
 	} else {
 		*base = priv->reg_base;
 		*clkout_ctl = &phy_cfg->clkout_ctl;
 	}
+
+	return 0;
 }
 
 /**
@@ -206,7 +213,8 @@ int rockchip_usb2phy_clk_enable(struct clk *clk)
 	const struct usb2phy_reg *clkout_ctl;
 	struct regmap *base;
 
-	rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl);
+	if (rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl))
+		return -ENOSYS;
 
 	/* turn on 480m clk output if it is off */
 	if (!property_enabled(base, clkout_ctl)) {
@@ -230,7 +238,8 @@ int rockchip_usb2phy_clk_disable(struct clk *clk)
 	const struct usb2phy_reg *clkout_ctl;
 	struct regmap *base;
 
-	rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl);
+	if (rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl))
+		return -ENOSYS;
 
 	/* turn off 480m clk output */
 	property_enable(base, clkout_ctl, false);
@@ -456,6 +465,28 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
 	{ /* sentinel */ }
 };
 
+static const struct rockchip_usb2phy_cfg rk3576_phy_cfgs[] = {
+	{
+		.reg		= 0x0000,
+		.clkout_ctl	= { 0x0008, 0, 0, 1, 0 },
+		.port_cfgs	= {
+			[USB2PHY_PORT_OTG] = {
+				.phy_sus	= { 0x0000, 1, 0, 2, 1 },
+			}
+		},
+	},
+	{
+		.reg		= 0x2000,
+		.clkout_ctl	= { 0x2008, 0, 0, 1, 0 },
+		.port_cfgs	= {
+			[USB2PHY_PORT_OTG] = {
+				.phy_sus	= { 0x2000, 1, 0, 2, 1 },
+			}
+		},
+	},
+	{ /* sentinel */ }
+};
+
 static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
 	{
 		.reg		= 0x0000,
@@ -518,6 +549,10 @@ static const struct udevice_id rockchip_usb2phy_ids[] = {
 		.data = (ulong)&rk3568_phy_cfgs,
 	},
 	{
+		.compatible = "rockchip,rk3576-usb2phy",
+		.data = (ulong)&rk3576_phy_cfgs,
+	},
+	{
 		.compatible = "rockchip,rk3588-usb2phy",
 		.data = (ulong)&rk3588_phy_cfgs,
 	},
@@ -538,7 +573,7 @@ U_BOOT_DRIVER(rockchip_usb2phy_clock) = {
 
 U_BOOT_DRIVER(rockchip_usb2phy) = {
 	.name	= "rockchip_usb2phy",
-	.id	= UCLASS_PHY,
+	.id	= UCLASS_NOP,
 	.of_match = rockchip_usb2phy_ids,
 	.probe = rockchip_usb2phy_probe,
 	.bind = rockchip_usb2phy_bind,
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index 5145b517aa4..d602f965d6a 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -37,6 +37,7 @@ struct rockchip_combphy_grfcfg {
 	struct combphy_reg pipe_rxterm_set;
 	struct combphy_reg pipe_txelec_set;
 	struct combphy_reg pipe_txcomp_set;
+	struct combphy_reg pipe_clk_24m;
 	struct combphy_reg pipe_clk_25m;
 	struct combphy_reg pipe_clk_100m;
 	struct combphy_reg pipe_phymode_sel;
@@ -98,104 +99,41 @@ static int param_write(struct regmap *base,
 	return regmap_write(base, reg->offset, val);
 }
 
-static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv)
-{
-	int ret = 0;
-
-	if (priv->cfg->combphy_cfg) {
-		ret = priv->cfg->combphy_cfg(priv);
-		if (ret) {
-			dev_err(priv->dev, "failed to init phy for pcie\n");
-			return ret;
-		}
-	}
-
-	return ret;
-}
-
-static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv)
-{
-	int ret = 0;
-
-	if (priv->cfg->combphy_cfg) {
-		ret = priv->cfg->combphy_cfg(priv);
-		if (ret) {
-			dev_err(priv->dev, "failed to init phy for usb3\n");
-			return ret;
-		}
-	}
-
-	return ret;
-}
-
-static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv)
-{
-	int ret = 0;
-
-	if (priv->cfg->combphy_cfg) {
-		ret = priv->cfg->combphy_cfg(priv);
-		if (ret) {
-			dev_err(priv->dev, "failed to init phy for sata\n");
-			return ret;
-		}
-	}
-
-	return ret;
-}
-
-static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv)
+static int rockchip_combphy_init(struct phy *phy)
 {
-	int ret = 0;
-
-	if (priv->cfg->combphy_cfg) {
-		ret = priv->cfg->combphy_cfg(priv);
-		if (ret) {
-			dev_err(priv->dev, "failed to init phy for sgmii\n");
-			return ret;
-		}
-	}
+	struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev);
+	int ret;
 
-	return ret;
-}
+	ret = clk_enable(&priv->ref_clk);
+	if (ret < 0 && ret != -ENOSYS)
+		return ret;
 
-static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv)
-{
 	switch (priv->mode) {
 	case PHY_TYPE_PCIE:
-		rockchip_combphy_pcie_init(priv);
-		break;
 	case PHY_TYPE_USB3:
-		rockchip_combphy_usb3_init(priv);
-		break;
 	case PHY_TYPE_SATA:
-		rockchip_combphy_sata_init(priv);
-		break;
 	case PHY_TYPE_SGMII:
 	case PHY_TYPE_QSGMII:
-		return rockchip_combphy_sgmii_init(priv);
+		if (priv->cfg->combphy_cfg)
+			ret = priv->cfg->combphy_cfg(priv);
+		else
+			ret = 0;
+		break;
 	default:
 		dev_err(priv->dev, "incompatible PHY type\n");
-		return -EINVAL;
+		ret = -EINVAL;
+		break;
 	}
 
-	return 0;
-}
-
-static int rockchip_combphy_init(struct phy *phy)
-{
-	struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev);
-	int ret;
-
-	ret = clk_enable(&priv->ref_clk);
-	if (ret < 0 && ret != -ENOSYS)
-		return ret;
+	if (ret) {
+		dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->mode);
+		goto err_clk;
+	}
 
-	ret = rockchip_combphy_set_mode(priv);
+	ret = reset_deassert_bulk(&priv->phy_rsts);
 	if (ret)
 		goto err_clk;
 
-	reset_deassert_bulk(&priv->phy_rsts);
-
 	return 0;
 
 err_clk:
@@ -223,6 +161,7 @@ static int rockchip_combphy_xlate(struct phy *phy, struct ofnode_phandle_args *a
 		return -EINVAL;
 	}
 
+	phy->id = priv->id;
 	priv->mode = args->args[0];
 
 	return 0;
@@ -237,22 +176,19 @@ static const struct phy_ops rockchip_combphy_ops = {
 static int rockchip_combphy_parse_dt(struct udevice *dev,
 				     struct rockchip_combphy_priv *priv)
 {
-	struct udevice *syscon;
 	int ret;
 
-	ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-grf", &syscon);
-	if (ret) {
-		dev_err(dev, "failed to find peri_ctrl pipe-grf regmap");
-		return ret;
+	priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,pipe-grf");
+	if (IS_ERR(priv->pipe_grf)) {
+		dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n");
+		return PTR_ERR(priv->pipe_grf);
 	}
-	priv->pipe_grf = syscon_get_regmap(syscon);
 
-	ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-phy-grf", &syscon);
-	if (ret) {
+	priv->phy_grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,pipe-phy-grf");
+	if (IS_ERR(priv->phy_grf)) {
 		dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n");
-		return ret;
+		return PTR_ERR(priv->phy_grf);
 	}
-	priv->phy_grf = syscon_get_regmap(syscon);
 
 	ret = clk_get_by_index(dev, 0, &priv->ref_clk);
 	if (ret) {
@@ -304,12 +240,109 @@ static int rockchip_combphy_probe(struct udevice *udev)
 	}
 
 	priv->dev = udev;
-	priv->mode = PHY_TYPE_SATA;
+	priv->mode = PHY_NONE;
 	priv->cfg = phy_cfg;
 
 	return rockchip_combphy_parse_dt(udev, priv);
 }
 
+static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
+{
+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+	u32 val;
+
+	switch (priv->mode) {
+	case PHY_TYPE_PCIE:
+		/* Set SSC downward spread spectrum */
+		val = readl(priv->mmio + 0x18);
+		val &= ~GENMASK(5, 4);
+		val |= 0x01 << 4;
+		writel(val, priv->mmio + 0x18);
+
+		param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
+		param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
+		param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
+		param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
+		break;
+	case PHY_TYPE_USB3:
+		/* Set SSC downward spread spectrum */
+		val = readl(priv->mmio + 0x18);
+		val &= ~GENMASK(5, 4);
+		val |= 0x01 << 4;
+		writel(val, priv->mmio + 0x18);
+
+		/* Enable adaptive CTLE for USB3.0 Rx */
+		val = readl(priv->mmio + 0x200);
+		val &= ~GENMASK(17, 17);
+		val |= 0x01 << 17;
+		writel(val, priv->mmio + 0x200);
+
+		/* Set Rx squelch input filler bandwidth */
+		val = readl(priv->mmio + 0x20c);
+		val &= ~GENMASK(2, 0);
+		val |= 0x06;
+		writel(val, priv->mmio + 0x20c);
+
+		param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
+		param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
+		param_write(priv->phy_grf, &cfg->usb_mode_set, true);
+		param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true);
+		break;
+	default:
+		dev_err(priv->dev, "incompatible PHY type\n");
+		return -EINVAL;
+	}
+
+	param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
+
+	if (priv->mode == PHY_TYPE_PCIE) {
+		/* PLL KVCO tuning fine */
+		val = readl(priv->mmio + 0x18);
+		val &= ~(0x7 << 10);
+		val |= 0x2 << 10;
+		writel(val, priv->mmio + 0x18);
+
+		/* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */
+		val = readl(priv->mmio + 0x108);
+		val &= ~(0x7f7);
+		val |= 0x4f0;
+		writel(val, priv->mmio + 0x108);
+	}
+
+	return 0;
+}
+
+static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = {
+	/* pipe-phy-grf */
+	.pcie_mode_set		= { 0x0000, 5, 0, 0x00, 0x11 },
+	.usb_mode_set		= { 0x0000, 5, 0, 0x00, 0x04 },
+	.pipe_rxterm_set	= { 0x0000, 12, 12, 0x00, 0x01 },
+	.pipe_txelec_set	= { 0x0004, 1, 1, 0x00, 0x01 },
+	.pipe_txcomp_set	= { 0x0004, 4, 4, 0x00, 0x01 },
+	.pipe_clk_24m		= { 0x0004, 14, 13, 0x00, 0x00 },
+	.pipe_clk_100m		= { 0x0004, 14, 13, 0x00, 0x02 },
+	.pipe_rxterm_sel	= { 0x0008, 8, 8, 0x00, 0x01 },
+	.pipe_txelec_sel	= { 0x0008, 12, 12, 0x00, 0x01 },
+	.pipe_txcomp_sel	= { 0x0008, 15, 15, 0x00, 0x01 },
+	.pipe_clk_ext		= { 0x000c, 9, 8, 0x02, 0x01 },
+	.pipe_phy_status	= { 0x0034, 6, 6, 0x01, 0x00 },
+	.con0_for_pcie		= { 0x0000, 15, 0, 0x00, 0x110 },
+	.con1_for_pcie		= { 0x0004, 15, 0, 0x00, 0x00 },
+	.con2_for_pcie		= { 0x0008, 15, 0, 0x00, 0x101 },
+	.con3_for_pcie		= { 0x000c, 15, 0, 0x00, 0x0200 },
+	/* pipe-grf */
+	.u3otg0_port_en		= { 0x0044, 15, 0, 0x0181, 0x1100 },
+};
+
+static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {
+	.num_phys = 1,
+	.phy_ids = {
+		0xffdc0000,
+	},
+	.grfcfg		= &rk3528_combphy_grfcfgs,
+	.combphy_cfg	= rk3528_combphy_cfg,
+};
+
 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
 {
 	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
@@ -453,6 +486,149 @@ static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
 	.combphy_cfg	= rk3568_combphy_cfg,
 };
 
+static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
+{
+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+	u32 val;
+
+	switch (priv->mode) {
+	case PHY_TYPE_PCIE:
+		param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
+		param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
+		param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
+		param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
+		break;
+	case PHY_TYPE_USB3:
+		/* Set SSC downward spread spectrum */
+		val = readl(priv->mmio + (0x1f << 2));
+		val &= ~GENMASK(5, 4);
+		val |= 0x01 << 4;
+		writel(val, priv->mmio + 0x7c);
+
+		/* Enable adaptive CTLE for USB3.0 Rx */
+		val = readl(priv->mmio + (0x0e << 2));
+		val &= ~GENMASK(0, 0);
+		val |= 0x01;
+		writel(val, priv->mmio + (0x0e << 2));
+
+		/* Set PLL KVCO fine tuning signals */
+		val = readl(priv->mmio + (0x20 << 2));
+		val &= ~(0x7 << 2);
+		val |= 0x2 << 2;
+		writel(val, priv->mmio + (0x20 << 2));
+
+		/* Set PLL LPF R1 to su_trim[10:7]=1001 */
+		writel(0x4, priv->mmio + (0xb << 2));
+
+		/* Set PLL input clock divider 1/2 */
+		val = readl(priv->mmio + (0x5 << 2));
+		val &= ~(0x3 << 6);
+		val |= 0x1 << 6;
+		writel(val, priv->mmio + (0x5 << 2));
+
+		/* Set PLL loop divider */
+		writel(0x32, priv->mmio + (0x11 << 2));
+
+		/* Set PLL KVCO to min and set PLL charge pump current to max */
+		writel(0xf0, priv->mmio + (0xa << 2));
+
+		/* Set Rx squelch input filler bandwidth */
+		writel(0x0d, priv->mmio + (0x14 << 2));
+
+		param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
+		param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
+		param_write(priv->phy_grf, &cfg->usb_mode_set, true);
+		param_write(priv->pipe_grf, &cfg->u3otg1_port_en, true);
+		break;
+	case PHY_TYPE_SATA:
+		/* Enable adaptive CTLE for SATA Rx */
+		val = readl(priv->mmio + (0x0e << 2));
+		val &= ~GENMASK(0, 0);
+		val |= 0x01;
+		writel(val, priv->mmio + (0x0e << 2));
+		/* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */
+		writel(0x8F, priv->mmio + (0x06 << 2));
+
+		param_write(priv->phy_grf, &cfg->con0_for_sata, true);
+		param_write(priv->phy_grf, &cfg->con1_for_sata, true);
+		param_write(priv->phy_grf, &cfg->con2_for_sata, true);
+		param_write(priv->phy_grf, &cfg->con3_for_sata, true);
+		param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
+		param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true);
+		break;
+	case PHY_TYPE_SGMII:
+	case PHY_TYPE_QSGMII:
+	default:
+		dev_err(priv->dev, "incompatible PHY type\n");
+		return -EINVAL;
+	}
+
+	/* 100MHz refclock signal is good */
+	clk_set_rate(&priv->ref_clk, 100000000);
+	param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
+	if (priv->mode == PHY_TYPE_PCIE) {
+		/* gate_tx_pck_sel length select work for L1SS */
+		writel(0xc0, priv->mmio + 0x74);
+
+		/* PLL KVCO tuning fine */
+		val = readl(priv->mmio + (0x20 << 2));
+		val &= ~(0x7 << 2);
+		val |= 0x2 << 2;
+		writel(val, priv->mmio + (0x20 << 2));
+
+		/* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
+		writel(0x4c, priv->mmio + (0x1b << 2));
+
+		/* Set up su_trim: T3_P1 650mv */
+		writel(0x90, priv->mmio + (0xa << 2));
+		writel(0x43, priv->mmio + (0xb << 2));
+		writel(0x88, priv->mmio + (0xc << 2));
+		writel(0x56, priv->mmio + (0xd << 2));
+	}
+
+	return 0;
+}
+
+static const struct rockchip_combphy_grfcfg rk3576_combphy_grfcfgs = {
+	/* pipe-phy-grf */
+	.pcie_mode_set		= { 0x0000, 5, 0, 0x00, 0x11 },
+	.usb_mode_set		= { 0x0000, 5, 0, 0x00, 0x04 },
+	.pipe_rxterm_set	= { 0x0000, 12, 12, 0x00, 0x01 },
+	.pipe_txelec_set	= { 0x0004, 1, 1, 0x00, 0x01 },
+	.pipe_txcomp_set	= { 0x0004, 4, 4, 0x00, 0x01 },
+	.pipe_clk_25m		= { 0x0004, 14, 13, 0x00, 0x01 },
+	.pipe_clk_100m		= { 0x0004, 14, 13, 0x00, 0x02 },
+	.pipe_phymode_sel	= { 0x0008, 1, 1, 0x00, 0x01 },
+	.pipe_rate_sel		= { 0x0008, 2, 2, 0x00, 0x01 },
+	.pipe_rxterm_sel	= { 0x0008, 8, 8, 0x00, 0x01 },
+	.pipe_txelec_sel	= { 0x0008, 12, 12, 0x00, 0x01 },
+	.pipe_txcomp_sel	= { 0x0008, 15, 15, 0x00, 0x01 },
+	.pipe_clk_ext		= { 0x000c, 9, 8, 0x02, 0x01 },
+	.pipe_phy_status	= { 0x0034, 6, 6, 0x01, 0x00 },
+	.con0_for_pcie		= { 0x0000, 15, 0, 0x00, 0x1000 },
+	.con1_for_pcie		= { 0x0004, 15, 0, 0x00, 0x0000 },
+	.con2_for_pcie		= { 0x0008, 15, 0, 0x00, 0x0101 },
+	.con3_for_pcie		= { 0x000c, 15, 0, 0x00, 0x0200 },
+	.con0_for_sata		= { 0x0000, 15, 0, 0x00, 0x0129 },
+	.con1_for_sata		= { 0x0004, 15, 0, 0x00, 0x0000 },
+	.con2_for_sata		= { 0x0008, 15, 0, 0x00, 0x80c1 },
+	.con3_for_sata		= { 0x000c, 15, 0, 0x00, 0x0407 },
+	/* php-grf */
+	.pipe_con0_for_sata	= { 0x001C, 2, 0, 0x00, 0x2 },
+	.pipe_con1_for_sata	= { 0x0020, 2, 0, 0x00, 0x2 },
+	.u3otg1_port_en		= { 0x0038, 15, 0, 0x0181, 0x1100 },
+};
+
+static const struct rockchip_combphy_cfg rk3576_combphy_cfgs = {
+	.num_phys = 2,
+	.phy_ids = {
+		0x2b050000,
+		0x2b060000,
+	},
+	.grfcfg		= &rk3576_combphy_grfcfgs,
+	.combphy_cfg	= rk3576_combphy_cfg,
+};
+
 static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
 {
 	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
@@ -561,10 +737,18 @@ static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
 
 static const struct udevice_id rockchip_combphy_ids[] = {
 	{
+		.compatible = "rockchip,rk3528-naneng-combphy",
+		.data = (ulong)&rk3528_combphy_cfgs
+	},
+	{
 		.compatible = "rockchip,rk3568-naneng-combphy",
 		.data = (ulong)&rk3568_combphy_cfgs
 	},
 	{
+		.compatible = "rockchip,rk3576-naneng-combphy",
+		.data = (ulong)&rk3576_combphy_cfgs
+	},
+	{
 		.compatible = "rockchip,rk3588-naneng-combphy",
 		.data = (ulong)&rk3588_combphy_cfgs
 	},
diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c
index c48a5cd5267..66d1d32d25c 100644
--- a/drivers/phy/rockchip/phy-rockchip-typec.c
+++ b/drivers/phy/rockchip/phy-rockchip-typec.c
@@ -788,7 +788,7 @@ U_BOOT_DRIVER(rockchip_tcphy_usb3_port) = {
 
 U_BOOT_DRIVER(rockchip_typec_phy) = {
 	.name	= "rockchip_typec_phy",
-	.id	= UCLASS_PHY,
+	.id	= UCLASS_NOP,
 	.of_match = rockchip_typec_phy_ids,
 	.probe = rockchip_tcphy_probe,
 	.bind = rockchip_tcphy_bind,
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index 9deec47ae46..cca67dd3611 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -96,9 +96,7 @@ struct rockchip_udphy {
 
 	/* PHY status management */
 	bool flip;
-	bool mode_change;
 	u8 mode;
-	u8 status;
 
 	/* utilized for USB */
 	bool hs; /* flag for high-speed */
@@ -525,80 +523,26 @@ static int udphy_parse_dt(struct rockchip_udphy *udphy, struct udevice *dev)
 	return 0;
 }
 
-static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode)
-{
-	int ret;
-
-	if (!(udphy->mode & mode)) {
-		dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
-		return 0;
-	}
-
-	if (udphy->status == UDPHY_MODE_NONE) {
-		udphy->mode_change = false;
-		ret = udphy_setup(udphy);
-		if (ret)
-			return ret;
-
-		if (udphy->mode & UDPHY_MODE_USB)
-			udphy_u3_port_disable(udphy, false);
-	} else if (udphy->mode_change) {
-		udphy->mode_change = false;
-		udphy->status = UDPHY_MODE_NONE;
-		if (udphy->mode == UDPHY_MODE_DP)
-			udphy_u3_port_disable(udphy, true);
-
-		ret = udphy_disable(udphy);
-		if (ret)
-			return ret;
-		ret = udphy_setup(udphy);
-		if (ret)
-			return ret;
-	}
-
-	udphy->status |= mode;
-
-	return 0;
-}
-
-static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode)
-{
-	int ret;
-
-	if (!(udphy->mode & mode)) {
-		dev_info(udphy->dev, "mode 0x%02x is not supported\n", mode);
-		return 0;
-	}
-
-	if (!udphy->status)
-		return 0;
-
-	udphy->status &= ~mode;
-
-	if (udphy->status == UDPHY_MODE_NONE) {
-		ret = udphy_disable(udphy);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-
 static int rockchip_u3phy_of_xlate(struct phy *phy,
 				   struct ofnode_phandle_args *args)
 {
+	struct rockchip_udphy *udphy = dev_get_priv(phy->dev);
+
 	if (args->args_count == 0)
 		return -EINVAL;
 
 	if (args->args[0] != PHY_TYPE_USB3)
 		return -EINVAL;
 
+	phy->id = udphy->id;
+
 	return 0;
 }
 
 static int rockchip_u3phy_init(struct phy *phy)
 {
 	struct rockchip_udphy *udphy = dev_get_priv(phy->dev);
+	int ret;
 
 	/* DP only or high-speed, disable U3 port */
 	if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
@@ -606,7 +550,12 @@ static int rockchip_u3phy_init(struct phy *phy)
 		return 0;
 	}
 
-	return udphy_power_on(udphy, UDPHY_MODE_USB);
+	ret = udphy_setup(udphy);
+	if (ret)
+		return ret;
+
+	udphy_u3_port_disable(udphy, false);
+	return 0;
 }
 
 static int rockchip_u3phy_exit(struct phy *phy)
@@ -617,7 +566,7 @@ static int rockchip_u3phy_exit(struct phy *phy)
 	if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
 		return 0;
 
-	return udphy_power_off(udphy, UDPHY_MODE_USB);
+	return udphy_disable(udphy);
 }
 
 static const struct phy_ops rockchip_u3phy_ops = {
@@ -813,6 +762,28 @@ static const char * const rk3588_udphy_rst_l[] = {
 	"init", "cmn", "lane", "pcs_apb", "pma_apb"
 };
 
+static const struct rockchip_udphy_cfg rk3576_udphy_cfgs = {
+	.num_phys = 1,
+	.phy_ids = {
+		0x2b010000,
+	},
+	.num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l),
+	.rst_list = rk3588_udphy_rst_l,
+	.grfcfg	= {
+		/* u2phy-grf */
+		.bvalid_phy_con		= { 0x0010, 1, 0, 0x2, 0x3 },
+		.bvalid_grf_con		= { 0x0000, 15, 14, 0x1, 0x3 },
+
+		/* usb-grf */
+		.usb3otg0_cfg		= { 0x0030, 15, 0, 0x1100, 0x0188 },
+
+		/* usbdpphy-grf */
+		.low_pwrn		= { 0x0004, 13, 13, 0, 1 },
+		.rx_lfps		= { 0x0004, 14, 14, 0, 1 },
+	},
+	.combophy_init = rk3588_udphy_init,
+};
+
 static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = {
 	.num_phys = 2,
 	.phy_ids = {
@@ -839,6 +810,10 @@ static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = {
 
 static const struct udevice_id rockchip_udphy_dt_match[] = {
 	{
+		.compatible = "rockchip,rk3576-usbdp-phy",
+		.data = (ulong)&rk3576_udphy_cfgs
+	},
+	{
 		.compatible = "rockchip,rk3588-usbdp-phy",
 		.data = (ulong)&rk3588_udphy_cfgs
 	},
diff --git a/drivers/pinctrl/renesas/rzg2l-pfc.c b/drivers/pinctrl/renesas/rzg2l-pfc.c
index 3c751e9473a..4a75e0b2372 100644
--- a/drivers/pinctrl/renesas/rzg2l-pfc.c
+++ b/drivers/pinctrl/renesas/rzg2l-pfc.c
@@ -353,7 +353,7 @@ static int rzg2l_pinconf_set(struct udevice *dev, unsigned int pin_selector,
 		/* The pin selector refers to a multiplexed pin */
 		int port = rzg2l_selector_decode(data, pin_selector, &pin);
 		if (port < 0) {
-			dev_err(dev, "Invalid pin selector %u:%u\n", port, pin);
+			dev_err(dev, "Invalid pin selector %u\n", pin_selector);
 			return port;
 		}
 
@@ -550,7 +550,7 @@ static int rzg2l_get_pin_muxing(struct udevice *dev, unsigned int selector,
 
 	port = rzg2l_selector_decode(data, selector, &pin);
 	if (port < 0) {
-		dev_err(dev, "Invalid pin selector %u:%u\n", port, pin);
+		dev_err(dev, "Invalid pin selector %u\n", selector);
 		return port;
 	}
 
diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c
index 3bc696d4caa..d11f7a7886e 100644
--- a/drivers/power/pmic/rk8xx.c
+++ b/drivers/power/pmic/rk8xx.c
@@ -89,11 +89,6 @@ void rk8xx_off_for_plugin(struct udevice *dev)
 	}
 }
 
-static struct reg_data rk806_init_reg[] = {
-	/* RST_FUN */
-	{ RK806_REG_SYS_CFG3, BIT(7), GENMASK(7, 6)},
-};
-
 static struct reg_data rk817_init_reg[] = {
 /* enable the under-voltage protection,
  * the under-voltage protection will shutdown the LDO3 and reset the PMIC
@@ -306,12 +301,20 @@ static int rk8xx_probe(struct udevice *dev)
 		value = (power_en2 & 0x0f) | ((power_en3 & 0x0f) << 4);
 		pmic_reg_write(dev, RK817_POWER_EN_SAVE1, value);
 		break;
-	case RK806_ID:
+	case RK806_ID: {
+		u32 rst_fun = 2;
+
 		on_source = RK806_ON_SOURCE;
 		off_source = RK806_OFF_SOURCE;
-		init_data = rk806_init_reg;
-		init_data_num = ARRAY_SIZE(rk806_init_reg);
-		break;
+
+		ret = dev_read_u32(dev, "rockchip,reset-mode", &rst_fun);
+		if (ret)
+			debug("rockchip,reset-mode property missing, defaulting to %d\n",
+			      rst_fun);
+
+		pmic_clrsetbits(dev, RK806_REG_SYS_CFG3, RK806_RST_FUN_MSK,
+				FIELD_PREP(RK806_RST_FUN_MSK, rst_fun));
+		break; }
 	default:
 		printf("Unknown PMIC: RK%x!!\n", show_variant);
 		return -EINVAL;
diff --git a/drivers/rng/rockchip_rng.c b/drivers/rng/rockchip_rng.c
index d854ea90044..8cf750e043c 100644
--- a/drivers/rng/rockchip_rng.c
+++ b/drivers/rng/rockchip_rng.c
@@ -394,6 +394,10 @@ static const struct udevice_id rockchip_rng_match[] = {
 		.data = (ulong)&rk_trngv1_soc_data,
 	},
 	{
+		.compatible = "rockchip,rk3576-rng",
+		.data = (ulong)&rkrng_soc_data,
+	},
+	{
 		.compatible = "rockchip,rkrng",
 		.data = (ulong)&rkrng_soc_data,
 	},
diff --git a/drivers/serial/serial_efi.c b/drivers/serial/serial_efi.c
index 5733eaaf9d4..d3cd4de34a2 100644
--- a/drivers/serial/serial_efi.c
+++ b/drivers/serial/serial_efi.c
@@ -33,7 +33,7 @@ int serial_efi_setbrg(struct udevice *dev, int baudrate)
 
 static int serial_efi_get_key(struct serial_efi_priv *priv)
 {
-	int ret;
+	efi_status_t ret;
 
 	if (priv->have_key)
 		return 0;
diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
index 8aa7a83aef4..b2b96e1c4b9 100644
--- a/drivers/spi/atmel-quadspi.c
+++ b/drivers/spi/atmel-quadspi.c
@@ -615,7 +615,8 @@ static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
 static int atmel_qspi_transfer(struct atmel_qspi *aq,
 			       const struct spi_mem_op *op, u32 offset)
 {
-	u32 sr, imr;
+	u32 imr, val = 0;
+	unsigned long timeout;
 
 	/* Skip to the final steps if there is no data */
 	if (op->data.nbytes) {
@@ -636,8 +637,16 @@ static int atmel_qspi_transfer(struct atmel_qspi *aq,
 
 	/* Poll INSTruction End and Chip Select Rise flags. */
 	imr = QSPI_SR_INSTRE | QSPI_SR_CSR;
-	return readl_poll_timeout(aq->regs + QSPI_SR, sr, (sr & imr) == imr,
-				  ATMEL_QSPI_TIMEOUT);
+
+	timeout = timer_get_us() + ATMEL_QSPI_TIMEOUT;
+	while (1) {
+		val |= readl(aq->regs + QSPI_SR) & imr;
+		if ((val & imr) == imr)
+			return 0;
+
+		if (time_after(timer_get_us(), timeout))
+			return -ETIMEDOUT;
+	}
 }
 
 static int atmel_qspi_sama7g5_set_cfg(struct atmel_qspi *aq,
diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c
index 1b9bf004b7c..7f2965f8321 100644
--- a/drivers/spi/exynos_spi.c
+++ b/drivers/spi/exynos_spi.c
@@ -105,14 +105,10 @@ static int spi_rx_tx(struct exynos_spi_priv *priv, int todo,
 	uint out_bytes, in_bytes;
 	int toread;
 	unsigned start = get_timer(0);
-	int stopping;
 	int step;
 
 	out_bytes = in_bytes = todo;
 
-	stopping = priv->skip_preamble && (flags & SPI_XFER_END) &&
-					!(priv->mode & SPI_SLAVE);
-
 	/*
 	 * Try to transfer words if we can. This helps read performance at
 	 * SPI clock speeds above about 20MHz.
@@ -161,12 +157,10 @@ static int spi_rx_tx(struct exynos_spi_priv *priv, int todo,
 			while (rx_lvl >= step) {
 				temp = readl(&regs->rx_data);
 				if (priv->skip_preamble) {
-					if (temp == SPI_PREAMBLE_END_BYTE) {
+					if (temp == SPI_PREAMBLE_END_BYTE)
 						priv->skip_preamble = 0;
-						stopping = 0;
-					}
 				} else {
-					if (rxp || stopping) {
+					if (rxp) {
 						if (step == 4)
 							*(uint32_t *)rxp = temp;
 						else
diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c
index a30c40ef80e..9eaf7e40ab6 100644
--- a/drivers/usb/cdns3/gadget.c
+++ b/drivers/usb/cdns3/gadget.c
@@ -557,10 +557,10 @@ static void cdns3_wa2_remove_old_request(struct cdns3_endpoint *priv_ep)
 
 		trace_cdns3_wa2(priv_ep, "removes eldest request");
 
+		list_del_init(&priv_req->list);
 		kfree(priv_req->request.buf);
 		cdns3_gadget_ep_free_request(&priv_ep->endpoint,
 					     &priv_req->request);
-		list_del_init(&priv_req->list);
 		--priv_ep->wa2_counter;
 
 		if (!chain)
@@ -1959,10 +1959,10 @@ static int cdns3_gadget_ep_disable(struct usb_ep *ep)
 	while (!list_empty(&priv_ep->wa2_descmiss_req_list)) {
 		priv_req = cdns3_next_priv_request(&priv_ep->wa2_descmiss_req_list);
 
+		list_del_init(&priv_req->list);
 		kfree(priv_req->request.buf);
 		cdns3_gadget_ep_free_request(&priv_ep->endpoint,
 					     &priv_req->request);
-		list_del_init(&priv_req->list);
 		--priv_ep->wa2_counter;
 	}
 
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 3cda2b74b7e..c09014aec60 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -698,7 +698,9 @@ static const struct udevice_id dwc3_glue_ids[] = {
 	{ .compatible = "ti,am654-dwc3" },
 	{ .compatible = "rockchip,rk3328-dwc3", .data = (ulong)&rk_ops },
 	{ .compatible = "rockchip,rk3399-dwc3" },
+	{ .compatible = "rockchip,rk3528-dwc3", .data = (ulong)&rk_ops },
 	{ .compatible = "rockchip,rk3568-dwc3", .data = (ulong)&rk_ops },
+	{ .compatible = "rockchip,rk3576-dwc3", .data = (ulong)&rk_ops },
 	{ .compatible = "rockchip,rk3588-dwc3", .data = (ulong)&rk_ops },
 	{ .compatible = "qcom,dwc3", .data = (ulong)&qcom_ops },
 	{ .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops },
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 46a83141481..0121f9872ae 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -86,6 +86,7 @@ config USB_GADGET_PRODUCT_NUM
 	default 0x350a if ROCKCHIP_RK3568
 	default 0x350b if ROCKCHIP_RK3588
 	default 0x350c if ROCKCHIP_RK3528
+	default 0x350e if ROCKCHIP_RK3576
 	default 0x0
 	help
 	  Product ID of the USB device emulated, reported to the host device.
@@ -201,12 +202,13 @@ config USB_FUNCTION_MASS_STORAGE
 	  the eMMC/SD card content to HOST PC so it can be mounted.
 
 config USB_FUNCTION_ROCKUSB
-        bool "Enable USB rockusb gadget"
-        help
-          Rockusb protocol is widely used by Rockchip SoC based devices. It can
-          read/write info, image to/from devices. This enables the USB part of
-          the rockusb gadget.for more detail about Rockusb protocol, please see
-          doc/README.rockusb
+	bool "Enable USB rockusb gadget"
+	depends on ARCH_ROCKCHIP
+	help
+	  Rockusb protocol is widely used by Rockchip SoC based devices. It can
+	  read/write info, image to/from devices. This enables the USB part of
+	  the rockusb gadget.for more detail about Rockusb protocol, please see
+	  doc/README.rockusb
 
 config USB_FUNCTION_SDP
 	bool "Enable USB SDP (Serial Download Protocol)"
diff --git a/drivers/usb/host/dwc3-of-simple.c b/drivers/usb/host/dwc3-of-simple.c
index d52e7d22d1a..362178b7900 100644
--- a/drivers/usb/host/dwc3-of-simple.c
+++ b/drivers/usb/host/dwc3-of-simple.c
@@ -91,6 +91,7 @@ static int dwc3_of_simple_remove(struct udevice *dev)
 static const struct udevice_id dwc3_of_simple_ids[] = {
 	{ .compatible = "amlogic,meson-gxl-dwc3" },
 	{ .compatible = "rockchip,rk3399-dwc3" },
+	{ .compatible = "samsung,exynos850-dwusb3" },
 	{ .compatible = "ti,dwc3" },
 	{ }
 };