Merge tag 'u-boot-rockchip-20260309' of https://source.denx.de/u-boot/custodians/u-boot-rockchip into next

CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/29452

- New SoC support: RK3506, RK3582;
- New Board support: RK3528 FriendlyElec NanoPi Zero2;
- Other fixes

16 files changed, 2031 insertions, 27 deletions

diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 34b63d4df34..07525c36432 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += clk_rk3308.o
 obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
 obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3506) += clk_rk3506.o
 obj-$(CONFIG_ROCKCHIP_RK3528) += clk_rk3528.o
 obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o
 obj-$(CONFIG_ROCKCHIP_RK3576) += clk_rk3576.o
diff --git a/drivers/clk/rockchip/clk_rk3506.c b/drivers/clk/rockchip/clk_rk3506.c
new file mode 100644
index 00000000000..38066c5c3e3
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rk3506.c
@@ -0,0 +1,1166 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ * Author: Finley Xiao <[email protected]>
+ */
+
+#define LOG_CATEGORY UCLASS_CLK
+
+#include <clk-uclass.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3506.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dt-bindings/clock/rockchip,rk3506-cru.h>
+
+#define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
+
+/*
+ * [FRAC PLL]: GPLL, V0PLL, V1PLL
+ *   - VCO Frequency: 950MHz to 3800MHZ
+ *   - Output Frequency: 19MHz to 3800MHZ
+ *   - refdiv: 1 to 63 (Int Mode), 1 to 2 (Frac Mode)
+ *   - fbdiv: 16 to 3800 (Int Mode), 20 to 380 (Frac Mode)
+ *   - post1div: 1 to 7
+ *   - post2div: 1 to 7
+ */
+static struct rockchip_pll_rate_table rk3506_pll_rates[] = {
+	/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+	RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
+	RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
+	RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
+	RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
+	RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
+	RK3036_PLL_RATE(1500000000, 1, 125, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
+	RK3036_PLL_RATE(1350000000, 4, 225, 1, 1, 1, 0),
+	RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
+	RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
+	RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1179648000, 1, 49, 1, 1, 0, 2550137),
+	RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1000000000, 3, 125, 1, 1, 1, 0),
+	RK3036_PLL_RATE(993484800, 1, 41, 1, 1, 0, 6630355),
+	RK3036_PLL_RATE(983040000, 1, 40, 1, 1, 0, 16106127),
+	RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
+	RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
+	RK3036_PLL_RATE(903168000, 1, 75, 2, 1, 0, 4429185),
+	RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
+	RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
+	RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0),
+	RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
+	RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
+	RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
+	RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
+	RK3036_PLL_RATE(96000000, 1, 48, 6, 2, 1, 0),
+	{ /* sentinel */ },
+};
+
+static struct rockchip_pll_clock rk3506_pll_clks[] = {
+	[GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3506_PLL_CON(0),
+		     RK3506_MODE_CON, 0, 10, 0, rk3506_pll_rates),
+	[V0PLL] = PLL(pll_rk3328, PLL_V0PLL, RK3506_PLL_CON(8),
+		      RK3506_MODE_CON, 2, 10, 0, rk3506_pll_rates),
+	[V1PLL] = PLL(pll_rk3328, PLL_V1PLL, RK3506_PLL_CON(16),
+		      RK3506_MODE_CON, 4, 10, 0, rk3506_pll_rates),
+};
+
+#define RK3506_CPUCLK_RATE(_rate, _aclk_m_core, _pclk_dbg)	\
+{								\
+	.rate = _rate##U,					\
+	.aclk_div = (_aclk_m_core),				\
+	.pclk_div = (_pclk_dbg),				\
+}
+
+/* SIGN-OFF: aclk_core: 500M, pclk_core: 125M, */
+static struct rockchip_cpu_rate_table rk3506_cpu_rates[] = {
+	RK3506_CPUCLK_RATE(1179648000, 1, 6),
+	RK3506_CPUCLK_RATE(903168000, 1, 5),
+	RK3506_CPUCLK_RATE(800000000, 1, 4),
+	RK3506_CPUCLK_RATE(589824000, 1, 3),
+	RK3506_CPUCLK_RATE(400000000, 1, 2),
+	RK3506_CPUCLK_RATE(200000000, 1, 1),
+	{ /* sentinel */ },
+};
+
+static int rk3506_armclk_get_rate(struct rk3506_clk_priv *priv)
+{
+	u32 con, div, sel;
+	ulong prate;
+
+	con = readl(RK3506_CLKSEL_CON(15));
+	sel = FIELD_GET(CLK_CORE_SRC_SEL_MASK, con);
+	div = FIELD_GET(CLK_CORE_SRC_DIV_MASK, con);
+
+	if (sel == CLK_CORE_SEL_GPLL)
+		prate = priv->gpll_hz;
+	else if (sel ==  CLK_CORE_SEL_V0PLL)
+		prate = priv->v0pll_hz;
+	else if (sel ==  CLK_CORE_SEL_V1PLL)
+		prate = priv->v1pll_hz;
+	else
+		return -EINVAL;
+
+	return DIV_TO_RATE(prate, div);
+}
+
+static int rk3506_armclk_set_rate(struct rk3506_clk_priv *priv, ulong new_rate)
+{
+	const struct rockchip_cpu_rate_table *rate;
+	u32 con, div, old_div, sel;
+	ulong old_rate, prate;
+
+	rate = rockchip_get_cpu_settings(rk3506_cpu_rates, new_rate);
+	if (!rate) {
+		log_debug("unsupported cpu rate %lu\n", new_rate);
+		return -EINVAL;
+	}
+
+	/*
+	 * set up dependent divisors for PCLK and ACLK clocks.
+	 */
+	old_rate = rk3506_armclk_get_rate(priv);
+	if (new_rate >= old_rate) {
+		rk_clrsetreg(RK3506_CLKSEL_CON(15), ACLK_CORE_DIV_MASK,
+			     FIELD_PREP(ACLK_CORE_DIV_MASK, rate->aclk_div));
+		rk_clrsetreg(RK3506_CLKSEL_CON(16), PCLK_CORE_DIV_MASK,
+			     FIELD_PREP(PCLK_CORE_DIV_MASK, rate->pclk_div));
+	}
+
+	if (new_rate == 589824000 || new_rate == 1179648000) {
+		sel = CLK_CORE_SEL_V0PLL;
+		div = DIV_ROUND_UP(priv->v0pll_hz, new_rate);
+		prate = priv->v0pll_hz;
+	} else if (new_rate == 903168000) {
+		sel = CLK_CORE_SEL_V1PLL;
+		div = DIV_ROUND_UP(priv->v1pll_hz, new_rate);
+		prate = priv->v1pll_hz;
+	} else {
+		sel = CLK_CORE_SEL_GPLL;
+		div = DIV_ROUND_UP(priv->gpll_hz, new_rate);
+		prate = priv->gpll_hz;
+	}
+	assert(div - 1 <= 31);
+
+	con = readl(RK3506_CLKSEL_CON(15));
+	old_div = FIELD_GET(CLK_CORE_SRC_DIV_MASK, con);
+	if (DIV_TO_RATE(prate, old_div) > new_rate) {
+		rk_clrsetreg(RK3506_CLKSEL_CON(15), CLK_CORE_SRC_DIV_MASK,
+			     FIELD_PREP(CLK_CORE_SRC_DIV_MASK, div - 1));
+		rk_clrsetreg(RK3506_CLKSEL_CON(15), CLK_CORE_SRC_SEL_MASK,
+			     FIELD_PREP(CLK_CORE_SRC_SEL_MASK, sel));
+	} else {
+		rk_clrsetreg(RK3506_CLKSEL_CON(15), CLK_CORE_SRC_SEL_MASK,
+			     FIELD_PREP(CLK_CORE_SRC_SEL_MASK, sel));
+		rk_clrsetreg(RK3506_CLKSEL_CON(15), CLK_CORE_SRC_DIV_MASK,
+			     FIELD_PREP(CLK_CORE_SRC_DIV_MASK, div - 1));
+	}
+
+	if (new_rate < old_rate) {
+		rk_clrsetreg(RK3506_CLKSEL_CON(15), ACLK_CORE_DIV_MASK,
+			     FIELD_PREP(ACLK_CORE_DIV_MASK, rate->aclk_div));
+		rk_clrsetreg(RK3506_CLKSEL_CON(16), PCLK_CORE_DIV_MASK,
+			     FIELD_PREP(PCLK_CORE_DIV_MASK, rate->pclk_div));
+	}
+
+	return rk3506_armclk_get_rate(priv);
+}
+
+static ulong rk3506_pll_div_get_rate(struct rk3506_clk_priv *priv, ulong clk_id)
+{
+	u32 con, div;
+	ulong prate;
+
+	switch (clk_id) {
+	case CLK_GPLL_DIV:
+		con = readl(RK3506_CLKSEL_CON(0));
+		div = FIELD_GET(CLK_GPLL_DIV_MASK, con);
+		prate = priv->gpll_hz;
+		break;
+	case CLK_GPLL_DIV_100M:
+		con = readl(RK3506_CLKSEL_CON(0));
+		div = FIELD_GET(CLK_GPLL_DIV_100M_MASK, con);
+		prate = priv->gpll_div_hz;
+		break;
+	case CLK_V0PLL_DIV:
+		con = readl(RK3506_CLKSEL_CON(1));
+		div = FIELD_GET(CLK_V0PLL_DIV_MASK, con);
+		prate = priv->v0pll_hz;
+		break;
+	case CLK_V1PLL_DIV:
+		con = readl(RK3506_CLKSEL_CON(1));
+		div = FIELD_GET(CLK_V1PLL_DIV_MASK, con);
+		prate = priv->v1pll_hz;
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return DIV_TO_RATE(prate, div);
+}
+
+static ulong rk3506_pll_div_set_rate(struct rk3506_clk_priv *priv, ulong clk_id,
+				     ulong rate)
+{
+	u32 div;
+
+	switch (clk_id) {
+	case CLK_GPLL_DIV:
+		div = DIV_ROUND_UP(priv->gpll_hz, rate);
+		assert(div - 1 <= 15);
+		rk_clrsetreg(RK3506_CLKSEL_CON(0), CLK_GPLL_DIV_MASK,
+			     FIELD_PREP(CLK_GPLL_DIV_MASK, div - 1));
+		break;
+	case CLK_GPLL_DIV_100M:
+		div = DIV_ROUND_UP(priv->gpll_div_hz, rate);
+		assert(div - 1 <= 15);
+		rk_clrsetreg(RK3506_CLKSEL_CON(0), CLK_GPLL_DIV_100M_MASK,
+			     FIELD_PREP(CLK_GPLL_DIV_100M_MASK, div - 1));
+		break;
+	case CLK_V0PLL_DIV:
+		div = DIV_ROUND_UP(priv->v0pll_hz, rate);
+		assert(div - 1 <= 15);
+		rk_clrsetreg(RK3506_CLKSEL_CON(1), CLK_V0PLL_DIV_MASK,
+			     FIELD_PREP(CLK_V0PLL_DIV_MASK, div - 1));
+		break;
+	case CLK_V1PLL_DIV:
+		div = DIV_ROUND_UP(priv->v1pll_hz, rate);
+		assert(div - 1 <= 15);
+		rk_clrsetreg(RK3506_CLKSEL_CON(1), CLK_V1PLL_DIV_MASK,
+			     FIELD_PREP(CLK_V1PLL_DIV_MASK, div - 1));
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return rk3506_pll_div_get_rate(priv, clk_id);
+}
+
+static ulong rk3506_bus_get_rate(struct rk3506_clk_priv *priv, ulong clk_id)
+{
+	u32 con, div, sel;
+	ulong prate;
+
+	switch (clk_id) {
+	case ACLK_BUS_ROOT:
+		con = readl(RK3506_CLKSEL_CON(21));
+		sel = FIELD_GET(ACLK_BUS_SEL_MASK, con);
+		div = FIELD_GET(ACLK_BUS_DIV_MASK, con);
+		break;
+	case HCLK_BUS_ROOT:
+		con = readl(RK3506_CLKSEL_CON(21));
+		sel = FIELD_GET(HCLK_BUS_SEL_MASK, con);
+		div = FIELD_GET(HCLK_BUS_DIV_MASK, con);
+		break;
+	case PCLK_BUS_ROOT:
+		con = readl(RK3506_CLKSEL_CON(22));
+		sel = FIELD_GET(PCLK_BUS_SEL_MASK, con);
+		div = FIELD_GET(PCLK_BUS_DIV_MASK, con);
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	if (sel == ACLK_BUS_SEL_GPLL_DIV)
+		prate = priv->gpll_div_hz;
+	else if (sel == ACLK_BUS_SEL_V0PLL_DIV)
+		prate = priv->v0pll_div_hz;
+	else if (sel == ACLK_BUS_SEL_V1PLL_DIV)
+		prate = priv->v1pll_div_hz;
+	else
+		return -EINVAL;
+
+	return DIV_TO_RATE(prate, div);
+}
+
+static ulong rk3506_bus_set_rate(struct rk3506_clk_priv *priv, ulong clk_id,
+				 ulong rate)
+{
+	u32 div, sel;
+
+	if (priv->v0pll_div_hz % rate == 0) {
+		sel = ACLK_BUS_SEL_V0PLL_DIV;
+		div = DIV_ROUND_UP(priv->v0pll_div_hz, rate);
+	} else if (priv->v1pll_div_hz % rate == 0) {
+		sel = ACLK_BUS_SEL_V1PLL_DIV;
+		div = DIV_ROUND_UP(priv->v1pll_div_hz, rate);
+	} else {
+		sel = ACLK_BUS_SEL_GPLL_DIV;
+		div = DIV_ROUND_UP(priv->gpll_div_hz, rate);
+	}
+	assert(div - 1 <= 31);
+
+	switch (clk_id) {
+	case ACLK_BUS_ROOT:
+		rk_clrsetreg(RK3506_CLKSEL_CON(21),
+			     ACLK_BUS_SEL_MASK | ACLK_BUS_DIV_MASK,
+			     FIELD_PREP(ACLK_BUS_SEL_MASK, sel) |
+			     FIELD_PREP(ACLK_BUS_DIV_MASK, div - 1));
+		break;
+	case HCLK_BUS_ROOT:
+		rk_clrsetreg(RK3506_CLKSEL_CON(21),
+			     HCLK_BUS_SEL_MASK | HCLK_BUS_DIV_MASK,
+			     FIELD_PREP(HCLK_BUS_SEL_MASK, sel) |
+			     FIELD_PREP(HCLK_BUS_DIV_MASK, div - 1));
+		break;
+	case PCLK_BUS_ROOT:
+		rk_clrsetreg(RK3506_CLKSEL_CON(22),
+			     PCLK_BUS_SEL_MASK | PCLK_BUS_DIV_MASK,
+			     FIELD_PREP(PCLK_BUS_SEL_MASK, sel) |
+			     FIELD_PREP(PCLK_BUS_DIV_MASK, div - 1));
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return rk3506_bus_get_rate(priv, clk_id);
+}
+
+static ulong rk3506_peri_get_rate(struct rk3506_clk_priv *priv, ulong clk_id)
+{
+	u32 con, div, sel;
+	ulong prate;
+
+	switch (clk_id) {
+	case ACLK_HSPERI_ROOT:
+		con = readl(RK3506_CLKSEL_CON(49));
+		sel = FIELD_GET(ACLK_HSPERI_SEL_MASK, con);
+		div = FIELD_GET(ACLK_HSPERI_DIV_MASK, con);
+		break;
+	case HCLK_LSPERI_ROOT:
+		con = readl(RK3506_CLKSEL_CON(29));
+		sel = FIELD_GET(HCLK_LSPERI_SEL_MASK, con);
+		div = FIELD_GET(HCLK_LSPERI_DIV_MASK, con);
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	if (sel == ACLK_HSPERI_SEL_GPLL_DIV)
+		prate = priv->gpll_div_hz;
+	else if (sel == ACLK_HSPERI_SEL_V0PLL_DIV)
+		prate = priv->v0pll_div_hz;
+	else if (sel == ACLK_HSPERI_SEL_V1PLL_DIV)
+		prate = priv->v1pll_div_hz;
+	else
+		return -EINVAL;
+
+	return DIV_TO_RATE(prate, div);
+}
+
+static ulong rk3506_peri_set_rate(struct rk3506_clk_priv *priv, ulong clk_id,
+				  ulong rate)
+{
+	u32 div, sel;
+
+	if (priv->v0pll_div_hz % rate == 0) {
+		sel = ACLK_BUS_SEL_V0PLL_DIV;
+		div = DIV_ROUND_UP(priv->v0pll_div_hz, rate);
+	} else if (priv->v1pll_div_hz % rate == 0) {
+		sel = ACLK_BUS_SEL_V1PLL_DIV;
+		div = DIV_ROUND_UP(priv->v1pll_div_hz, rate);
+	} else {
+		sel = ACLK_BUS_SEL_GPLL_DIV;
+		div = DIV_ROUND_UP(priv->gpll_div_hz, rate);
+	}
+	assert(div - 1 <= 31);
+
+	switch (clk_id) {
+	case ACLK_HSPERI_ROOT:
+		rk_clrsetreg(RK3506_CLKSEL_CON(49),
+			     ACLK_HSPERI_SEL_MASK | ACLK_HSPERI_DIV_MASK,
+			     FIELD_PREP(ACLK_HSPERI_SEL_MASK, sel) |
+			     FIELD_PREP(ACLK_HSPERI_DIV_MASK, div - 1));
+		break;
+	case HCLK_LSPERI_ROOT:
+		rk_clrsetreg(RK3506_CLKSEL_CON(29),
+			     HCLK_LSPERI_SEL_MASK | HCLK_LSPERI_DIV_MASK,
+			     FIELD_PREP(HCLK_LSPERI_SEL_MASK, sel) |
+			     FIELD_PREP(HCLK_LSPERI_DIV_MASK, div - 1));
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return rk3506_peri_get_rate(priv, clk_id);
+}
+
+static ulong rk3506_sdmmc_get_rate(struct rk3506_clk_priv *priv, ulong clk_id)
+{
+	u32 con, div, sel;
+	ulong prate;
+
+	con = readl(RK3506_CLKSEL_CON(49));
+	sel = FIELD_GET(CCLK_SDMMC_SEL_MASK, con);
+	div = FIELD_GET(CCLK_SDMMC_DIV_MASK, con);
+
+	if (sel == CCLK_SDMMC_SEL_24M)
+		prate = OSC_HZ;
+	else if (sel == CCLK_SDMMC_SEL_GPLL)
+		prate = priv->gpll_hz;
+	else if (sel == CCLK_SDMMC_SEL_V0PLL)
+		prate = priv->v0pll_hz;
+	else if (sel == CCLK_SDMMC_SEL_V1PLL)
+		prate = priv->v1pll_hz;
+	else
+		return -EINVAL;
+
+	return DIV_TO_RATE(prate, div);
+}
+
+static ulong rk3506_sdmmc_set_rate(struct rk3506_clk_priv *priv, ulong clk_id,
+				   ulong rate)
+{
+	u32 div, sel;
+
+	if (OSC_HZ % rate == 0) {
+		sel = CCLK_SDMMC_SEL_24M;
+		div = DIV_ROUND_UP(OSC_HZ, rate);
+	} else if (priv->v0pll_hz % rate == 0) {
+		sel = CCLK_SDMMC_SEL_V0PLL;
+		div = DIV_ROUND_UP(priv->v0pll_hz, rate);
+	} else if (priv->v1pll_hz % rate == 0) {
+		sel = CCLK_SDMMC_SEL_V1PLL;
+		div = DIV_ROUND_UP(priv->v1pll_hz, rate);
+	} else {
+		sel = CCLK_SDMMC_SEL_GPLL;
+		div = DIV_ROUND_UP(priv->gpll_hz, rate);
+	}
+	assert(div - 1 <= 63);
+
+	rk_clrsetreg(RK3506_CLKSEL_CON(49),
+		     CCLK_SDMMC_SEL_MASK | CCLK_SDMMC_DIV_MASK,
+		     FIELD_PREP(CCLK_SDMMC_SEL_MASK, sel) |
+		     FIELD_PREP(CCLK_SDMMC_DIV_MASK, div - 1));
+
+	return rk3506_sdmmc_get_rate(priv, clk_id);
+}
+
+static ulong rk3506_saradc_get_rate(struct rk3506_clk_priv *priv, ulong clk_id)
+{
+	u32 con, div, sel;
+	ulong prate;
+
+	con = readl(RK3506_CLKSEL_CON(54));
+	sel = FIELD_GET(CLK_SARADC_SEL_MASK, con);
+	div = FIELD_GET(CLK_SARADC_DIV_MASK, con);
+
+	if (sel == CLK_SARADC_SEL_24M)
+		prate = OSC_HZ;
+	else if (sel == CLK_SARADC_SEL_400K)
+		prate = 400000;
+	else if (sel == CLK_SARADC_SEL_32K)
+		prate = 32000;
+	else
+		return -EINVAL;
+
+	return DIV_TO_RATE(prate, div);
+}
+
+static ulong rk3506_saradc_set_rate(struct rk3506_clk_priv *priv, ulong clk_id,
+				    ulong rate)
+{
+	u32 div, sel;
+
+	if (32000 % rate == 0) {
+		sel = CLK_SARADC_SEL_32K;
+		div = 1;
+	} else if (400000 % rate == 0) {
+		sel = CLK_SARADC_SEL_400K;
+		div = 1;
+	} else {
+		sel = CLK_SARADC_SEL_24M;
+		div = DIV_ROUND_UP(OSC_HZ, rate);
+	}
+	assert(div - 1 <= 15);
+
+	rk_clrsetreg(RK3506_CLKSEL_CON(54),
+		     CLK_SARADC_SEL_MASK | CLK_SARADC_DIV_MASK,
+		     FIELD_PREP(CLK_SARADC_SEL_MASK, sel) |
+		     FIELD_PREP(CLK_SARADC_DIV_MASK, div - 1));
+
+	return rk3506_saradc_get_rate(priv, clk_id);
+}
+
+static ulong rk3506_tsadc_get_rate(struct rk3506_clk_priv *priv, ulong clk_id)
+{
+	u32 con, div;
+
+	con = readl(RK3506_CLKSEL_CON(61));
+	switch (clk_id) {
+	case CLK_TSADC_TSEN:
+		div = FIELD_GET(CLK_TSADC_TSEN_DIV_MASK, con);
+		break;
+	case CLK_TSADC:
+		div = FIELD_GET(CLK_TSADC_DIV_MASK, con);
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return DIV_TO_RATE(OSC_HZ, div);
+}
+
+static ulong rk3506_tsadc_set_rate(struct rk3506_clk_priv *priv, ulong clk_id,
+				   ulong rate)
+{
+	u32 div;
+
+	switch (clk_id) {
+	case CLK_TSADC_TSEN:
+		div = DIV_ROUND_UP(OSC_HZ, rate);
+		assert(div - 1 <= 7);
+		rk_clrsetreg(RK3506_CLKSEL_CON(61), CLK_TSADC_TSEN_DIV_MASK,
+			     FIELD_PREP(CLK_TSADC_TSEN_DIV_MASK, div - 1));
+		break;
+	case CLK_TSADC:
+		div = DIV_ROUND_UP(OSC_HZ, rate);
+		assert(div - 1 <= 255);
+		rk_clrsetreg(RK3506_CLKSEL_CON(61), CLK_TSADC_DIV_MASK,
+			     FIELD_PREP(CLK_TSADC_DIV_MASK, div - 1));
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return rk3506_tsadc_get_rate(priv, clk_id);
+}
+
+static ulong rk3506_i2c_get_rate(struct rk3506_clk_priv *priv, ulong clk_id)
+{
+	u32 con, div, sel;
+	ulong prate;
+
+	switch (clk_id) {
+	case CLK_I2C0:
+		con = readl(RK3506_CLKSEL_CON(32));
+		sel = FIELD_GET(CLK_I2C0_SEL_MASK, con);
+		div = FIELD_GET(CLK_I2C0_DIV_MASK, con);
+	case CLK_I2C1:
+		con = readl(RK3506_CLKSEL_CON(32));
+		sel = FIELD_GET(CLK_I2C1_SEL_MASK, con);
+		div = FIELD_GET(CLK_I2C1_DIV_MASK, con);
+	case CLK_I2C2:
+		con = readl(RK3506_CLKSEL_CON(33));
+		sel = FIELD_GET(CLK_I2C2_SEL_MASK, con);
+		div = FIELD_GET(CLK_I2C2_DIV_MASK, con);
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	if (sel == CLK_I2C_SEL_GPLL)
+		prate = priv->gpll_hz;
+	else if (sel == CLK_I2C_SEL_V0PLL)
+		prate = priv->v0pll_hz;
+	else if (sel == CLK_I2C_SEL_V1PLL)
+		prate = priv->v1pll_hz;
+	else
+		return -EINVAL;
+
+	return DIV_TO_RATE(prate, div);
+}
+
+static ulong rk3506_i2c_set_rate(struct rk3506_clk_priv *priv, ulong clk_id,
+				 ulong rate)
+{
+	u32 div, sel;
+
+	if (priv->v0pll_hz % rate == 0) {
+		sel = CLK_I2C_SEL_V0PLL;
+		div = DIV_ROUND_UP(priv->v0pll_hz, rate);
+	} else if (priv->v1pll_hz % rate == 0) {
+		sel = CLK_I2C_SEL_V1PLL;
+		div = DIV_ROUND_UP(priv->v1pll_hz, rate);
+	} else {
+		sel = CLK_I2C_SEL_GPLL;
+		div = DIV_ROUND_UP(priv->gpll_hz, rate);
+	}
+	assert(div - 1 <= 15);
+
+	switch (clk_id) {
+	case CLK_I2C0:
+		rk_clrsetreg(RK3506_CLKSEL_CON(32),
+			     CLK_I2C0_SEL_MASK | CLK_I2C0_DIV_MASK,
+			     FIELD_PREP(CLK_I2C0_SEL_MASK, sel) |
+			     FIELD_PREP(CLK_I2C0_DIV_MASK, div - 1));
+		break;
+	case CLK_I2C1:
+		rk_clrsetreg(RK3506_CLKSEL_CON(32),
+			     CLK_I2C1_SEL_MASK | CLK_I2C1_DIV_MASK,
+			     FIELD_PREP(CLK_I2C1_SEL_MASK, sel) |
+			     FIELD_PREP(CLK_I2C1_DIV_MASK, div - 1));
+		break;
+	case CLK_I2C2:
+		rk_clrsetreg(RK3506_CLKSEL_CON(33),
+			     CLK_I2C2_SEL_MASK | CLK_I2C2_DIV_MASK,
+			     FIELD_PREP(CLK_I2C2_SEL_MASK, sel) |
+			     FIELD_PREP(CLK_I2C2_DIV_MASK, div - 1));
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return rk3506_i2c_get_rate(priv, clk_id);
+}
+
+static ulong rk3506_pwm_get_rate(struct rk3506_clk_priv *priv, ulong clk_id)
+{
+	u32 con, div, sel;
+	ulong prate;
+
+	switch (clk_id) {
+	case CLK_PWM0:
+		con = readl(RK3506_PMU_CLKSEL_CON(0));
+		div = FIELD_GET(CLK_PWM0_DIV_MASK, con);
+		prate = priv->gpll_div_100mhz;
+		break;
+	case CLK_PWM1:
+		con = readl(RK3506_CLKSEL_CON(33));
+		sel = FIELD_GET(CLK_PWM1_SEL_MASK, con);
+		div = FIELD_GET(CLK_PWM1_DIV_MASK, con);
+		if (sel == CLK_PWM1_SEL_GPLL_DIV)
+			prate = priv->gpll_div_hz;
+		else if (sel == CLK_PWM1_SEL_V0PLL_DIV)
+			prate = priv->v0pll_div_hz;
+		else if (sel == CLK_PWM1_SEL_V1PLL_DIV)
+			prate = priv->v1pll_div_hz;
+		else
+			return -EINVAL;
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return DIV_TO_RATE(prate, div);
+}
+
+static ulong rk3506_pwm_set_rate(struct rk3506_clk_priv *priv, ulong clk_id,
+				 ulong rate)
+{
+	u32 div, sel;
+
+	switch (clk_id) {
+	case CLK_PWM0:
+		div = DIV_ROUND_UP(priv->gpll_div_100mhz, rate);
+		assert(div - 1 <= 15);
+		rk_clrsetreg(RK3506_PMU_CLKSEL_CON(0), CLK_PWM0_DIV_MASK,
+			     FIELD_PREP(CLK_PWM0_DIV_MASK, div - 1));
+		break;
+	case CLK_PWM1:
+		if (priv->v0pll_hz % rate == 0) {
+			sel = CLK_PWM1_SEL_V0PLL_DIV;
+			div = DIV_ROUND_UP(priv->v0pll_div_hz, rate);
+		} else if (priv->v1pll_hz % rate == 0) {
+			sel = CLK_PWM1_SEL_V1PLL_DIV;
+			div = DIV_ROUND_UP(priv->v1pll_div_hz, rate);
+		} else {
+			sel = CLK_PWM1_SEL_GPLL_DIV;
+			div = DIV_ROUND_UP(priv->gpll_div_hz, rate);
+		}
+		assert(div - 1 <= 15);
+		rk_clrsetreg(RK3506_CLKSEL_CON(33),
+			     CLK_PWM1_SEL_MASK | CLK_PWM1_DIV_MASK,
+			     FIELD_PREP(CLK_PWM1_SEL_MASK, sel) |
+			     FIELD_PREP(CLK_PWM1_DIV_MASK, div - 1));
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return rk3506_pwm_get_rate(priv, clk_id);
+}
+
+static ulong rk3506_spi_get_rate(struct rk3506_clk_priv *priv, ulong clk_id)
+{
+	u32 con, div, sel;
+	ulong prate;
+
+	switch (clk_id) {
+	case CLK_SPI0:
+		con = readl(RK3506_CLKSEL_CON(34));
+		sel = FIELD_GET(CLK_SPI0_SEL_MASK, con);
+		div = FIELD_GET(CLK_SPI0_DIV_MASK, con);
+		break;
+	case CLK_SPI1:
+		con = readl(RK3506_CLKSEL_CON(34));
+		sel = FIELD_GET(CLK_SPI1_SEL_MASK, con);
+		div = FIELD_GET(CLK_SPI1_DIV_MASK, con);
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	if (sel == CLK_SPI_SEL_24M)
+		prate = OSC_HZ;
+	else if (sel == CLK_SPI_SEL_GPLL_DIV)
+		prate = priv->gpll_div_hz;
+	else if (sel == CLK_SPI_SEL_V0PLL_DIV)
+		prate = priv->v0pll_div_hz;
+	else if (sel == CLK_SPI_SEL_V1PLL_DIV)
+		prate = priv->v1pll_div_hz;
+	else
+		return -EINVAL;
+
+	return DIV_TO_RATE(prate, div);
+}
+
+static ulong rk3506_spi_set_rate(struct rk3506_clk_priv *priv, ulong clk_id,
+				 ulong rate)
+{
+	u32 div, sel;
+
+	if (OSC_HZ % rate == 0) {
+		sel = CLK_SPI_SEL_24M;
+		div = DIV_ROUND_UP(OSC_HZ, rate);
+	} else if (priv->v0pll_div_hz % rate == 0) {
+		sel = CLK_SPI_SEL_V0PLL_DIV;
+		div = DIV_ROUND_UP(priv->v0pll_div_hz, rate);
+	} else if (priv->v1pll_div_hz % rate == 0) {
+		sel = CLK_SPI_SEL_V1PLL_DIV;
+		div = DIV_ROUND_UP(priv->v1pll_div_hz, rate);
+	} else {
+		sel = CLK_SPI_SEL_GPLL_DIV;
+		div = DIV_ROUND_UP(priv->gpll_div_hz, rate);
+	}
+	assert(div - 1 <= 15);
+
+	switch (clk_id) {
+	case CLK_SPI0:
+		rk_clrsetreg(RK3506_CLKSEL_CON(34),
+			     CLK_SPI0_SEL_MASK | CLK_SPI0_DIV_MASK,
+			     FIELD_PREP(CLK_SPI0_SEL_MASK, sel) |
+			     FIELD_PREP(CLK_SPI0_DIV_MASK, div - 1));
+		break;
+	case CLK_SPI1:
+		rk_clrsetreg(RK3506_CLKSEL_CON(34),
+			     CLK_SPI1_SEL_MASK | CLK_SPI1_DIV_MASK,
+			     FIELD_PREP(CLK_SPI1_SEL_MASK, sel) |
+			     FIELD_PREP(CLK_SPI1_DIV_MASK, div - 1));
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return rk3506_spi_get_rate(priv, clk_id);
+}
+
+static ulong rk3506_fspi_get_rate(struct rk3506_clk_priv *priv)
+{
+	u32 con, div, sel;
+	ulong prate;
+
+	con = readl(RK3506_CLKSEL_CON(50));
+	sel = FIELD_GET(SCLK_FSPI_SEL_MASK, con);
+	div = FIELD_GET(SCLK_FSPI_DIV_MASK, con);
+
+	if (sel == SCLK_FSPI_SEL_24M)
+		prate = OSC_HZ;
+	else if (sel == SCLK_FSPI_SEL_GPLL)
+		prate = priv->gpll_hz;
+	else if (sel == SCLK_FSPI_SEL_V0PLL)
+		prate = priv->v0pll_hz;
+	else if (sel == SCLK_FSPI_SEL_V1PLL)
+		prate = priv->v1pll_hz;
+	else
+		return -EINVAL;
+
+	return DIV_TO_RATE(prate, div);
+}
+
+static ulong rk3506_fspi_set_rate(struct rk3506_clk_priv *priv, ulong rate)
+{
+	int div, sel;
+
+	if (OSC_HZ % rate == 0) {
+		sel = SCLK_FSPI_SEL_24M;
+		div = DIV_ROUND_UP(OSC_HZ, rate);
+	} else if (priv->v0pll_hz % rate == 0) {
+		sel = SCLK_FSPI_SEL_V0PLL;
+		div = DIV_ROUND_UP(priv->v0pll_hz, rate);
+	} else if (priv->v1pll_hz % rate == 0) {
+		sel = SCLK_FSPI_SEL_V1PLL;
+		div = DIV_ROUND_UP(priv->v1pll_hz, rate);
+	} else {
+		sel = SCLK_FSPI_SEL_GPLL;
+		div = DIV_ROUND_UP(priv->gpll_hz, rate);
+	}
+	assert(div - 1 <= 31);
+
+	rk_clrsetreg(RK3506_CLKSEL_CON(50),
+		     SCLK_FSPI_SEL_MASK | SCLK_FSPI_DIV_MASK,
+		     FIELD_PREP(SCLK_FSPI_SEL_MASK, sel) |
+		     FIELD_PREP(SCLK_FSPI_DIV_MASK, div - 1));
+
+	return rk3506_fspi_get_rate(priv);
+}
+
+static ulong rk3506_vop_dclk_get_rate(struct rk3506_clk_priv *priv)
+{
+	u32 con, div, sel;
+	ulong prate;
+
+	con = readl(RK3506_CLKSEL_CON(60));
+	sel = FIELD_GET(DCLK_VOP_SEL_MASK, con);
+	div = FIELD_GET(DCLK_VOP_DIV_MASK, con);
+
+	if (sel == DCLK_VOP_SEL_24M)
+		prate = OSC_HZ;
+	else if (sel == DCLK_VOP_SEL_GPLL)
+		prate = priv->gpll_hz;
+	else if (sel == DCLK_VOP_SEL_V0PLL)
+		prate = priv->v0pll_hz;
+	else if (sel == DCLK_VOP_SEL_V1PLL)
+		prate = priv->v1pll_hz;
+	else
+		return -EINVAL;
+
+	return DIV_TO_RATE(prate, div);
+}
+
+static ulong rk3506_vop_dclk_set_rate(struct rk3506_clk_priv *priv, ulong rate)
+{
+	int div, sel;
+
+	if (OSC_HZ % rate == 0) {
+		sel = DCLK_VOP_SEL_24M;
+		div = DIV_ROUND_UP(OSC_HZ, rate);
+	} else if (priv->v0pll_hz % rate == 0) {
+		sel = DCLK_VOP_SEL_V0PLL;
+		div = DIV_ROUND_UP(priv->v0pll_hz, rate);
+	} else if (priv->v1pll_hz % rate == 0) {
+		sel = DCLK_VOP_SEL_V1PLL;
+		div = DIV_ROUND_UP(priv->v1pll_hz, rate);
+	} else {
+		sel = DCLK_VOP_SEL_GPLL;
+		div = DIV_ROUND_UP(priv->gpll_hz, rate);
+	}
+	assert(div - 1 <= 255);
+
+	rk_clrsetreg(RK3506_CLKSEL_CON(60),
+		     DCLK_VOP_SEL_MASK | DCLK_VOP_DIV_MASK,
+		     FIELD_PREP(DCLK_VOP_SEL_MASK, sel) |
+		     FIELD_PREP(DCLK_VOP_DIV_MASK, div - 1));
+
+	return rk3506_vop_dclk_get_rate(priv);
+}
+
+static ulong rk3506_mac_get_rate(struct rk3506_clk_priv *priv, ulong clk_id)
+{
+	u32 con, div;
+
+	switch (clk_id) {
+	case CLK_MAC0:
+	case CLK_MAC1:
+		con = readl(RK3506_CLKSEL_CON(50));
+		div = FIELD_GET(CLK_MAC_DIV_MASK, con);
+		break;
+	case CLK_MAC_OUT:
+		con = readl(RK3506_PMU_CLKSEL_CON(0));
+		div = FIELD_GET(CLK_MAC_OUT_DIV_MASK, con);
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return DIV_TO_RATE(priv->gpll_hz, div);
+}
+
+static ulong rk3506_mac_set_rate(struct rk3506_clk_priv *priv, ulong clk_id,
+				 ulong rate)
+{
+	u32 div;
+
+	switch (clk_id) {
+	case CLK_MAC0:
+	case CLK_MAC1:
+		div = DIV_ROUND_UP(priv->gpll_hz, rate);
+		rk_clrsetreg(RK3506_CLKSEL_CON(50), CLK_MAC_DIV_MASK,
+			     FIELD_PREP(CLK_MAC_DIV_MASK, div - 1));
+		break;
+	case CLK_MAC_OUT:
+		div = DIV_ROUND_UP(priv->gpll_hz, rate);
+		rk_clrsetreg(RK3506_PMU_CLKSEL_CON(0), CLK_MAC_OUT_DIV_MASK,
+			     FIELD_PREP(CLK_MAC_OUT_DIV_MASK, div - 1));
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return rk3506_mac_get_rate(priv, clk_id);
+}
+
+static ulong rk3506_clk_get_rate(struct clk *clk)
+{
+	struct rk3506_clk_priv *priv = dev_get_priv(clk->dev);
+	ulong rate = 0;
+
+	if (!priv->gpll_hz || !priv->v0pll_hz || !priv->v1pll_hz) {
+		log_debug("gpll=%lu, v0pll=%lu, v1pll=%lu\n",
+			  priv->gpll_hz, priv->v0pll_hz, priv->v1pll_hz);
+		return -ENOENT;
+	}
+
+	switch (clk->id) {
+	case PLL_GPLL:
+		rate = priv->gpll_hz;
+		break;
+	case PLL_V0PLL:
+		rate = priv->v0pll_hz;
+		break;
+	case PLL_V1PLL:
+		rate = priv->v1pll_hz;
+		break;
+	case ARMCLK:
+		rate = rk3506_armclk_get_rate(priv);
+		break;
+	case CLK_GPLL_DIV:
+	case CLK_GPLL_DIV_100M:
+	case CLK_V0PLL_DIV:
+	case CLK_V1PLL_DIV:
+		rate = rk3506_pll_div_get_rate(priv, clk->id);
+		break;
+	case ACLK_BUS_ROOT:
+	case HCLK_BUS_ROOT:
+	case PCLK_BUS_ROOT:
+		rate = rk3506_bus_get_rate(priv, clk->id);
+		break;
+	case ACLK_HSPERI_ROOT:
+	case HCLK_LSPERI_ROOT:
+		rate = rk3506_peri_get_rate(priv, clk->id);
+		break;
+	case HCLK_SDMMC:
+	case CCLK_SRC_SDMMC:
+		rate = rk3506_sdmmc_get_rate(priv, clk->id);
+		break;
+	case CLK_SARADC:
+		rate = rk3506_saradc_get_rate(priv, clk->id);
+		break;
+	case CLK_TSADC:
+	case CLK_TSADC_TSEN:
+		rate = rk3506_tsadc_get_rate(priv, clk->id);
+		break;
+	case CLK_I2C0:
+	case CLK_I2C1:
+	case CLK_I2C2:
+		rate = rk3506_i2c_get_rate(priv, clk->id);
+		break;
+	case CLK_PWM0:
+	case CLK_PWM1:
+		rate = rk3506_pwm_get_rate(priv, clk->id);
+		break;
+	case CLK_SPI0:
+	case CLK_SPI1:
+		rate = rk3506_spi_get_rate(priv, clk->id);
+		break;
+	case SCLK_FSPI:
+		rate = rk3506_fspi_get_rate(priv);
+		break;
+	case DCLK_VOP:
+		rate = rk3506_vop_dclk_get_rate(priv);
+		break;
+	case CLK_MAC0:
+	case CLK_MAC1:
+	case CLK_MAC_OUT:
+		rate = rk3506_mac_get_rate(priv, clk->id);
+		break;
+	default:
+		log_debug("unsupported clk id=%ld\n", clk->id);
+		return -ENOENT;
+	}
+
+	return rate;
+};
+
+static ulong rk3506_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct rk3506_clk_priv *priv = dev_get_priv(clk->dev);
+	ulong ret = 0;
+
+	if (!priv->gpll_hz || !priv->v0pll_hz || !priv->v1pll_hz) {
+		log_debug("gpll=%lu, v0pll=%lu, v1pll=%lu\n",
+			  priv->gpll_hz, priv->v0pll_hz, priv->v1pll_hz);
+		return -ENOENT;
+	}
+
+	switch (clk->id) {
+	case ARMCLK:
+		ret = rk3506_armclk_set_rate(priv, rate);
+		break;
+	case CLK_GPLL_DIV:
+	case CLK_GPLL_DIV_100M:
+	case CLK_V0PLL_DIV:
+	case CLK_V1PLL_DIV:
+		ret = rk3506_pll_div_set_rate(priv, clk->id, rate);
+		break;
+	case ACLK_BUS_ROOT:
+	case HCLK_BUS_ROOT:
+	case PCLK_BUS_ROOT:
+		ret = rk3506_bus_set_rate(priv, clk->id, rate);
+		break;
+	case ACLK_HSPERI_ROOT:
+	case HCLK_LSPERI_ROOT:
+		ret = rk3506_peri_set_rate(priv, clk->id, rate);
+		break;
+	case HCLK_SDMMC:
+	case CCLK_SRC_SDMMC:
+		ret = rk3506_sdmmc_set_rate(priv, clk->id, rate);
+		break;
+	case CLK_SARADC:
+		ret = rk3506_saradc_set_rate(priv, clk->id, rate);
+		break;
+	case CLK_TSADC:
+	case CLK_TSADC_TSEN:
+		ret = rk3506_tsadc_set_rate(priv, clk->id, rate);
+		break;
+	case CLK_I2C0:
+	case CLK_I2C1:
+	case CLK_I2C2:
+		ret = rk3506_i2c_set_rate(priv, clk->id, rate);
+		break;
+	case CLK_PWM0:
+	case CLK_PWM1:
+		ret = rk3506_pwm_set_rate(priv, clk->id, rate);
+		break;
+	case CLK_SPI0:
+	case CLK_SPI1:
+		ret = rk3506_spi_set_rate(priv, clk->id, rate);
+		break;
+	case SCLK_FSPI:
+		ret = rk3506_fspi_set_rate(priv, rate);
+		break;
+	case DCLK_VOP:
+		ret = rk3506_vop_dclk_set_rate(priv, rate);
+		break;
+	case CLK_MAC0:
+	case CLK_MAC1:
+	case CLK_MAC_OUT:
+		ret = rk3506_mac_set_rate(priv, clk->id, rate);
+		break;
+	default:
+		log_debug("unsupported clk id=%ld rate=%ld\n", clk->id, rate);
+		return -ENOENT;
+	}
+
+	return ret;
+};
+
+static struct clk_ops rk3506_clk_ops = {
+	.get_rate = rk3506_clk_get_rate,
+	.set_rate = rk3506_clk_set_rate,
+};
+
+static void rk3506_clk_init(struct rk3506_clk_priv *priv)
+{
+	static void * const cru_base = (void *)RK3506_CRU_BASE;
+
+	if (!priv->gpll_hz) {
+		priv->gpll_hz = rockchip_pll_get_rate(&rk3506_pll_clks[GPLL],
+						      cru_base, GPLL);
+		priv->gpll_hz = roundup(priv->gpll_hz, 1000);
+	}
+	if (!priv->v0pll_hz) {
+		priv->v0pll_hz = rockchip_pll_get_rate(&rk3506_pll_clks[V0PLL],
+						       cru_base, V0PLL);
+		priv->v0pll_hz = roundup(priv->v0pll_hz, 1000);
+	}
+	if (!priv->v1pll_hz) {
+		priv->v1pll_hz = rockchip_pll_get_rate(&rk3506_pll_clks[V1PLL],
+						       cru_base, V1PLL);
+		priv->v1pll_hz = roundup(priv->v1pll_hz, 1000);
+	}
+	if (!priv->gpll_div_hz) {
+		priv->gpll_div_hz = rk3506_pll_div_get_rate(priv, CLK_GPLL_DIV);
+		priv->gpll_div_hz = roundup(priv->gpll_div_hz, 1000);
+	}
+	if (!priv->gpll_div_100mhz) {
+		priv->gpll_div_100mhz = rk3506_pll_div_get_rate(priv,
+								CLK_GPLL_DIV_100M);
+		priv->gpll_div_100mhz = roundup(priv->gpll_div_100mhz, 1000);
+	}
+	if (!priv->v0pll_div_hz) {
+		priv->v0pll_div_hz = rk3506_pll_div_get_rate(priv, CLK_V0PLL_DIV);
+		priv->v0pll_div_hz = roundup(priv->v0pll_div_hz, 1000);
+	}
+	if (!priv->v1pll_div_hz) {
+		priv->v1pll_div_hz = rk3506_pll_div_get_rate(priv, CLK_V1PLL_DIV);
+		priv->v1pll_div_hz = roundup(priv->v1pll_div_hz, 1000);
+	}
+}
+
+static void rk3506_clk_init_xpl(void)
+{
+	/* Init pka crypto rate, sel=v0pll, div=3 */
+	rk_clrsetreg(RK3506_SCRU_BASE + 0x0010,
+		     CLK_PKA_CRYPTO_SEL_MASK | CLK_PKA_CRYPTO_DIV_MASK,
+		     FIELD_PREP(CLK_PKA_CRYPTO_SEL_MASK, CLK_PKA_CRYPTO_SEL_V0PLL) |
+		     FIELD_PREP(CLK_PKA_CRYPTO_DIV_MASK, 3));
+
+	/* Change clk core src rate, sel=gpll, div=3 */
+	rk_clrsetreg(RK3506_CLKSEL_CON(15),
+		     CLK_CORE_SRC_SEL_MASK | CLK_CORE_SRC_DIV_MASK,
+		     FIELD_PREP(CLK_CORE_SRC_SEL_MASK, CLK_CORE_SEL_GPLL) |
+		     FIELD_PREP(CLK_CORE_SRC_DIV_MASK, 3));
+}
+
+static int rk3506_clk_probe(struct udevice *dev)
+{
+	struct rk3506_clk_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	rk3506_clk_init(priv);
+
+	/* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
+	ret = clk_set_defaults(dev, 1);
+	if (ret)
+		log_debug("clk_set_defaults failed: ret=%d\n", ret);
+
+	return 0;
+}
+
+static int rk3506_clk_bind(struct udevice *dev)
+{
+	struct udevice *sys_child;
+	struct sysreset_reg *priv;
+	int ret;
+
+	if (IS_ENABLED(CONFIG_XPL_BUILD))
+		rk3506_clk_init_xpl();
+
+	/* The reset driver does not have a device node, so bind it here */
+	ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
+				 &sys_child);
+	if (ret) {
+		log_debug("Warning: No sysreset driver: ret=%d\n", ret);
+	} else {
+		priv = malloc(sizeof(struct sysreset_reg));
+		priv->glb_srst_fst_value = RK3506_GLB_SRST_FST;
+		priv->glb_srst_snd_value = RK3506_GLB_SRST_SND;
+		dev_set_priv(sys_child, priv);
+	}
+
+	if (!CONFIG_IS_ENABLED(RESET_ROCKCHIP))
+		return 0;
+
+	ret = rk3506_reset_bind_lut(dev, RK3506_SOFTRST_CON0, 23);
+	if (ret)
+		log_debug("Warning: software reset driver bind failed\n");
+
+	return 0;
+}
+
+static const struct udevice_id rk3506_clk_ids[] = {
+	{ .compatible = "rockchip,rk3506-cru" },
+	{ }
+};
+
+U_BOOT_DRIVER(rockchip_rk3506_cru) = {
+	.name		= "rockchip_rk3506_cru",
+	.id		= UCLASS_CLK,
+	.of_match	= rk3506_clk_ids,
+	.priv_auto	= sizeof(struct rk3506_clk_priv),
+	.ops		= &rk3506_clk_ops,
+	.bind		= rk3506_clk_bind,
+	.probe		= rk3506_clk_probe,
+};
diff --git a/drivers/misc/rockchip-otp.c b/drivers/misc/rockchip-otp.c
index 46820425a84..64b6238981b 100644
--- a/drivers/misc/rockchip-otp.c
+++ b/drivers/misc/rockchip-otp.c
@@ -391,6 +391,10 @@ static const struct udevice_id rockchip_otp_ids[] = {
 		.data = (ulong)&px30_data,
 	},
 	{
+		.compatible = "rockchip,rk3506-otp",
+		.data = (ulong)&rk3568_data,
+	},
+	{
 		.compatible = "rockchip,rk3528-otp",
 		.data = (ulong)&rk3568_data,
 	},
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 8a396d0b29e..0f31d646845 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1621,6 +1621,10 @@ static const struct udevice_id eqos_ids[] = {
 #endif
 #if IS_ENABLED(CONFIG_DWC_ETH_QOS_ROCKCHIP)
 	{
+		.compatible = "rockchip,rk3506-gmac",
+		.data = (ulong)&eqos_rockchip_config
+	},
+	{
 		.compatible = "rockchip,rk3528-gmac",
 		.data = (ulong)&eqos_rockchip_config
 	},
diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c
index d646d3ebac8..4ccefda0ef5 100644
--- a/drivers/net/dwc_eth_qos_rockchip.c
+++ b/drivers/net/dwc_eth_qos_rockchip.c
@@ -50,6 +50,80 @@ struct rockchip_platform_data {
 	(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
 	 ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
 
+#define RK3506_GRF_SOC_CON8		0x0020
+#define RK3506_GRF_SOC_CON11		0x002c
+
+#define RK3506_GMAC_RMII_MODE		GRF_BIT(1)
+
+#define RK3506_GMAC_CLK_RMII_DIV2	GRF_BIT(3)
+#define RK3506_GMAC_CLK_RMII_DIV20	GRF_CLR_BIT(3)
+
+#define RK3506_GMAC_CLK_SELECT_CRU	GRF_CLR_BIT(5)
+#define RK3506_GMAC_CLK_SELECT_IO	GRF_BIT(5)
+
+#define RK3506_GMAC_CLK_RMII_GATE	GRF_BIT(2)
+#define RK3506_GMAC_CLK_RMII_NOGATE	GRF_CLR_BIT(2)
+
+static int rk3506_set_to_rgmii(struct udevice *dev,
+			       int tx_delay, int rx_delay)
+{
+	return -EINVAL;
+}
+
+static int rk3506_set_to_rmii(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_plat(dev);
+	struct rockchip_platform_data *data = pdata->priv_pdata;
+	u32 reg;
+
+	reg = data->id == 1 ? RK3506_GRF_SOC_CON11 :
+			      RK3506_GRF_SOC_CON8;
+	regmap_write(data->grf, reg, RK3506_GMAC_RMII_MODE);
+
+	return 0;
+}
+
+static int rk3506_set_gmac_speed(struct udevice *dev)
+{
+	struct eqos_priv *eqos = dev_get_priv(dev);
+	struct eth_pdata *pdata = dev_get_plat(dev);
+	struct rockchip_platform_data *data = pdata->priv_pdata;
+	u32 val, reg;
+
+	switch (eqos->phy->speed) {
+	case SPEED_10:
+		val = RK3506_GMAC_CLK_RMII_DIV20;
+		break;
+	case SPEED_100:
+		val = RK3506_GMAC_CLK_RMII_DIV2;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	reg = data->id == 1 ? RK3506_GRF_SOC_CON11 :
+			      RK3506_GRF_SOC_CON8;
+	regmap_write(data->grf, reg, val);
+
+	return 0;
+}
+
+static void rk3506_set_clock_selection(struct udevice *dev, bool enable)
+{
+	struct eth_pdata *pdata = dev_get_plat(dev);
+	struct rockchip_platform_data *data = pdata->priv_pdata;
+	u32 val, reg;
+
+	val = data->clock_input ? RK3506_GMAC_CLK_SELECT_IO :
+				  RK3506_GMAC_CLK_SELECT_CRU;
+	val |= enable ? RK3506_GMAC_CLK_RMII_NOGATE :
+			RK3506_GMAC_CLK_RMII_GATE;
+
+	reg = data->id == 1 ? RK3506_GRF_SOC_CON11 :
+			      RK3506_GRF_SOC_CON8;
+	regmap_write(data->grf, reg, val);
+}
+
 #define RK3528_VO_GRF_GMAC_CON		0x0018
 #define RK3528_VPU_GRF_GMAC_CON5	0x0018
 #define RK3528_VPU_GRF_GMAC_CON6	0x001c
@@ -535,6 +609,18 @@ static void rk3588_set_clock_selection(struct udevice *dev, bool enable)
 
 static const struct rk_gmac_ops rk_gmac_ops[] = {
 	{
+		.compatible = "rockchip,rk3506-gmac",
+		.set_to_rgmii = rk3506_set_to_rgmii,
+		.set_to_rmii = rk3506_set_to_rmii,
+		.set_gmac_speed = rk3506_set_gmac_speed,
+		.set_clock_selection = rk3506_set_clock_selection,
+		.regs = {
+			0xff4c8000, /* gmac0 */
+			0xff4d0000, /* gmac1 */
+			0x0, /* sentinel */
+		},
+	},
+	{
 		.compatible = "rockchip,rk3528-gmac",
 		.set_to_rgmii = rk3528_set_to_rgmii,
 		.set_to_rmii = rk3528_set_to_rmii,
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 4ea6600ce7f..f80b2789333 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -421,6 +421,22 @@ static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = {
 	{ /* sentinel */ }
 };
 
+static const struct rockchip_usb2phy_cfg rk3506_phy_cfgs[] = {
+	{
+		.reg		= 0xff2b0000,
+		.clkout_ctl_phy = { 0x041c, 7, 2, 0, 0x27 },
+		.port_cfgs	= {
+			[USB2PHY_PORT_OTG] = {
+				.phy_sus	= { 0x0060, 1, 0, 2, 1 },
+			},
+			[USB2PHY_PORT_HOST] = {
+				.phy_sus	= { 0x0070, 1, 0, 2, 1 },
+			}
+		},
+	},
+	{ /* sentinel */ }
+};
+
 static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = {
 	{
 		.reg		= 0xffdf0000,
@@ -541,6 +557,10 @@ static const struct udevice_id rockchip_usb2phy_ids[] = {
 		.data = (ulong)&rk3399_usb2phy_cfgs,
 	},
 	{
+		.compatible = "rockchip,rk3506-usb2phy",
+		.data = (ulong)&rk3506_phy_cfgs,
+	},
+	{
 		.compatible = "rockchip,rk3528-usb2phy",
 		.data = (ulong)&rk3528_phy_cfgs,
 	},
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index d602f965d6a..82353ae7678 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -399,6 +399,14 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
 		param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
 		param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
 		param_write(priv->phy_grf, &cfg->usb_mode_set, true);
+		switch (priv->id) {
+		case 0:
+			param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true);
+			break;
+		case 1:
+			param_write(priv->pipe_grf, &cfg->u3otg1_port_en, true);
+			break;
+		}
 		break;
 	case PHY_TYPE_SATA:
 		writel(0x41, priv->mmio + 0x38);
diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
index e17415e1ca6..0405df128df 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl-rk3308.o
 obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
 obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3506) += pinctrl-rk3506.o
 obj-$(CONFIG_ROCKCHIP_RK3528) += pinctrl-rk3528.o
 obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
 obj-$(CONFIG_ROCKCHIP_RK3576) += pinctrl-rk3576.o
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3506.c b/drivers/pinctrl/rockchip/pinctrl-rk3506.c
new file mode 100644
index 00000000000..969acb66f15
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3506.c
@@ -0,0 +1,462 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#include "pinctrl-rockchip.h"
+#include <dt-bindings/pinctrl/rockchip.h>
+
+static int rk3506_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+	struct rockchip_pinctrl_priv *priv = bank->priv;
+	int iomux_num = (pin / 8);
+	struct regmap *regmap;
+	int reg, mask;
+	u8 bit;
+	u32 data, rmask;
+
+	if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+		regmap = priv->regmap_pmu;
+	else
+		regmap = priv->regmap_base;
+
+	if (bank->bank_num == 1)
+		regmap = priv->regmap_ioc1;
+	else if (bank->bank_num == 4)
+		return 0;
+
+	reg = bank->iomux[iomux_num].offset;
+	if ((pin % 8) >= 4)
+		reg += 0x4;
+	bit = (pin % 4) * 4;
+	mask = 0xf;
+
+	if (bank->recalced_mask & BIT(pin))
+		rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
+
+	data = (mask << (bit + 16));
+	rmask = data | (data >> 16);
+	data |= (mux & mask) << bit;
+
+	return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+#define RK3506_DRV_BITS_PER_PIN		8
+#define RK3506_DRV_PINS_PER_REG		2
+#define RK3506_DRV_GPIO0_A_OFFSET	0x100
+#define RK3506_DRV_GPIO0_D_OFFSET	0x830
+#define RK3506_DRV_GPIO1_OFFSET		0x140
+#define RK3506_DRV_GPIO2_OFFSET		0x180
+#define RK3506_DRV_GPIO3_OFFSET		0x1c0
+#define RK3506_DRV_GPIO4_OFFSET		0x840
+
+static int rk3506_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+				       int pin_num, struct regmap **regmap,
+				       int *reg, u8 *bit)
+{
+	struct rockchip_pinctrl_priv *priv = bank->priv;
+	int ret = 0;
+
+	switch (bank->bank_num) {
+	case 0:
+		*regmap = priv->regmap_pmu;
+		if (pin_num > 24) {
+			ret = -EINVAL;
+		} else if (pin_num < 24) {
+			*reg = RK3506_DRV_GPIO0_A_OFFSET;
+		} else {
+			*reg = RK3506_DRV_GPIO0_D_OFFSET;
+			*bit = 3;
+
+			return 0;
+		}
+		break;
+
+	case 1:
+		*regmap = priv->regmap_ioc1;
+		if (pin_num < 28)
+			*reg = RK3506_DRV_GPIO1_OFFSET;
+		else
+			ret = -EINVAL;
+		break;
+
+	case 2:
+		*regmap = priv->regmap_base;
+		if (pin_num < 17)
+			*reg = RK3506_DRV_GPIO2_OFFSET;
+		else
+			ret = -EINVAL;
+		break;
+
+	case 3:
+		*regmap = priv->regmap_base;
+		if (pin_num < 15)
+			*reg = RK3506_DRV_GPIO3_OFFSET;
+		else
+			ret = -EINVAL;
+		break;
+
+	case 4:
+		*regmap = priv->regmap_base;
+		if (pin_num < 8 || pin_num > 11) {
+			ret = -EINVAL;
+		} else {
+			*reg = RK3506_DRV_GPIO4_OFFSET;
+			*bit = 10;
+
+			return 0;
+		}
+		break;
+
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+	if (ret) {
+		debug("unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
+		return ret;
+	}
+
+	*reg += ((pin_num / RK3506_DRV_PINS_PER_REG) * 4);
+	*bit = pin_num % RK3506_DRV_PINS_PER_REG;
+	*bit *= RK3506_DRV_BITS_PER_PIN;
+
+	return 0;
+}
+
+static int rk3506_set_drive(struct rockchip_pin_bank *bank,
+			    int pin_num, int strength)
+{
+	struct regmap *regmap;
+	int reg, ret, i;
+	u32 data, rmask;
+	u8 bit;
+	int rmask_bits = RK3506_DRV_BITS_PER_PIN;
+
+	ret = rk3506_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	if (ret)
+		return ret;
+
+	for (i = 0, ret = 1; i < strength; i++)
+		ret = (ret << 1) | 1;
+
+	if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) {
+		rmask_bits = 2;
+		ret = strength;
+	}
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << rmask_bits) - 1) << (bit + 16);
+	rmask = data | (data >> 16);
+	data |= (ret << bit);
+
+	return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+#define RK3506_PULL_BITS_PER_PIN	2
+#define RK3506_PULL_PINS_PER_REG	8
+#define RK3506_PULL_GPIO0_A_OFFSET	0x200
+#define RK3506_PULL_GPIO0_D_OFFSET	0x830
+#define RK3506_PULL_GPIO1_OFFSET	0x210
+#define RK3506_PULL_GPIO2_OFFSET	0x220
+#define RK3506_PULL_GPIO3_OFFSET	0x230
+#define RK3506_PULL_GPIO4_OFFSET	0x840
+
+static int rk3506_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+					int pin_num, struct regmap **regmap,
+					int *reg, u8 *bit)
+{
+	struct rockchip_pinctrl_priv *priv = bank->priv;
+	int ret = 0;
+
+	switch (bank->bank_num) {
+	case 0:
+		*regmap = priv->regmap_pmu;
+		if (pin_num > 24) {
+			ret = -EINVAL;
+		} else if (pin_num < 24) {
+			*reg = RK3506_PULL_GPIO0_A_OFFSET;
+		} else {
+			*reg = RK3506_PULL_GPIO0_D_OFFSET;
+			*bit = 5;
+
+			return 0;
+		}
+		break;
+
+	case 1:
+		*regmap = priv->regmap_ioc1;
+		if (pin_num < 28)
+			*reg = RK3506_PULL_GPIO1_OFFSET;
+		else
+			ret = -EINVAL;
+		break;
+
+	case 2:
+		*regmap = priv->regmap_base;
+		if (pin_num < 17)
+			*reg = RK3506_PULL_GPIO2_OFFSET;
+		else
+			ret = -EINVAL;
+		break;
+
+	case 3:
+		*regmap = priv->regmap_base;
+		if (pin_num < 15)
+			*reg = RK3506_PULL_GPIO3_OFFSET;
+		else
+			ret = -EINVAL;
+		break;
+
+	case 4:
+		*regmap = priv->regmap_base;
+		if (pin_num < 8 || pin_num > 11) {
+			ret = -EINVAL;
+		} else {
+			*reg = RK3506_PULL_GPIO4_OFFSET;
+			*bit = 13;
+
+			return 0;
+		}
+		break;
+
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+	if (ret) {
+		debug("unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
+		return ret;
+	}
+
+	*reg += ((pin_num / RK3506_PULL_PINS_PER_REG) * 4);
+	*bit = pin_num % RK3506_PULL_PINS_PER_REG;
+	*bit *= RK3506_PULL_BITS_PER_PIN;
+
+	return 0;
+}
+
+static int rk3506_set_pull(struct rockchip_pin_bank *bank,
+			   int pin_num, int pull)
+{
+	struct regmap *regmap;
+	int reg, ret;
+	u8 bit, type;
+	u32 data, rmask;
+
+	if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+		return -EOPNOTSUPP;
+
+	ret = rk3506_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	if (ret)
+		return ret;
+	type = bank->pull_type[pin_num / 8];
+
+	if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4)
+		type = 1;
+
+	ret = rockchip_translate_pull_value(type, pull);
+	if (ret < 0) {
+		debug("unsupported pull setting %d\n", pull);
+		return ret;
+	}
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << RK3506_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+	rmask = data | (data >> 16);
+	data |= (ret << bit);
+
+	return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+#define RK3506_SMT_BITS_PER_PIN		1
+#define RK3506_SMT_PINS_PER_REG		8
+#define RK3506_SMT_GPIO0_A_OFFSET	0x400
+#define RK3506_SMT_GPIO0_D_OFFSET	0x830
+#define RK3506_SMT_GPIO1_OFFSET		0x410
+#define RK3506_SMT_GPIO2_OFFSET		0x420
+#define RK3506_SMT_GPIO3_OFFSET		0x430
+#define RK3506_SMT_GPIO4_OFFSET		0x840
+
+static int rk3506_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+					   int pin_num,
+					   struct regmap **regmap,
+					   int *reg, u8 *bit)
+{
+	struct rockchip_pinctrl_priv *priv = bank->priv;
+	int ret = 0;
+
+	switch (bank->bank_num) {
+	case 0:
+		*regmap = priv->regmap_pmu;
+		if (pin_num > 24) {
+			ret = -EINVAL;
+		} else if (pin_num < 24) {
+			*reg = RK3506_SMT_GPIO0_A_OFFSET;
+		} else {
+			*reg = RK3506_SMT_GPIO0_D_OFFSET;
+			*bit = 9;
+
+			return 0;
+		}
+		break;
+
+	case 1:
+		*regmap = priv->regmap_ioc1;
+		if (pin_num < 28)
+			*reg = RK3506_SMT_GPIO1_OFFSET;
+		else
+			ret = -EINVAL;
+		break;
+
+	case 2:
+		*regmap = priv->regmap_base;
+		if (pin_num < 17)
+			*reg = RK3506_SMT_GPIO2_OFFSET;
+		else
+			ret = -EINVAL;
+		break;
+
+	case 3:
+		*regmap = priv->regmap_base;
+		if (pin_num < 15)
+			*reg = RK3506_SMT_GPIO3_OFFSET;
+		else
+			ret = -EINVAL;
+		break;
+
+	case 4:
+		*regmap = priv->regmap_base;
+		if (pin_num < 8 || pin_num > 11) {
+			ret = -EINVAL;
+		} else {
+			*reg = RK3506_SMT_GPIO4_OFFSET;
+			*bit = 8;
+
+			return 0;
+		}
+		break;
+
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+	if (ret) {
+		debug("unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
+		return ret;
+	}
+
+	*reg += ((pin_num / RK3506_SMT_PINS_PER_REG) * 4);
+	*bit = pin_num % RK3506_SMT_PINS_PER_REG;
+	*bit *= RK3506_SMT_BITS_PER_PIN;
+
+	return 0;
+}
+
+static int rk3506_set_schmitt(struct rockchip_pin_bank *bank,
+			      int pin_num, int enable)
+{
+	struct regmap *regmap;
+	int reg, ret;
+	u32 data, rmask;
+	u8 bit;
+
+	ret = rk3506_calc_schmitt_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	if (ret)
+		return ret;
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << RK3506_SMT_BITS_PER_PIN) - 1) << (bit + 16);
+	rmask = data | (data >> 16);
+	data |= (enable << bit);
+
+	if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) {
+		data = 0x3 << (bit + 16);
+		rmask = data | (data >> 16);
+		data |= ((enable ? 0x3 : 0) << bit);
+	}
+
+	return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+static struct rockchip_mux_recalced_data rk3506_mux_recalced_data[] = {
+	{
+		.num = 0,
+		.pin = 24,
+		.reg = 0x830,
+		.bit = 0,
+		.mask = 0x3
+	},
+};
+
+static struct rockchip_pin_bank rk3506_pin_banks[] = {
+	PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
+				    IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
+				    IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
+				    IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
+				    IOMUX_8WIDTH_2BIT | IOMUX_SOURCE_PMU,
+				    0x0, 0x8, 0x10, 0x830),
+	PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    0x20, 0x28, 0x30, 0x38),
+	PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    0x40, 0x48, 0x50, 0x58),
+	PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    0x60, 0x68, 0x70, 0x78),
+	PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4",
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    0x80, 0x88, 0x90, 0x98),
+};
+
+static const struct rockchip_pin_ctrl rk3506_pin_ctrl = {
+	.pin_banks		= rk3506_pin_banks,
+	.nr_banks		= ARRAY_SIZE(rk3506_pin_banks),
+	.iomux_recalced		= rk3506_mux_recalced_data,
+	.niomux_recalced	= ARRAY_SIZE(rk3506_mux_recalced_data),
+	.set_mux		= rk3506_set_mux,
+	.set_pull		= rk3506_set_pull,
+	.set_drive		= rk3506_set_drive,
+	.set_schmitt		= rk3506_set_schmitt,
+};
+
+static const struct udevice_id rk3506_pinctrl_ids[] = {
+	{
+		.compatible = "rockchip,rk3506-pinctrl",
+		.data = (ulong)&rk3506_pin_ctrl
+	},
+	{ }
+};
+
+U_BOOT_DRIVER(rockchip_rk3506_pinctrl) = {
+	.name		= "rockchip_rk3506_pinctrl",
+	.id		= UCLASS_PINCTRL,
+	.of_match	= rk3506_pinctrl_ids,
+	.priv_auto	= sizeof(struct rockchip_pinctrl_priv),
+	.ops		= &rockchip_pinctrl_ops,
+#if CONFIG_IS_ENABLED(OF_REAL)
+	.bind		= dm_scan_fdt_dev,
+#endif
+	.probe		= rockchip_pinctrl_probe,
+};
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
index 4de67aba1c3..957dcb52059 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
@@ -10,6 +10,7 @@
 #include <syscon.h>
 #include <fdtdec.h>
 #include <linux/bitops.h>
+#include <linux/err.h>
 #include <linux/libfdt.h>
 
 #include "pinctrl-rockchip.h"
@@ -641,37 +642,30 @@ int rockchip_pinctrl_probe(struct udevice *dev)
 {
 	struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
 	struct rockchip_pin_ctrl *ctrl;
-	struct udevice *syscon;
-	struct regmap *regmap;
-	int ret = 0;
 
-	/* get rockchip grf syscon phandle */
-	ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf",
-					   &syscon);
-	if (ret) {
-		debug("unable to find rockchip,grf syscon device (%d)\n", ret);
-		return ret;
+	priv->regmap_base =
+			syscon_regmap_lookup_by_phandle(dev, "rockchip,grf");
+	if (IS_ERR(priv->regmap_base)) {
+		debug("unable to find rockchip,grf regmap\n");
+		return PTR_ERR(priv->regmap_base);
 	}
 
-	/* get grf-reg base address */
-	regmap = syscon_get_regmap(syscon);
-	if (!regmap) {
-		debug("unable to find rockchip grf regmap\n");
-		return -ENODEV;
+	if (dev_read_bool(dev, "rockchip,pmu")) {
+		priv->regmap_pmu =
+			syscon_regmap_lookup_by_phandle(dev, "rockchip,pmu");
+		if (IS_ERR(priv->regmap_pmu)) {
+			debug("unable to find rockchip,pmu regmap\n");
+			return PTR_ERR(priv->regmap_pmu);
+		}
 	}
-	priv->regmap_base = regmap;
-
-	/* option: get pmu-reg base address */
-	ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu",
-					   &syscon);
-	if (!ret) {
-		/* get pmugrf-reg base address */
-		regmap = syscon_get_regmap(syscon);
-		if (!regmap) {
-			debug("unable to find rockchip pmu regmap\n");
-			return -ENODEV;
+
+	if (dev_read_bool(dev, "rockchip,ioc1")) {
+		priv->regmap_ioc1 =
+			syscon_regmap_lookup_by_phandle(dev, "rockchip,ioc1");
+		if (IS_ERR(priv->regmap_ioc1)) {
+			debug("unable to find rockchip,ioc1 regmap\n");
+			return PTR_ERR(priv->regmap_ioc1);
 		}
-		priv->regmap_pmu = regmap;
 	}
 
 	ctrl = rockchip_pinctrl_get_soc_data(dev);
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h
index ba684baed24..568e6024b78 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h
@@ -528,6 +528,7 @@ struct rockchip_pinctrl_priv {
 	struct rockchip_pin_ctrl	*ctrl;
 	struct regmap			*regmap_base;
 	struct regmap			*regmap_pmu;
+	struct regmap			*regmap_ioc1;
 };
 
 extern const struct pinctrl_ops rockchip_pinctrl_ops;
diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
index fd94aad0cd4..27921ae4921 100644
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
 obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o
 obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o sdram_pctl_px30.o sdram_phy_px30.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += sdram_rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3506) += sdram_rk3506.o
 obj-$(CONFIG_ROCKCHIP_RK3528) += sdram_rk3528.o
 obj-$(CONFIG_ROCKCHIP_RK3568) += sdram_rk3568.o
 obj-$(CONFIG_ROCKCHIP_RK3576) += sdram_rk3576.o
diff --git a/drivers/ram/rockchip/sdram_rk3506.c b/drivers/ram/rockchip/sdram_rk3506.c
new file mode 100644
index 00000000000..a8396ea8888
--- /dev/null
+++ b/drivers/ram/rockchip/sdram_rk3506.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright Contributors to the U-Boot project.
+
+#include <dm.h>
+#include <ram.h>
+#include <asm/arch-rockchip/sdram.h>
+
+#define PMUGRF_BASE			0xff910000
+#define OS_REG2_REG			0x208
+
+static int rk3506_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+	info->base = CFG_SYS_SDRAM_BASE;
+	info->size = rockchip_sdram_size(PMUGRF_BASE + OS_REG2_REG);
+
+	return 0;
+}
+
+static struct ram_ops rk3506_dmc_ops = {
+	.get_info = rk3506_dmc_get_info,
+};
+
+static const struct udevice_id rk3506_dmc_ids[] = {
+	{ .compatible = "rockchip,rk3506-dmc" },
+	{ }
+};
+
+U_BOOT_DRIVER(rockchip_rk3506_dmc) = {
+	.name = "rockchip_rk3506_dmc",
+	.id = UCLASS_RAM,
+	.of_match = rk3506_dmc_ids,
+	.ops = &rk3506_dmc_ops,
+};
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index ee5b009d134..088545c6473 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -16,7 +16,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
 obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
 obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
 obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o
-obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3528.o rst-rk3576.o rst-rk3588.o
+obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3506.o rst-rk3528.o rst-rk3576.o rst-rk3588.o
 obj-$(CONFIG_RESET_MESON) += reset-meson.o
 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
 obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
diff --git a/drivers/reset/rst-rk3506.c b/drivers/reset/rst-rk3506.c
new file mode 100644
index 00000000000..9c384db0589
--- /dev/null
+++ b/drivers/reset/rst-rk3506.c
@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ * Author: Finley Xiao <[email protected]>
+ */
+
+#include <dm.h>
+#include <asm/arch-rockchip/clock.h>
+#include <dt-bindings/reset/rockchip,rk3506-cru.h>
+
+/* 0xFF9A0000 + 0x0A00 */
+#define RK3506_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
+
+/* mapping table for reset ID to register offset */
+static const int rk3506_register_offset[] = {
+	/* CRU-->SOFTRST_CON00 */
+	RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET0_AC, 0, 0),
+	RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET1_AC, 0, 1),
+	RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET2_AC, 0, 2),
+	RK3506_CRU_RESET_OFFSET(SRST_NCORESET0_AC, 0, 4),
+	RK3506_CRU_RESET_OFFSET(SRST_NCORESET1_AC, 0, 5),
+	RK3506_CRU_RESET_OFFSET(SRST_NCORESET2_AC, 0, 6),
+	RK3506_CRU_RESET_OFFSET(SRST_NL2RESET_AC, 0, 8),
+	RK3506_CRU_RESET_OFFSET(SRST_A_CORE_BIU_AC, 0, 9),
+	RK3506_CRU_RESET_OFFSET(SRST_H_M0_AC, 0, 10),
+
+	/* CRU-->SOFTRST_CON02 */
+	RK3506_CRU_RESET_OFFSET(SRST_NDBGRESET, 2, 10),
+	RK3506_CRU_RESET_OFFSET(SRST_P_CORE_BIU, 2, 14),
+	RK3506_CRU_RESET_OFFSET(SRST_PMU, 2, 15),
+
+	/* CRU-->SOFTRST_CON03 */
+	RK3506_CRU_RESET_OFFSET(SRST_P_DBG, 3, 1),
+	RK3506_CRU_RESET_OFFSET(SRST_POT_DBG, 3, 2),
+	RK3506_CRU_RESET_OFFSET(SRST_P_CORE_GRF, 3, 4),
+	RK3506_CRU_RESET_OFFSET(SRST_CORE_EMA_DETECT, 3, 6),
+	RK3506_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 3, 7),
+	RK3506_CRU_RESET_OFFSET(SRST_P_GPIO1, 3, 8),
+	RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO1, 3, 9),
+
+	/* CRU-->SOFTRST_CON04 */
+	RK3506_CRU_RESET_OFFSET(SRST_A_CORE_PERI_BIU, 4, 3),
+	RK3506_CRU_RESET_OFFSET(SRST_A_DSMC, 4, 5),
+	RK3506_CRU_RESET_OFFSET(SRST_P_DSMC, 4, 6),
+	RK3506_CRU_RESET_OFFSET(SRST_FLEXBUS, 4, 7),
+	RK3506_CRU_RESET_OFFSET(SRST_A_FLEXBUS, 4, 9),
+	RK3506_CRU_RESET_OFFSET(SRST_H_FLEXBUS, 4, 10),
+	RK3506_CRU_RESET_OFFSET(SRST_A_DSMC_SLV, 4, 11),
+	RK3506_CRU_RESET_OFFSET(SRST_H_DSMC_SLV, 4, 12),
+	RK3506_CRU_RESET_OFFSET(SRST_DSMC_SLV, 4, 13),
+
+	/* CRU-->SOFTRST_CON05 */
+	RK3506_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 5, 3),
+	RK3506_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 5, 4),
+	RK3506_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 5, 5),
+	RK3506_CRU_RESET_OFFSET(SRST_A_SYSRAM, 5, 6),
+	RK3506_CRU_RESET_OFFSET(SRST_H_SYSRAM, 5, 7),
+	RK3506_CRU_RESET_OFFSET(SRST_A_DMAC0, 5, 8),
+	RK3506_CRU_RESET_OFFSET(SRST_A_DMAC1, 5, 9),
+	RK3506_CRU_RESET_OFFSET(SRST_H_M0, 5, 10),
+	RK3506_CRU_RESET_OFFSET(SRST_M0_JTAG, 5, 11),
+	RK3506_CRU_RESET_OFFSET(SRST_H_CRYPTO, 5, 15),
+
+	/* CRU-->SOFTRST_CON06 */
+	RK3506_CRU_RESET_OFFSET(SRST_H_RNG, 6, 0),
+	RK3506_CRU_RESET_OFFSET(SRST_P_BUS_GRF, 6, 1),
+	RK3506_CRU_RESET_OFFSET(SRST_P_TIMER0, 6, 2),
+	RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH0, 6, 3),
+	RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH1, 6, 4),
+	RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH2, 6, 5),
+	RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH3, 6, 6),
+	RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH4, 6, 7),
+	RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH5, 6, 8),
+	RK3506_CRU_RESET_OFFSET(SRST_P_WDT0, 6, 9),
+	RK3506_CRU_RESET_OFFSET(SRST_T_WDT0, 6, 10),
+	RK3506_CRU_RESET_OFFSET(SRST_P_WDT1, 6, 11),
+	RK3506_CRU_RESET_OFFSET(SRST_T_WDT1, 6, 12),
+	RK3506_CRU_RESET_OFFSET(SRST_P_MAILBOX, 6, 13),
+	RK3506_CRU_RESET_OFFSET(SRST_P_INTMUX, 6, 14),
+	RK3506_CRU_RESET_OFFSET(SRST_P_SPINLOCK, 6, 15),
+
+	/* CRU-->SOFTRST_CON07 */
+	RK3506_CRU_RESET_OFFSET(SRST_P_DDRC, 7, 0),
+	RK3506_CRU_RESET_OFFSET(SRST_H_DDRPHY, 7, 1),
+	RK3506_CRU_RESET_OFFSET(SRST_P_DDRMON, 7, 2),
+	RK3506_CRU_RESET_OFFSET(SRST_DDRMON_OSC, 7, 3),
+	RK3506_CRU_RESET_OFFSET(SRST_P_DDR_LPC, 7, 4),
+	RK3506_CRU_RESET_OFFSET(SRST_H_USBOTG0, 7, 5),
+	RK3506_CRU_RESET_OFFSET(SRST_USBOTG0_ADP, 7, 7),
+	RK3506_CRU_RESET_OFFSET(SRST_H_USBOTG1, 7, 8),
+	RK3506_CRU_RESET_OFFSET(SRST_USBOTG1_ADP, 7, 10),
+	RK3506_CRU_RESET_OFFSET(SRST_P_USBPHY, 7, 11),
+	RK3506_CRU_RESET_OFFSET(SRST_USBPHY_POR, 7, 12),
+	RK3506_CRU_RESET_OFFSET(SRST_USBPHY_OTG0, 7, 13),
+	RK3506_CRU_RESET_OFFSET(SRST_USBPHY_OTG1, 7, 14),
+
+	/* CRU-->SOFTRST_CON08 */
+	RK3506_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 8, 0),
+	RK3506_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 8, 1),
+
+	/* CRU-->SOFTRST_CON09 */
+	RK3506_CRU_RESET_OFFSET(SRST_USBOTG0_UTMI, 9, 0),
+	RK3506_CRU_RESET_OFFSET(SRST_USBOTG1_UTMI, 9, 1),
+
+	/* CRU-->SOFTRST_CON10 */
+	RK3506_CRU_RESET_OFFSET(SRST_A_DDRC_0, 10, 0),
+	RK3506_CRU_RESET_OFFSET(SRST_A_DDRC_1, 10, 1),
+	RK3506_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 10, 2),
+	RK3506_CRU_RESET_OFFSET(SRST_DDRC, 10, 3),
+	RK3506_CRU_RESET_OFFSET(SRST_DDRMON, 10, 4),
+
+	/* CRU-->SOFTRST_CON11 */
+	RK3506_CRU_RESET_OFFSET(SRST_H_LSPERI_BIU, 11, 2),
+	RK3506_CRU_RESET_OFFSET(SRST_P_UART0, 11, 4),
+	RK3506_CRU_RESET_OFFSET(SRST_P_UART1, 11, 5),
+	RK3506_CRU_RESET_OFFSET(SRST_P_UART2, 11, 6),
+	RK3506_CRU_RESET_OFFSET(SRST_P_UART3, 11, 7),
+	RK3506_CRU_RESET_OFFSET(SRST_P_UART4, 11, 8),
+	RK3506_CRU_RESET_OFFSET(SRST_UART0, 11, 9),
+	RK3506_CRU_RESET_OFFSET(SRST_UART1, 11, 10),
+	RK3506_CRU_RESET_OFFSET(SRST_UART2, 11, 11),
+	RK3506_CRU_RESET_OFFSET(SRST_UART3, 11, 12),
+	RK3506_CRU_RESET_OFFSET(SRST_UART4, 11, 13),
+	RK3506_CRU_RESET_OFFSET(SRST_P_I2C0, 11, 14),
+	RK3506_CRU_RESET_OFFSET(SRST_I2C0, 11, 15),
+
+	/* CRU-->SOFTRST_CON12 */
+	RK3506_CRU_RESET_OFFSET(SRST_P_I2C1, 12, 0),
+	RK3506_CRU_RESET_OFFSET(SRST_I2C1, 12, 1),
+	RK3506_CRU_RESET_OFFSET(SRST_P_I2C2, 12, 2),
+	RK3506_CRU_RESET_OFFSET(SRST_I2C2, 12, 3),
+	RK3506_CRU_RESET_OFFSET(SRST_P_PWM1, 12, 4),
+	RK3506_CRU_RESET_OFFSET(SRST_PWM1, 12, 5),
+	RK3506_CRU_RESET_OFFSET(SRST_P_SPI0, 12, 10),
+	RK3506_CRU_RESET_OFFSET(SRST_SPI0, 12, 11),
+	RK3506_CRU_RESET_OFFSET(SRST_P_SPI1, 12, 12),
+	RK3506_CRU_RESET_OFFSET(SRST_SPI1, 12, 13),
+	RK3506_CRU_RESET_OFFSET(SRST_P_GPIO2, 12, 14),
+	RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO2, 12, 15),
+
+	/* CRU-->SOFTRST_CON13 */
+	RK3506_CRU_RESET_OFFSET(SRST_P_GPIO3, 13, 0),
+	RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO3, 13, 1),
+	RK3506_CRU_RESET_OFFSET(SRST_P_GPIO4, 13, 2),
+	RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO4, 13, 3),
+	RK3506_CRU_RESET_OFFSET(SRST_H_CAN0, 13, 4),
+	RK3506_CRU_RESET_OFFSET(SRST_CAN0, 13, 5),
+	RK3506_CRU_RESET_OFFSET(SRST_H_CAN1, 13, 6),
+	RK3506_CRU_RESET_OFFSET(SRST_CAN1, 13, 7),
+	RK3506_CRU_RESET_OFFSET(SRST_H_PDM, 13, 8),
+	RK3506_CRU_RESET_OFFSET(SRST_M_PDM, 13, 9),
+	RK3506_CRU_RESET_OFFSET(SRST_PDM, 13, 10),
+	RK3506_CRU_RESET_OFFSET(SRST_SPDIFTX, 13, 11),
+	RK3506_CRU_RESET_OFFSET(SRST_H_SPDIFTX, 13, 12),
+	RK3506_CRU_RESET_OFFSET(SRST_H_SPDIFRX, 13, 13),
+	RK3506_CRU_RESET_OFFSET(SRST_SPDIFRX, 13, 14),
+	RK3506_CRU_RESET_OFFSET(SRST_M_SAI0, 13, 15),
+
+	/* CRU-->SOFTRST_CON14 */
+	RK3506_CRU_RESET_OFFSET(SRST_H_SAI0, 14, 0),
+	RK3506_CRU_RESET_OFFSET(SRST_M_SAI1, 14, 2),
+	RK3506_CRU_RESET_OFFSET(SRST_H_SAI1, 14, 3),
+	RK3506_CRU_RESET_OFFSET(SRST_H_ASRC0, 14, 5),
+	RK3506_CRU_RESET_OFFSET(SRST_ASRC0, 14, 6),
+	RK3506_CRU_RESET_OFFSET(SRST_H_ASRC1, 14, 7),
+	RK3506_CRU_RESET_OFFSET(SRST_ASRC1, 14, 8),
+
+	/* CRU-->SOFTRST_CON17 */
+	RK3506_CRU_RESET_OFFSET(SRST_H_HSPERI_BIU, 17, 4),
+	RK3506_CRU_RESET_OFFSET(SRST_H_SDMMC, 17, 7),
+	RK3506_CRU_RESET_OFFSET(SRST_H_FSPI, 17, 8),
+	RK3506_CRU_RESET_OFFSET(SRST_S_FSPI, 17, 9),
+	RK3506_CRU_RESET_OFFSET(SRST_P_SPI2, 17, 10),
+	RK3506_CRU_RESET_OFFSET(SRST_A_MAC0, 17, 11),
+	RK3506_CRU_RESET_OFFSET(SRST_A_MAC1, 17, 12),
+
+	/* CRU-->SOFTRST_CON18 */
+	RK3506_CRU_RESET_OFFSET(SRST_M_SAI2, 18, 2),
+	RK3506_CRU_RESET_OFFSET(SRST_H_SAI2, 18, 3),
+	RK3506_CRU_RESET_OFFSET(SRST_H_SAI3, 18, 6),
+	RK3506_CRU_RESET_OFFSET(SRST_M_SAI3, 18, 7),
+	RK3506_CRU_RESET_OFFSET(SRST_H_SAI4, 18, 10),
+	RK3506_CRU_RESET_OFFSET(SRST_M_SAI4, 18, 11),
+	RK3506_CRU_RESET_OFFSET(SRST_H_DSM, 18, 12),
+	RK3506_CRU_RESET_OFFSET(SRST_M_DSM, 18, 13),
+	RK3506_CRU_RESET_OFFSET(SRST_P_AUDIO_ADC, 18, 14),
+	RK3506_CRU_RESET_OFFSET(SRST_M_AUDIO_ADC, 18, 15),
+
+	/* CRU-->SOFTRST_CON19 */
+	RK3506_CRU_RESET_OFFSET(SRST_P_SARADC, 19, 0),
+	RK3506_CRU_RESET_OFFSET(SRST_SARADC, 19, 1),
+	RK3506_CRU_RESET_OFFSET(SRST_SARADC_PHY, 19, 2),
+	RK3506_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 19, 3),
+	RK3506_CRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 19, 4),
+	RK3506_CRU_RESET_OFFSET(SRST_USER_OTPC_NS, 19, 5),
+	RK3506_CRU_RESET_OFFSET(SRST_P_UART5, 19, 6),
+	RK3506_CRU_RESET_OFFSET(SRST_UART5, 19, 7),
+	RK3506_CRU_RESET_OFFSET(SRST_P_GPIO234_IOC, 19, 8),
+
+	/* CRU-->SOFTRST_CON21 */
+	RK3506_CRU_RESET_OFFSET(SRST_A_VIO_BIU, 21, 3),
+	RK3506_CRU_RESET_OFFSET(SRST_H_VIO_BIU, 21, 4),
+	RK3506_CRU_RESET_OFFSET(SRST_H_RGA, 21, 6),
+	RK3506_CRU_RESET_OFFSET(SRST_A_RGA, 21, 7),
+	RK3506_CRU_RESET_OFFSET(SRST_CORE_RGA, 21, 8),
+	RK3506_CRU_RESET_OFFSET(SRST_A_VOP, 21, 9),
+	RK3506_CRU_RESET_OFFSET(SRST_H_VOP, 21, 10),
+	RK3506_CRU_RESET_OFFSET(SRST_VOP, 21, 11),
+	RK3506_CRU_RESET_OFFSET(SRST_P_DPHY, 21, 12),
+	RK3506_CRU_RESET_OFFSET(SRST_P_DSI_HOST, 21, 13),
+	RK3506_CRU_RESET_OFFSET(SRST_P_TSADC, 21, 14),
+	RK3506_CRU_RESET_OFFSET(SRST_TSADC, 21, 15),
+
+	/* CRU-->SOFTRST_CON22 */
+	RK3506_CRU_RESET_OFFSET(SRST_P_GPIO1_IOC, 22, 1),
+};
+
+int rk3506_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number)
+{
+	return rockchip_reset_bind_lut(pdev, rk3506_register_offset,
+				       reg_offset, reg_number);
+}
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index ebb306852a6..baa2eb61ea3 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -89,6 +89,7 @@ config USB_GADGET_PRODUCT_NUM
 	default 0x350b if ROCKCHIP_RK3588
 	default 0x350c if ROCKCHIP_RK3528
 	default 0x350e if ROCKCHIP_RK3576
+	default 0x350f if ROCKCHIP_RK3506
 	default 0x4ee0 if ARCH_SNAPDRAGON
 	default 0x0
 	help