diff options
| author | Peng Fan <[email protected]> | 2024-10-06 08:22:51 +0800 |
|---|---|---|
| committer | Fabio Estevam <[email protected]> | 2024-10-13 09:43:05 -0300 |
| commit | e7431340743962b4cfaffda95016c55bd2df297a (patch) | |
| tree | f06eac963053d87bc884cb4b437ee606da74ed12 /drivers | |
| parent | 2630ceecef9d0de1cd037c5b64679ac7a89e2f9c (diff) | |
misc: ele_mu: Clear RR when initialize MU
When OS is doing ELE API call, before OS get the response, OS is force
reseted, then it is possible that MU RR has data during initialization
in SPL stage. So clear the RR registers, otherwise SPL ELE API call will
work abnormal.
Cc: Alice Guo <[email protected]>
Cc: Marek Vasut <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/misc/imx_ele/ele_mu.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/misc/imx_ele/ele_mu.c b/drivers/misc/imx_ele/ele_mu.c index f5ba3a4ffa5..cdb85b999db 100644 --- a/drivers/misc/imx_ele/ele_mu.c +++ b/drivers/misc/imx_ele/ele_mu.c @@ -25,9 +25,20 @@ struct imx8ulp_mu { void mu_hal_init(ulong base) { struct mu_type *mu_base = (struct mu_type *)base; + u32 rr_num = (readl(&mu_base->par) & 0xFF00) >> 8; + int i; writel(0, &mu_base->tcr); writel(0, &mu_base->rcr); + + while (true) { + /* If there is pending RX data, clear them by read them out */ + if (!(readl(&mu_base->sr) & BIT(6))) + return; + + for (i = 0; i < rr_num; i++) + readl(&mu_base->rr[i]); + } } int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg) |