diff options
| author | Tom Rini <[email protected]> | 2026-03-18 08:37:41 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2026-03-18 08:37:41 -0600 |
| commit | eb53af2b4a455eeec3e4dc5a3b1457ff707de4d7 (patch) | |
| tree | 873338f8e15ac152c0d51dbb7895fb9f27043bd8 /drivers | |
| parent | fac5bce2a1ef7d237d536ccbe8a887c29e53a87a (diff) | |
| parent | 142c805d470cd02470146d6d70aa9c522d4da16c (diff) | |
Merge tag 'mediatek-for-next-2026-03-17' of https://source.denx.de/u-boot/custodians/u-boot-mediatek into next
- A fix for mt8188 clock oscillator rates.
- New driver for mt8189 clocks.
- The rest is a first wave of a larger effort to refactor and clean up the
mediatek clocks to replace various hacks that built up over time with
something that is easier to understand and maintain.
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/mediatek/Makefile | 1 | ||||
| -rw-r--r-- | drivers/clk/mediatek/clk-mt7622.c | 10 | ||||
| -rw-r--r-- | drivers/clk/mediatek/clk-mt7623.c | 15 | ||||
| -rw-r--r-- | drivers/clk/mediatek/clk-mt7629.c | 8 | ||||
| -rw-r--r-- | drivers/clk/mediatek/clk-mt7981.c | 3 | ||||
| -rw-r--r-- | drivers/clk/mediatek/clk-mt7986.c | 5 | ||||
| -rw-r--r-- | drivers/clk/mediatek/clk-mt7987.c | 2 | ||||
| -rw-r--r-- | drivers/clk/mediatek/clk-mt7988.c | 2 | ||||
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8183.c | 12 | ||||
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8188.c | 10 | ||||
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8189.c | 1746 | ||||
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8195.c | 6 | ||||
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8365.c | 4 | ||||
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8512.c | 6 | ||||
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8516.c | 6 | ||||
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8518.c | 6 | ||||
| -rw-r--r-- | drivers/clk/mediatek/clk-mtk.c | 279 | ||||
| -rw-r--r-- | drivers/clk/mediatek/clk-mtk.h | 54 |
18 files changed, 1974 insertions, 201 deletions
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 5bede819c0d..d4cac6aaf52 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_TARGET_MT7988) += clk-mt7988.o obj-$(CONFIG_TARGET_MT7987) += clk-mt7987.o obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o obj-$(CONFIG_TARGET_MT8188) += clk-mt8188.o +obj-$(CONFIG_TARGET_MT8189) += clk-mt8189.o obj-$(CONFIG_TARGET_MT8195) += clk-mt8195.o obj-$(CONFIG_TARGET_MT8365) += clk-mt8365.o obj-$(CONFIG_TARGET_MT8512) += clk-mt8512.o diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 782eb14e9c5..44d2836710e 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -48,9 +48,9 @@ static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0, 21, 0x204, 24, 0x204, 0), - PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR, + PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, CLK_PLL_HAVE_RST_BAR, 21, 0x214, 24, 0x214, 0), - PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR, + PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, CLK_PLL_HAVE_RST_BAR, 7, 0x224, 24, 0x224, 14), PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0, 21, 0x300, 1, 0x304, 0), @@ -95,7 +95,7 @@ static const struct mtk_gate apmixed_cgs[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, 0) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_TO_U2_PHY, 31250000), @@ -362,7 +362,7 @@ static const struct mtk_composite top_muxes[] = { /* CLK_CFG_5 */ MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7), MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, eth_parents, 0x90, 8, 3, 15, - CLK_DOMAIN_SCPSYS), + CLK_MUX_DOMAIN_SCPSYS), MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x90, 16, 2, 23), MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31), @@ -387,8 +387,6 @@ static const struct mtk_composite top_muxes[] = { }; /* infracfg */ -#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED) -#define XTAL_PARENT(_id) PARENT(_id, CLK_PARENT_XTAL) static const struct mtk_parent infra_mux1_parents[] = { XTAL_PARENT(CLK_XTAL), diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c index 071c4cf8a84..d52555283d2 100644 --- a/drivers/clk/mediatek/clk-mt7623.c +++ b/drivers/clk/mediatek/clk-mt7623.c @@ -61,9 +61,9 @@ static const int pll_id_offs_map[] = { static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x80000001, 0, 21, 0x204, 24, 0x204, 0), - PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf0000001, HAVE_RST_BAR, + PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf0000001, CLK_PLL_HAVE_RST_BAR, 21, 0x210, 4, 0x214, 0), - PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf3000001, HAVE_RST_BAR, + PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf3000001, CLK_PLL_HAVE_RST_BAR, 7, 0x220, 4, 0x224, 14), PLL(CLK_APMIXED_MMPLL, 0x230, 0x23c, 0x00000001, 0, 21, 0x230, 4, 0x234, 0), @@ -269,7 +269,7 @@ static const int top_id_offs_map[CLK_TOP_NR + 1] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, 0) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_DPI, 108 * MHZ), @@ -701,12 +701,12 @@ static const struct mtk_composite top_muxes[] = { MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), MUX_GATE_FLAGS(CLK_TOP_MM_SEL, mm_parents, 0x40, 24, 3, 31, - CLK_DOMAIN_SCPSYS), + CLK_MUX_DOMAIN_SCPSYS), MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), MUX_GATE(CLK_TOP_VDEC_SEL, vdec_parents, 0x50, 8, 4, 15), MUX_GATE_FLAGS(CLK_TOP_MFG_SEL, mfg_parents, 0x50, 16, 3, 23, - CLK_DOMAIN_SCPSYS), + CLK_MUX_DOMAIN_SCPSYS), MUX_GATE(CLK_TOP_CAMTG_SEL, camtg_parents, 0x50, 24, 3, 31), MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), @@ -745,7 +745,7 @@ static const struct mtk_composite top_muxes[] = { MUX_GATE(CLK_TOP_ASM_H_SEL, asm_parents, 0xD0, 0, 2, 7), MUX_GATE(CLK_TOP_MS_CARD_SEL, ms_card_parents, 0xD0, 16, 2, 23), MUX_GATE_FLAGS(CLK_TOP_ETHIF_SEL, ethif_parents, 0xD0, 24, 3, 31, - CLK_DOMAIN_SCPSYS), + CLK_MUX_DOMAIN_SCPSYS), MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, hdmirx_parents, 0xE0, 0, 1, 7), MUX_GATE(CLK_TOP_MSDC30_3_SEL, msdc30_parents, 0xE0, 8, 3, 15), @@ -866,9 +866,6 @@ static const int peri_id_offs_map[] = { [CLK_PERI_FCI] = 48, }; -#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) -#define XTAL_PARENT(_id) PARENT(_id, CLK_PARENT_XTAL) - static const struct mtk_parent uart_ck_sel_parents[] = { XTAL_PARENT(CLK_XTAL), TOP_PARENT(CLK_TOP_UART_SEL), diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index 582394f594b..1d697539ce2 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -48,9 +48,9 @@ static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0, 21, 0x204, 24, 0x204, 0), - PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR, + PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, CLK_PLL_HAVE_RST_BAR, 21, 0x214, 24, 0x214, 0), - PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR, + PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, CLK_PLL_HAVE_RST_BAR, 7, 0x224, 24, 0x224, 14), PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0, 21, 0x300, 1, 0x304, 0), @@ -71,7 +71,7 @@ static const struct mtk_pll_data apmixed_plls[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, 0) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_TO_U2_PHY, 31250000), @@ -397,7 +397,7 @@ static const struct mtk_composite top_muxes[] = { /* CLK_CFG_5 */ MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7), MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, hif_parents, 0x90, 8, 3, 15, - CLK_DOMAIN_SCPSYS), + CLK_MUX_DOMAIN_SCPSYS), MUX_GATE(CLK_TOP_SATA_SEL, sata_parents, 0x90, 16, 1, 23), MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31), diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c index 09ed4d8a97f..40e8429521a 100644 --- a/drivers/clk/mediatek/clk-mt7981.c +++ b/drivers/clk/mediatek/clk-mt7981.c @@ -319,9 +319,6 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = { }; /* INFRASYS MUX PARENTS */ -#define INFRA_PARENT(_id) PARENT(_id, CLK_PARENT_INFRASYS) -#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) -#define VOID_PARENT PARENT(-1, 0) static const struct mtk_parent infra_uart0_parents[] = { TOP_PARENT(CLK_TOP_F26M_SEL), diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c index 79efbf43bc4..c2c216fcdf4 100644 --- a/drivers/clk/mediatek/clk-mt7986.c +++ b/drivers/clk/mediatek/clk-mt7986.c @@ -18,11 +18,6 @@ #define MT7986_CLK_PDN 0x250 #define MT7986_CLK_PDN_EN_WRITE BIT(31) -#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED) -#define INFRA_PARENT(_id) PARENT(_id, CLK_PARENT_INFRASYS) -#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) -#define VOID_PARENT PARENT(-1, 0) - #define FIXED_CLK0(_id, _rate) \ FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) diff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c index 959b1c9cff6..641881fcb28 100644 --- a/drivers/clk/mediatek/clk-mt7987.c +++ b/drivers/clk/mediatek/clk-mt7987.c @@ -111,8 +111,6 @@ static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = { }; /* TOPCKGEN MUX PARENTS */ -#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED) -#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) /* CLK_TOP_NETSYS_SEL (netsys_sel) in topckgen */ static const struct mtk_parent netsys_parents[] = { diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c index cd8726852d7..83f7c559e31 100644 --- a/drivers/clk/mediatek/clk-mt7988.c +++ b/drivers/clk/mediatek/clk-mt7988.c @@ -94,8 +94,6 @@ static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = { }; /* TOPCKGEN MUX PARENTS */ -#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED) -#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) static const struct mtk_parent netsys_parents[] = { TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D2), diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 9d9d00622db..752cb1c61ab 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -38,24 +38,24 @@ static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL_LL, 0x0200, 0x020C, 0x00000001, - HAVE_RST_BAR, BIT(24), 22, 8, 0x0204, 24, + CLK_PLL_HAVE_RST_BAR, BIT(24), 22, 8, 0x0204, 24, 0x0204, 0), PLL(CLK_APMIXED_ARMPLL_L, 0x0210, 0x021C, 0x00000001, - HAVE_RST_BAR, BIT(24), 22, 8, 0x0214, 24, + CLK_PLL_HAVE_RST_BAR, BIT(24), 22, 8, 0x0214, 24, 0x0214, 0), PLL(CLK_APMIXED_CCIPLL, 0x0290, 0x029C, 0x00000001, - HAVE_RST_BAR, BIT(24), 22, 8, 0x0294, 24, + CLK_PLL_HAVE_RST_BAR, BIT(24), 22, 8, 0x0294, 24, 0x0294, 0), PLL(CLK_APMIXED_MAINPLL, 0x0220, 0x022C, 0x00000001, - HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, + CLK_PLL_HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0224, 0), PLL(CLK_APMIXED_UNIV2PLL, 0x0230, 0x023C, 0x00000001, - HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, + CLK_PLL_HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0234, 0), PLL(CLK_APMIXED_MSDCPLL, 0x0250, 0x025C, 0x00000001, 0, 0, 22, 8, 0x0254, 24, 0x0254, 0), PLL(CLK_APMIXED_MMPLL, 0x0270, 0x027C, 0x00000001, - HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, + CLK_PLL_HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0274, 0), PLL(CLK_APMIXED_MFGPLL, 0x0240, 0x024C, 0x00000001, 0, 0, 22, 8, 0x0244, 24, 0x0244, 0), diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c index b720eec8ba7..3d20d2d93fc 100644 --- a/drivers/clk/mediatek/clk-mt8188.c +++ b/drivers/clk/mediatek/clk-mt8188.c @@ -56,13 +56,13 @@ static const struct mtk_pll_data apmixed_plls[] = { 0x0528, 0), PLL(CLK_APMIXED_TVDPLL2, 0x0534, 0x0540, 0, 0, 22, 0x0538, 24, 0x0538, 0), - PLL(CLK_APMIXED_MMPLL, 0x0544, 0x0550, 0xff000000, HAVE_RST_BAR, + PLL(CLK_APMIXED_MMPLL, 0x0544, 0x0550, 0xff000000, CLK_PLL_HAVE_RST_BAR, 22, 0x0548, 24, 0x0548, 0), - PLL(CLK_APMIXED_MAINPLL, 0x045C, 0x0468, 0xff000000, HAVE_RST_BAR, + PLL(CLK_APMIXED_MAINPLL, 0x045C, 0x0468, 0xff000000, CLK_PLL_HAVE_RST_BAR, 22, 0x0460, 24, 0x0460, 0), PLL(CLK_APMIXED_IMGPLL, 0x0554, 0x0560, 0, 0, 22, 0x0558, 24, 0x0558, 0), - PLL(CLK_APMIXED_UNIVPLL, 0x0504, 0x0510, 0xff000000, HAVE_RST_BAR, + PLL(CLK_APMIXED_UNIVPLL, 0x0504, 0x0510, 0xff000000, CLK_PLL_HAVE_RST_BAR, 22, 0x0508, 24, 0x0508, 0), PLL(CLK_APMIXED_ADSPPLL, 0x042C, 0x0438, 0, 0, 22, 0x0430, 24, 0x0430, 0), @@ -97,8 +97,8 @@ static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_466M_FMEM, 533000000), FIXED_CLK0(CLK_TOP_PEXTP_PIPE, 250000000), FIXED_CLK0(CLK_TOP_DSI_PHY, 500000000), - FIXED_CLK0(CLK_TOP_CLK13M, 130000000), - FIXED_CLK0(CLK_TOP_CLK26M, 260000000), + FIXED_CLK0(CLK_TOP_CLK13M, 13000000), + FIXED_CLK0(CLK_TOP_CLK26M, 26000000), FIXED_CLK0(CLK_TOP_CLK32K, 32000), }; diff --git a/drivers/clk/mediatek/clk-mt8189.c b/drivers/clk/mediatek/clk-mt8189.c new file mode 100644 index 00000000000..60e6f53013a --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189.c @@ -0,0 +1,1746 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026 MediaTek Inc. + * Author: Chris Chen <[email protected]> + * Author: David Lechner <[email protected]> + */ + +#include <dm.h> +#include <dt-bindings/clock/mediatek,mt8189-clk.h> +#include <linux/kernel.h> + +#include "clk-mtk.h" + +/* TOPCK MUX SEL REG */ +#define CLK_CFG_UPDATE 0x0004 +#define CLK_CFG_UPDATE1 0x0008 +#define CLK_CFG_UPDATE2 0x000c +#define VLP_CLK_CFG_UPDATE 0x0004 +#define CLK_CFG_0 0x0010 +#define CLK_CFG_0_SET 0x0014 +#define CLK_CFG_0_CLR 0x0018 +#define CLK_CFG_1 0x0020 +#define CLK_CFG_1_SET 0x0024 +#define CLK_CFG_1_CLR 0x0028 +#define CLK_CFG_2 0x0030 +#define CLK_CFG_2_SET 0x0034 +#define CLK_CFG_2_CLR 0x0038 +#define CLK_CFG_3 0x0040 +#define CLK_CFG_3_SET 0x0044 +#define CLK_CFG_3_CLR 0x0048 +#define CLK_CFG_4 0x0050 +#define CLK_CFG_4_SET 0x0054 +#define CLK_CFG_4_CLR 0x0058 +#define CLK_CFG_5 0x0060 +#define CLK_CFG_5_SET 0x0064 +#define CLK_CFG_5_CLR 0x0068 +#define CLK_CFG_6 0x0070 +#define CLK_CFG_6_SET 0x0074 +#define CLK_CFG_6_CLR 0x0078 +#define CLK_CFG_7 0x0080 +#define CLK_CFG_7_SET 0x0084 +#define CLK_CFG_7_CLR 0x0088 +#define CLK_CFG_8 0x0090 +#define CLK_CFG_8_SET 0x0094 +#define CLK_CFG_8_CLR 0x0098 +#define CLK_CFG_9 0x00A0 +#define CLK_CFG_9_SET 0x00A4 +#define CLK_CFG_9_CLR 0x00A8 +#define CLK_CFG_10 0x00B0 +#define CLK_CFG_10_SET 0x00B4 +#define CLK_CFG_10_CLR 0x00B8 +#define CLK_CFG_11 0x00C0 +#define CLK_CFG_11_SET 0x00C4 +#define CLK_CFG_11_CLR 0x00C8 +#define CLK_CFG_12 0x00D0 +#define CLK_CFG_12_SET 0x00D4 +#define CLK_CFG_12_CLR 0x00D8 +#define CLK_CFG_13 0x00E0 +#define CLK_CFG_13_SET 0x00E4 +#define CLK_CFG_13_CLR 0x00E8 +#define CLK_CFG_14 0x00F0 +#define CLK_CFG_14_SET 0x00F4 +#define CLK_CFG_14_CLR 0x00F8 +#define CLK_CFG_15 0x0100 +#define CLK_CFG_15_SET 0x0104 +#define CLK_CFG_15_CLR 0x0108 +#define CLK_CFG_16 0x0110 +#define CLK_CFG_16_SET 0x0114 +#define CLK_CFG_16_CLR 0x0118 +#define CLK_CFG_17 0x0180 +#define CLK_CFG_17_SET 0x0184 +#define CLK_CFG_17_CLR 0x0188 +#define CLK_CFG_18 0x0190 +#define CLK_CFG_18_SET 0x0194 +#define CLK_CFG_18_CLR 0x0198 +#define CLK_CFG_19 0x0240 +#define CLK_CFG_19_SET 0x0244 +#define CLK_CFG_19_CLR 0x0248 +#define CLK_AUDDIV_0 0x0320 +#define CLK_MISC_CFG_3 0x0510 +#define CLK_MISC_CFG_3_SET 0x0514 +#define CLK_MISC_CFG_3_CLR 0x0518 +#define VLP_CLK_CFG_0 0x0008 +#define VLP_CLK_CFG_0_SET 0x000C +#define VLP_CLK_CFG_0_CLR 0x0010 +#define VLP_CLK_CFG_1 0x0014 +#define VLP_CLK_CFG_1_SET 0x0018 +#define VLP_CLK_CFG_1_CLR 0x001C +#define VLP_CLK_CFG_2 0x0020 +#define VLP_CLK_CFG_2_SET 0x0024 +#define VLP_CLK_CFG_2_CLR 0x0028 +#define VLP_CLK_CFG_3 0x002C +#define VLP_CLK_CFG_3_SET 0x0030 +#define VLP_CLK_CFG_3_CLR 0x0034 +#define VLP_CLK_CFG_4 0x0038 +#define VLP_CLK_CFG_4_SET 0x003C +#define VLP_CLK_CFG_4_CLR 0x0040 +#define VLP_CLK_CFG_5 0x0044 +#define VLP_CLK_CFG_5_SET 0x0048 +#define VLP_CLK_CFG_5_CLR 0x004C + +/* TOPCK MUX SHIFT */ +#define TOP_MUX_AXI_SHIFT 0 +#define TOP_MUX_AXI_PERI_SHIFT 1 +#define TOP_MUX_AXI_UFS_SHIFT 2 +#define TOP_MUX_BUS_AXIMEM_SHIFT 3 +#define TOP_MUX_DISP0_SHIFT 4 +#define TOP_MUX_MMINFRA_SHIFT 5 +#define TOP_MUX_UART_SHIFT 6 +#define TOP_MUX_SPI0_SHIFT 7 +#define TOP_MUX_SPI1_SHIFT 8 +#define TOP_MUX_SPI2_SHIFT 9 +#define TOP_MUX_SPI3_SHIFT 10 +#define TOP_MUX_SPI4_SHIFT 11 +#define TOP_MUX_SPI5_SHIFT 12 +#define TOP_MUX_MSDC_MACRO_0P_SHIFT 13 +#define TOP_MUX_MSDC50_0_HCLK_SHIFT 14 +#define TOP_MUX_MSDC50_0_SHIFT 15 +#define TOP_MUX_AES_MSDCFDE_SHIFT 16 +#define TOP_MUX_MSDC_MACRO_1P_SHIFT 17 +#define TOP_MUX_MSDC30_1_SHIFT 18 +#define TOP_MUX_MSDC30_1_HCLK_SHIFT 19 +#define TOP_MUX_MSDC_MACRO_2P_SHIFT 20 +#define TOP_MUX_MSDC30_2_SHIFT 21 +#define TOP_MUX_MSDC30_2_HCLK_SHIFT 22 +#define TOP_MUX_AUD_INTBUS_SHIFT 23 +#define TOP_MUX_ATB_SHIFT 24 +#define TOP_MUX_DISP_PWM_SHIFT 25 +#define TOP_MUX_USB_TOP_P0_SHIFT 26 +#define TOP_MUX_SSUSB_XHCI_P0_SHIFT 27 +#define TOP_MUX_USB_TOP_P1_SHIFT 28 +#define TOP_MUX_SSUSB_XHCI_P1_SHIFT 29 +#define TOP_MUX_USB_TOP_P2_SHIFT 30 +#define TOP_MUX_SSUSB_XHCI_P2_SHIFT 0 +#define TOP_MUX_USB_TOP_P3_SHIFT 1 +#define TOP_MUX_SSUSB_XHCI_P3_SHIFT 2 +#define TOP_MUX_USB_TOP_P4_SHIFT 3 +#define TOP_MUX_SSUSB_XHCI_P4_SHIFT 4 +#define TOP_MUX_I2C_SHIFT 5 +#define TOP_MUX_SENINF_SHIFT 6 +#define TOP_MUX_SENINF1_SHIFT 7 +#define TOP_MUX_AUD_ENGEN1_SHIFT 8 +#define TOP_MUX_AUD_ENGEN2_SHIFT 9 +#define TOP_MUX_AES_UFSFDE_SHIFT 10 +#define TOP_MUX_UFS_SHIFT 11 +#define TOP_MUX_UFS_MBIST_SHIFT 12 +#define TOP_MUX_AUD_1_SHIFT 13 +#define TOP_MUX_AUD_2_SHIFT 14 +#define TOP_MUX_VENC_SHIFT 15 +#define TOP_MUX_VDEC_SHIFT 16 +#define TOP_MUX_PWM_SHIFT 17 +#define TOP_MUX_AUDIO_H_SHIFT 18 +#define TOP_MUX_MCUPM_SHIFT 19 +#define TOP_MUX_MEM_SUB_SHIFT 20 +#define TOP_MUX_MEM_SUB_PERI_SHIFT 21 +#define TOP_MUX_MEM_SUB_UFS_SHIFT 22 +#define TOP_MUX_EMI_N_SHIFT 23 +#define TOP_MUX_DSI_OCC_SHIFT 24 +#define TOP_MUX_AP2CONN_HOST_SHIFT 25 +#define TOP_MUX_IMG1_SHIFT 26 +#define TOP_MUX_IPE_SHIFT 27 +#define TOP_MUX_CAM_SHIFT 28 +#define TOP_MUX_CAMTM_SHIFT 29 +#define TOP_MUX_DSP_SHIFT 30 +#define TOP_MUX_SR_PKA_SHIFT 0 +#define TOP_MUX_DXCC_SHIFT 1 +#define TOP_MUX_MFG_REF_SHIFT 2 +#define TOP_MUX_MDP0_SHIFT 3 +#define TOP_MUX_DP_SHIFT 4 +#define TOP_MUX_EDP_SHIFT 5 +#define TOP_MUX_EDP_FAVT_SHIFT 6 +#define TOP_MUX_SNPS_ETH_250M_SHIFT 7 +#define TOP_MUX_SNPS_ETH_62P4M_PTP_SHIFT 8 +#define TOP_MUX_SNPS_ETH_50M_RMII_SHIFT 9 +#define TOP_MUX_SFLASH_SHIFT 10 +#define TOP_MUX_GCPU_SHIFT 11 +#define TOP_MUX_PCIE_MAC_TL_SHIFT 12 +#define TOP_MUX_VDSTX_CLKDIG_CTS_SHIFT 13 +#define TOP_MUX_PLL_DPIX_SHIFT 14 +#define TOP_MUX_ECC_SHIFT 15 +#define TOP_MUX_SCP_SHIFT 0 +#define TOP_MUX_PWRAP_ULPOSC_SHIFT 1 +#define TOP_MUX_SPMI_P_MST_SHIFT 2 +#define TOP_MUX_DVFSRC_SHIFT 3 +#define TOP_MUX_PWM_VLP_SHIFT 4 +#define TOP_MUX_AXI_VLP_SHIFT 5 +#define TOP_MUX_SYSTIMER_26M_SHIFT 6 +#define TOP_MUX_SSPM_SHIFT 7 +#define TOP_MUX_SSPM_F26M_SHIFT 8 +#define TOP_MUX_SRCK_SHIFT 9 +#define TOP_MUX_SCP_SPI_SHIFT 10 +#define TOP_MUX_SCP_IIC_SHIFT 11 +#define TOP_MUX_SCP_SPI_HIGH_SPD_SHIFT 12 +#define TOP_MUX_SCP_IIC_HIGH_SPD_SHIFT 13 +#define TOP_MUX_SSPM_ULPOSC_SHIFT 14 +#define TOP_MUX_APXGPT_26M_SHIFT 15 +#define TOP_MUX_VADSP_SHIFT 16 +#define TOP_MUX_VADSP_VOWPLL_SHIFT 17 +#define TOP_MUX_VADSP_UARTHUB_BCLK_SHIFT 18 +#define TOP_MUX_CAMTG0_SHIFT 19 +#define TOP_MUX_CAMTG1_SHIFT 20 +#define TOP_MUX_CAMTG2_SHIFT 21 +#define TOP_MUX_AUD_ADC_SHIFT 22 +#define TOP_MUX_KP_IRQ_GEN_SHIFT 23 + +/* TOPCK DIVIDER REG */ +#define CLK_AUDDIV_2 0x0328 +#define CLK_AUDDIV_3 0x0334 +#define CLK_AUDDIV_5 0x033C + +/* APMIXED PLL REG */ +#define AP_PLL_CON3 0x00C +#define APLL1_TUNER_CON0 0x040 +#define APLL2_TUNER_CON0 0x044 +#define ARMPLL_LL_CON0 0x204 +#define ARMPLL_LL_CON1 0x208 +#define ARMPLL_LL_CON2 0x20C +#define ARMPLL_LL_CON3 0x210 +#define ARMPLL_BL_CON0 0x214 +#define ARMPLL_BL_CON1 0x218 +#define ARMPLL_BL_CON2 0x21C +#define ARMPLL_BL_CON3 0x220 +#define CCIPLL_CON0 0x224 +#define CCIPLL_CON1 0x228 +#define CCIPLL_CON2 0x22C +#define CCIPLL_CON3 0x230 +#define MAINPLL_CON0 0x304 +#define MAINPLL_CON1 0x308 +#define MAINPLL_CON2 0x30C +#define MAINPLL_CON3 0x310 +#define UNIVPLL_CON0 0x314 +#define UNIVPLL_CON1 0x318 +#define UNIVPLL_CON2 0x31C +#define UNIVPLL_CON3 0x320 +#define MMPLL_CON0 0x324 +#define MMPLL_CON1 0x328 +#define MMPLL_CON2 0x32C +#define MMPLL_CON3 0x330 +#define MFGPLL_CON0 0x504 +#define MFGPLL_CON1 0x508 +#define MFGPLL_CON2 0x50C +#define MFGPLL_CON3 0x510 +#define APLL1_CON0 0x404 +#define APLL1_CON1 0x408 +#define APLL1_CON2 0x40C +#define APLL1_CON3 0x410 +#define APLL1_CON4 0x414 +#define APLL2_CON0 0x418 +#define APLL2_CON1 0x41C +#define APLL2_CON2 0x420 +#define APLL2_CON3 0x424 +#define APLL2_CON4 0x428 +#define EMIPLL_CON0 0x334 +#define EMIPLL_CON1 0x338 +#define EMIPLL_CON2 0x33C +#define EMIPLL_CON3 0x340 +#define APUPLL2_CON0 0x614 +#define APUPLL2_CON1 0x618 +#define APUPLL2_CON2 0x61C +#define APUPLL2_CON3 0x620 +#define APUPLL_CON0 0x604 +#define APUPLL_CON1 0x608 +#define APUPLL_CON2 0x60C +#define APUPLL_CON3 0x610 +#define TVDPLL1_CON0 0x42C +#define TVDPLL1_CON1 0x430 +#define TVDPLL1_CON2 0x434 +#define TVDPLL1_CON3 0x438 +#define TVDPLL2_CON0 0x43C +#define TVDPLL2_CON1 0x440 +#define TVDPLL2_CON2 0x444 +#define TVDPLL2_CON3 0x448 +#define ETHPLL_CON0 0x514 +#define ETHPLL_CON1 0x518 +#define ETHPLL_CON2 0x51C +#define ETHPLL_CON3 0x520 +#define MSDCPLL_CON0 0x524 +#define MSDCPLL_CON1 0x528 +#define MSDCPLL_CON2 0x52C +#define MSDCPLL_CON3 0x530 +#define UFSPLL_CON0 0x534 +#define UFSPLL_CON1 0x538 +#define UFSPLL_CON2 0x53C +#define UFSPLL_CON3 0x540 + +enum { + CLK_PAD_CLK32K, + CLK_PAD_CLK26M, + CLK_PAD_ULPOSC, +}; + +static ulong ext_clock_rates[] = { + [CLK_PAD_CLK32K] = 32000, + [CLK_PAD_CLK26M] = 26 * MHZ, + [CLK_PAD_ULPOSC] = 260 * MHZ, +}; + +#define MT8189_PLL_FMAX (3800UL * MHZ) +#define MT8189_PLL_FMIN (1500UL * MHZ) + +#define PLL(_id, _reg, _flags, _pd_reg, _pd_shift, _pcw_reg, _pcw_shift, _pcwbits) \ + { \ + .id = _id, \ + .reg = _reg, \ + .flags = (_flags), \ + .fmax = MT8189_PLL_FMAX, \ + .fmin = MT8189_PLL_FMIN, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + .pcwbits = _pcwbits, \ + .pcwibits = 8, \ + } + +static const struct mtk_pll_data apmixed_plls[] = { + PLL(CLK_APMIXED_ARMPLL_LL, ARMPLL_LL_CON0, 0, ARMPLL_LL_CON1, 24, ARMPLL_LL_CON1, 0, 22), + PLL(CLK_APMIXED_ARMPLL_BL, ARMPLL_BL_CON0, 0, ARMPLL_BL_CON1, 24, ARMPLL_BL_CON1, 0, 22), + PLL(CLK_APMIXED_CCIPLL, CCIPLL_CON0, 0, CCIPLL_CON1, 24, CCIPLL_CON1, 0, 22), + PLL(CLK_APMIXED_MAINPLL, MAINPLL_CON0, 0, MAINPLL_CON1, 24, MAINPLL_CON1, 0, 22), + PLL(CLK_APMIXED_UNIVPLL, UNIVPLL_CON0, 0, UNIVPLL_CON1, 24, UNIVPLL_CON1, 0, 22), + PLL(CLK_APMIXED_MMPLL, MMPLL_CON0, 0, MMPLL_CON1, 24, MMPLL_CON1, 0, 22), + PLL(CLK_APMIXED_MFGPLL, MFGPLL_CON0, 0, MFGPLL_CON1, 24, MFGPLL_CON1, 0, 22), + PLL(CLK_APMIXED_APLL1, APLL1_CON0, 0, APLL1_CON1, 24, APLL1_CON2, 0, 32), + PLL(CLK_APMIXED_APLL2, APLL2_CON0, 0, APLL2_CON1, 24, APLL2_CON2, 0, 32), + PLL(CLK_APMIXED_EMIPLL, EMIPLL_CON0, 0, EMIPLL_CON1, 24, EMIPLL_CON1, 0, 22), + PLL(CLK_APMIXED_APUPLL2, APUPLL2_CON0, 0, APUPLL2_CON1, 24, APUPLL2_CON1, 0, 22), + PLL(CLK_APMIXED_APUPLL, APUPLL_CON0, 0, APUPLL_CON1, 24, APUPLL_CON1, 0, 22), + PLL(CLK_APMIXED_TVDPLL1, TVDPLL1_CON0, 0, TVDPLL1_CON1, 24, TVDPLL1_CON1, 0, 22), + PLL(CLK_APMIXED_TVDPLL2, TVDPLL2_CON0, 0, TVDPLL2_CON1, 24, TVDPLL2_CON1, 0, 22), + PLL(CLK_APMIXED_ETHPLL, ETHPLL_CON0, 0, ETHPLL_CON1, 24, ETHPLL_CON1, 0, 22), + PLL(CLK_APMIXED_MSDCPLL, MSDCPLL_CON0, 0, MSDCPLL_CON1, 24, MSDCPLL_CON1, 0, 22), + PLL(CLK_APMIXED_UFSPLL, UFSPLL_CON0, 0, UFSPLL_CON1, 24, UFSPLL_CON1, 0, 22), +}; + +#define FACTOR0(id, parent, mult, div) \ + FACTOR(id, parent, mult, div, CLK_PARENT_APMIXED) + +#define FACTOR1(id, parent, mult, div) \ + FACTOR(id, parent, mult, div, CLK_PARENT_EXT) + +static const struct mtk_fixed_factor top_fixed_divs[] = { + FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3), + FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4), + FACTOR0(CLK_TOP_MAINPLL_D4_D2, CLK_APMIXED_MAINPLL, 1, 8), + FACTOR0(CLK_TOP_MAINPLL_D4_D4, CLK_APMIXED_MAINPLL, 1, 16), + FACTOR0(CLK_TOP_MAINPLL_D4_D8, CLK_APMIXED_MAINPLL, 43, 1375), + FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5), + FACTOR0(CLK_TOP_MAINPLL_D5_D2, CLK_APMIXED_MAINPLL, 1, 10), + FACTOR0(CLK_TOP_MAINPLL_D5_D4, CLK_APMIXED_MAINPLL, 1, 20), + FACTOR0(CLK_TOP_MAINPLL_D5_D8, CLK_APMIXED_MAINPLL, 1, 40), + FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6), + FACTOR0(CLK_TOP_MAINPLL_D6_D2, CLK_APMIXED_MAINPLL, 1, 12), + FACTOR0(CLK_TOP_MAINPLL_D6_D4, CLK_APMIXED_MAINPLL, 1, 24), + FACTOR0(CLK_TOP_MAINPLL_D6_D8, CLK_APMIXED_MAINPLL, 1, 48), + FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7), + FACTOR0(CLK_TOP_MAINPLL_D7_D2, CLK_APMIXED_MAINPLL, 1, 14), + FACTOR0(CLK_TOP_MAINPLL_D7_D4, CLK_APMIXED_MAINPLL, 1, 28), + FACTOR0(CLK_TOP_MAINPLL_D7_D8, CLK_APMIXED_MAINPLL, 1, 56), + FACTOR0(CLK_TOP_MAINPLL_D9, CLK_APMIXED_MAINPLL, 1, 9), + FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2), + FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3), + FACTOR0(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4), + FACTOR0(CLK_TOP_UNIVPLL_D4_D2, CLK_APMIXED_UNIVPLL, 1, 8), + FACTOR0(CLK_TOP_UNIVPLL_D4_D4, CLK_APMIXED_UNIVPLL, 1, 16), + FACTOR0(CLK_TOP_UNIVPLL_D4_D8, CLK_APMIXED_UNIVPLL, 1, 32), + FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5), + FACTOR0(CLK_TOP_UNIVPLL_D5_D2, CLK_APMIXED_UNIVPLL, 1, 10), + FACTOR0(CLK_TOP_UNIVPLL_D5_D4, CLK_APMIXED_UNIVPLL, 1, 20), + FACTOR0(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6), + FACTOR0(CLK_TOP_UNIVPLL_D6_D2, CLK_APMIXED_UNIVPLL, 1, 12), + FACTOR0(CLK_TOP_UNIVPLL_D6_D4, CLK_APMIXED_UNIVPLL, 1, 24), + FACTOR0(CLK_TOP_UNIVPLL_D6_D8, CLK_APMIXED_UNIVPLL, 1, 48), + FACTOR0(CLK_TOP_UNIVPLL_D6_D16, CLK_APMIXED_UNIVPLL, 1, 96), + FACTOR0(CLK_TOP_UNIVPLL_D7, CLK_APMIXED_UNIVPLL, 1, 7), + FACTOR0(CLK_TOP_UNIVPLL_D7_D2, CLK_APMIXED_UNIVPLL, 1, 14), + FACTOR0(CLK_TOP_UNIVPLL_D7_D3, CLK_APMIXED_UNIVPLL, 1, 21), + FACTOR0(CLK_TOP_LVDSTX_DG_CTS, CLK_APMIXED_UNIVPLL, 1, 21), + FACTOR0(CLK_TOP_UNIVPLL_192M, CLK_APMIXED_UNIVPLL, 1, 13), + FACTOR0(CLK_TOP_UNIVPLL_192M_D2, CLK_APMIXED_UNIVPLL, 1, 26), + FACTOR0(CLK_TOP_UNIVPLL_192M_D4, CLK_APMIXED_UNIVPLL, 1, 52), + FACTOR0(CLK_TOP_UNIVPLL_192M_D8, CLK_APMIXED_UNIVPLL, 1, 104), + FACTOR0(CLK_TOP_UNIVPLL_192M_D10, CLK_APMIXED_UNIVPLL, 1, 130), + FACTOR0(CLK_TOP_UNIVPLL_192M_D16, CLK_APMIXED_UNIVPLL, 1, 208), + FACTOR0(CLK_TOP_UNIVPLL_192M_D32, CLK_APMIXED_UNIVPLL, 1, 416), + FACTOR0(CLK_TOP_APLL1_D2, CLK_APMIXED_APLL1, 1, 2), + FACTOR0(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4), + FACTOR0(CLK_TOP_APLL1_D8, CLK_APMIXED_APLL1, 1, 8), + FACTOR0(CLK_TOP_APLL1_D3, CLK_APMIXED_APLL1, 1, 3), + FACTOR0(CLK_TOP_APLL2_D2, CLK_APMIXED_APLL2, 1, 2), + FACTOR0(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4), + FACTOR0(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8), + FACTOR0(CLK_TOP_APLL2_D3, CLK_APMIXED_APLL2, 1, 3), + FACTOR0(CLK_TOP_MMPLL_D4, CLK_APMIXED_MMPLL, 1, 4), + FACTOR0(CLK_TOP_MMPLL_D4_D2, CLK_APMIXED_MMPLL, 1, 8), + FACTOR0(CLK_TOP_MMPLL_D4_D4, CLK_APMIXED_MMPLL, 1, 16), + FACTOR0(CLK_TOP_VPLL_DPIX, CLK_APMIXED_MMPLL, 1, 16), + FACTOR0(CLK_TOP_MMPLL_D5, CLK_APMIXED_MMPLL, 1, 5), + FACTOR0(CLK_TOP_MMPLL_D5_D2, CLK_APMIXED_MMPLL, 1, 10), + FACTOR0(CLK_TOP_MMPLL_D5_D4, CLK_APMIXED_MMPLL, 1, 20), + FACTOR0(CLK_TOP_MMPLL_D6, CLK_APMIXED_MMPLL, 1, 6), + FACTOR0(CLK_TOP_MMPLL_D6_D2, CLK_APMIXED_MMPLL, 1, 12), + FACTOR0(CLK_TOP_MMPLL_D7, CLK_APMIXED_MMPLL, 1, 7), + FACTOR0(CLK_TOP_MMPLL_D9, CLK_APMIXED_MMPLL, 1, 9), + FACTOR0(CLK_TOP_TVDPLL1_D2, CLK_APMIXED_TVDPLL1, 1, 2), + FACTOR0(CLK_TOP_TVDPLL1_D4, CLK_APMIXED_TVDPLL1, 1, 4), + FACTOR0(CLK_TOP_TVDPLL1_D8, CLK_APMIXED_TVDPLL1, 1, 8), + FACTOR0(CLK_TOP_TVDPLL1_D16, CLK_APMIXED_TVDPLL1, 92, 1473), + FACTOR0(CLK_TOP_TVDPLL2_D2, CLK_APMIXED_TVDPLL2, 1, 2), + FACTOR0(CLK_TOP_TVDPLL2_D4, CLK_APMIXED_TVDPLL2, 1, 4), + FACTOR0(CLK_TOP_TVDPLL2_D8, CLK_APMIXED_TVDPLL2, 1, 8), + FACTOR0(CLK_TOP_TVDPLL2_D16, CLK_APMIXED_TVDPLL2, 92, 1473), + FACTOR0(CLK_TOP_ETHPLL_D2, CLK_APMIXED_ETHPLL, 1, 2), + FACTOR0(CLK_TOP_ETHPLL_D8, CLK_APMIXED_ETHPLL, 1, 8), + FACTOR0(CLK_TOP_ETHPLL_D10, CLK_APMIXED_ETHPLL, 1, 10), + FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2), + FACTOR1(CLK_TOP_VOWPLL, CLK_PAD_CLK26M, 1, 1), + FACTOR0(CLK_TOP_UFSPLL_D2, CLK_APMIXED_UFSPLL, 1, 2), + FACTOR1(CLK_TOP_F26M_CK_D2, CLK_PAD_CLK26M, 1, 2), + FACTOR1(CLK_TOP_OSC_D2, CLK_PAD_ULPOSC, 1, 2), + FACTOR1(CLK_TOP_OSC_D4, CLK_PAD_ULPOSC, 1, 4), + FACTOR1(CLK_TOP_OSC_D8, CLK_PAD_ULPOSC, 1, 8), + FACTOR1(CLK_TOP_OSC_D16, CLK_PAD_ULPOSC, 61, 973), + FACTOR1(CLK_TOP_OSC_D3, CLK_PAD_ULPOSC, 1, 3), + FACTOR1(CLK_TOP_OSC_D7, CLK_PAD_ULPOSC, 1, 7), + FACTOR1(CLK_TOP_OSC_D10, CLK_PAD_ULPOSC, 1, 10), + FACTOR1(CLK_TOP_OSC_D20, CLK_PAD_ULPOSC, 1, 20), +}; + +static const struct mtk_parent axi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_OSC_D4), +}; + +static const struct mtk_parent axi_peri_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_OSC_D4), +}; + +static const struct mtk_parent axi_u_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), + TOP_PARENT(CLK_TOP_OSC_D8), +}; + +static const struct mtk_parent bus_aximem_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), +}; + +static const struct mtk_parent disp0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + APMIXED_PARENT(CLK_APMIXED_TVDPLL1), + APMIXED_PARENT(CLK_APMIXED_TVDPLL2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), +}; + +static const struct mtk_parent mminfra_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + APMIXED_PARENT(CLK_APMIXED_EMIPLL), +}; + +static const struct mtk_parent uart_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), +}; + +static const struct mtk_parent spi0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_192M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent spi1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_192M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent spi2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_192M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent spi3_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_192M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent spi4_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_192M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent spi5_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_192M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent msdc_macro_0p_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_MSDCPLL), + TOP_PARENT(CLK_TOP_MMPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), +}; + +static const struct mtk_parent msdc5hclk_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), +}; + +static const struct mtk_parent msdc50_0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_MSDCPLL), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), +}; + +static const struct mtk_parent aes_msdcfde_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + APMIXED_PARENT(CLK_APMIXED_MSDCPLL), +}; + +static const struct mtk_parent msdc_macro_1p_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_MSDCPLL), + TOP_PARENT(CLK_TOP_MMPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), +}; + +static const struct mtk_parent msdc30_1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), +}; + +static const struct mtk_parent msdc30_1_h_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D4), +}; + +static const struct mtk_parent msdc_macro_2p_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_MSDCPLL), + TOP_PARENT(CLK_TOP_MMPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), +}; + +static const struct mtk_parent msdc30_2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), +}; + +static const struct mtk_parent msdc30_2_h_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D4), +}; + +static const struct mtk_parent aud_intbus_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), +}; + +static const struct mtk_parent atb_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), +}; + +static const struct mtk_parent disp_pwm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_OSC_D4), + TOP_PARENT(CLK_TOP_OSC_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), +}; + +static const struct mtk_parent usb_p0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent ssusb_xhci_p0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent usb_p1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent ssusb_xhci_p1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent usb_p2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent ssusb_xhci_p2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent usb_p3_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent ssusb_xhci_p3_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent usb_p4_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent ssusb_xhci_p4_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent i2c_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), +}; + +static const struct mtk_parent seninf_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), +}; + +static const struct mtk_parent seninf1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), +}; + +static const struct mtk_parent aud_engen1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_D2), + TOP_PARENT(CLK_TOP_APLL1_D4), + TOP_PARENT(CLK_TOP_APLL1_D8), +}; + +static const struct mtk_parent aud_engen2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_D2), + TOP_PARENT(CLK_TOP_APLL2_D4), + TOP_PARENT(CLK_TOP_APLL2_D8), +}; + +static const struct mtk_parent aes_ufsfde_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), +}; + +static const struct mtk_parent ufs_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), +}; + +static const struct mtk_parent ufs_mbist_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UFSPLL_D2), +}; + +static const struct mtk_parent aud_1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_APLL1), +}; + +static const struct mtk_parent aud_2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_APLL2), +}; + +static const struct mtk_parent venc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MMPLL_D9), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5), +}; + +static const struct mtk_parent vdec_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D5_D2), +}; + +static const struct mtk_parent pwm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), +}; + +static const struct mtk_parent audio_h_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D7_D2), + APMIXED_PARENT(CLK_APMIXED_APLL1), + APMIXED_PARENT(CLK_APMIXED_APLL2), +}; + +static const struct mtk_parent mcupm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), +}; + +static const struct mtk_parent mem_sub_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), +}; + +static const struct mtk_parent mem_sub_peri_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D4), +}; + +static const struct mtk_parent mem_sub_u_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D4), +}; + +static const struct mtk_parent emi_n_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D9), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + APMIXED_PARENT(CLK_APMIXED_EMIPLL), +}; + +static const struct mtk_parent dsi_occ_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), +}; + +static const struct mtk_parent ap2conn_host_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), +}; + +static const struct mtk_parent img1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_MMPLL_D5_D2), +}; + +static const struct mtk_parent ipe_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_MMPLL_D5_D2), +}; + +static const struct mtk_parent cam_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D9), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_OSC_D2), +}; + +static const struct mtk_parent camtm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent dsp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D4), + TOP_PARENT(CLK_TOP_OSC_D3), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), +}; + +static const struct mtk_parent sr_pka_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), +}; + +static const struct mtk_parent dxcc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), +}; + +static const struct mtk_parent mfg_ref_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), +}; + +static const struct mtk_parent mdp0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + APMIXED_PARENT(CLK_APMIXED_TVDPLL1), + APMIXED_PARENT(CLK_APMIXED_TVDPLL2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), +}; + +static const struct mtk_parent dp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL1_D16), + TOP_PARENT(CLK_TOP_TVDPLL1_D8), + TOP_PARENT(CLK_TOP_TVDPLL1_D4), + TOP_PARENT(CLK_TOP_TVDPLL1_D2), +}; + +static const struct mtk_parent edp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL2_D16), + TOP_PARENT(CLK_TOP_TVDPLL2_D8), + TOP_PARENT(CLK_TOP_TVDPLL2_D4), + TOP_PARENT(CLK_TOP_TVDPLL2_D2), + TOP_PARENT(CLK_TOP_APLL1_D4), + TOP_PARENT(CLK_TOP_APLL2_D4), +}; + +static const struct mtk_parent edp_favt_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL2_D16), + TOP_PARENT(CLK_TOP_TVDPLL2_D8), + TOP_PARENT(CLK_TOP_TVDPLL2_D4), + TOP_PARENT(CLK_TOP_TVDPLL2_D2), + TOP_PARENT(CLK_TOP_APLL1_D4), + TOP_PARENT(CLK_TOP_APLL2_D4), +}; + +static const struct mtk_parent snps_eth_250m_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D2), +}; + +static const struct mtk_parent snps_eth_62p4m_ptp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D8), + TOP_PARENT(CLK_TOP_APLL1_D3), + TOP_PARENT(CLK_TOP_APLL2_D3), +}; + +static const struct mtk_parent snps_eth_50m_rmii_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D10), +}; + +static const struct mtk_parent sflash_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D7_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), +}; + +static const struct mtk_parent gcpu_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), +}; + +static const struct mtk_parent pcie_mac_tl_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), +}; + +static const struct mtk_parent vdstx_dg_cts_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_LVDSTX_DG_CTS), + TOP_PARENT(CLK_TOP_UNIVPLL_D7_D3), +}; + +static const struct mtk_parent pll_dpix_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_VPLL_DPIX), + TOP_PARENT(CLK_TOP_MMPLL_D4_D4), +}; + +static const struct mtk_parent ecc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), +}; + +#define MUX_CLR_SET_UPD(_id, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ + _shift, _width, _upd_ofs, _upd) \ + MUX_MIXED_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs, \ + _mux_clr_ofs, _shift, _width, -1, _upd_ofs, \ + _upd, CLK_MUX_SETCLR_UPD) + +#define MUX_GATE_CLR_SET_UPD(_id, _parents, _mux_ofs, _mux_set_ofs, \ + _mux_clr_ofs, _shift, _width, _gate, _upd_ofs, \ + _upd) \ + MUX_MIXED_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs, \ + _mux_clr_ofs, _shift, _width, _gate, \ + _upd_ofs, _upd, CLK_MUX_SETCLR_UPD) + +const struct mtk_composite top_muxes[] = { + /* CLK_CFG_0 */ + MUX_CLR_SET_UPD(CLK_TOP_AXI_SEL, axi_parents, CLK_CFG_0, CLK_CFG_0_SET, + CLK_CFG_0_CLR, 0, 3, CLK_CFG_UPDATE, TOP_MUX_AXI_SHIFT), + MUX_CLR_SET_UPD(CLK_TOP_AXI_PERI_SEL, axi_peri_parents, CLK_CFG_0, + CLK_CFG_0_SET, CLK_CFG_0_CLR, 8, 2, CLK_CFG_UPDATE, + TOP_MUX_AXI_PERI_SHIFT), + MUX_CLR_SET_UPD(CLK_TOP_AXI_U_SEL, axi_u_parents, CLK_CFG_0, + CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 2, CLK_CFG_UPDATE, + TOP_MUX_AXI_UFS_SHIFT), + MUX_CLR_SET_UPD(CLK_TOP_BUS_AXIMEM_SEL, bus_aximem_parents, CLK_CFG_0, + CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, CLK_CFG_UPDATE, + TOP_MUX_BUS_AXIMEM_SHIFT), + /* CLK_CFG_1 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP0_SEL, disp0_parents, CLK_CFG_1, + CLK_CFG_1_SET, CLK_CFG_1_CLR, 0, 4, 7, + CLK_CFG_UPDATE, TOP_MUX_DISP0_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MMINFRA_SEL, mminfra_parents, CLK_CFG_1, + CLK_CFG_1_SET, CLK_CFG_1_CLR, 8, 4, 15, + CLK_CFG_UPDATE, TOP_MUX_MMINFRA_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, uart_parents, CLK_CFG_1, + CLK_CFG_1_SET, CLK_CFG_1_CLR, 16, 1, 23, + CLK_CFG_UPDATE, TOP_MUX_UART_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI0_SEL, spi0_parents, CLK_CFG_1, + CLK_CFG_1_SET, CLK_CFG_1_CLR, 24, 3, 31, + CLK_CFG_UPDATE, TOP_MUX_SPI0_SHIFT), + /* CLK_CFG_2 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI1_SEL, spi1_parents, CLK_CFG_2, + CLK_CFG_2_SET, CLK_CFG_2_CLR, 0, 3, 7, + CLK_CFG_UPDATE, TOP_MUX_SPI1_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI2_SEL, spi2_parents, CLK_CFG_2, + CLK_CFG_2_SET, CLK_CFG_2_CLR, 8, 3, 15, + CLK_CFG_UPDATE, TOP_MUX_SPI2_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI3_SEL, spi3_parents, CLK_CFG_2, + CLK_CFG_2_SET, CLK_CFG_2_CLR, 16, 3, 23, + CLK_CFG_UPDATE, TOP_MUX_SPI3_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI4_SEL, spi4_parents, CLK_CFG_2, + CLK_CFG_2_SET, CLK_CFG_2_CLR, 24, 3, 31, + CLK_CFG_UPDATE, TOP_MUX_SPI4_SHIFT), + /* CLK_CFG_3 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI5_SEL, spi5_parents, CLK_CFG_3, + CLK_CFG_3_SET, CLK_CFG_3_CLR, 0, 3, 7, + CLK_CFG_UPDATE, TOP_MUX_SPI5_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC_MACRO_0P_SEL, msdc_macro_0p_parents, + CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 8, 2, 15, + CLK_CFG_UPDATE, TOP_MUX_MSDC_MACRO_0P_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, msdc5hclk_parents, + CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 16, 2, 23, + CLK_CFG_UPDATE, TOP_MUX_MSDC50_0_HCLK_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents, CLK_CFG_3, + CLK_CFG_3_SET, CLK_CFG_3_CLR, 24, 3, 31, + CLK_CFG_UPDATE, TOP_MUX_MSDC50_0_SHIFT), + /* CLK_CFG_4 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE_SEL, aes_msdcfde_parents, + CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 0, 3, 7, + CLK_CFG_UPDATE, TOP_MUX_AES_MSDCFDE_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC_MACRO_1P_SEL, msdc_macro_1p_parents, + CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 8, 2, 15, + CLK_CFG_UPDATE, TOP_MUX_MSDC_MACRO_1P_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, CLK_CFG_4, + CLK_CFG_4_SET, CLK_CFG_4_CLR, 16, 3, 23, + CLK_CFG_UPDATE, TOP_MUX_MSDC30_1_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_HCLK_SEL, msdc30_1_h_parents, + CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 24, 2, 31, + CLK_CFG_UPDATE, TOP_MUX_MSDC30_1_HCLK_SHIFT), + /* CLK_CFG_5 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC_MACRO_2P_SEL, msdc_macro_2p_parents, + CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 0, 2, 7, + CLK_CFG_UPDATE, TOP_MUX_MSDC_MACRO_2P_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL, msdc30_2_parents, CLK_CFG_5, + CLK_CFG_5_SET, CLK_CFG_5_CLR, 8, 3, 15, + CLK_CFG_UPDATE, TOP_MUX_MSDC30_2_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_HCLK_SEL, msdc30_2_h_parents, + CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 16, 2, 23, + CLK_CFG_UPDATE, TOP_MUX_MSDC30_2_HCLK_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, + CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 24, 2, 31, + CLK_CFG_UPDATE, TOP_MUX_AUD_INTBUS_SHIFT), + /* CLK_CFG_6 */ + MUX_CLR_SET_UPD(CLK_TOP_ATB_SEL, atb_parents, CLK_CFG_6, CLK_CFG_6_SET, + CLK_CFG_6_CLR, 0, 2, CLK_CFG_UPDATE, TOP_MUX_ATB_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, disp_pwm_parents, CLK_CFG_6, + CLK_CFG_6_SET, CLK_CFG_6_CLR, 8, 3, 15, + CLK_CFG_UPDATE, TOP_MUX_DISP_PWM_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P0_SEL, usb_p0_parents, CLK_CFG_6, + CLK_CFG_6_SET, CLK_CFG_6_CLR, 16, 2, 23, + CLK_CFG_UPDATE, TOP_MUX_USB_TOP_P0_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P0_SEL, ssusb_xhci_p0_parents, + CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 24, 2, 31, + CLK_CFG_UPDATE, TOP_MUX_SSUSB_XHCI_P0_SHIFT), + /* CLK_CFG_7 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P1_SEL, usb_p1_parents, CLK_CFG_7, + CLK_CFG_7_SET, CLK_CFG_7_CLR, 0, 2, 7, + CLK_CFG_UPDATE, TOP_MUX_USB_TOP_P1_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, ssusb_xhci_p1_parents, + CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 8, 2, 15, + CLK_CFG_UPDATE, TOP_MUX_SSUSB_XHCI_P1_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P2_SEL, usb_p2_parents, CLK_CFG_7, + CLK_CFG_7_SET, CLK_CFG_7_CLR, 16, 2, 23, + CLK_CFG_UPDATE, TOP_MUX_USB_TOP_P2_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P2_SEL, ssusb_xhci_p2_parents, + CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 24, 2, 31, + CLK_CFG_UPDATE1, TOP_MUX_SSUSB_XHCI_P2_SHIFT), + /* CLK_CFG_8 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P3_SEL, usb_p3_parents, CLK_CFG_8, + CLK_CFG_8_SET, CLK_CFG_8_CLR, 0, 2, 7, + CLK_CFG_UPDATE1, TOP_MUX_USB_TOP_P3_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P3_SEL, ssusb_xhci_p3_parents, + CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR, 8, 2, 15, + CLK_CFG_UPDATE1, TOP_MUX_SSUSB_XHCI_P3_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P4_SEL, usb_p4_parents, CLK_CFG_8, + CLK_CFG_8_SET, CLK_CFG_8_CLR, 16, 2, 23, + CLK_CFG_UPDATE1, TOP_MUX_USB_TOP_P4_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P4_SEL, ssusb_xhci_p4_parents, + CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR, 24, 2, 31, + CLK_CFG_UPDATE1, TOP_MUX_SSUSB_XHCI_P4_SHIFT), + /* CLK_CFG_9 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, i2c_parents, CLK_CFG_9, + CLK_CFG_9_SET, CLK_CFG_9_CLR, 0, 2, 7, + CLK_CFG_UPDATE1, TOP_MUX_I2C_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, seninf_parents, + CLK_CFG_9, CLK_CFG_9_SET, CLK_CFG_9_CLR, 8, 3, 15, + CLK_CFG_UPDATE1, TOP_MUX_SENINF_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1_SEL, seninf1_parents, CLK_CFG_9, + CLK_CFG_9_SET, CLK_CFG_9_CLR, 16, 3, 23, + CLK_CFG_UPDATE1, TOP_MUX_SENINF1_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, + CLK_CFG_9, CLK_CFG_9_SET, CLK_CFG_9_CLR, 24, 2, 31, + CLK_CFG_UPDATE1, TOP_MUX_AUD_ENGEN1_SHIFT), + /* CLK_CFG_10 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, + CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR, 0, 2, 7, + CLK_CFG_UPDATE1, TOP_MUX_AUD_ENGEN2_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE_SEL, aes_ufsfde_parents, + CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR, 8, 3, 15, + CLK_CFG_UPDATE1, TOP_MUX_AES_UFSFDE_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_U_SEL, ufs_parents, CLK_CFG_10, + CLK_CFG_10_SET, CLK_CFG_10_CLR, 16, 3, 23, + CLK_CFG_UPDATE1, TOP_MUX_UFS_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_U_MBIST_SEL, ufs_mbist_parents, CLK_CFG_10, + CLK_CFG_10_SET, CLK_CFG_10_CLR, 24, 2, 31, + CLK_CFG_UPDATE1, TOP_MUX_UFS_MBIST_SHIFT), + /* CLK_CFG_11 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, aud_1_parents, CLK_CFG_11, + CLK_CFG_11_SET, CLK_CFG_11_CLR, 0, 1, 7, + CLK_CFG_UPDATE1, TOP_MUX_AUD_1_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, aud_2_parents, CLK_CFG_11, + CLK_CFG_11_SET, CLK_CFG_11_CLR, 8, 1, 15, + CLK_CFG_UPDATE1, TOP_MUX_AUD_2_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, venc_parents, CLK_CFG_11, + CLK_CFG_11_SET, CLK_CFG_11_CLR, 16, 4, 23, + CLK_CFG_UPDATE1, TOP_MUX_VENC_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, vdec_parents, CLK_CFG_11, + CLK_CFG_11_SET, CLK_CFG_11_CLR, 24, 4, 31, + CLK_CFG_UPDATE1, TOP_MUX_VDEC_SHIFT), + /* CLK_CFG_12 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, pwm_parents, CLK_CFG_12, + CLK_CFG_12_SET, CLK_CFG_12_CLR, 0, 1, 7, + CLK_CFG_UPDATE1, TOP_MUX_PWM_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H_SEL, audio_h_parents, CLK_CFG_12, + CLK_CFG_12_SET, CLK_CFG_12_CLR, 8, 2, 15, + CLK_CFG_UPDATE1, TOP_MUX_AUDIO_H_SHIFT), + MUX_CLR_SET_UPD(CLK_TOP_MCUPM_SEL, mcupm_parents, CLK_CFG_12, + CLK_CFG_12_SET, CLK_CFG_12_CLR, 16, 2, CLK_CFG_UPDATE1, + TOP_MUX_MCUPM_SHIFT), + MUX_CLR_SET_UPD(CLK_TOP_MEM_SUB_SEL, mem_sub_parents, CLK_CFG_12, + CLK_CFG_12_SET, CLK_CFG_12_CLR, 24, 4, CLK_CFG_UPDATE1, + TOP_MUX_MEM_SUB_SHIFT), + /* CLK_CFG_13 */ + MUX_CLR_SET_UPD(CLK_TOP_MEM_SUB_PERI_SEL, mem_sub_peri_parents, CLK_CFG_13, + CLK_CFG_13_SET, CLK_CFG_13_CLR, 0, 3, CLK_CFG_UPDATE1, + TOP_MUX_MEM_SUB_PERI_SHIFT), + MUX_CLR_SET_UPD(CLK_TOP_MEM_SUB_U_SEL, mem_sub_u_parents, CLK_CFG_13, + CLK_CFG_13_SET, CLK_CFG_13_CLR, 8, 3, CLK_CFG_UPDATE1, + TOP_MUX_MEM_SUB_UFS_SHIFT), + MUX_CLR_SET_UPD(CLK_TOP_EMI_N_SEL, emi_n_parents, CLK_CFG_13, + CLK_CFG_13_SET, CLK_CFG_13_CLR, 16, 3, CLK_CFG_UPDATE1, + TOP_MUX_EMI_N_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC_SEL, dsi_occ_parents, CLK_CFG_13, + CLK_CFG_13_SET, CLK_CFG_13_CLR, 24, 2, 31, + CLK_CFG_UPDATE1, TOP_MUX_DSI_OCC_SHIFT), + /* CLK_CFG_14 */ + MUX_CLR_SET_UPD(CLK_TOP_AP2CONN_HOST_SEL, ap2conn_host_parents, CLK_CFG_14, + CLK_CFG_14_SET, CLK_CFG_14_CLR, 0, 1, CLK_CFG_UPDATE1, + TOP_MUX_AP2CONN_HOST_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1_SEL, img1_parents, CLK_CFG_14, + CLK_CFG_14_SET, CLK_CFG_14_CLR, 8, 4, 15, + CLK_CFG_UPDATE1, TOP_MUX_IMG1_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, ipe_parents, CLK_CFG_14, + CLK_CFG_14_SET, CLK_CFG_14_CLR, 16, 4, 23, + CLK_CFG_UPDATE1, TOP_MUX_IPE_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL, cam_parents, CLK_CFG_14, + CLK_CFG_14_SET, CLK_CFG_14_CLR, 24, 4, 31, + CLK_CFG_UPDATE1, TOP_MUX_CAM_SHIFT), + /* CLK_CFG_15 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, camtm_parents, CLK_CFG_15, + CLK_CFG_15_SET, CLK_CFG_15_CLR, 0, 2, 7, + CLK_CFG_UPDATE1, TOP_MUX_CAMTM_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, dsp_parents, CLK_CFG_15, + CLK_CFG_15_SET, CLK_CFG_15_CLR, 8, 3, 15, + CLK_CFG_UPDATE1, TOP_MUX_DSP_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SR_PKA_SEL, sr_pka_parents, CLK_CFG_15, + CLK_CFG_15_SET, CLK_CFG_15_CLR, 16, 3, 23, + CLK_CFG_UPDATE2, TOP_MUX_SR_PKA_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, dxcc_parents, CLK_CFG_15, + CLK_CFG_15_SET, CLK_CFG_15_CLR, 24, 2, 31, + CLK_CFG_UPDATE2, TOP_MUX_DXCC_SHIFT), + /* CLK_CFG_16 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, mfg_ref_parents, CLK_CFG_16, + CLK_CFG_16_SET, CLK_CFG_16_CLR, 0, 2, 7, + CLK_CFG_UPDATE2, TOP_MUX_MFG_REF_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP0_SEL, mdp0_parents, CLK_CFG_16, + CLK_CFG_16_SET, CLK_CFG_16_CLR, 8, 4, 15, + CLK_CFG_UPDATE2, TOP_MUX_MDP0_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DP_SEL, dp_parents, CLK_CFG_16, + CLK_CFG_16_SET, CLK_CFG_16_CLR, 16, 3, 23, + CLK_CFG_UPDATE2, TOP_MUX_DP_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP_SEL, edp_parents, CLK_CFG_16, + CLK_CFG_16_SET, CLK_CFG_16_CLR, 24, 3, 31, + CLK_CFG_UPDATE2, TOP_MUX_EDP_SHIFT), + /* CLK_CFG_17 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP_FAVT_SEL, edp_favt_parents, CLK_CFG_17, + CLK_CFG_17_SET, CLK_CFG_17_CLR, 0, 3, 7, + CLK_CFG_UPDATE2, TOP_MUX_EDP_FAVT_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_250M_SEL, snps_eth_250m_parents, CLK_CFG_17, + CLK_CFG_17_SET, CLK_CFG_17_CLR, 8, 1, 15, + CLK_CFG_UPDATE2, TOP_MUX_SNPS_ETH_250M_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_62P4M_PTP_SEL, + snps_eth_62p4m_ptp_parents, CLK_CFG_17, + CLK_CFG_17_SET, CLK_CFG_17_CLR, 16, 2, 23, + CLK_CFG_UPDATE2, TOP_MUX_SNPS_ETH_62P4M_PTP_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_50M_RMII_SEL, + snps_eth_50m_rmii_parents, CLK_CFG_17, + CLK_CFG_17_SET, CLK_CFG_17_CLR, 24, 1, 31, + CLK_CFG_UPDATE2, TOP_MUX_SNPS_ETH_50M_RMII_SHIFT), + /* CLK_CFG_18 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_SFLASH_SEL, sflash_parents, CLK_CFG_18, + CLK_CFG_18_SET, CLK_CFG_18_CLR, 0, 3, 7, + CLK_CFG_UPDATE2, TOP_MUX_SFLASH_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_SEL, gcpu_parents, CLK_CFG_18, + CLK_CFG_18_SET, CLK_CFG_18_CLR, 8, 3, 15, + CLK_CFG_UPDATE2, TOP_MUX_GCPU_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MAC_TL_SEL, pcie_mac_tl_parents, CLK_CFG_18, + CLK_CFG_18_SET, CLK_CFG_18_CLR, 16, 2, 23, + CLK_CFG_UPDATE2, TOP_MUX_PCIE_MAC_TL_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_VDSTX_DG_CTS_SEL, vdstx_dg_cts_parents, CLK_CFG_18, + CLK_CFG_18_SET, CLK_CFG_18_CLR, 24, 2, 31, + CLK_CFG_UPDATE2, TOP_MUX_VDSTX_CLKDIG_CTS_SHIFT), + /* CLK_CFG_19 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_PLL_DPIX_SEL, pll_dpix_parents, CLK_CFG_19, + CLK_CFG_19_SET, CLK_CFG_19_CLR, 0, 2, 7, + CLK_CFG_UPDATE2, TOP_MUX_PLL_DPIX_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC_SEL, ecc_parents, CLK_CFG_19, + CLK_CFG_19_SET, CLK_CFG_19_CLR, 8, 3, 15, + CLK_CFG_UPDATE2, TOP_MUX_ECC_SHIFT), +}; + +static const struct mtk_gate_regs top_cg_regs = { + .set_ofs = 0x514, + .clr_ofs = 0x518, + .sta_ofs = 0x510, +}; + +#define GATE_TOP(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &top_cg_regs, _shift, \ + CLK_GATE_NO_SETCLR_INV | CLK_PARENT_EXT) + +static const struct mtk_gate top_gates[] = { + GATE_TOP(CLK_TOP_USB2_PHY_RF_P0_EN, CLK_PAD_CLK26M, 7), + GATE_TOP(CLK_TOP_USB2_PHY_RF_P1_EN, CLK_PAD_CLK26M, 10), + GATE_TOP(CLK_TOP_USB2_PHY_RF_P2_EN, CLK_PAD_CLK26M, 11), + GATE_TOP(CLK_TOP_USB2_PHY_RF_P3_EN, CLK_PAD_CLK26M, 12), + GATE_TOP(CLK_TOP_USB2_PHY_RF_P4_EN, CLK_PAD_CLK26M, 13), +}; + +static const struct mtk_gate_regs perao0_cg_regs = { + .set_ofs = 0x24, + .clr_ofs = 0x28, + .sta_ofs = 0x10, +}; + +static const struct mtk_gate_regs perao1_cg_regs = { + .set_ofs = 0x2C, + .clr_ofs = 0x30, + .sta_ofs = 0x14, +}; + +static const struct mtk_gate_regs perao2_cg_regs = { + .set_ofs = 0x34, + .clr_ofs = 0x38, + .sta_ofs = 0x18, +}; + +#define GATE_PERAO0(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &perao0_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +#define GATE_PERAO0P(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &perao0_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_EXT) + +#define GATE_PERAO1(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &perao1_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +#define GATE_PERAO1P(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &perao1_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_EXT) + +#define GATE_PERAO2(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &perao2_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +#define GATE_PERAO2P(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &perao2_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_EXT) + +static const struct mtk_gate perao_clks[] = { + /* PERAO0 */ + GATE_PERAO0(CLK_PERAO_UART0, CLK_TOP_UART_SEL, 0), + GATE_PERAO0(CLK_PERAO_UART1, CLK_TOP_UART_SEL, 1), + GATE_PERAO0(CLK_PERAO_UART2, CLK_TOP_UART_SEL, 2), + GATE_PERAO0(CLK_PERAO_UART3, CLK_TOP_UART_SEL, 3), + GATE_PERAO0(CLK_PERAO_PWM_H, CLK_TOP_AXI_PERI_SEL, 4), + GATE_PERAO0(CLK_PERAO_PWM_B, CLK_TOP_PWM_SEL, 5), + GATE_PERAO0(CLK_PERAO_PWM_FB1, CLK_TOP_PWM_SEL, 6), + GATE_PERAO0(CLK_PERAO_PWM_FB2, CLK_TOP_PWM_SEL, 7), + GATE_PERAO0(CLK_PERAO_PWM_FB3, CLK_TOP_PWM_SEL, 8), + GATE_PERAO0(CLK_PERAO_PWM_FB4, CLK_TOP_PWM_SEL, 9), + GATE_PERAO0(CLK_PERAO_DISP_PWM0, CLK_TOP_DISP_PWM_SEL, 10), + GATE_PERAO0(CLK_PERAO_DISP_PWM1, CLK_TOP_DISP_PWM_SEL, 11), + GATE_PERAO0(CLK_PERAO_SPI0_B, CLK_TOP_SPI0_SEL, 12), + GATE_PERAO0(CLK_PERAO_SPI1_B, CLK_TOP_SPI1_SEL, 13), + GATE_PERAO0(CLK_PERAO_SPI2_B, CLK_TOP_SPI2_SEL, 14), + GATE_PERAO0(CLK_PERAO_SPI3_B, CLK_TOP_SPI3_SEL, 15), + GATE_PERAO0(CLK_PERAO_SPI4_B, CLK_TOP_SPI4_SEL, 16), + GATE_PERAO0(CLK_PERAO_SPI5_B, CLK_TOP_SPI5_SEL, 17), + GATE_PERAO0(CLK_PERAO_SPI0_H, CLK_TOP_AXI_PERI_SEL, 18), + GATE_PERAO0(CLK_PERAO_SPI1_H, CLK_TOP_AXI_PERI_SEL, 19), + GATE_PERAO0(CLK_PERAO_SPI2_H, CLK_TOP_AXI_PERI_SEL, 20), + GATE_PERAO0(CLK_PERAO_SPI3_H, CLK_TOP_AXI_PERI_SEL, 21), + GATE_PERAO0(CLK_PERAO_SPI4_H, CLK_TOP_AXI_PERI_SEL, 22), + GATE_PERAO0(CLK_PERAO_SPI5_H, CLK_TOP_AXI_PERI_SEL, 23), + GATE_PERAO0(CLK_PERAO_AXI, CLK_TOP_MEM_SUB_PERI_SEL, 24), + GATE_PERAO0(CLK_PERAO_AHB_APB, CLK_TOP_AXI_PERI_SEL, 25), + GATE_PERAO0(CLK_PERAO_TL, CLK_TOP_MAC_TL_SEL, 26), + GATE_PERAO0P(CLK_PERAO_REF, CLK_PAD_CLK26M, 27), + GATE_PERAO0(CLK_PERAO_I2C, CLK_TOP_AXI_PERI_SEL, 28), + GATE_PERAO0(CLK_PERAO_DMA_B, CLK_TOP_AXI_PERI_SEL, 29), + /* PERAO1 */ + GATE_PERAO1P(CLK_PERAO_SSUSB0_REF, CLK_PAD_CLK26M, 1), + GATE_PERAO1(CLK_PERAO_SSUSB0_FRMCNT, CLK_TOP_UNIVPLL_192M_D4, 2), + GATE_PERAO1(CLK_PERAO_SSUSB0_SYS, CLK_TOP_USB_TOP_P0_SEL, 4), + GATE_PERAO1(CLK_PERAO_SSUSB0_XHCI, CLK_TOP_USB_XHCI_P0_SEL, 5), + GATE_PERAO1(CLK_PERAO_SSUSB0_F, CLK_TOP_AXI_PERI_SEL, 6), + GATE_PERAO1(CLK_PERAO_SSUSB0_H, CLK_TOP_AXI_PERI_SEL, 7), + GATE_PERAO1P(CLK_PERAO_SSUSB1_REF, CLK_PAD_CLK26M, 8), + GATE_PERAO1(CLK_PERAO_SSUSB1_FRMCNT, CLK_TOP_UNIVPLL_192M_D4, 9), + GATE_PERAO1(CLK_PERAO_SSUSB1_SYS, CLK_TOP_USB_TOP_P1_SEL, 11), + GATE_PERAO1(CLK_PERAO_SSUSB1_XHCI, CLK_TOP_USB_XHCI_P1_SEL, 12), + GATE_PERAO1(CLK_PERAO_SSUSB1_F, CLK_TOP_AXI_PERI_SEL, 13), + GATE_PERAO1(CLK_PERAO_SSUSB1_H, CLK_TOP_AXI_PERI_SEL, 14), + GATE_PERAO1P(CLK_PERAO_SSUSB2_REF, CLK_PAD_CLK26M, 15), + GATE_PERAO1(CLK_PERAO_SSUSB2_FRMCNT, CLK_TOP_UNIVPLL_192M_D4, 16), + GATE_PERAO1(CLK_PERAO_SSUSB2_SYS, CLK_TOP_USB_TOP_P2_SEL, 18), + GATE_PERAO1(CLK_PERAO_SSUSB2_XHCI, CLK_TOP_USB_XHCI_P2_SEL, 19), + GATE_PERAO1(CLK_PERAO_SSUSB2_F, CLK_TOP_AXI_PERI_SEL, 20), + GATE_PERAO1(CLK_PERAO_SSUSB2_H, CLK_TOP_AXI_PERI_SEL, 21), + GATE_PERAO1P(CLK_PERAO_SSUSB3_REF, CLK_PAD_CLK26M, 23), + GATE_PERAO1(CLK_PERAO_SSUSB3_FRMCNT, CLK_TOP_UNIVPLL_192M_D4, 24), + GATE_PERAO1(CLK_PERAO_SSUSB3_SYS, CLK_TOP_USB_TOP_P3_SEL, 26), + GATE_PERAO1(CLK_PERAO_SSUSB3_XHCI, CLK_TOP_USB_XHCI_P3_SEL, 27), + GATE_PERAO1(CLK_PERAO_SSUSB3_F, CLK_TOP_AXI_PERI_SEL, 28), + GATE_PERAO1(CLK_PERAO_SSUSB3_H, CLK_TOP_AXI_PERI_SEL, 29), + /* PERAO2 */ + GATE_PERAO2P(CLK_PERAO_SSUSB4_REF, CLK_PAD_CLK26M, 0), + GATE_PERAO2(CLK_PERAO_SSUSB4_FRMCNT, CLK_TOP_UNIVPLL_192M_D4, 1), + GATE_PERAO2(CLK_PERAO_SSUSB4_SYS, CLK_TOP_USB_TOP_P4_SEL, 3), + GATE_PERAO2(CLK_PERAO_SSUSB4_XHCI, CLK_TOP_USB_XHCI_P4_SEL, 4), + GATE_PERAO2(CLK_PERAO_SSUSB4_F, CLK_TOP_AXI_PERI_SEL, 5), + GATE_PERAO2(CLK_PERAO_SSUSB4_H, CLK_TOP_AXI_PERI_SEL, 6), + GATE_PERAO2(CLK_PERAO_MSDC0, CLK_TOP_MSDC50_0_SEL, 7), + GATE_PERAO2(CLK_PERAO_MSDC0_H, CLK_TOP_MSDC50_0_HCLK_SEL, 8), + GATE_PERAO2(CLK_PERAO_MSDC0_FAES, CLK_TOP_AES_MSDCFDE_SEL, 9), + GATE_PERAO2(CLK_PERAO_MSDC0_MST_F, CLK_TOP_AXI_PERI_SEL, 10), + GATE_PERAO2(CLK_PERAO_MSDC0_SLV_H, CLK_TOP_AXI_PERI_SEL, 11), + GATE_PERAO2(CLK_PERAO_MSDC1, CLK_TOP_MSDC30_1_SEL, 12), + GATE_PERAO2(CLK_PERAO_MSDC1_H, CLK_TOP_MSDC30_1_HCLK_SEL, 13), + GATE_PERAO2(CLK_PERAO_MSDC1_MST_F, CLK_TOP_AXI_PERI_SEL, 14), + GATE_PERAO2(CLK_PERAO_MSDC1_SLV_H, CLK_TOP_AXI_PERI_SEL, 15), + GATE_PERAO2(CLK_PERAO_MSDC2, CLK_TOP_MSDC30_2_SEL, 16), + GATE_PERAO2(CLK_PERAO_MSDC2_H, CLK_TOP_MSDC30_2_HCLK_SEL, 17), + GATE_PERAO2(CLK_PERAO_MSDC2_MST_F, CLK_TOP_AXI_PERI_SEL, 18), + GATE_PERAO2(CLK_PERAO_MSDC2_SLV_H, CLK_TOP_AXI_PERI_SEL, 19), + GATE_PERAO2(CLK_PERAO_SFLASH, CLK_TOP_SFLASH_SEL, 20), + GATE_PERAO2(CLK_PERAO_SFLASH_F, CLK_TOP_AXI_PERI_SEL, 21), + GATE_PERAO2(CLK_PERAO_SFLASH_H, CLK_TOP_AXI_PERI_SEL, 22), + GATE_PERAO2(CLK_PERAO_SFLASH_P, CLK_TOP_AXI_PERI_SEL, 23), + GATE_PERAO2(CLK_PERAO_AUDIO0, CLK_TOP_AXI_PERI_SEL, 24), + GATE_PERAO2(CLK_PERAO_AUDIO1, CLK_TOP_AXI_PERI_SEL, 25), + GATE_PERAO2(CLK_PERAO_AUDIO2, CLK_TOP_AUD_INTBUS_SEL, 26), + GATE_PERAO2P(CLK_PERAO_AUXADC_26M, CLK_PAD_CLK26M, 27), +}; + +static const struct mtk_gate_regs imp_cg_regs = { + .set_ofs = 0xE08, + .clr_ofs = 0xE04, + .sta_ofs = 0xE00, +}; + +#define GATE_IMP(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &imp_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +static const struct mtk_gate imp_clks[] = { + GATE_IMP(CLK_IMPE_I2C0, CLK_TOP_I2C_SEL, 0), + GATE_IMP(CLK_IMPE_I2C1, CLK_TOP_I2C_SEL, 1), + GATE_IMP(CLK_IMPWS_I2C2, CLK_TOP_I2C_SEL, 0), + GATE_IMP(CLK_IMPS_I2C3, CLK_TOP_I2C_SEL, 0), + GATE_IMP(CLK_IMPS_I2C4, CLK_TOP_I2C_SEL, 1), + GATE_IMP(CLK_IMPS_I2C5, CLK_TOP_I2C_SEL, 2), + GATE_IMP(CLK_IMPS_I2C6, CLK_TOP_I2C_SEL, 3), + GATE_IMP(CLK_IMPEN_I2C7, CLK_TOP_I2C_SEL, 0), + GATE_IMP(CLK_IMPEN_I2C8, CLK_TOP_I2C_SEL, 1), +}; + +static const struct mtk_gate_regs mm0_cg_regs = { + .set_ofs = 0x104, + .clr_ofs = 0x108, + .sta_ofs = 0x100, +}; + +static const struct mtk_gate_regs mm1_cg_regs = { + .set_ofs = 0x114, + .clr_ofs = 0x118, + .sta_ofs = 0x110, +}; + +#define GATE_MM0(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &mm0_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +#define GATE_MM1(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &mm1_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +static const struct mtk_gate mm_clks[] = { + /* MM0 */ + GATE_MM0(CLK_MM_DISP_OVL0_4L, CLK_TOP_DISP0_SEL, 0), + GATE_MM0(CLK_MM_DISP_OVL1_4L, CLK_TOP_DISP0_SEL, 1), + GATE_MM0(CLK_MM_VPP_RSZ0, CLK_TOP_DISP0_SEL, 2), + GATE_MM0(CLK_MM_VPP_RSZ1, CLK_TOP_DISP0_SEL, 3), + GATE_MM0(CLK_MM_DISP_RDMA0, CLK_TOP_DISP0_SEL, 4), + GATE_MM0(CLK_MM_DISP_RDMA1, CLK_TOP_DISP0_SEL, 5), + GATE_MM0(CLK_MM_DISP_COLOR0, CLK_TOP_DISP0_SEL, 6), + GATE_MM0(CLK_MM_DISP_COLOR1, CLK_TOP_DISP0_SEL, 7), + GATE_MM0(CLK_MM_DISP_CCORR0, CLK_TOP_DISP0_SEL, 8), + GATE_MM0(CLK_MM_DISP_CCORR1, CLK_TOP_DISP0_SEL, 9), + GATE_MM0(CLK_MM_DISP_CCORR2, CLK_TOP_DISP0_SEL, 10), + GATE_MM0(CLK_MM_DISP_CCORR3, CLK_TOP_DISP0_SEL, 11), + GATE_MM0(CLK_MM_DISP_AAL0, CLK_TOP_DISP0_SEL, 12), + GATE_MM0(CLK_MM_DISP_AAL1, CLK_TOP_DISP0_SEL, 13), + GATE_MM0(CLK_MM_DISP_GAMMA0, CLK_TOP_DISP0_SEL, 14), + GATE_MM0(CLK_MM_DISP_GAMMA1, CLK_TOP_DISP0_SEL, 15), + GATE_MM0(CLK_MM_DISP_DITHER0, CLK_TOP_DISP0_SEL, 16), + GATE_MM0(CLK_MM_DISP_DITHER1, CLK_TOP_DISP0_SEL, 17), + GATE_MM0(CLK_MM_DISP_DSC_WRAP0, CLK_TOP_DISP0_SEL, 18), + GATE_MM0(CLK_MM_VPP_MERGE0, CLK_TOP_DISP0_SEL, 19), + GATE_MM0(CLK_MMSYS_0_DISP_DVO, CLK_TOP_DISP0_SEL, 20), + GATE_MM0(CLK_MMSYS_0_DISP_DSI0, CLK_TOP_DISP0_SEL, 21), + GATE_MM0(CLK_MM_DP_INTF0, CLK_TOP_DISP0_SEL, 22), + GATE_MM0(CLK_MM_DPI0, CLK_TOP_DISP0_SEL, 23), + GATE_MM0(CLK_MM_DISP_WDMA0, CLK_TOP_DISP0_SEL, 24), + GATE_MM0(CLK_MM_DISP_WDMA1, CLK_TOP_DISP0_SEL, 25), + GATE_MM0(CLK_MM_DISP_FAKE_ENG0, CLK_TOP_DISP0_SEL, 26), + GATE_MM0(CLK_MM_DISP_FAKE_ENG1, CLK_TOP_DISP0_SEL, 27), + GATE_MM0(CLK_MM_SMI_LARB, CLK_TOP_DISP0_SEL, 28), + GATE_MM0(CLK_MM_DISP_MUTEX0, CLK_TOP_DISP0_SEL, 29), + GATE_MM0(CLK_MM_DIPSYS_CONFIG, CLK_TOP_DISP0_SEL, 30), + GATE_MM0(CLK_MM_DUMMY, CLK_TOP_DISP0_SEL, 31), + /* MM1 */ + GATE_MM1(CLK_MMSYS_1_DISP_DSI0, CLK_TOP_DSI_OCC_SEL, 0), + GATE_MM1(CLK_MMSYS_1_LVDS_ENCODER, CLK_TOP_PLL_DPIX_SEL, 1), + GATE_MM1(CLK_MMSYS_1_DPI0, CLK_TOP_PLL_DPIX_SEL, 2), + GATE_MM1(CLK_MMSYS_1_DISP_DVO, CLK_TOP_EDP_SEL, 3), + GATE_MM1(CLK_MM_DP_INTF, CLK_TOP_DP_SEL, 4), + GATE_MM1(CLK_MMSYS_1_LVDS_ENCODER_CTS, CLK_TOP_VDSTX_DG_CTS_SEL, 5), + GATE_MM1(CLK_MMSYS_1_DISP_DVO_AVT, CLK_TOP_EDP_FAVT_SEL, 6), +}; + +static const struct mtk_gate_regs mminfra_config0_cg_regs = { + .set_ofs = 0x104, + .clr_ofs = 0x108, + .sta_ofs = 0x100, +}; + +static const struct mtk_gate_regs mminfra_config1_cg_regs = { + .set_ofs = 0x114, + .clr_ofs = 0x118, + .sta_ofs = 0x110, +}; + +#define GATE_MMINFRA_CONFIG0(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &mminfra_config0_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +#define GATE_MMINFRA_CONFIG1(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &mminfra_config1_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +static const struct mtk_gate mminfra_config_clks[] = { + GATE_MMINFRA_CONFIG0(CLK_MMINFRA_GCE_D, CLK_TOP_MMINFRA_SEL, 0), + GATE_MMINFRA_CONFIG0(CLK_MMINFRA_GCE_M, CLK_TOP_MMINFRA_SEL, 1), + GATE_MMINFRA_CONFIG0(CLK_MMINFRA_SMI, CLK_TOP_MMINFRA_SEL, 2), + GATE_MMINFRA_CONFIG1(CLK_MMINFRA_GCE_26M, CLK_TOP_MMINFRA_SEL, 17), +}; + +static const struct mtk_clk_tree mt8189_apmixedsys_clk_tree = { + .xtal_rate = 26 * MHZ, + .xtal2_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), + .plls = apmixed_plls, + .num_plls = ARRAY_SIZE(apmixed_plls), +}; + +static const struct mtk_clk_tree mt8189_topckgen_clk_tree = { + .xtal_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), + .fdivs_offs = CLK_TOP_MAINPLL_D3, + .muxes_offs = CLK_TOP_AXI_SEL, + .gates_offs = CLK_TOP_USB2_PHY_RF_P0_EN, + .fdivs = top_fixed_divs, + .muxes = top_muxes, + .gates = top_gates, + .num_fdivs = ARRAY_SIZE(top_fixed_divs), + .num_muxes = ARRAY_SIZE(top_muxes), + .num_gates = ARRAY_SIZE(top_gates), +}; + +static const struct udevice_id mt8189_apmixed[] = { + { .compatible = "mediatek,mt8189-apmixedsys", }, + { } +}; + +static const struct udevice_id mt8189_topckgen_compat[] = { + { .compatible = "mediatek,mt8189-topckgen", }, + { } +}; + +struct mt8189_gate_clk_data { + const struct mtk_gate *gates; + int num_gates; +}; + +#define GATE_CLK_DATA(name) \ +static const struct mt8189_gate_clk_data name##_data = { \ + .gates = name, .num_gates = ARRAY_SIZE(name) \ +} + +GATE_CLK_DATA(perao_clks); +GATE_CLK_DATA(imp_clks); +GATE_CLK_DATA(mm_clks); +GATE_CLK_DATA(mminfra_config_clks); + +static const struct udevice_id of_match_mt8189_clk_gate[] = { + { .compatible = "mediatek,mt8189-peri-ao", .data = (ulong)&perao_clks_data }, + { .compatible = "mediatek,mt8189-iic-wrap", .data = (ulong)&imp_clks_data }, + { .compatible = "mediatek,mt8189-dispsys", .data = (ulong)&mm_clks_data }, + { .compatible = "mediatek,mt8189-mm-infra", .data = (ulong)&mminfra_config_clks_data }, + { } +}; + +static int mt8189_apmixedsys_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt8189_apmixedsys_clk_tree); +} + +static int mt8189_topckgen_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt8189_topckgen_clk_tree); +} + +static int mt8189_clk_gate_probe(struct udevice *dev) +{ + struct mt8189_gate_clk_data *data; + + data = (void *)dev_get_driver_data(dev); + + return mtk_common_clk_gate_init(dev, &mt8189_topckgen_clk_tree, + data->gates, data->num_gates, + data->gates[0].id); +} + +U_BOOT_DRIVER(mtk_clk_apmixedsys) = { + .name = "mt8189-apmixedsys", + .id = UCLASS_CLK, + .of_match = mt8189_apmixed, + .probe = mt8189_apmixedsys_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_apmixedsys_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_topckgen) = { + .name = "mt8189-topckgen", + .id = UCLASS_CLK, + .of_match = mt8189_topckgen_compat, + .probe = mt8189_topckgen_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_topckgen_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_gate) = { + .name = "mt8189-gate-clk", + .id = UCLASS_CLK, + .of_match = of_match_mt8189_clk_gate, + .probe = mt8189_clk_gate_probe, + .priv_auto = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/mediatek/clk-mt8195.c b/drivers/clk/mediatek/clk-mt8195.c index d05d56c9bf6..d9d63601cc4 100644 --- a/drivers/clk/mediatek/clk-mt8195.c +++ b/drivers/clk/mediatek/clk-mt8195.c @@ -62,15 +62,15 @@ static const struct mtk_pll_data apmixed_plls[] = { 0x00a8, 0, 0x00a8), PLL(CLK_APMIXED_TVDPLL2, 0x00c0, 0x00d0, 0, 0, 0, 22, 0x00c8, 24, 0x00c8, 0, 0x00c8), - PLL(CLK_APMIXED_MMPLL, 0x00e0, 0x00f0, 0xff000000, HAVE_RST_BAR, + PLL(CLK_APMIXED_MMPLL, 0x00e0, 0x00f0, 0xff000000, CLK_PLL_HAVE_RST_BAR, BIT(23), 22, 0x00e8, 24, 0x00e8, 0, 0x00e8), - PLL(CLK_APMIXED_MAINPLL, 0x01d0, 0x01e0, 0xff000000, HAVE_RST_BAR, + PLL(CLK_APMIXED_MAINPLL, 0x01d0, 0x01e0, 0xff000000, CLK_PLL_HAVE_RST_BAR, BIT(23), 22, 0x01d8, 24, 0x01d8, 0, 0x01d8), PLL(CLK_APMIXED_VDECPLL, 0x0890, 0x08a0, 0, 0, 0, 22, 0x0898, 24, 0x0898, 0, 0x0898), PLL(CLK_APMIXED_IMGPLL, 0x0100, 0x0110, 0, 0, 0, 22, 0x0108, 24, 0x0108, 0, 0x0108), - PLL(CLK_APMIXED_UNIVPLL, 0x01f0, 0x0700, 0xff000000, HAVE_RST_BAR, + PLL(CLK_APMIXED_UNIVPLL, 0x01f0, 0x0700, 0xff000000, CLK_PLL_HAVE_RST_BAR, BIT(23), 22, 0x01f8, 24, 0x01f8, 0, 0x01f8), PLL(CLK_APMIXED_HDMIPLL1, 0x08c0, 0x08d0, 0, 0, 0, 22, 0x08c8, 24, 0x08c8, 0, 0x08c8), diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index 6ba464097ae..2b1703e7203 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -45,9 +45,9 @@ static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001, PLL_AO, 22, 0x0310, 24, 0x0310, 0, 0, 0), - PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0xFF000001, HAVE_RST_BAR, 22, + PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0xFF000001, CLK_PLL_HAVE_RST_BAR, 22, 0x022C, 24, 0x022C, 0, CON0_MT8365_RST_BAR, 0), - PLL(CLK_APMIXED_UNIVPLL, 0x0208, 0x0214, 0xFF000001, HAVE_RST_BAR, 22, + PLL(CLK_APMIXED_UNIVPLL, 0x0208, 0x0214, 0xFF000001, CLK_PLL_HAVE_RST_BAR, 22, 0x020C, 24, 0x020C, 0, CON0_MT8365_RST_BAR, 0), PLL(CLK_APMIXED_MFGPLL, 0x0218, 0x0224, 0x00000001, 0, 22, 0x021C, 24, 0x021C, 0, 0, 0), diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c index e6ced91fd06..7af5858286c 100644 --- a/drivers/clk/mediatek/clk-mt8512.c +++ b/drivers/clk/mediatek/clk-mt8512.c @@ -41,9 +41,9 @@ static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001, 0, 22, 0x0310, 24, 0x0310, 0, 0), PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0x00000001, - HAVE_RST_BAR, 22, 0x022C, 24, 0x022C, 0, 0), + CLK_PLL_HAVE_RST_BAR, 22, 0x022C, 24, 0x022C, 0, 0), PLL(CLK_APMIXED_UNIVPLL2, 0x0208, 0x0214, 0x00000001, - HAVE_RST_BAR, 22, 0x020C, 24, 0x020C, 0, 0), + CLK_PLL_HAVE_RST_BAR, 22, 0x020C, 24, 0x020C, 0, 0), PLL(CLK_APMIXED_MSDCPLL, 0x0350, 0x035C, 0x00000001, 0, 22, 0x0354, 24, 0x0354, 0, 0), PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x00000001, @@ -69,7 +69,7 @@ static const struct mtk_pll_data apmixed_plls[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, 0) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_CLK_NULL, 26000000), diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c index 4985ba3e5ce..9d03e245886 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -37,9 +37,9 @@ static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001, 0, 21, 0x0104, 24, 0x0104, 0), PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001, - HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0), + CLK_PLL_HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0), PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001, - HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0), + CLK_PLL_HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0), PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001, 0, 21, 0x0164, 24, 0x0164, 0), PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001, 0, @@ -62,7 +62,7 @@ static const struct mtk_pll_data apmixed_plls[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, 0) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_CLK_NULL, 26000000), diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c index 2fc492e7170..e7de9d33e00 100644 --- a/drivers/clk/mediatek/clk-mt8518.c +++ b/drivers/clk/mediatek/clk-mt8518.c @@ -37,9 +37,9 @@ static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001, 0, 21, 0x0104, 24, 0x0104, 0), PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001, - HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0), + CLK_PLL_HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0), PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001, - HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0), + CLK_PLL_HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0), PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001, 0, 21, 0x0164, 24, 0x0164, 0), PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001, @@ -64,7 +64,7 @@ static const struct mtk_pll_data apmixed_plls[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, 0) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_CLK_NULL, 26000000), diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index b4de38719e1..e86e677d8ac 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -85,6 +85,34 @@ static int mtk_common_clk_get_unmapped_id(struct clk *clk) return -ENOENT; } +static bool mtk_clk_id_is_pll(const struct mtk_clk_tree *tree, int mapped_id) +{ + return tree->plls && mapped_id < tree->num_plls; +} + +static bool mtk_clk_id_is_fclk(const struct mtk_clk_tree *tree, int mapped_id) +{ + return tree->fclks && mapped_id < tree->num_fclks; +} + +static bool mtk_clk_id_is_fdiv(const struct mtk_clk_tree *tree, int mapped_id) +{ + return tree->fdivs && mapped_id >= tree->fdivs_offs && + mapped_id < tree->fdivs_offs + tree->num_fdivs; +} + +static bool mtk_clk_id_is_mux(const struct mtk_clk_tree *tree, int mapped_id) +{ + return tree->muxes && mapped_id >= tree->muxes_offs && + mapped_id < tree->muxes_offs + tree->num_muxes; +} + +static bool mtk_clk_id_is_gate(const struct mtk_clk_tree *tree, int mapped_id) +{ + return tree->gates && mapped_id >= tree->gates_offs && + mapped_id < tree->gates_offs + tree->num_gates; +} + static int mtk_dummy_enable(struct clk *clk) { return 0; @@ -140,6 +168,14 @@ static int mtk_gate_disable(void __iomem *base, const struct mtk_gate *gate) return 0; } +static ulong mtk_ext_clock_get_rate(const struct mtk_clk_tree *tree, int id) +{ + if (!tree->ext_clk_rates || id >= tree->num_ext_clks) + return -ENOENT; + + return tree->ext_clk_rates[id]; +} + /* * In case the rate change propagation to parent clocks is undesirable, * this function is recursively called to find the parent to calculate @@ -168,6 +204,55 @@ static ulong mtk_clk_find_parent_rate(struct clk *clk, int id, return clk_get_rate(&parent); } +const struct clk_ops mtk_clk_apmixedsys_ops; +const struct clk_ops mtk_clk_topckgen_ops; +const struct clk_ops mtk_clk_infrasys_ops; + +static ulong mtk_find_parent_rate(struct mtk_clk_priv *priv, struct clk *clk, + const int parent, u16 flags) +{ + struct udevice *parent_dev; + + switch (flags & CLK_PARENT_MASK) { + case CLK_PARENT_APMIXED: + /* APMIXEDSYS can be parent or grandparent. */ + if (dev_get_driver_ops(clk->dev) == &mtk_clk_apmixedsys_ops) + parent_dev = clk->dev; + else if (dev_get_driver_ops(priv->parent) == &mtk_clk_apmixedsys_ops) + parent_dev = priv->parent; + else if (dev_get_driver_ops(dev_get_parent(priv->parent)) == &mtk_clk_apmixedsys_ops) + parent_dev = dev_get_parent(priv->parent); + else + return -EINVAL; + + break; + case CLK_PARENT_TOPCKGEN: + if (dev_get_driver_ops(clk->dev) == &mtk_clk_topckgen_ops) + parent_dev = clk->dev; + else if (dev_get_driver_ops(priv->parent) == &mtk_clk_topckgen_ops) + parent_dev = priv->parent; + else + return -EINVAL; + + break; + case CLK_PARENT_INFRASYS: + if (dev_get_driver_ops(clk->dev) != &mtk_clk_infrasys_ops) + return -EINVAL; + + parent_dev = clk->dev; + break; + case CLK_PARENT_XTAL: + return priv->tree->xtal_rate; + case CLK_PARENT_EXT: + return mtk_ext_clock_get_rate(priv->tree, parent); + default: + parent_dev = NULL; + break; + } + + return mtk_clk_find_parent_rate(clk, parent, parent_dev); +} + static int mtk_clk_mux_set_parent(void __iomem *base, u32 parent, u32 parent_type, const struct mtk_composite *mux) @@ -262,6 +347,9 @@ static void mtk_clk_print_parent(const char *prefix, int parent, u32 flags) case CLK_PARENT_XTAL: parent_type_str = "xtal"; break; + case CLK_PARENT_EXT: + parent_type_str = "ext"; + break; case CLK_PARENT_MIXED: parent_type_str = "mixed"; break; @@ -328,15 +416,10 @@ static const int mtk_apmixedsys_of_xlate(struct clk *clk, return ret; /* apmixedsys only uses plls and gates. */ + if (!mtk_clk_id_is_pll(tree, clk->id) && !mtk_clk_id_is_gate(tree, clk->id)) + return -ENOENT; - if (tree->plls && clk->id < tree->num_plls) - return 0; - - if (tree->gates && clk->id >= tree->gates_offs && - clk->id < tree->gates_offs + tree->num_gates) - return 0; - - return -ENOENT; + return 0; } static unsigned long __mtk_pll_recalc_rate(const struct mtk_pll_data *pll, @@ -450,7 +533,7 @@ static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate) u32 pcw = 0; u32 postdiv; - if (priv->tree->gates && clk->id >= priv->tree->gates_offs) + if (!mtk_clk_id_is_pll(priv->tree, clk->id)) return -EINVAL; mtk_pll_calc_values(priv, clk->id, &pcw, &postdiv, rate); @@ -468,9 +551,9 @@ static ulong mtk_apmixedsys_get_rate(struct clk *clk) u32 pcw; /* GATE handling */ - if (priv->tree->gates && clk->id >= priv->tree->gates_offs) { + if (mtk_clk_id_is_gate(priv->tree, clk->id)) { gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; - return mtk_clk_find_parent_rate(clk, gate->parent, NULL); + return mtk_find_parent_rate(priv, clk, gate->parent, gate->flags); } pll = &priv->tree->plls[clk->id]; @@ -494,7 +577,7 @@ static int mtk_apmixedsys_enable(struct clk *clk) u32 r; /* GATE handling */ - if (priv->tree->gates && clk->id >= priv->tree->gates_offs) { + if (mtk_clk_id_is_gate(priv->tree, clk->id)) { gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; return mtk_gate_enable(priv->base, gate); } @@ -515,7 +598,7 @@ static int mtk_apmixedsys_enable(struct clk *clk) udelay(20); - if (pll->flags & HAVE_RST_BAR) { + if (pll->flags & CLK_PLL_HAVE_RST_BAR) { r = readl(priv->base + pll->reg + REG_CON0); r |= pll->rst_bar_mask; writel(r, priv->base + pll->reg + REG_CON0); @@ -532,14 +615,14 @@ static int mtk_apmixedsys_disable(struct clk *clk) u32 r; /* GATE handling */ - if (priv->tree->gates && clk->id >= priv->tree->gates_offs) { + if (mtk_clk_id_is_gate(priv->tree, clk->id)) { gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; return mtk_gate_disable(priv->base, gate); } pll = &priv->tree->plls[clk->id]; - if (pll->flags & HAVE_RST_BAR) { + if (pll->flags & CLK_PLL_HAVE_RST_BAR) { r = readl(priv->base + pll->reg + REG_CON0); r &= ~pll->rst_bar_mask; writel(r, priv->base + pll->reg + REG_CON0); @@ -602,23 +685,11 @@ static const int mtk_topckgen_of_xlate(struct clk *clk, return ret; /* topckgen only uses fclks, fdivs, muxes and gates. */ + if (!mtk_clk_id_is_fclk(tree, clk->id) && !mtk_clk_id_is_fdiv(tree, clk->id) && + !mtk_clk_id_is_mux(tree, clk->id) && !mtk_clk_id_is_gate(tree, clk->id)) + return -ENOENT; - if (tree->fclks && clk->id < tree->num_fclks) - return 0; - - if (tree->fdivs && clk->id >= tree->fdivs_offs && - clk->id < tree->fdivs_offs + tree->num_fdivs) - return 0; - - if (tree->muxes && clk->id >= tree->muxes_offs && - clk->id < tree->muxes_offs + tree->num_muxes) - return 0; - - if (tree->gates && clk->id >= tree->gates_offs && - clk->id < tree->gates_offs + tree->num_gates) - return 0; - - return -ENOENT; + return 0; } static ulong mtk_factor_recalc_rate(const struct mtk_fixed_factor *fdiv, @@ -637,39 +708,13 @@ static ulong mtk_topckgen_get_factor_rate(struct clk *clk, u32 off) const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off]; ulong rate; - switch (fdiv->flags & CLK_PARENT_MASK) { - case CLK_PARENT_APMIXED: - rate = mtk_clk_find_parent_rate(clk, fdiv->parent, - priv->parent); - break; - case CLK_PARENT_TOPCKGEN: - rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL); - break; - - case CLK_PARENT_XTAL: - default: - rate = priv->tree->xtal_rate; - } - + rate = mtk_find_parent_rate(priv, clk, fdiv->parent, fdiv->flags); if (IS_ERR_VALUE(rate)) return rate; return mtk_factor_recalc_rate(fdiv, rate); } -static ulong mtk_topckgen_find_parent_rate(struct mtk_clk_priv *priv, struct clk *clk, - const int parent, u16 flags) -{ - switch (flags & CLK_PARENT_MASK) { - case CLK_PARENT_XTAL: - return priv->tree->xtal_rate; - case CLK_PARENT_APMIXED: - return mtk_clk_find_parent_rate(clk, parent, priv->parent); - default: - return mtk_clk_find_parent_rate(clk, parent, NULL); - } -} - static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); @@ -687,33 +732,14 @@ static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off) if (mux->flags & CLK_PARENT_MIXED) { const struct mtk_parent *parent = &mux->parent_flags[index]; - return mtk_topckgen_find_parent_rate(priv, clk, parent->id, - parent->flags); + return mtk_find_parent_rate(priv, clk, parent->id, parent->flags); } if (mux->parent[index] == CLK_XTAL && !(priv->tree->flags & CLK_BYPASS_XTAL)) return priv->tree->xtal_rate; - return mtk_topckgen_find_parent_rate(priv, clk, mux->parent[index], - mux->flags); -} - -static ulong mtk_find_parent_rate(struct mtk_clk_priv *priv, struct clk *clk, - const int parent, u16 flags) -{ - switch (flags & CLK_PARENT_MASK) { - case CLK_PARENT_XTAL: - return priv->tree->xtal_rate; - /* Assume the second level parent is always APMIXED */ - case CLK_PARENT_APMIXED: - priv = dev_get_priv(priv->parent); - fallthrough; - case CLK_PARENT_TOPCKGEN: - return mtk_clk_find_parent_rate(clk, parent, priv->parent); - default: - return mtk_clk_find_parent_rate(clk, parent, NULL); - } + return mtk_find_parent_rate(priv, clk, mux->parent[index], mux->flags); } static ulong mtk_topckgen_get_rate(struct clk *clk) @@ -721,21 +747,22 @@ static ulong mtk_topckgen_get_rate(struct clk *clk) struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_clk_tree *tree = priv->tree; - if (tree->gates && clk->id >= tree->gates_offs && - clk->id < tree->gates_offs + tree->num_gates) { + if (mtk_clk_id_is_fclk(tree, clk->id)) + return tree->fclks[clk->id].rate; + + if (mtk_clk_id_is_fdiv(tree, clk->id)) + return mtk_topckgen_get_factor_rate(clk, clk->id - tree->fdivs_offs); + + if (mtk_clk_id_is_mux(tree, clk->id)) + return mtk_topckgen_get_mux_rate(clk, clk->id - tree->muxes_offs); + + if (mtk_clk_id_is_gate(tree, clk->id)) { const struct mtk_gate *gate = &tree->gates[clk->id - tree->gates_offs]; - return mtk_clk_find_parent_rate(clk, gate->parent, NULL); + return mtk_find_parent_rate(priv, clk, gate->parent, gate->flags); } - if (clk->id < priv->tree->fdivs_offs) - return priv->tree->fclks[clk->id].rate; - else if (clk->id < priv->tree->muxes_offs) - return mtk_topckgen_get_factor_rate(clk, clk->id - - priv->tree->fdivs_offs); - else - return mtk_topckgen_get_mux_rate(clk, clk->id - - priv->tree->muxes_offs); + return -ENOENT; } static int mtk_clk_mux_enable(struct clk *clk) @@ -744,7 +771,7 @@ static int mtk_clk_mux_enable(struct clk *clk) const struct mtk_composite *mux; u32 val; - if (clk->id < priv->tree->muxes_offs) + if (!mtk_clk_id_is_mux(priv->tree, clk->id)) return 0; mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs]; @@ -761,7 +788,7 @@ static int mtk_clk_mux_enable(struct clk *clk) writel(val, priv->base + mux->gate_reg); } - if (mux->flags & CLK_DOMAIN_SCPSYS) { + if (mux->flags & CLK_MUX_DOMAIN_SCPSYS) { /* enable scpsys clock off control */ writel(SCP_ARMCK_OFF_EN, priv->base + CLK_SCP_CFG0); writel(SCP_AXICK_DCM_DIS_EN | SCP_AXICK_26M_SEL_EN, @@ -776,8 +803,7 @@ static int mtk_topckgen_enable(struct clk *clk) struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_clk_tree *tree = priv->tree; - if (tree->gates && clk->id >= tree->gates_offs && - clk->id < tree->gates_offs + tree->num_gates) { + if (mtk_clk_id_is_gate(tree, clk->id)) { const struct mtk_gate *gate = &tree->gates[clk->id - tree->gates_offs]; return mtk_gate_enable(priv->base, gate); @@ -792,7 +818,7 @@ static int mtk_clk_mux_disable(struct clk *clk) const struct mtk_composite *mux; u32 val; - if (clk->id < priv->tree->muxes_offs) + if (!mtk_clk_id_is_mux(priv->tree, clk->id)) return 0; mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs]; @@ -817,8 +843,7 @@ static int mtk_topckgen_disable(struct clk *clk) struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_clk_tree *tree = priv->tree; - if (tree->gates && clk->id >= tree->gates_offs && - clk->id < tree->gates_offs + tree->num_gates) { + if (mtk_clk_id_is_gate(tree, clk->id)) { const struct mtk_gate *gate = &tree->gates[clk->id - tree->gates_offs]; return mtk_gate_disable(priv->base, gate); @@ -834,8 +859,7 @@ static int mtk_common_clk_set_parent(struct clk *clk, struct clk *parent) int parent_unmapped_id; u32 parent_type; - if (!priv->tree->muxes || clk->id < priv->tree->muxes_offs || - clk->id >= priv->tree->muxes_offs + priv->tree->num_muxes) + if (!mtk_clk_id_is_mux(priv->tree, clk->id)) return 0; if (!parent_priv) @@ -915,29 +939,20 @@ static const int mtk_infrasys_of_xlate(struct clk *clk, return ret; /* ifrasys only uses fdivs, muxes and gates. */ + if (!mtk_clk_id_is_fdiv(tree, clk->id) && !mtk_clk_id_is_mux(tree, clk->id) && + !mtk_clk_id_is_gate(tree, clk->id)) + return -ENOENT; - if (tree->fdivs && clk->id >= tree->fdivs_offs && - clk->id < tree->fdivs_offs + tree->num_fdivs) - return 0; - - if (tree->muxes && clk->id >= tree->muxes_offs && - clk->id < tree->muxes_offs + tree->num_muxes) - return 0; - - if (tree->gates && clk->id >= tree->gates_offs && - clk->id < tree->gates_offs + tree->num_gates) - return 0; - - return -ENOENT; + return 0; } static int mtk_clk_infrasys_enable(struct clk *clk) { - struct mtk_cg_priv *priv = dev_get_priv(clk->dev); + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_gate *gate; /* MUX handling */ - if (!priv->tree->gates || clk->id < priv->tree->gates_offs) + if (!mtk_clk_id_is_gate(priv->tree, clk->id)) return mtk_clk_mux_enable(clk); gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; @@ -946,11 +961,11 @@ static int mtk_clk_infrasys_enable(struct clk *clk) static int mtk_clk_infrasys_disable(struct clk *clk) { - struct mtk_cg_priv *priv = dev_get_priv(clk->dev); + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_gate *gate; /* MUX handling */ - if (!priv->tree->gates || clk->id < priv->tree->gates_offs) + if (!mtk_clk_id_is_gate(priv->tree, clk->id)) return mtk_clk_mux_disable(clk); gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; @@ -963,18 +978,7 @@ static ulong mtk_infrasys_get_factor_rate(struct clk *clk, u32 off) const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off]; ulong rate; - switch (fdiv->flags & CLK_PARENT_MASK) { - case CLK_PARENT_TOPCKGEN: - rate = mtk_clk_find_parent_rate(clk, fdiv->parent, - priv->parent); - break; - case CLK_PARENT_XTAL: - rate = priv->tree->xtal_rate; - break; - default: - rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL); - } - + rate = mtk_find_parent_rate(priv, clk, fdiv->parent, fdiv->flags); if (IS_ERR_VALUE(rate)) return rate; @@ -1013,31 +1017,22 @@ static ulong mtk_infrasys_get_rate(struct clk *clk) struct mtk_clk_priv *priv = dev_get_priv(clk->dev); ulong rate; - if (clk->id < priv->tree->fdivs_offs) { + if (mtk_clk_id_is_fclk(priv->tree, clk->id)) { rate = priv->tree->fclks[clk->id].rate; - } else if (clk->id < priv->tree->muxes_offs) { + } else if (mtk_clk_id_is_fdiv(priv->tree, clk->id)) { rate = mtk_infrasys_get_factor_rate(clk, clk->id - priv->tree->fdivs_offs); /* No gates defined or ID is a MUX */ - } else if (!priv->tree->gates || clk->id < priv->tree->gates_offs) { + } else if (!mtk_clk_id_is_gate(priv->tree, clk->id)) { rate = mtk_infrasys_get_mux_rate(clk, clk->id - priv->tree->muxes_offs); /* Only valid with muxes + gates implementation */ } else { - struct udevice *parent = NULL; const struct mtk_gate *gate; gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; - if (gate->flags & CLK_PARENT_TOPCKGEN) - parent = priv->parent; - /* - * Assume xtal_rate to be declared if some gates have - * XTAL as parent - */ - else if (gate->flags & CLK_PARENT_XTAL) - return priv->tree->xtal_rate; - rate = mtk_clk_find_parent_rate(clk, gate->parent, parent); + rate = mtk_find_parent_rate(priv, clk, gate->parent, gate->flags); } return rate; @@ -1152,6 +1147,8 @@ static ulong mtk_clk_gate_get_rate(struct clk *clk) */ } else if (gate->flags & CLK_PARENT_XTAL) { return priv->tree->xtal_rate; + } else if (gate->flags & CLK_PARENT_EXT) { + return mtk_ext_clock_get_rate(priv->tree, gate->parent); } return mtk_clk_find_parent_rate(clk, gate->parent, parent); diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index f3d2377aee4..f81e214bf00 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -20,8 +20,9 @@ */ #define CLK_BYPASS_XTAL BIT(0) -#define HAVE_RST_BAR BIT(0) -#define CLK_DOMAIN_SCPSYS BIT(0) +#define CLK_PLL_HAVE_RST_BAR BIT(0) + +#define CLK_MUX_DOMAIN_SCPSYS BIT(0) #define CLK_MUX_SETCLR_UPD BIT(1) #define CLK_GATE_SETCLR BIT(0) @@ -34,12 +35,13 @@ #define CLK_PARENT_TOPCKGEN BIT(5) #define CLK_PARENT_INFRASYS BIT(6) #define CLK_PARENT_XTAL BIT(7) +#define CLK_PARENT_EXT BIT(8) /* * For CLK_PARENT_MIXED to correctly work, is required to * define in clk_tree flags the clk type using the alias. */ -#define CLK_PARENT_MIXED BIT(8) -#define CLK_PARENT_MASK GENMASK(8, 4) +#define CLK_PARENT_MIXED BIT(9) +#define CLK_PARENT_MASK GENMASK(9, 4) #define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34 @@ -127,6 +129,13 @@ struct mtk_parent { .flags = _flags, \ } +#define APMIXED_PARENT(id) PARENT(id, CLK_PARENT_APMIXED) +#define TOP_PARENT(id) PARENT(id, CLK_PARENT_TOPCKGEN) +#define INFRA_PARENT(id) PARENT(id, CLK_PARENT_INFRASYS) +#define XTAL_PARENT(id) PARENT(id, CLK_PARENT_XTAL) +#define EXT_PARENT(id) PARENT(id, CLK_PARENT_EXT) +#define VOID_PARENT PARENT(-1, 0) + /** * struct mtk_composite - aggregate clock of mux, divider and gate clocks * @@ -176,6 +185,22 @@ struct mtk_composite { #define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate) \ MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0) +#define MUX_GATE_MIXED_FLAGS(_id, _parents, _reg, _shift, _width, _gate,\ + _flags) { \ + .id = _id, \ + .mux_reg = _reg, \ + .mux_shift = _shift, \ + .mux_mask = BIT(_width) - 1, \ + .gate_reg = _reg, \ + .gate_shift = _gate, \ + .parent_flags = _parents, \ + .num_parents = ARRAY_SIZE(_parents), \ + .flags = (_flags) | CLK_PARENT_MIXED, \ + } + +#define MUX_GATE_MIXED(_id, _parents, _reg, _shift, _width, _gate) \ + MUX_GATE_MIXED_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0) + #define MUX_MIXED_FLAGS(_id, _parents, _reg, _shift, _width, _flags) { \ .id = _id, \ .mux_reg = _reg, \ @@ -220,6 +245,24 @@ struct mtk_composite { .flags = _flags, \ } +#define MUX_MIXED_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs,\ + _mux_clr_ofs, _shift, _width, _gate,\ + _upd_ofs, _upd, _flags) { \ + .id = _id, \ + .mux_reg = _mux_ofs, \ + .mux_set_reg = _mux_set_ofs, \ + .mux_clr_reg = _mux_clr_ofs, \ + .upd_reg = _upd_ofs, \ + .upd_shift = _upd, \ + .mux_shift = _shift, \ + .mux_mask = BIT(_width) - 1, \ + .gate_reg = _mux_ofs, \ + .gate_shift = _gate, \ + .parent_flags = _parents, \ + .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_PARENT_MIXED | (_flags), \ + } + struct mtk_gate_regs { u32 sta_ofs; u32 clr_ofs; @@ -255,6 +298,9 @@ struct mtk_gate { struct mtk_clk_tree { unsigned long xtal_rate; unsigned long xtal2_rate; + /* External fixed clocks - excluded from mapping. */ + const ulong *ext_clk_rates; + const int num_ext_clks; /* * Clock IDs may be remapped with an auxiliary table. Enable this by * defining .id_offs_map and .id_offs_map_size. This is needed e.g. when |