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authorTom Rini <[email protected]>2021-07-23 08:30:48 -0400
committerTom Rini <[email protected]>2021-07-23 08:30:48 -0400
commitf534d93cbf34f1d1762b04eb5680e84bef5e1fe1 (patch)
tree09a0231852e9df884a8da30db093ac1932978814 /drivers
parent4906d698d3960b70cf8000299da35412efd4f51d (diff)
parent988002dcd931e7236422e4d158c397d964ba1360 (diff)
Merge branch '2021-07-23-assorted-fixes'
- Assorted FIT, optee, pcf8575, mux, vexpress64 and distro bootcmd fixes. - Allow pinmux status to take pin names
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpio/pcf8575_gpio.c43
-rw-r--r--drivers/tee/optee/core.c21
-rw-r--r--drivers/tee/tee-uclass.c19
3 files changed, 57 insertions, 26 deletions
diff --git a/drivers/gpio/pcf8575_gpio.c b/drivers/gpio/pcf8575_gpio.c
index 359646266c9..d5930d941fc 100644
--- a/drivers/gpio/pcf8575_gpio.c
+++ b/drivers/gpio/pcf8575_gpio.c
@@ -12,15 +12,9 @@
*
* Copyright (C) 2007 David Brownell
*
- */
-
-/*
- * NOTE: The driver and devicetree bindings are borrowed from Linux
- * Kernel, but driver does not support all PCF857x devices. It currently
- * supports PCF8575 16-bit expander by TI and NXP.
+ * Add support for 8 bit expanders - like pca8574
+ * Copyright (C) 2021 Lukasz Majewski - DENX Software Engineering
*
- * Support 8 bit PCF857x compatible expanders.
*/
#include <common.h>
@@ -34,8 +28,6 @@
DECLARE_GLOBAL_DATA_PTR;
struct pcf8575_chip {
- int gpio_count; /* No. GPIOs supported by the chip */
-
/* NOTE: these chips have strange "quasi-bidirectional" I/O pins.
* We can't actually know whether a pin is configured (a) as output
* and driving the signal low, or (b) as input and reporting a low
@@ -49,18 +41,17 @@ struct pcf8575_chip {
* reset state. Otherwise it flags pins to be driven low.
*/
unsigned int out; /* software latch */
- const char *bank_name; /* Name of the expander bank */
};
-/* Read/Write to 16-bit I/O expander */
+/* Read/Write to I/O expander */
-static int pcf8575_i2c_write_le16(struct udevice *dev, unsigned int word)
+static int pcf8575_i2c_write(struct udevice *dev, unsigned int word)
{
struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
u8 buf[2] = { word & 0xff, word >> 8, };
int ret;
- ret = dm_i2c_write(dev, 0, buf, 2);
+ ret = dm_i2c_write(dev, 0, buf, dev_get_driver_data(dev));
if (ret)
printf("%s i2c write failed to addr %x\n", __func__,
chip->chip_addr);
@@ -68,13 +59,13 @@ static int pcf8575_i2c_write_le16(struct udevice *dev, unsigned int word)
return ret;
}
-static int pcf8575_i2c_read_le16(struct udevice *dev)
+static int pcf8575_i2c_read(struct udevice *dev)
{
struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
- u8 buf[2];
+ u8 buf[2] = {0x00, 0x00};
int ret;
- ret = dm_i2c_read(dev, 0, buf, 2);
+ ret = dm_i2c_read(dev, 0, buf, dev_get_driver_data(dev));
if (ret) {
printf("%s i2c read failed from addr %x\n", __func__,
chip->chip_addr);
@@ -90,7 +81,7 @@ static int pcf8575_direction_input(struct udevice *dev, unsigned offset)
int status;
plat->out |= BIT(offset);
- status = pcf8575_i2c_write_le16(dev, plat->out);
+ status = pcf8575_i2c_write(dev, plat->out);
return status;
}
@@ -106,7 +97,7 @@ static int pcf8575_direction_output(struct udevice *dev,
else
plat->out &= ~BIT(offset);
- ret = pcf8575_i2c_write_le16(dev, plat->out);
+ ret = pcf8575_i2c_write(dev, plat->out);
return ret;
}
@@ -115,7 +106,7 @@ static int pcf8575_get_value(struct udevice *dev, unsigned int offset)
{
int value;
- value = pcf8575_i2c_read_le16(dev);
+ value = pcf8575_i2c_read(dev);
return (value < 0) ? value : ((value & BIT(offset)) >> offset);
}
@@ -133,8 +124,11 @@ static int pcf8575_ofdata_plat(struct udevice *dev)
int n_latch;
- uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "gpio-count", 16);
+ /*
+ * Number of pins depends on the expander device and is specified
+ * in the struct udevice_id (as in the Linue kernel).
+ */
+ uc_priv->gpio_count = dev_get_driver_data(dev) * 8;
uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
"gpio-bank-name", NULL);
if (!uc_priv->bank_name)
@@ -166,8 +160,9 @@ static const struct dm_gpio_ops pcf8575_gpio_ops = {
};
static const struct udevice_id pcf8575_gpio_ids[] = {
- { .compatible = "nxp,pcf8575" },
- { .compatible = "ti,pcf8575" },
+ { .compatible = "nxp,pcf8575", .data = 2 },
+ { .compatible = "ti,pcf8575", .data = 2 },
+ { .compatible = "nxp,pca8574", .data = 1 },
{ }
};
diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c
index 73dbb22ba09..dad46aa388a 100644
--- a/drivers/tee/optee/core.c
+++ b/drivers/tee/optee/core.c
@@ -1,9 +1,10 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (c) 2018 Linaro Limited
+ * Copyright (c) 2018-2020 Linaro Limited
*/
#include <common.h>
+#include <cpu_func.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <log.h>
@@ -295,6 +296,16 @@ static u32 call_err_to_res(u32 call_err)
}
}
+static void flush_shm_dcache(struct udevice *dev, struct optee_msg_arg *arg)
+{
+ size_t sz = OPTEE_MSG_GET_ARG_SIZE(arg->num_params);
+
+ flush_dcache_range(rounddown((ulong)arg, CONFIG_SYS_CACHELINE_SIZE),
+ roundup((ulong)arg + sz, CONFIG_SYS_CACHELINE_SIZE));
+
+ tee_flush_all_shm_dcache(dev);
+}
+
static u32 do_call_with_arg(struct udevice *dev, struct optee_msg_arg *arg)
{
struct optee_pdata *pdata = dev_get_plat(dev);
@@ -305,9 +316,17 @@ static u32 do_call_with_arg(struct udevice *dev, struct optee_msg_arg *arg)
while (true) {
struct arm_smccc_res res;
+ /* If cache are off from U-Boot, sync the cache shared with OP-TEE */
+ if (!dcache_status())
+ flush_shm_dcache(dev, arg);
+
pdata->invoke_fn(param.a0, param.a1, param.a2, param.a3,
param.a4, param.a5, param.a6, param.a7, &res);
+ /* If cache are off from U-Boot, sync the cache shared with OP-TEE */
+ if (!dcache_status())
+ flush_shm_dcache(dev, arg);
+
free(page_list);
page_list = NULL;
diff --git a/drivers/tee/tee-uclass.c b/drivers/tee/tee-uclass.c
index cb1b28e2f83..52412a4098e 100644
--- a/drivers/tee/tee-uclass.c
+++ b/drivers/tee/tee-uclass.c
@@ -1,15 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (c) 2018 Linaro Limited
+ * Copyright (c) 2018-2020 Linaro Limited
*/
#define LOG_CATEGORY UCLASS_TEE
#include <common.h>
+#include <cpu_func.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
#include <tee.h>
+#include <asm/cache.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
@@ -235,3 +237,18 @@ void tee_optee_ta_uuid_to_octets(u8 d[TEE_UUID_LEN],
d[7] = s->time_hi_and_version;
memcpy(d + 8, s->clock_seq_and_node, sizeof(s->clock_seq_and_node));
}
+
+void tee_flush_all_shm_dcache(struct udevice *dev)
+{
+ struct tee_uclass_priv *priv = dev_get_uclass_priv(dev);
+ struct tee_shm *s;
+
+ list_for_each_entry(s, &priv->list_shm, link) {
+ ulong start = rounddown((ulong)s->addr,
+ CONFIG_SYS_CACHELINE_SIZE);
+ ulong end = roundup((ulong)s->addr + s->size,
+ CONFIG_SYS_CACHELINE_SIZE);
+
+ flush_dcache_range(start, end);
+ }
+}